Surge-voltage-resistant planar gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides an anti-surge-voltage planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer on the drift layer, and performing etching and ion implantation to form a protection region, a current sharing region, a second P-type well region, a Schottky region, a first P-type well region and a lug boss; a barrier layer is formed again, etching and ion implantation are carried out, and an N-type source region is formed; forming a barrier layer again, etching and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the method comprises the following steps: preparing a source electrode metal layer, re-forming a barrier layer, etching, depositing metal, forming a source electrode metal layer, removing the barrier layer, and completing preparation. The reliability of the device is improved, the conduction loss of the device is reduced, and the surge voltage resistance is improved.

Description

Technical Field

[0001] The invention relates to a planar gate silicon carbide VDMOS capable of resisting surge voltage and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different focuses, but the overall requirements include higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), and lower body diode conduction loss.

[0003] In the fields of aerospace, high reliability has become the key to restricting applications. Large surge voltages are prone to occur in the fields of aerospace, electric vehicles, etc. In high-reliability application scenarios, improving the device's surge resistance while ensuring the device's low on-resistance is the key to special applications. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a planar gate silicon carbide VDMOS that is resistant to surge voltage and a preparation method thereof. By optimizing the protection zone and the current equalizing zone of the device and the parasitic JBS body diode design, the device reliability is improved, the conduction loss of the device is reduced, and the ability to resist surge voltage is improved.

[0005] In a first aspect, the present invention provides a method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a protection zone; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a current equalizing area; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a second P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a Schottky region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a first P-type well region and a protruding portion; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form an N-type source region; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0006] In a second aspect, the present invention provides a planar gate silicon carbide VDMOS with surge voltage resistance, wherein the silicon carbide VDMOS is prepared by the method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance described in the first aspect.

[0007] The advantages of the present invention are: 1. The present invention designs a protection zone. When a large surge voltage is applied to the protection zone, the drift layer and the protection zone form a voltage-resistant space charge zone, thereby preventing the drain surge voltage from impacting the device gate structure. Second, the invention designs a current balancing area, which is horizontally distributed on the left and right sides above the protection zone, without affecting the surge voltage resistance of the protection zone. At the same time, when the device is turned on, the current in the JFET zone is redistributed to the left and right sides of the P-type protection zone, thereby reducing the on-resistance of the device; 3. Based on the JBS body diode constructed inside the device, a second P-type well region is constructed. The bottom of the second P-type well region is in direct contact with the current equalizing region, constructing a low-resistance path from the device's parasitic pn junction body diode to the device drain, which can reduce the device's conduction loss under high current conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0009] Figure 1 The schematic diagram of the planar gate silicon carbide VDMOS with surge voltage resistance of the present invention is shown.

[0010] Figure 2 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 1 .

[0011] Figure 3 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 2 .

[0012] Figure 4 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 3 .

[0013] Figure 5 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 4 .

[0014] Figure 6 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 5 .

[0015] Figure 7 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 6 .

[0016] Figure 8 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 7 .

[0017] Fig. 9 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 8 .

[0018] Fig.10 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 9 .

[0019] Fig.11 The process section of the present invention is a planar gate silicon carbide VDMOS with surge voltage resistance Figure 10 . DETAILED DESCRIPTION

[0020] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0022] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0023] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0024] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2; Step 2, forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a through hole, and implanting ions to form a protection zone 21; Step 3, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and implanting ions to form a current equalizing region 22; Step 4, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form a second P-type well region 41; Step 5, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and implanting ions to form the Schottky region 4; Step 6, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form a first P-type well region 3 and a protruding portion 23; Step 7, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form an N-type source region 31; Step 8, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and depositing to form an insulating dielectric layer 5; Step 9, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, depositing metal, and forming a gate metal layer 6; Step 10: remove the original barrier layer, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, deposit metal to form a source metal layer 7, remove the barrier layer 9, and complete the preparation.

[0026] In this embodiment, preferably, the sum of the width of the current balancing region 22 and the width of the protection region 21 is equal to the width of the drift layer 2 , and the width of the protection region 21 is equal to the width of the protrusion 23 .

[0027] In this embodiment, preferably, the upper side surface of the protection area 21 and the lower side surface of the flow equalizing area 22 are located in the same plane.

[0028] In this embodiment, preferably, the thickness of the protection area 21 is 300 nm; the thickness of the current equalizing area 22 is 300 nm.

[0029] In this embodiment, preferably, the silicon carbide substrate 1 , the drift layer 2 , the current balancing region 22 and the Schottky region 4 are all of N type, and the protection region 21 is of P type.

[0030] In this embodiment, preferably, the doping concentration of the protection zone 21 is greater than the doping concentration of the drift layer 2 ; the doping concentration of the protection zone 21 is greater than the doping concentration of the current balancing zone 22 .

[0031] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 1; A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a protection zone 21, a flow balancing zone 22 and a protrusion 23 are provided in the drift layer 2; the protection zone 21 is located below the flow balancing zone 22 and directly below the protrusion 23, and the flow balancing zone 22 is not directly below the protrusion 23; A first P-type well region 3, wherein the lower side of the first P-type well region 3 is connected to the upper side of the drift layer 2, and the inner side of the first P-type well region 3 is connected to the outer side of the protrusion 23; an N-type source region 31 is provided on the first P-type well region 3; A Schottky region 4, wherein the lower side of the Schottky region 4 is connected to the upper side of the drift layer 2, and the inner side of the Schottky region 4 is connected to the outer side of the first P-type well region 3; a second P-type well region 41 is provided in the Schottky region 4, and the lower part of the second P-type well region 41 passes through the drift layer 2 and is connected to the upper side of the current balancing region 22; An insulating dielectric layer 5, wherein the lower side of the insulating dielectric layer 5 is respectively connected to the upper side of the protrusion 23, the first P-type well region 3 and the N-type source region 31; A gate metal layer 6, wherein the gate metal layer 6 is connected to the insulating dielectric layer 5; A source metal layer 7, the lower side of the source metal layer 7 is respectively connected to the upper side of the N-type source region 31, the upper side of the first P-type well region 3, the upper side of the second P-type well region 41 and the upper side of the Schottky region 4; and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0032] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e16cm -3 , the doping concentration of the P-type protection zone 21 is 5-12e17cm -3 , the doping concentration of the N-type current balancing region 22 is 1-5e17cm -3 , the doping concentration of the first P-type well region 3 is 1-5e17cm -3 , the doping concentration of the N-type source region 31 is 2-8e18cm -3 , the material of the insulating dielectric layer 5 may be silicon dioxide; the doping concentration of the first P-type well region 3 is less than the doping concentration of the second P-type well region 41; The doping concentration of the N-type silicon carbide substrate 1 is to ensure the formation of low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the P-type protection zone 21 is to construct a P-type buffer zone directly below the gate of the device, thereby suppressing the impact of the drain voltage on the gate structure; the doping concentration of the first P-type well region 3 is mainly considered in two aspects, one is to achieve the protection of the gate and source structure of the device, to ensure a high doping concentration, and the other is to ensure that the gate charge is small, so that the device has a low concentration when driving the gate charge. Therefore, a compromise is made between the two and the doping concentration is selected; the doping concentration of the N-type current equalizing region 22 is mainly to reduce the on-resistance of the device, while not affecting the protective effect of the P-type protection zone 21 of the device on the device structure; the N-type source region 31 is to reduce the ohmic contact resistance of the source of the device while not damaging the device lattice due to ion implantation due to too high a concentration, affecting the stability of the device; The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the N-type drift layer 2 is 30-100 μm, and is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the N-type source region 31 is 200 nm, the thickness of the first P-type well region 3 is 500 nm, the thickness of the N-type Schottky region 4 is 500 nm, the thickness of the N-type current equalizing region 22 is 300 nm, the thickness of the P-type protection region 21 is 300 nm, the top of the P-type protection region 21 is flush with the bottom of the N-type current equalizing region 22, the thickness of the insulating dielectric layer 5 is 50 nm, and the thickness of the source metal layer 7 is 200 nm; this embodiment In the formula, a P-type protection zone 21 is designed. When the drain of the device is subjected to a large surge voltage, a withstand voltage space charge zone is formed in the N-type drift layer 2 and the P-type protection zone 21, thereby avoiding the impact of the drain surge voltage on the gate structure of the device. An N-type current averaging zone 22 is designed in the device structure. The N-type current averaging zone 22 is horizontally distributed on the left and right sides of the P-type protection zone 21 and vertically distributed above the P-type protection zone 21, so as not to affect the surge voltage resistance of the P-type protection zone 21. At the same time, the current in the JFET zone is redistributed to the left and right sides of the P-type protection zone 21 when the device is turned on, thereby reducing the on-resistance of the device; On the basis of constructing a JBS body diode inside the device, a second P-type well region 41 is constructed on the left and right sides of the device. The bottom of the second P-type well region 41 is in direct contact with the N-type current equalizing region 22, constructing a low-resistance path from the device's parasitic pn junction body diode to the device drain, which can reduce the conduction loss of the device under high current conditions.

[0033] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a protection zone; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a current equalizing area; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a second P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a Schottky region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a first P-type well region and a protruding portion; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form an N-type source region; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The sum of the width of the current balancing area and the width of the protection area is equal to the width of the drift layer, and the width of the protection area is equal to the width of the protrusion.

3. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The upper side surface of the protection zone and the lower side surface of the flow equalization zone are located in the same plane.

4. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The thickness of the protection zone is 300 nm; the thickness of the flow equalization zone is 300 nm.

5. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The silicon carbide substrate, drift layer, current balancing region and Schottky region are all N-type, and the protection region is P-type.

6. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The doping concentration of the protection zone is greater than the doping concentration of the drift layer; the doping concentration of the protection zone is greater than the doping concentration of the current balancing zone.

7. A planar gate silicon carbide VDMOS with surge voltage resistance, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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