Left and right shielding trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a left-right shielding trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type source region, a low-resistance region, a P-type well region and an N-type source region; forming a barrier layer again, etching to form a first groove, and depositing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and a barrier layer is formed again, the barrier layer is etched to form a through hole, the low-resistance region, the P-type source region and the N-type source region are etched, metal is deposited, a second source electrode metal layer is formed, the barrier layer is removed, and preparation is completed.

Description

Technical Field

[0001] The invention relates to a left-right shielded trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different focuses, but the overall requirements include higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), and lower body diode conduction loss.

[0003] For silicon carbide VDMOS devices in the range of 650-900V, it is urgently necessary to provide a technical solution for silicon carbide VDMOS devices in the range of 650-900V to reduce their on-resistance and increase their switching speed. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a left and right shielded trench gate silicon carbide VDMOS and a preparation method thereof, which reduces the on-resistance of the device and simplifies the process difficulty by improving the design of the shielded gate structure.

[0005] In a first aspect, the present invention provides a method for preparing a left and right shielded trench gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type source region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a low resistance area; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to form a first groove, and deposit to form an insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a first trench and a second trench, depositing metal to form a first gate metal layer and a second gate metal layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a third trench, depositing metal, and forming a first source metal layer; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the low resistance area, P-type source area and N-type source area, deposit metal to form a second source metal layer, remove the barrier layer, and complete the preparation.

[0006] In a second aspect, the present invention provides a left and right shielded trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the preparation method of the left and right shielded trench gate silicon carbide VDMOS described in the first aspect.

[0007] The advantages of the present invention are: 1. The present invention designs a first gate metal layer, a first source metal layer and a second gate metal layer, all of which are wrapped by an insulating dielectric layer, wherein the depth of the first source metal layer is 1.5-3 times the depth of the first gate metal layer, thereby ensuring that the first source metal layer distributed between the first gate metal layer and the second gate metal layer can assist in depleting the impurities of the epitaxial layer, thereby reducing the equivalent concentration of the epitaxial region near the left and right sides of the first source metal layer, avoiding the problem of large electric field breakdown caused by high doping concentration in the epitaxial region, and achieving the goal of increasing the doping concentration in the epitaxial region and reducing the on-resistance of the device; Second, the first gate metal layer and the second gate metal layer of the present invention form a gate control structure-P-type source region-N-type low resistance region structure, and through the expansion of the space charge region of the P-type source region, the low-doped P-type well region and the N-type low resistance region of the device are protected when the drain is subjected to a large voltage, thereby improving the drain-source withstand voltage capability of the device; 3. Due to the gate control structure - P-type source region - N-type low resistance region structure, the doping concentration of the P-type well region can be effectively reduced. Therefore, when the device gate controls the device switch, the concentration of the inversion layer is reduced, which can reduce the driving charge and increase the device switching speed; 4. The first source metal layer and the second source metal layer of the present invention are distributed in the middle and the top of the device and can directly contact the source electrode, thus avoiding the problem of the traditional upper and lower shielding gate structure, which leads to the complex structure of the shielding gate source potential lead-out, and reduces the complexity of the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0009] Figure 1 The schematic diagram of the left and right shielded trench gate silicon carbide VDMOS of the present invention is shown.

[0010] Figure 2 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 1 .

[0011] Figure 3 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 2 .

[0012] Figure 4 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 3 .

[0013] Figure 5 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 4 .

[0014] Figure 6 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 5 .

[0015] Figure 7 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 6 .

[0016] Figure 8 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 7 .

[0017] Fig. 9 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 8 .

[0018] Fig.10 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 9 .

[0019] Fig.11 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 10 .

[0020] Fig.12 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 10 one.

[0021] Fig.13 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 10 two.

[0022] Fig.14 The process section of the present invention is a left and right shielded trench gate silicon carbide VDMOS Figure 10 three. DETAILED DESCRIPTION

[0023] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0025] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0026] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0027] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] like Figures 1 to 14 As shown, the embodiment of the present application provides a method for preparing left and right shielded trench gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112; epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102; Step 2, forming a barrier layer 113 on the drift layer 102, etching the barrier layer 113 to form a through hole, and implanting ions to form a P-type source region 104; Step 3, removing the original barrier layer, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and implanting ions to form a low resistance region 103; Step 4, removing the original barrier layer, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and ion implantation to form a P-type well region 105; Step 5, removing the original barrier layer, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and ion implantation to form an N-type source region 106; Step 6: remove the original barrier layer, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and etch the drift layer 102 to form a first groove 1021, and deposit to form an insulating dielectric layer 107; Step 7, remove the original barrier layer, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and etch the insulating dielectric layer 107 to form a first trench 1071 and a second trench 1072, and deposit metal to form a first gate metal layer 108 and a second gate metal layer 109; Step 8, removing the original barrier layer, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and etching the insulating dielectric layer 107 to form a third trench 1073, depositing metal to form a first source metal layer 110; Step 9, remove the original barrier layer, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and etch the low resistance area 103, the P-type source area 104 and the N-type source area 106, deposit metal to form a second source metal layer 111, remove the barrier layer 113, and complete the preparation.

[0029] In this embodiment, preferably, the lower side surface of the insulating dielectric layer 107 is lower than the lower side surface of the P-type source region 105 .

[0030] In this embodiment, preferably, the lower side surface of the first gate metal layer 108 , the lower side surface of the second gate metal layer 109 , and the lower side surface of the P-type well region 105 are located in the same plane.

[0031] In this embodiment, preferably, the depth of the third groove 1073 is greater than the depth of the first groove 1071 .

[0032] In this embodiment, preferably, the thickness of the insulating dielectric layer 107 on the left side of the first gate metal layer 108 is smaller than the thickness of the insulating dielectric layer 107 on the right side of the first gate metal layer 108 .

[0033] In this embodiment, preferably, the thickness of the insulating dielectric layer 107 on the left side of the second gate metal layer 109 is greater than that of the insulating dielectric layer 107 on the right side of the second gate metal layer 109 .

[0034] In this embodiment, preferably, the doping concentration of the P-type source region 104 is greater than the doping concentration of the low resistance region 103 , and the doping concentration of the low resistance region 103 is greater than the doping concentration of the drift layer 102 .

[0035] In this embodiment, preferably, the doping concentration of the P-type source region 104 is greater than the doping concentration of the P-type well region 105 , and the doping concentration of the P-type source region 104 is greater than the doping concentration of the N-type source region 106 .

[0036] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 101; A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, and a first groove 1021 and a second groove 1022 are provided on the drift layer 102; A low resistance region 103, wherein the lower side of the low resistance region 103 is connected to the upper side of the drift layer 102; A P-type source region 104, wherein the lower portion of the P-type source region 104 is disposed in the second groove 1022, and the outer side surface of the P-type source region 104 is connected to the inner side surface of the low resistance region 103; A P-type well region 105 , wherein the lower side of the P-type well region 105 is connected to the upper side of the drift layer 102 , and the outer side of the P-type well region 105 is connected to the inner side of the P-type source region 104 ; An N-type source region 106, wherein the lower side of the N-type source region 106 is connected to the upper side of the P-type well region 105, and the outer side of the N-type source region 106 is connected to the inner side of the P-type source region 104; An insulating dielectric layer 107, wherein the lower portion of the insulating dielectric layer 107 is disposed in the first groove 1021, and the outer side surface of the insulating dielectric layer 107 is connected to the inner side surface of the P-type well region 105 and the inner side surface of the N-type source region 106; a first trench 1071, a second trench 1072 and a third trench 1073 are disposed on the insulating dielectric layer 107; A first gate metal layer 108 , wherein the first gate metal layer 108 is disposed in the first trench 1071 ; A second gate metal layer 109, wherein the second gate metal layer 109 is disposed in the second trench 1072; A first source metal layer 110, wherein the first source metal layer 110 is disposed in the third trench 1073; A second source metal layer 111, wherein the second source metal layer 111 is respectively connected to the low resistance region 103, the P-type source region 104 and the N-type source region 106; and a drain metal layer 112 , wherein the drain metal layer 112 is connected to the lower side of the silicon carbide substrate 101 .

[0037] In another embodiment of the present invention, the silicon carbide substrate 101, the drift layer 102, and the low resistance region 103 are all N-type; the doping concentration of the silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the drift layer 102 is 5-9e17cm -3 , the doping concentration of the low resistance region 103 is 6-10e17cm -3 , the doping concentration of the P-type well region 105 is 1-5e16cm -3 , the doping concentration of the P-type source region 104 is 1-5e19cm -3 The material of the insulating dielectric layer 107 can be silicon dioxide, and the doping concentration of the N-type source region 106 is 2-8e18cm -3; Among them, the doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 112, thereby reducing the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device. Due to the design of the left and right shielded trench gate structure, the N-type drift layer 102 can increase the doping concentration while ensuring the withstand voltage and reduce the on-resistance of the device; the doping concentration of the P-type well region 105 is to achieve the withstand voltage of the device pn junction structure when the device drain is subjected to a high voltage. Reducing the doping concentration can reduce the gate switching charge and reduce the driving loss; P-type The concentration of the source region 104 is to form a space charge region with the N-type drift layer 102 that diffuses toward the N-type drift layer 102, so as to protect the device P-type well 105 and the gate from withstanding a large voltage at the drain. At the same time, the P-type source region 104 also needs to achieve ohmic contact with the second source metal layer 111, so as to supplement the device current capacity when the device parasitic Schottky body diode is insufficient to continue current, thereby improving the device current capacity. The doping concentration of the N-type low resistance region 103 is to form a Schottky contact with the second source metal layer 111, reduce the device body diode conduction voltage drop and ensure reverse withstand voltage. The thickness of the N-type silicon carbide substrate 101 of the device is 500nm, which is to form a low-resistance ohmic contact with the drain metal layer 112 to reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 30-60μm, which is adjusted within the above range according to the requirements for the withstand voltage characteristics of the device, and the withstand voltage range of the device is 650-900V; the thickness of the second source metal layer 111 is 200nm and the width is 3μm; the thickness of the first source metal layer 110 is 1.5-3 times the thickness of the first gate metal layer 108, the thickness of the first source metal layer 110 is 900-1800nm, and the width is 800nm; the thickness of the P-type source region 104 is 600nm and the width is 2μm; the thickness of the N-type source region 106 is 100nm and the width is 500nm; the P-type well region 1 05 has a thickness of 300nm and a width of 500nm; the thickness of the N-type low resistance region 103 is 400nm and the width is 500nm; the thickness of the first gate metal layer 108 and the second gate metal layer are both 600nm, and the thickness of the insulating dielectric layer 107 directly below the first gate metal layer 108 is 150nm; the width of the insulating dielectric layer 107 located on one side of the first gate metal layer 108 and the second gate metal layer 109 and close to the P-type well region 105 is 50nm, and the width of the insulating dielectric layer 107 away from the P-type well region 105 is 100nm, the thickness of the insulating dielectric layer 107 directly below the first source metal layer 110 is 100nm, and the width of the first gate metal layer 108 and the second gate metal layer 109 is 300-500nm; Among them, the tops of the N-type low resistance region 103, the P-type source region 104, and the N-type source region 106 are flush and directly contact the second source metal layer 111, and the lower side of the N-type low resistance region 103, the lower side of the P-type well region 105, the lower side of the first gate metal layer 108, and the lower side of the second gate metal layer 109 are flush.

[0038] In this embodiment, a first gate metal layer 108, a first source metal layer 110 and a second gate metal layer 109 are designed, all of which are wrapped by an insulating dielectric layer 107, wherein the depth of the first source metal layer 110 is 1.5-3 times the depth of the first gate metal layer 108, thereby ensuring that the first source metal layer 110 distributed between the first gate metal layer 108 and the second gate metal layer 109 can assist in depleting the impurities of the epitaxial layer, thereby reducing the equivalent concentration of the epitaxial region near the left and right sides of the first source metal layer 110, avoiding the problem of large electric field breakdown caused by high doping concentration in the epitaxial region, and achieving increased doping concentration in the epitaxial region and reduced device on-resistance; In this embodiment, the first gate metal layer 108 and the second gate metal layer 109 form a gate control structure-P-type source region-N-type low resistance region structure. By expanding the space charge region of the P-type source region 104, the low-doped P-type well region 105 and the N-type low resistance region 103 of the device are protected when the drain is subjected to a large voltage, thereby improving the drain-source voltage resistance of the device; due to the use of the gate control structure-P-type source region-N-type low resistance region structure, the doping concentration of the P-type well region 105 can be effectively reduced, so that when the device gate controls the device switch, the driving charge can be reduced due to the reduction in the inversion layer concentration, thereby improving the device switching speed; the first source metal layer 110 and the second source metal layer 111 are distributed in the middle and top of the device, and can directly contact the source electrode, avoiding the traditional upper and lower shielding gate structure, resulting in the problem of complex shielding gate source potential lead-out structure, thereby reducing the complexity of the preparation process.

[0039] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing left and right shielded trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type source region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a low resistance area; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to form a first groove, and deposit to form an insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a first trench and a second trench, depositing metal to form a first gate metal layer and a second gate metal layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a third trench, depositing metal, and forming a first source metal layer; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the low resistance area, P-type source area and N-type source area, deposit metal to form a second source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side surface of the insulating dielectric layer is lower than the lower side surface of the P-type source region.

3. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side surface of the first gate metal layer, the lower side surface of the second gate metal layer and the lower side surface of the P-type well region are located in the same plane.

4. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The depth of the third trench is greater than the depth of the first trench.

5. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the insulating dielectric layer on the left side of the first gate metal layer is smaller than that of the insulating dielectric layer on the right side of the first gate metal layer.

6. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the insulating dielectric layer on the left side of the second gate metal layer is greater than that of the insulating dielectric layer on the right side of the second gate metal layer.

7. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the low resistance region, and the doping concentration of the low resistance region is greater than the doping concentration of the drift layer.

8. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the P-type well region, and the doping concentration of the P-type source region is greater than the doping concentration of the N-type source region.

9. A left and right shielded trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 8.

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