Preparation method of ultrafast and robust multifunctional floating gate transistor based on charge tunneling potential barrier and atomic-scale sharp interface

By building a charge-selective tunneling barrier and atomic-level sharp interface in a floating gate transistor, the problem of existing floating gate devices being difficult to achieve positive/negative photoconductivity behavior and storage characteristics is solved, and the effects of ultra-large switching ratio, multi-bit storage and nanosecond ultra-fast storage are achieved.

CN119855200APending Publication Date: 2025-04-18BEIJING INST OF TECH
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Patent Information

Application Number
CN202510010987.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-01-03
Publication Date
2025-04-18

AI Technical Summary

Technical Problem

Existing floating gate devices are difficult to achieve positive/negative photoconductivity behavior in the same unit, and the storage characteristics are lost, making it impossible to achieve a large storage window and switch ratio.

Method used

By building a charge-selective tunneling barrier and atomic-level sharp interface in a floating gate transistor, the structure of the MLG floating gate layer, hBN tunneling layer and PtS2 channel is adopted, and combined with mechanical peeling and dry transfer technology, FGFETs with multifunctional characteristics are prepared.

Benefits of technology

It realizes ultra-large switching ratio and storage window, has multi-bit storage capabilities, data retention can exceed 10 years, has strong cycle durability, can realize NPC and PPC characteristics in the same device, and has nanosecond ultra-fast storage characteristics.

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Abstract

The invention belongs to the field of two-dimensional materials and electronic information devices, and particularly relates to a preparation method of an ultrafast and stable multifunctional floating gate transistor based on a charge tunneling barrier and an atomic-scale sharp interface. The FGFET constructed by the method provided by the invention has an ultra-large switch ratio (108) and an ultra-large storage window, and can realize multi-bit storage. The storage characteristic is still realized under small scanning voltage, so that the scanning voltage can be greatly reduced; the device has relatively strong data retention and cycle durability, the data retention at room temperature can exceed 10 years, and the erasable number of times can exceed 10 < 5 >; according to the invention, two-end and three-end storage capability can be realized, the storage function is expanded, the storage characteristic close to 109 switch ratio can still be shown under the condition of two-end storage, and the multi-functional characteristic is realized; according to the invention, NPC and PPC characteristics can be realized in the same device, and good light response is realized; the FGFET constructed by the method disclosed by the invention can realize nanosecond ultrafast storage.
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Citation Information

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