Semiconductor structure and manufacturing method thereof

Abstract

The semiconductor structure provided by the invention comprises a substrate, a nucleating layer, a buffer layer and a heterojunction structure layer which are sequentially stacked, the nucleating layer comprises a first nucleating layer and a second nucleating layer, the first nucleating layer is of a plurality of strip-shaped structures, a strip-shaped groove is formed between every two adjacent strip-shaped structures, the extending direction of the strip-shaped grooves is parallel to the plane where the substrate is located, and the second nucleating layer covers the strip-shaped grooves and the first nucleating layer; the ion permeability of the second nucleating layer is higher than that of the first nucleating layer. The first nucleating layer and the second nucleating layer which are different in ion permeability are designed, and silicon ions in the substrate are diffused into the buffer layer through the second nucleating layer, so that the buffer layer forms the first buffer layer and the second buffer layer which are different in silicon concentration. Different threshold voltages can be formed on the channel layers at different positions along the width direction of the channel due to the change of the doping concentration of the buffer layer and the change of the influence on the concentration of the two-dimensional electron gas, so that the linearity of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Gallium nitride (GaN) materials have the advantages of large bandgap and high breakdown field strength. AlGaN / GaN heterojunction devices prepared based on this have high electron mobility, and can form a high concentration of two-dimensional electron gas (2DEG) at the heterojunction interface through polarization in the case of unintentional doping. Therefore, gallium nitride-based high electron mobility transistor (GaN HEMT) devices have broad application prospects in the field of microwave power. However, GaN HEMT devices face serious nonlinear problems, which seriously restricts the application of GaN HEMT devices in the communication field. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to further improve the linearity of a gallium nitride high electron mobility transistor device.

[0004] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, characterized in that it includes:

[0005] A substrate, a nucleation layer, a buffer layer and a heterojunction structure layer are stacked in sequence;

[0006] The nucleation layer includes a first nucleation layer and a second nucleation layer, the first nucleation layer is a plurality of strip structures, and a strip groove is between two adjacent strip structures, and the extension direction of the strip groove is parallel to the plane where the substrate is located. The second nucleation layer covers the strip groove and covers the first nucleation layer, and the ion permeability of the second nucleation layer is higher than that of the first nucleation layer.

[0007] As an optional embodiment, the thickness of the second nucleation layer is smaller than the thickness of the first nucleation layer.

[0008] As an optional embodiment, the thickness of the second nucleation layer is less than 100 nm.

[0009] As an optional embodiment, the materials of the first nucleation layer and the second nucleation layer include Al a In b Ga 1-a- b N, where 0≤a≤1, 0≤b≤1 and 0≤1-ab≤1.

[0010] As an optional embodiment, the Al component content of the second nucleation layer is less than the Al component content of the first nucleation layer.

[0011] As an optional embodiment, at least two of the plurality of strip-shaped grooves have different widths; or, at least two of the plurality of strip-shaped grooves have different spacing distances.

[0012] As an optional embodiment, the buffer layer includes a first buffer layer and a second buffer layer, the first buffer layer corresponds to the first nucleation layer, the second buffer layer corresponds to the strip-shaped groove, and the n-type ion doping concentration of the second buffer layer is higher than the n-type ion doping concentration of the first buffer layer.

[0013] As an optional embodiment, a surface of the buffer layer away from the substrate is a plane.

[0014] As an optional embodiment, the buffer layer is conformally disposed on the nucleation layer.

[0015] As an optional embodiment, the n-type ion doping concentration of the buffer layer gradually decreases in a direction away from the substrate.

[0016] As an optional embodiment, the material of the substrate includes silicon or silicon carbide.

[0017] As an optional embodiment, the n-type ions in the buffer layer are silicon ions.

[0018] As an optional embodiment, the semiconductor structure further comprises:

[0019] A source electrode and a drain electrode are located on the heterojunction structure layer, and the direction in which the source electrode points to the drain electrode is parallel to the extending direction of the strip-shaped groove;

[0020] A gate electrode, located on the heterojunction structure layer and between the source electrode and the drain electrode;

[0021] The dielectric layer is located on a side of the gate electrode close to the heterojunction structure layer.

[0022] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, characterized in that it includes the following steps:

[0023] S1. providing a substrate;

[0024] S2, growing a first nucleation layer on the substrate, etching a plurality of strip-shaped grooves in the first nucleation layer to form a plurality of strip-shaped structures, wherein the extending direction of the strip-shaped grooves is parallel to the plane where the substrate is located;

[0025] S3, conformally growing a second nucleation layer in the strip-shaped grooves and on the first nucleation layer, wherein the ion permeability of the second nucleation layer is higher than that of the first nucleation layer;

[0026] S4, growing a buffer layer on the nucleation layer including the first nucleation layer and the second nucleation layer;

[0027] S5. Growing a heterojunction structure layer on the buffer layer.

[0028] As an optional embodiment, after growing the buffer layer in step S4, the n-type ions in the substrate below the strip-shaped groove diffuse into the buffer layer to form a second buffer layer corresponding to the strip-shaped groove, the buffer layer above the first nucleation layer is the first buffer layer, and the n-type ion doping concentration of the second buffer layer is higher than the n-type ion doping concentration of the first buffer layer.

[0029] As an optional embodiment, the n-type ions forming the second buffer layer are silicon ions.

[0030] As an optional embodiment, the method for manufacturing the semiconductor structure further comprises:

[0031] S6. Form a dielectric layer, a source electrode, a drain electrode, and a gate electrode on the dielectric layer and between the source electrode and the drain electrode, wherein the direction in which the source electrode points to the drain electrode is parallel to the extension direction of the strip-shaped groove.

[0032] The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a nucleation layer, a buffer layer and a heterojunction structure layer which are stacked in sequence. The nucleation layer includes a first nucleation layer and a second nucleation layer. The first nucleation layer is a plurality of strip structures. A strip groove is formed between two adjacent strip structures. The extension direction of the strip groove is parallel to the plane where the substrate is located. The second nucleation layer covers the strip groove and the first nucleation layer. The ion permeability of the second nucleation layer is higher than that of the first nucleation layer.

[0033] The present disclosure designs a first nucleation layer and a second nucleation layer with different ion permeability. Silicon ions in the substrate diffuse into the buffer layer through the second nucleation layer with higher ion permeability, so that the buffer layer forms a first buffer layer and a second buffer layer arranged alternately along the channel width direction, and the silicon concentration of the second buffer layer is greater than the silicon concentration of the first buffer layer. The silicon-doped buffer layer can release electrons, and the energy level of the half-filled state formed by impurities and defects in the nucleation layer can capture the electrons, thereby reducing the capture of device electrons, enhancing device performance and increasing device reliability; at the same time, the silicon-doped buffer layer can supplement carriers, increase the concentration of two-dimensional electron gas, and reduce the on-resistance of the channel. Along the channel width direction, the doping concentration of the buffer layer changes, and the influence on the concentration of two-dimensional electron gas changes, so different threshold voltages can be formed in the channel layer at different positions, thereby improving the linearity of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0035] Figure 2 Shown Figure 1 Schematic diagram of the structure of the AA' cross section of the semiconductor structure.

[0036] Figure 3 to Figure 4 Shown is a schematic structural diagram of a semiconductor structure provided by some embodiments of the present disclosure.

[0037] Figures 5 to 7 Shown is a schematic structural diagram of a semiconductor structure provided by some embodiments of the present disclosure.

[0038] Figure 8 Shown is a flow chart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure.

[0039] Figure 9-17 The figure shows a schematic diagram of the decomposition of a semiconductor structure provided by an embodiment of the present disclosure during the manufacturing process. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] In order to further improve the linearity of a gallium nitride high electron mobility transistor device, the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate, a nucleation layer, a buffer layer and a heterojunction structure layer stacked in sequence; the nucleation layer comprises a first nucleation layer and a second nucleation layer, wherein the first nucleation layer is a plurality of strip structures, and a strip groove is provided between two adjacent strip structures, and the extension direction of the strip groove is parallel to the plane where the substrate is located, and the second nucleation layer covers the strip groove and the first nucleation layer, and the ion permeability of the second nucleation layer is higher than that of the first nucleation layer. The present disclosure designs a first nucleation layer and a second nucleation layer with different ion permeability, and silicon ions in the substrate diffuse into the buffer layer through the second nucleation layer, so that the buffer layer forms a first buffer layer and a second buffer layer with different silicon concentrations. Along the channel width direction, the doping concentration of the buffer layer changes, and the influence on the concentration of the two-dimensional electron gas changes, so that different threshold voltages can be formed in the channel layer at different positions, thereby improving the linearity of the device.

[0042] Combine the following Figures 1 to 17 A semiconductor structure and a manufacturing method thereof mentioned in the present disclosure are further illustrated by way of example.

[0043] Figure 1 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 2 Shown Figure 1 Schematic diagram of the structure of the semiconductor structure AA' section. Figure 2 As shown, the semiconductor structure includes a substrate 10, a nucleation layer 20, a buffer layer 30 and a heterojunction structure layer 40 which are stacked in sequence; the nucleation layer 20 includes a first nucleation layer 21 and a second nucleation layer 22, the first nucleation layer 21 is a plurality of strip structures, and a strip groove 201 is between two adjacent strip structures, and the extension direction of the strip groove 201 is parallel to the plane where the substrate 10 is located, and the second nucleation layer 22 covers the strip groove 201 and the first nucleation layer 21, and the ion permeability of the second nucleation layer 22 is higher than the ion permeability of the first nucleation layer 21. The buffer layer 30 includes a first buffer layer 31 and a second buffer layer 32, the first buffer layer 31 corresponds to the first nucleation layer 21, and the second buffer layer 32 corresponds to the strip groove 201, and the n-type ion doping concentration of the second buffer layer 32 is higher than the n-type ion doping concentration of the first buffer layer 31. Figure 1 As shown, the semiconductor structure further includes: a source 51 and a drain 52, which are located on the heterojunction structure layer 40, and the direction in which the source 51 points to the drain 52 is parallel to the extension direction of the strip groove 201; a gate 53, which is located on the heterojunction structure layer 40 and between the source 51 and the drain 52; and a dielectric layer 54, which is located on the side of the gate 53 close to the heterojunction structure layer 40.

[0044] In this embodiment, the material of the substrate 10 includes silicon or silicon carbide. The substrate 10 contains silicon ions. Since the ion permeability of the second nucleation layer 22 is higher than that of the first nucleation layer 21, the silicon ions in the substrate 10 can pass through the second nucleation layer 22 and diffuse into the buffer layer 30. The n-type ions in the buffer layer 30 are silicon ions. The silicon-doped buffer layer 30 can release electrons. The energy level of the half-filled state formed by impurities and defects in the nucleation layer 20 can capture the electrons, thereby reducing the capture of device electrons, enhancing device performance and increasing device reliability; at the same time, the silicon-doped buffer layer 30 can supplement carriers, increase the concentration of two-dimensional electron gas, and reduce the channel on-resistance. Since the n-type ions in the buffer layer 30 diffuse from the substrate 10, the n-type ion doping concentration of the buffer layer 30 gradually decreases in the direction away from the substrate 10. The n-type ion doping concentration of the buffer layer 30 is negatively correlated with the thickness of the buffer layer 30, which avoids the high resistance of the buffer layer 30 affected by doping and reduces the possibility of leakage.

[0045] In this embodiment, the ion permeability of the second nucleation layer 22 is higher than that of the first nucleation layer 21. In one embodiment, the materials of the first nucleation layer 21 and the second nucleation layer 22 include Al a In b Ga1-a-b N, where 0≤a≤1, 0≤b≤1 and 0≤1-ab≤1. The Al component content of the second nucleation layer 22 is less than the Al component content of the first nucleation layer 21. The smaller the Al component content, the greater the In component content or the Ga component content, the larger the lattice constant of the material of the second nucleation layer 22, and the larger the lattice gap, then the silicon ions in the substrate 10 can enter the buffer layer 30 through the second nucleation layer 22, while the first nucleation layer 21 prevents the silicon ions in the substrate 10 from penetrating into the buffer layer 30. In another embodiment, the thickness of the second nucleation layer 22 is less than the thickness of the first nucleation layer 21, so as to achieve a higher ion permeability of the second nucleation layer 22 than the ion permeability of the first nucleation layer 21. The thickness of the second nucleation layer 22 is less than 100nm, which further facilitates the silicon ions in the substrate 10 to enter the buffer layer 30 through the second nucleation layer 22. The first nucleation layer 21 and the second nucleation layer 22 are designed to have different ion permeability, and the silicon ions in the substrate 10 diffuse into the buffer layer 30 through the second nucleation layer 22, so that the buffer layer 30 forms the first buffer layer 31 and the second buffer layer 32 arranged alternately along the channel width direction, and the silicon concentration of the second buffer layer 32 is greater than the silicon concentration of the first buffer layer 31. Along the channel width direction, the doping concentration of the buffer layer 30 changes, and the influence on the concentration of the two-dimensional electron gas changes, so different threshold voltages can be formed in the channel layer at different positions, thereby improving the linearity of the device.

[0046] Figure 3 to Figure 4 FIG. 2 is a schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure. In one embodiment, at least two of the plurality of strip-shaped grooves 201 have different widths (a1, a2) (e.g. Figure 3 or, at least two of the plurality of strip-shaped grooves 201 have different spacing distances (b1, b2) (such as Figure 4 The width or spacing distance of the strip grooves 201 changes, that is, the width or spacing distance of the second buffer layer 32 corresponding to the strip grooves 201 changes. By changing the width or spacing distance of the strip grooves 201, the transconductance peak value of the heterojunction structure layer 40 at different positions of the subsequent growth can be changed, and the threshold voltage of the heterojunction structure layer 40 at different positions can be changed, thereby improving the linear working characteristics of the device.

[0047] Figures 5 to 7 FIG. 1 is a schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure. In one embodiment, the surface of the buffer layer 30 away from the substrate 10 is a plane (eg Figure 2 In another embodiment, the buffer layer 30 is conformally disposed on the nucleation layer 20 (as shown in FIG. Figure 5), the heterojunction structure layer 40 includes a channel layer 41 and a barrier layer 42. The channel layer 41 grows from the groove of the buffer layer 30 by lateral epitaxy technology, which can greatly reduce the dislocation density in the heterojunction structure layer 40 and improve the crystal quality of the heterojunction structure layer 40, thereby improving the device's electron mobility, breakdown voltage, leakage current and other characteristics. In another embodiment, the buffer layer 30 is conformally disposed on the nucleation layer 20, and the channel layer 41 is further conformally disposed on the buffer layer 30 (as shown in FIG. Figure 6 As shown in FIG. 4 ), the two-dimensional electron gas generated at the heterojunction interface between the channel layer 41 and the barrier layer 42 is not in the same horizontal plane, forming a lateral multi-channel structure, which is conducive to realizing mutual compensation of different transconductances of the device, achieving relative stability of transconductance within a larger gate-source bias range, and is conducive to improving the breakdown voltage, improving dynamic characteristics, and further improving the linearity of the device. In other embodiments, the barrier layer 42 is further conformally disposed on the channel layer 41 (as shown in FIG. Figure 7 As shown in the figure, the two-dimensional electron gas generated at the heterojunction interface between the channel layer 41 and the barrier layer 42 is not in the same horizontal plane and the gate 53 fills the groove in the barrier layer 42. In addition to further forming the effect of a lateral multi-channel structure, the gate 53 greatly improves the control ability of the carriers, thereby greatly improving the breakdown voltage of the device and reducing the leakage problem, and improving the efficiency and linearity of the device.

[0048] According to another aspect of the present disclosure, Figure 8 FIG. 1 is a flow chart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure. Figure 9-17 FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure during the manufacturing process. Figure 8 As shown, a semiconductor structure manufacturing method provided by an embodiment of the present disclosure includes the following steps:

[0049] like Fig. 9 As shown, step S1: providing a substrate. The material of the substrate 10 includes silicon or silicon carbide. The substrate 10 contains silicon ions.

[0050] Step S2: growing a first nucleation layer on the substrate, etching a plurality of strip-shaped grooves in the first nucleation layer to form a plurality of strip-shaped structures, wherein the extension direction of the strip-shaped grooves is parallel to the plane where the substrate is located.

[0051] Specifically, Fig.10 As shown, a first nucleation layer 21 is grown on the substrate 10. Fig.11 As shown, a plurality of strip-shaped grooves 201 are etched in the first nucleation layer 21 to form a plurality of strip-shaped structures, and the extending direction of the strip-shaped grooves 201 is parallel to the plane where the substrate 10 is located.

[0052] Step S3: conformally growing a second nucleation layer in the strip-shaped grooves and on the first nucleation layer, wherein the ion permeability of the second nucleation layer is higher than that of the first nucleation layer.

[0053] Specifically, Fig.12 As shown, the second nucleation layer 22 is conformally grown in the strip groove 201 and on the first nucleation layer 21 , and the ion permeability of the second nucleation layer 22 is higher than that of the first nucleation layer 21 , so that silicon ions in the substrate 10 can pass through the second nucleation layer 22 and diffuse into the buffer layer 30 .

[0054] Step S4: growing a buffer layer on the nucleation layer including the first nucleation layer and the second nucleation layer.

[0055] Specifically, Fig.13 As shown, a buffer layer 30 is grown on the nucleation layer 20 including the first nucleation layer 21 and the second nucleation layer 22. After the buffer layer 30 is grown, the n-type ions in the substrate 10 below the strip groove 201 diffuse into the buffer layer 30 to form a second buffer layer 32 corresponding to the strip groove 201. The buffer layer 30 above the first nucleation layer 21 is the first buffer layer 31. The n-type ion doping concentration of the second buffer layer 32 is higher than the n-type ion doping concentration of the first buffer layer 31, and the n-type ions forming the second buffer layer 32 are the silicon ions in the substrate 10.

[0056] Step S5: growing a heterojunction structure layer on the buffer layer.

[0057] Specifically, Fig.14 As shown, a heterojunction structure layer 40 is grown on the buffer layer 30 .

[0058] In one embodiment, the surface of the buffer layer 30 and the heterojunction structure layer 40 away from the substrate 10 may be a plane. Fig.14 As shown; the buffer layer 30 can be conformally disposed on the nucleation layer 20, having a groove, the heterojunction structure layer 40 includes a channel layer 41 and a barrier layer 42, the channel layer 41 is grown from the groove of the buffer layer 30 by lateral epitaxial technology, as shown Fig.15 As shown; the buffer layer 30 can be conformally disposed on the nucleation layer 20, having a groove, the channel layer 41 is conformally disposed on the buffer layer 30, and the barrier layer 42 is grown from the groove of the channel layer 41 by lateral epitaxial technology, as shown Fig.16 As shown; the barrier layer 42 can also be conformally disposed on the channel layer 41, such as Fig.17 shown.

[0059] Step S6: forming a dielectric layer, a source electrode, a drain electrode, and a gate electrode on the dielectric layer and between the source electrode and the drain electrode, wherein the direction from the source electrode to the drain electrode is parallel to the extension direction of the strip groove.

[0060] Specifically, a dielectric layer 54, a source electrode 51, a drain electrode 52, and a gate electrode 53 located on the dielectric layer 54 and between the source electrode 51 and the drain electrode 52 are formed on the heterojunction structure layer 40. The direction in which the source electrode 51 points to the drain electrode 52 is parallel to the extension direction of the strip groove 201. Figure 1 The semiconductor structure shown. The material of the dielectric layer 54 includes at least one of aluminum oxide, aluminum nitride and aluminum oxynitride. The material of the dielectric layer 54 has a strong charge binding ability. In the formed external electric field, the charge is not easily polarized, the polarized charge is small, and the polarized electric field is weak, which effectively avoids the short channel effect of the semiconductor structure. The dielectric layer 54 is provided to form a MIS gate structure, which can effectively reduce the gate leakage current, increase the gate voltage swing and the drain current swing, and further improve the device performance.

[0061] The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate, a nucleation layer, a buffer layer and a heterojunction structure layer which are stacked in sequence; the nucleation layer comprises a first nucleation layer and a second nucleation layer, wherein the first nucleation layer is a plurality of strip structures, and a strip groove is provided between two adjacent strip structures, and the extension direction of the strip groove is parallel to the plane where the substrate is located, and the second nucleation layer covers the strip groove and the first nucleation layer, and the ion permeability of the second nucleation layer is higher than that of the first nucleation layer. The present disclosure designs a first nucleation layer and a second nucleation layer with different ion permeability, and silicon ions in the substrate diffuse into the buffer layer through the second nucleation layer, so that the buffer layer forms a first buffer layer and a second buffer layer with different silicon concentrations. Along the channel width direction, the doping concentration of the buffer layer changes, and the influence on the concentration of the two-dimensional electron gas changes, so that different threshold voltages can be formed in the channel layer at different positions, thereby improving the linearity of the device.

[0062] It should be understood that the term "including" and its variations used in the present disclosure are open inclusions, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0063] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A substrate (10), a nucleation layer (20), a buffer layer (30), and a heterojunction structure layer (40) are stacked in sequence; The nucleation layer (20) comprises a first nucleation layer (21) and a second nucleation layer (22); the first nucleation layer (21) is a plurality of strip structures; a strip groove (201) is provided between two adjacent strip structures; the extension direction of the strip groove (201) is parallel to the plane where the substrate (10) is located; the second nucleation layer (22) covers the strip groove (201) and covers the first nucleation layer (21); and the ion permeability of the second nucleation layer (22) is higher than that of the first nucleation layer (21).

2. The semiconductor structure according to claim 1, characterized in that: The thickness of the second nucleation layer (22) is smaller than the thickness of the first nucleation layer (21).

3. The semiconductor structure according to claim 1, characterized in that: The thickness of the second nucleation layer (22) is less than 100 nm.

4. The semiconductor structure according to claim 1, characterized in that: The materials of the first nucleation layer (21) and the second nucleation layer (22) include Al a In b Ga 1-a-b N, where 0≤a≤1, 0≤b≤1 and 0≤1-ab≤1.

5. The semiconductor structure according to claim 4, characterized in that: The Al component content of the second nucleation layer (22) is less than the Al component content of the first nucleation layer (21).

6. The semiconductor structure according to claim 1, characterized in that: At least two of the plurality of strip-shaped grooves (201) have different widths; or at least two of the plurality of strip-shaped grooves (201) have different spacing distances.

7. The semiconductor structure according to claim 1, characterized in that: The buffer layer (30) comprises a first buffer layer (31) and a second buffer layer (32), the first buffer layer (31) corresponds to the first nucleation layer (21), the second buffer layer (32) corresponds to the strip-shaped groove (201), and the n-type ion doping concentration of the second buffer layer (32) is higher than the n-type ion doping concentration of the first buffer layer (31).

8. The semiconductor structure according to claim 7, characterized in that: The surface of the buffer layer (30) that is away from the substrate (10) is a plane.

9. The semiconductor structure according to claim 7, characterized in that: The buffer layer (30) is conformally disposed on the nucleation layer (20).

10. The semiconductor structure according to claim 7, characterized in that: The n-type ion doping concentration of the buffer layer (30) gradually decreases in a direction away from the substrate (10).

11. The semiconductor structure according to claim 1, characterized in that: The material of the substrate (10) includes silicon or silicon carbide.

12. The semiconductor structure according to claim 11, characterized in that: The n-type ions in the buffer layer (30) are silicon ions.

13. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A source electrode (51) and a drain electrode (52) are located on the heterojunction structure layer (40), and the direction in which the source electrode (51) points to the drain electrode (52) is parallel to the extension direction of the strip-shaped groove (201); A gate (53) located on the heterojunction structure layer (40) and between the source (51) and the drain (52); The dielectric layer (54) is located on a side of the gate (53) close to the heterojunction structure layer (40).

14. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: S1. providing a substrate (10); S2, growing a first nucleation layer (21) on the substrate (10), etching a plurality of strip-shaped grooves (201) in the first nucleation layer (21) to form a plurality of strip-shaped structures, wherein the extension direction of the strip-shaped grooves (201) is parallel to the plane where the substrate (10) is located; S3, conformally growing a second nucleation layer (22) in the strip-shaped groove (201) and on the first nucleation layer (21), wherein the ion permeability of the second nucleation layer (22) is higher than the ion permeability of the first nucleation layer (21); S4, growing a buffer layer (30) on the nucleation layer (20) including the first nucleation layer (21) and the second nucleation layer (22); S5. Growing a heterojunction structure layer (40) on the buffer layer (30).

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: After the buffer layer (30) is grown in step S4, the n-type ions in the substrate (10) below the strip-shaped groove (201) diffuse into the buffer layer (30) to form a second buffer layer (32) corresponding to the strip-shaped groove (201); the buffer layer (30) above the first nucleation layer (21) is the first buffer layer (31); and the n-type ion doping concentration of the second buffer layer (32) is higher than the n-type ion doping concentration of the first buffer layer (31).

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The n-type ions forming the second buffer layer (32) are silicon ions.

17. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: The method for manufacturing the semiconductor structure further comprises: S6. Forming a dielectric layer (54), a source electrode (51), a drain electrode (52), and a gate electrode (53) located on the dielectric layer (54) and between the source electrode (51) and the drain electrode (52), wherein the direction in which the source electrode (51) points to the drain electrode (52) is parallel to the extension direction of the strip-shaped groove (201).

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