Semiconductor structure and manufacturing method thereof
By forming spaced ion implantation regions in the buffer layer and injecting impurity ions, the carrier concentration of the two-dimensional electron gas is modulated, and the nonlinearity problem of gallium nitride-based devices is solved, and the linearity and transconductance flatness of the device are improved.
Patent Information
- Application Number
- CN202311330998.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-13
- Publication Date
- 2025-04-18
AI Technical Summary
GaN-based devices face serious nonlinear problems, limiting their application in the field of communications.
By forming a plurality of ion implantation regions arranged parallel to the plane where the buffer layer is located, impurity ions are injected to increase or decrease the local carrier concentration, the two-dimensional electron gas in the heterojunction structure layer is spatially charged modulated.
Different threshold voltages are formed at different locations, so that the device is gradually opened along the channel width direction, slowing down the transconductance curve when the drain current is large, thereby improving the transconductance flatness and linearity of the device.
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Figure CN119855202A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art
[0002] Gallium nitride (GaN) materials have the advantages of large bandgap and high breakdown field strength. AlGaN / GaN heterojunction devices prepared based on this have high electron mobility, and can form a high concentration of two-dimensional electron gas (2DEG) at the heterojunction interface through polarization in the case of unintentional doping. Therefore, gallium nitride-based devices with heterojunctions (such as HEMT and JBS) have broad application prospects in the field of microwave power. However, GaN-based devices face serious nonlinear problems, which seriously restricts the application of GaN-based devices in the communication field. Summary of the invention
[0003] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same to improve the linearity of gallium nitride-based devices.
[0004] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, characterized in that it includes:
[0005] substrate;
[0006] A buffer layer and a heterojunction structure layer are sequentially arranged on the substrate;
[0007] The buffer layer includes a plurality of ion implantation regions arranged at intervals along a plane parallel to the plane where the buffer layer is located, and the ion implantation regions include impurity ions.
[0008] As an optional embodiment, the impurity ions include any one of silicon or germanium or a combination thereof.
[0009] As an optional embodiment, the impurity ions include any one of magnesium or beryllium or a combination thereof.
[0010] As an optional embodiment, the impurity ions include any one of helium, argon, oxygen, aluminum, arsenic, nitrogen or phosphorus, or a combination thereof.
[0011] As an optional embodiment, the semiconductor structure further comprises:
[0012] A source electrode, a drain electrode and a gate electrode are arranged on the heterojunction structure layer, wherein the source electrode and the drain electrode are located at two ends of the heterojunction structure layer, and the gate electrode is located between the source electrode and the drain electrode.
[0013] As an optional embodiment, the ion implantation region is a long strip of nanowires, and the extension direction of the ion implantation region is parallel to the direction from the source electrode to the drain electrode.
[0014] As an optional embodiment, the semiconductor structure further comprises:
[0015] An anode and a cathode are arranged on the heterojunction structure layer, wherein the anode and the cathode are located at two ends of the heterojunction structure layer, and an extending direction of the ion implantation region is parallel to a direction from the anode to the cathode.
[0016] As an optional embodiment, at least two of the plurality of ion implantation regions have different widths; or at least two of the plurality of ion implantation regions have different spacing distances.
[0017] As an optional embodiment, the thickness of the ion implantation region is less than or equal to the thickness of the buffer layer.
[0018] As an optional embodiment, the impurity ion concentration of the ion implantation region gradually decreases in a direction away from the substrate.
[0019] As an optional embodiment, at least one of the ion implantation regions has impurity ions different from those of the other ion implantation regions.
[0020] As an optional embodiment, along a direction perpendicular to the plane where the substrate is located, a cross-sectional shape of the ion implantation region includes any one of a rectangular shape, a triangular shape, a trapezoidal shape and a teardrop shape.
[0021] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, characterized in that it includes the following steps:
[0022] S1. providing a substrate;
[0023] S2, forming a buffer layer on the substrate;
[0024] S3, forming a plurality of ion implantation regions arranged at intervals in the buffer layer by ion implantation along a plane parallel to the plane where the buffer layer is located, wherein the ion implantation regions include impurity ions;
[0025] S4. Forming a heterojunction structure layer on the buffer layer.
[0026] As an optional embodiment, the method for manufacturing the semiconductor structure further comprises:
[0027] S5. Forming a source electrode, a drain electrode and a gate electrode on the heterojunction structure layer, wherein the source electrode and the drain electrode are located at two ends of the heterojunction structure layer, and the gate electrode is located between the source electrode and the drain electrode.
[0028] As an optional embodiment, the extension direction of the ion implantation region is controlled in a direction from the source to the drain through ion implantation.
[0029] As an optional embodiment, the method for manufacturing the semiconductor structure further comprises:
[0030] S6. Forming an anode and a cathode on the heterojunction structure layer, wherein the anode and the cathode are located at two ends of the heterojunction structure layer, and an extending direction of the ion implantation region is parallel to a direction from the anode to the cathode.
[0031] As an optional embodiment, the impurity ions include at least one of silicon, germanium, magnesium, beryllium, helium, argon, oxygen, aluminum, arsenic, nitrogen and phosphorus.
[0032] As an optional embodiment, different impurity ions are implanted into at least one of the ion implantation regions than those implanted into the other ion implantation regions.
[0033] The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate; a buffer layer and a heterojunction structure layer sequentially arranged on the substrate; wherein the buffer layer includes a plurality of ion implantation regions spaced apart and parallel to a plane where the buffer layer is located, and the ion implantation regions include impurity ions. The impurity ions implanted into the buffer layer intervals of the present disclosure can increase or decrease the local carrier concentration, perform spatial charge modulation on the two-dimensional electron gas in the heterojunction structure layer, thereby forming different threshold voltages in the heterojunction structure layer at different positions, so that the device is gradually turned on along the channel width direction, and the decline of the transconductance curve at a larger drain current can be slowed down, thereby improving the device transconductance flatness, and further improving the linearity of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
[0035] Figure 2 Shown Figure 1 Schematic top view of the semiconductor structure in .
[0036] Figure 3 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
[0037] Figure 4 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
[0038] Figure 5a to Figure 5d Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
[0039] Figure 6 to Figure 7 Shown is a schematic structural diagram of a semiconductor structure provided by some embodiments of the present disclosure.
[0040] Figure 8Shown is a flow chart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure.
[0041] Figure 9-12 The figure shows a schematic diagram of the decomposition of a semiconductor structure provided by an embodiment of the present disclosure during the preparation process. DETAILED DESCRIPTION
[0042] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0043] In order to improve the linearity of gallium nitride high electron mobility transistor devices, the present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate; a buffer layer and a heterojunction structure layer sequentially arranged on the substrate; wherein the buffer layer includes a plurality of ion implantation regions arranged at intervals parallel to the plane where the buffer layer is located, and the ion implantation regions include impurity ions. The impurity ions injected into the buffer layer intervals of the present disclosure can increase or decrease the local carrier concentration, perform spatial charge modulation on the two-dimensional electron gas in the heterojunction structure layer, thereby forming different threshold voltages in the heterojunction structure layer at different positions, so that the device is gradually turned on along the channel width direction, which can slow down the decline of the transconductance curve when the drain current is large, thereby improving the transconductance flatness of the device, and further improving the linearity of the device.
[0044] Combine the following Figures 1 to 12 A semiconductor structure and a manufacturing method thereof mentioned in the present disclosure are further illustrated by way of example.
[0045] Figure 1 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 2 Shown Figure 1 Schematic top view of the semiconductor structure in . Figure 3 FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 As shown, the semiconductor structure includes: a substrate 10; a buffer layer 20 and a heterojunction structure layer 30 sequentially arranged on the substrate 10; wherein the buffer layer 20 includes a plurality of ion implantation regions 21 (such as Figure 2 As shown in FIG. 1 , the ion implantation region 21 includes impurity ions. The buffer layer 20 further includes a non-ion implantation region 22 that surrounds the ion implantation region 21. In one embodiment, as shown in FIG. Figure 1As shown, the semiconductor structure is a HEMT structure, further comprising: a source 41, a drain 42 and a gate 43 arranged on the heterojunction structure layer 30, the source 41 and the drain 42 are located at both ends of the heterojunction structure layer 30, and the gate 43 is located between the source 41 and the drain 42. Figure 2 As shown, the ion implantation region 21 is a long strip of nanowires, and the extension direction of the ion implantation region 21 is parallel to the direction from the source 41 to the drain 42. In another embodiment, as Figure 3 As shown, the semiconductor structure is a JBS structure, further comprising: an anode 51 and a cathode 52 arranged on the heterojunction structure layer 30, the anode 51 and the cathode 52 are located at both ends of the heterojunction structure layer 30, and the extension direction of the ion implantation region 21 is parallel to the direction from the anode 51 to the cathode 52.
[0046] In this embodiment, the material of the buffer layer 20 is a group III nitride material, and the impurity ions in the ion implantation area 21 include at least one of silicon, germanium, magnesium, beryllium, helium, argon, oxygen, aluminum, arsenic, nitrogen and phosphorus. The impurity ions in the ion implantation area 21 can be any one of silicon or germanium or a combination thereof, so as to increase the local carrier concentration of the buffer layer 20, thereby increasing the local two-dimensional electron gas concentration in the heterojunction structure layer 30; the impurity ions in the ion implantation area 21 can also be any one of magnesium or beryllium or a combination thereof, and the p-type ions are implanted in the buffer layer 20 to compensate for the doping and reduce the local carrier concentration of the buffer layer 20; the impurity ions in the ion implantation area 21 can also be any one of helium, argon, oxygen, aluminum, arsenic, nitrogen or phosphorus or a combination thereof, and the implanted ions can damage the lattice of the buffer layer 20, so that the lattice of the buffer layer 20 material is distorted, and the periodicity of the lattice potential field is destroyed, thereby increasing the probability of electron scattering, reducing the local carrier concentration of the buffer layer 20, and increasing the resistivity of the buffer layer 20. The impurity ions injected at intervals in the buffer layer 20 increase or decrease the local carrier concentration, and perform spatial charge modulation on the two-dimensional electron gas in the heterojunction structure layer 30, thereby forming different threshold voltages at different positions of the heterojunction structure layer 30, so that the device is gradually turned on along the channel width direction, which can slow down the decline of the transconductance curve when the drain current is large, thereby improving the transconductance flatness of the device and further improving the linearity of the device.
[0047] In one embodiment, the impurity ion concentration of the ion implantation region 21 gradually decreases in a direction away from the substrate 10. The impurity ion doping concentration of the buffer layer 20 is negatively correlated with the thickness of the buffer layer 20, thereby avoiding the doping from affecting the high resistance performance of the side of the buffer layer 20 close to the heterojunction structure layer 30 and reducing the possibility of leakage.
[0048] In one embodiment, the buffer layer 20 includes a plurality of ion implantation regions 21, and at least one ion implantation region 21 has impurity ions different from those of the other ion implantation regions 21. Multiple ion implantation regions 21 are formed in the buffer layer 20, and the impurity ions of the multiple ion implantation regions 21 are different, which further changes the carrier concentration difference of the buffer layer 20, thereby improving the linearity of the semiconductor structure.
[0049] In one embodiment, Figure 4 FIG. 2 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. The thickness of the ion implantation region 21 is less than or equal to the thickness of the buffer layer 20. Optionally, when the thickness of the ion implantation region 21 is less than the thickness of the buffer layer 20, the buffer layer 20 may surround the upper and lower surfaces and side walls of the ion implantation region 21, the buffer layer 20 may also surround the upper surface and side walls of the ion implantation region 21, and the buffer layer 20 may also surround the lower surface and side walls of the ion implantation region 21. In the case where the buffer layer 20 surrounds the upper surface of the ion implantation region (such as Figure 4 As shown), the growth surface of the buffer layer 20 used for subsequent epitaxy is the non-ion implantation area 22, and the buffer layer 20 has an epitaxial surface with good lattice quality. While changing the carrier concentration of the buffer layer 20, no defects are introduced on the surface of the buffer layer 20, which is beneficial to the subsequent epitaxial growth of an epitaxial layer with good quality, thereby improving device performance.
[0050] In one embodiment, Figure 5a to Figure 5d FIG. 2 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. In a direction perpendicular to the plane where the substrate 10 is located, the cross-sectional shape of the ion implantation region 21 includes a rectangular shape (eg Figure 5a As shown), triangle (as Figure 5b As shown), trapezoidal (as Figure 5c as shown) and teardrop-shaped (as Figure 5d The present disclosure does not impose any specific limitation on the cross-sectional shape of the ion implantation region 21.
[0051] Figure 6 to Figure 7 FIG. 1 is a schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure. In one embodiment, at least two of the plurality of ion implantation regions 21 have different widths (a 1 、a 2 )(like Figure 6 or, at least two of the plurality of ion implantation regions 21 have different spacing distances (b 1 , b 2 )(like Figure 7 By changing the width or spacing of the ion implantation region 21, the transconductance peak value of the heterojunction structure layer 30 at different positions of the subsequent growth can be changed, the threshold voltage of the heterojunction structure layer 30 at different positions can be changed, and the linear working characteristics of the device can be improved.
[0052] According to another aspect of the present disclosure, Figure 8 FIG. 1 is a flow chart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure. Figure 9-12 FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure during the preparation process. Figure 8 As shown, a semiconductor structure manufacturing method provided by an embodiment of the present disclosure includes the following steps:
[0053] Step S1: Fig. 9 As shown, a substrate 10 is provided. The material of the substrate 10 includes Si, Al 2 O 3 , GaN, SiC or AlN, or a combination of any one or more thereof.
[0054] Step S2: Fig.10 As shown, a buffer layer 20 is formed on a substrate 10. The material of the buffer layer 20 is a group III nitride material, which may include one or more of GaN, AlGaN, and AlInGaN, but is not limited thereto.
[0055] Step S3: Fig.11 As shown, a plurality of ion implantation regions 21 arranged at intervals are formed in the buffer layer 20 by ion implantation along a plane parallel to the buffer layer 20 , the ion implantation regions 21 include impurity ions, and the buffer layer 20 that has not been ion implanted forms a non-ion implantation region 22 that wraps the ion implantation region 21 , and the surface of the buffer layer 20 away from the substrate 10 may be the non-ion implantation region 22.
[0056] In this embodiment, the impurity ions injected into the buffer layer 20 include at least one of silicon, germanium, magnesium, beryllium, helium, argon, oxygen, aluminum, arsenic, nitrogen and phosphorus. The impurity ions in the ion implantation area 21 can be any one of silicon or germanium or a combination thereof, so as to increase the local carrier concentration of the buffer layer 20, thereby increasing the local two-dimensional electron gas concentration in the heterojunction structure layer 30; the impurity ions in the ion implantation area 21 can also be any one of magnesium or beryllium or a combination thereof, and the p-type ions injected into the buffer layer 20 can compensate for the doping and reduce the local carrier concentration of the buffer layer 20; the impurity ions in the ion implantation area 21 can also be any one of helium, argon, oxygen, aluminum, arsenic, nitrogen or phosphorus or a combination thereof, and the injected ions can damage the lattice of the buffer layer 20, so that the lattice of the buffer layer 20 material is distorted, and the periodicity of the lattice potential field is destroyed, thereby increasing the probability of electron scattering, reducing the local carrier concentration of the buffer layer 20, and increasing the resistivity of the buffer layer 20. The impurity ions injected at intervals in the buffer layer 20 increase or decrease the local carrier concentration, and perform spatial charge modulation on the two-dimensional electron gas in the heterojunction structure layer 30, thereby forming different threshold voltages in the heterojunction structure layer 30 at different positions, so that the device is gradually turned on along the channel width direction, which can slow down the decline of the transconductance curve when the drain current is large, thereby improving the device transconductance flatness, and further improving the linearity of the device. Multiple ion implantation regions 21 can be formed in the buffer layer 20 by ion implantation, and at least one ion implantation region 21 has impurity ions different from those of the other ion implantation regions 21. The extension direction of the ion implantation region 21 can be controlled by ion implantation to be parallel to the direction of the subsequently set source 41 pointing to the drain 42 (such as Figure 2 shown).
[0057] Step S4: Fig.12 As shown, a heterojunction structure layer 30 is formed on the buffer layer 20. The heterojunction structure layer 30 includes a channel layer 31 and a barrier layer 32. A two-dimensional electron gas can be formed at the interface between the channel layer 31 and the barrier layer 32. In an optional solution, the channel layer 31 is a GaN layer, and the barrier layer 32 is an AlGaN layer. In other optional solutions, the material combination of the channel layer 31 and the barrier layer can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN or InN / InAlN.
[0058] In one embodiment, the method for manufacturing a semiconductor structure includes step S5: Figure 1 As shown, a source 41, a drain 42 and a gate 43 are formed on the heterojunction structure layer 30, the source 41 and the drain 42 are located at two ends of the heterojunction structure layer 30, and the gate 43 is located between the source 41 and the drain 42, forming a HEMT structure. In another embodiment, the method for manufacturing a semiconductor structure includes step S6: Figure 3As shown, an anode 51 and a cathode 52 are formed on the heterojunction structure layer 30. The anode 51 and the cathode 52 are located at two ends of the heterojunction structure layer 30. The extension direction of the ion implantation region 21 is parallel to the direction from the anode 51 to the cathode 52, forming a JBS structure.
[0059] The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate; a buffer layer and a heterojunction structure layer sequentially arranged on the substrate; wherein the buffer layer includes a plurality of ion implantation regions spaced apart and parallel to a plane where the buffer layer is located, and the ion implantation regions include impurity ions. The impurity ions implanted into the buffer layer intervals of the present disclosure can increase or decrease the local carrier concentration, perform spatial charge modulation on the two-dimensional electron gas in the heterojunction structure layer, thereby forming different threshold voltages in the heterojunction structure layer at different positions, so that the device is gradually turned on along the channel width direction, and the decline of the transconductance curve at a larger drain current can be slowed down, thereby improving the device transconductance flatness, and further improving the linearity of the device.
[0060] It should be understood that the term "including" and its variations used in the present disclosure are open inclusions, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.
[0061] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A semiconductor structure, characterized in that: include: A substrate (10); A buffer layer (20) and a heterojunction structure layer (30) are sequentially arranged on the substrate (10); The buffer layer (20) comprises a plurality of ion implantation regions (21) arranged at intervals along a plane parallel to the plane where the buffer layer (20) is located, and the ion implantation regions (21) comprise impurity ions.
2. The semiconductor structure according to claim 1, characterized in that: The impurity ions include any one of silicon and germanium or a combination thereof.
3. The semiconductor structure according to claim 1, characterized in that: The impurity ions include any one of magnesium and beryllium or a combination thereof.
4. The semiconductor structure according to claim 1, characterized in that: The impurity ions include any one of helium, argon, oxygen, aluminum, arsenic, nitrogen or phosphorus, or a combination thereof.
5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A source electrode (41), a drain electrode (42) and a gate electrode (43) are arranged on the heterojunction structure layer (30), wherein the source electrode (41) and the drain electrode (42) are located at two ends of the heterojunction structure layer (30), and the gate electrode (43) is located between the source electrode (41) and the drain electrode (42).
6. The semiconductor structure according to claim 5, characterized in that: The ion implantation region (21) is a long strip of nanowires, and the extension direction of the ion implantation region (21) is parallel to the direction of the source electrode (41) pointing to the drain electrode (42).
7. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: An anode (51) and a cathode (52) are provided on the heterojunction structure layer (30), wherein the anode (51) and the cathode (52) are located at two ends of the heterojunction structure layer (30), and the ion implantation region (21) extends in a direction parallel to the direction from the anode (51) to the cathode (52).
8. The semiconductor structure according to claim 1, characterized in that: At least two of the plurality of ion implantation regions (21) have different widths; or at least two of the plurality of ion implantation regions (21) have different spacing distances.
9. The semiconductor structure according to claim 1, characterized in that: The thickness of the ion implantation region (21) is less than or equal to the thickness of the buffer layer (20).
10. The semiconductor structure according to claim 1, characterized in that: The impurity ion concentration of the ion implantation region (21) gradually decreases in a direction away from the substrate (10).
11. The semiconductor structure according to claim 1, characterized in that: At least one of the ion implantation regions (21) has impurity ions different from those of the other ion implantation regions (21).
12. The semiconductor structure according to claim 1, characterized in that: Along a direction perpendicular to the plane where the substrate (10) is located, the cross-sectional shape of the ion implantation region (21) includes any one of a rectangular, a triangular, a trapezoidal and a water drop shape.
13. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: S1. providing a substrate (10); S2, forming a buffer layer (20) on the substrate (10); S3, forming a plurality of ion implantation regions (21) arranged at intervals in the buffer layer (20) by ion implantation along a plane parallel to the buffer layer (20), wherein the ion implantation regions (21) include impurity ions; S4. Forming a heterojunction structure layer (30) on the buffer layer (20).
14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: The method for manufacturing the semiconductor structure further comprises: S5. Forming a source electrode (41), a drain electrode (42) and a gate electrode (43) on the heterojunction structure layer (30), wherein the source electrode (41) and the drain electrode (42) are located at two ends of the heterojunction structure layer (30), and the gate electrode (43) is located between the source electrode (41) and the drain electrode (42).
15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: By ion implantation, the extension direction of the ion implantation region (21) is controlled to be parallel to the direction of the source electrode (41) pointing to the drain electrode (42).
16. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: The method for manufacturing the semiconductor structure further comprises: S6. An anode (51) and a cathode (52) are formed on the heterojunction structure layer (30), wherein the anode (51) and the cathode (52) are located at two ends of the heterojunction structure layer (30), and an extension direction of the ion implantation region (21) is parallel to a direction from the anode (51) to the cathode (52).
17. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: The impurity ions include at least one of silicon, germanium, magnesium, beryllium, helium, argon, oxygen, aluminum, arsenic, nitrogen and phosphorus.
18. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: In at least one of the ion implantation regions (21), impurity ions different from those in the other ion implantation regions (21) are implanted.