Double-channel super-junction silicon carbide MOSFET

Abstract

The invention discloses a double-channel super-junction silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises an A-type substrate, an A-type epitaxial layer, a B-type second well region, a first groove, a second groove, drain metal, gate metal, source metal and Schottky metal, the conduction types of A and B are different; a super junction region and two B-type first well regions are arranged in the A-type epitaxial layer; the super junction region comprises an A-type columnar strip and two B-type columnar strips; the two B-type first well regions are arranged at the tops of the two B-type columnar strips; the first trench and the second trench are arranged at two sides of the B-type second well region; the Schottky metal is arranged at the bottom of the second groove; the gate metal is suspended in the insulating medium, a first conductive channel is formed at the top of the B-type first well region below the gate metal, and a second conductive channel is formed on the side wall of the B-type second well region adjacent to the gate metal. According to the invention, high breakdown voltage and low specific on-resistance can be ensured, and meanwhile, excellent dynamic performance, relatively high follow current capability and relatively high reliability are achieved.

Description

Technical Field

[0001] The invention relates to the technical field of power semiconductors, in particular to a double-channel super junction silicon carbide MOSFET. Background Art

[0002] Silicon carbide (SiC) has become a hot material in the field of power devices working under high voltage and high temperature due to its advantages such as wide bandgap and high thermal conductivity. Silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) are popular in application scenarios such as electric vehicles, industrial automation, and power transmission due to their advantages such as faster switching speeds and lower switching losses.

[0003] However, it is precisely because of the wider bandgap of the material itself that the body diode conduction voltage drop of SiC MOSFET is too high, resulting in excessive switching loss of the device. At the same time, the conduction of the body diode of SiC MOSFET will increase the defects in the drift region, increase the on-resistance of the device, and cause the problem of bipolar degradation.

[0004] To solve the above problems, traditional structures often use silicon carbide MOSFET and Schottky barrier diode (SBD) in anti-parallel. The extremely low on-state voltage drop of SBD can effectively suppress the conduction of the device body diode and provide a new path for the device to continue current. However, the external SBD will introduce additional parasitic inductance and capacitance, which will affect the dynamic performance of the device. In addition, it will increase the layout area and increase the cost.

[0005] On the other hand, the low channel mobility of planar gate SiC MOSFET limits the device's conduction capability, and the use of trench gate structure can achieve higher channel mobility in different crystal orientations. However, for SiC MOSFET in high-voltage and high-power application scenarios, the electric field is easily concentrated at the bottom corner of the trench, causing the device to break down prematurely and reducing the reliability of the gate oxide. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a double-channel super junction silicon carbide MOSFET in view of the deficiencies of the above-mentioned prior art. The double-channel super junction silicon carbide MOSFET can have excellent dynamic performance, strong freewheeling capability and high reliability while ensuring high breakdown voltage and low specific on-resistance.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: A double-channel superjunction silicon carbide MOSFET comprises an A-type substrate, an A-type epitaxial layer, a B-type second well region, a first trench, a second trench, a drain metal, a gate metal, a source metal and a Schottky metal; wherein the A-type is an N-type or P-type conductive semiconductor, the B-type is a P-type or N-type conductive semiconductor, and the conductivity types of A and B are different.

[0008] The drain metal, the A-type substrate, the A-type epitaxial layer, the B-type second well region and the source metal are arranged in sequence from bottom to top.

[0009] A super junction region and two B-type first well regions located on both sides of the top of the super junction region are arranged in the A-type epitaxial layer.

[0010] The super junction region includes an A-type columnar bar and two B-type columnar bars located on both sides of the A-type columnar bar; wherein the two B-type columnar bars are respectively a first B-type columnar bar and a second B-type columnar bar.

[0011] The two B-type first well regions are respectively arranged on the tops of the two B-type columnar strips.

[0012] The first trench and the second trench are arranged on both sides of the B-type second well region; wherein the bottom of the first trench contacts the B-type first well region at the top of the first B-type columnar strip, and the bottom of the second trench contacts the B-type first well region at the top of the second B-type columnar strip.

[0013] The Schottky metal is arranged at the bottom of the second trench.

[0014] The source metal is in an inverted U shape, with side leg one and side leg two; wherein, side leg one extends into the first trench and contacts the top of the B-type first well region below, and an insulating medium is filled between the inner wall of side leg one and the B-type second well region; side leg two extends into the second trench and contacts the top of the Schottky metal.

[0015] The gate metal is suspended in the insulating medium, a first conductive channel is formed on the top of the B-type first well region below the gate metal, and a second conductive channel is formed on the sidewall of the B-type second well region adjacent to the gate metal.

[0016] A B-type first ohmic contact region and an A-type first source contact region are embedded in parallel from the outside to the inside at the top of the B-type first well region located at the top of the first B-type columnar strip; wherein the A-type first source contact region is in contact with the side leg one, and a portion of it is located directly below the gate metal; the top of the B-type first well region on the inner side of the A-type first source contact region forms the first conductive channel.

[0017] A B-type first ohmic contact region is embedded at the top of the B-type first well region located at the top of the second B-type columnar strip; the B-type first ohmic contact region is in contact with the Schottky metal.

[0018] A type second source contact region and a type B second ohmic contact region are embedded in parallel on the top of the type B second well region; wherein the type A second source contact region is in contact with the source metal at the top and is adjacent to the gate metal; the side wall of the type B second well region directly below the type A second source contact region is formed as the second conductive channel.

[0019] The first conductive channel length L 1and the second conductive channel length L 2 equal.

[0020] The thickness of the insulating medium between the gate metal and the first conductive channel is equal to the thickness of the insulating medium between the gate metal and the second conductive channel.

[0021] The invention also includes an A-type JFET region, which is arranged between the A-type epitaxial layer and the B-type second well region and between the first trench and the second trench.

[0022] The first trench and the second trench have the same bottom depth.

[0023] The invention also includes an A-type buffer layer, which is arranged between the A-type substrate and the super junction region.

[0024] The gate metal can be a solid piece of metal or a split metal.

[0025] The source metal also includes a horizontal cross section connecting side leg one and side leg two, and a dielectric groove is arranged at the bottom of the horizontal cross section corresponding to the gate metal for filling the insulating medium; the top surface height of the gate metal is higher than the top surface height of the B-type second well region.

[0026] The present invention has the following beneficial effects: 1. The double-channel super-junction silicon carbide MOSFET proposed in the present invention has a second trench, which can reduce the depletion capacitance of the device and improve the dynamic performance of the device on the one hand; on the other hand, Schottky metal is integrated on the sidewall of the second trench, which saves layout area compared to planar Schottky metal.

[0027] 2. The dual-channel superjunction silicon carbide MOSFET proposed by the present invention introduces a B-type first well region and a B-type columnar strip under both the first trench and the second trench, thereby improving the reliability of the gate oxide; in addition, the setting of the superjunction region can optimize the electric field distribution, improve the blocking capability of the device, increase the doping concentration of the drift region, significantly reduce the specific on-resistance of the device, and thus reconcile the contradictory relationship between the specific on-resistance and the breakdown voltage of the device. Furthermore, the shielding effect of the B-type columnar strip can reduce the gate-drain capacitance of the device, thereby reducing the switching loss of the device.

[0028] 3. The dual-channel super-junction silicon carbide MOSFET proposed in the present invention introduces a dual conductive channel, and an additional first conductive channel is set at the top of the inner side of the B-type first well region located at the top of the first B-type columnar strip, providing an additional conduction path for carriers, which can compensate for the saturation current of the device during forward conduction and overcome the problem of narrow current path caused by the super-junction region. At the same time, the design of the dual conductive channel disperses the current path, avoids the formation of local hot spots, and improves the overall heat dissipation capacity of the device. Especially in the case of a short circuit, the additional first conductive channel can reduce instantaneous thermal stress and improve the device's ability to resist burning. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the structure of a double-channel superjunction silicon carbide MOSFET provided in Example 1 of the present invention.

[0030] Figure 2 It is a structural schematic diagram of embodiment 1 of the present invention, in which a super junction region, a first conductive channel and a second conductive channel are marked.

[0031] Figure 3 1 is a graph showing the relationship between the breakdown voltage, the specific on-resistance and the quality factor of Example 1 of the present invention as a function of the thickness of the super junction region; wherein (a) is a graph showing the relationship between the breakdown voltage and the specific on-resistance as a function of the thickness of the super junction region; and (b) is a graph showing the relationship between the quality factor and the thickness of the super junction region.

[0032] Figure 4 Schematic diagram comparing the forward conduction characteristics of Example 1 of the present invention and a conventional SiC MOSFET.

[0033] Figure 5 Schematic diagram comparing the reverse conduction characteristics of Example 1 of the present invention and a conventional SiC MOSFET.

[0034] Figure 6 Schematic diagram comparing the capacitance characteristics of Example 1 of the present invention and a conventional SiC MOSFET.

[0035] Figure 7 Schematic diagram comparing switching energy losses of Example 1 of the present invention and traditional SiC MOSFET.

[0036] Figure 8 This is a schematic diagram of the structure of Example 2 of the present invention.

[0037] Fig. 9 This is a schematic diagram of the structure of Example 3 of the present invention.

[0038] Fig.10 This is a schematic diagram of the growth of a portion of the A-type epitaxial layer in step 1 during the preparation of Example 1.

[0039] Fig.11 This is a schematic diagram of the preparation of the super junction region in step 2 of Example 1 after preparation is completed.

[0040] Fig.12 This is a schematic diagram of the preparation of a portion of the A-type JFET region after preparation is completed in step 3 of Example 1.

[0041] Fig.13 This is a schematic diagram of the preparation of the B-type first well region in step 4 of Example 1 after preparation is completed.

[0042] Fig.14This is a schematic diagram of the preparation of the B-type first ohmic contact region in step 5 of Example 1 after preparation is completed.

[0043] Fig.15 This is a schematic diagram of the preparation of the A-type first source contact region after preparation in step 6 of Example 1 is completed.

[0044] Fig.16 This is a schematic diagram of the preparation of the A-type JFET region in step 7 of Example 1 after preparation is completed.

[0045] Fig.17 This is a schematic diagram of the preparation of the B-type second well region in step 8 of Example 1 after preparation is completed.

[0046] Fig.18 This is a schematic diagram of the preparation of the A-type second source contact region after preparation in step 9 of Example 1 is completed.

[0047] Fig.19 This is a schematic diagram of the preparation of the B-type second ohmic contact region in step 10 in Example 1 after preparation is completed.

[0048] Fig. 20 This is a schematic diagram of the preparation of the first groove and the second groove in step 11 of Example 1 after preparation.

[0049] Fig.21 This is a schematic diagram of the process after the Schottky metal deposition in step 12 is completed when preparing Example 1.

[0050] Fig. 22 This is a schematic diagram of the L-shaped insulating medium after preparation in step 13 of Example 1.

[0051] Fig.23 This is a schematic diagram of the preparation of Example 1 after the gate metal and the insulating medium are completely deposited in step 14.

[0052] Fig.24 This is a schematic diagram of the process after the deposition of source metal and drain metal is completed in step 15 when preparing Example 1.

[0053] Fig.25 Schematic diagram of the structure of a traditional SiC MOSFET.

[0054] Among them are: 1. Drain metal; 2. Type A substrate; 3. Type A epitaxial layer; 4. Type B columnar strip; 5. Type B first well region; 6. Type B first ohmic contact region; 7. Type A first source contact region; 8. Type A JFET region; 9. Type B second well region; 10. Type A second source contact region; 11. Type B second ohmic contact region; 12. Insulating medium; 13. Gate metal; 14. Schottky metal; 15. Source metal; 16. Type B shielding layer; 17. Super junction region; 18. Type A buffer layer. DETAILED DESCRIPTION

[0055] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific preferred embodiments.

[0056] In the description of the present invention, it should be understood that the terms "left side", "right side", "upper part", "lower part" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. "First", "second" and the like do not indicate the importance of the components, and therefore cannot be understood as limiting the present invention. The specific dimensions used in this embodiment are only for illustrating the technical solution, and do not limit the scope of protection of the present invention.

[0057] Example 1

[0058] like Figure 1 As shown, a double-channel superjunction silicon carbide MOSFET includes an A-type substrate 2, an A-type epitaxial layer 3, an A-type JFET region 8, a B-type second well region 9, a first trench, a second trench, a drain metal 1, a gate metal 13, a source metal 15 and a Schottky metal 14; wherein the A-type is an N-type or P-type conductive semiconductor, the B-type is a P-type or N-type conductive semiconductor, and the conductivity types of A and B are different. In this embodiment 1, the preferred arrangement is: the A-type is an N-type conductive semiconductor, and the B-type is a P-type conductive semiconductor.

[0059] The drain metal 1, the A-type substrate 2, the A-type epitaxial layer 3, the A-type JFET region 8, the B-type second well region 9 and the source metal 15 are arranged in sequence from bottom to top. As an alternative, the A-type JFET region 8 may not be arranged. In this case, Figure 1 The A-type JFET region 8 in the structure is entirely formed as the A-type epitaxial layer 3 .

[0060] like Figure 2 As shown, a super junction region 17 and two B-type first well regions 5 located on both sides of the top of the super junction region are provided in the A-type epitaxial layer.

[0061] The super junction region includes two B-type columnar strips 4 and an A-type columnar strip between the two B-type columnar strips 4. The two B-type columnar strips are respectively a first B-type columnar strip and a second B-type columnar strip. In this embodiment, the width of the first B-type columnar strip is greater than the width of the second B-type columnar strip.

[0062] The two B-type first well regions are respectively arranged at the top of the two B-type columnar strips; among them, the B-type first well region 5 located at the top of the first B-type columnar strip is preferably arranged with the same width as the first B-type columnar strip; the B-type first well region 5 located at the top of the second B-type columnar strip is preferably arranged with the same width as the second B-type columnar strip.

[0063] The top of the B-type first well region 5 located at the top of the first B-type columnar strip is preferably embedded with a B-type first ohmic contact region 6 and an A-type first source contact region 7 with their ends touching and at the same height in parallel from the outside to the inside; wherein the top of the B-type first well region on the inner side of the A-type first source contact region forms a first conductive channel.

[0064] A B-type first ohmic contact region 6 is embedded on the top of the B-type first well region 5 located on the top of the second B-type columnar strip. Further, the first ohmic contact region 6 is arranged with the same width as the second B-type columnar strip.

[0065] Furthermore, the two B-type first ohmic contact regions 6 and the one A-type first source contact region 7 embedded on the top of the two B-type first well regions 5 are arranged at the same height, and the bottom surfaces are preferably arranged at the same height as the bottom surface of the A-type JFET region 8, and the top surfaces are flush with the top surfaces of the corresponding B-type first well regions 5. At this time, the bottom part of the A-type JFET region is embedded in the top of the A-type epitaxial layer. As an alternative, the bottom of the A-type JFET region may not be embedded in the A-type epitaxial layer.

[0066] The first trench and the second trench are arranged on both sides of the B-type second well region 9. Furthermore, the bottom depths of the first trench and the second trench are preferably the same. In this embodiment, the bottom of the first trench contacts the B-type first well region 5 at the top of the first B-type columnar strip, and is preferably arranged with the same width as the first B-type columnar strip; the bottom of the second trench contacts the B-type first well region 5 at the top of the second B-type columnar strip, and is preferably arranged with the same width as the second B-type columnar strip.

[0067] The Schottky metal 14 is disposed at the bottom of the second trench, the bottom of the Schottky metal 14 contacts the B-type first ohmic contact region 6 directly below, and the top surface of the Schottky metal 14 is preferably disposed at the same height as the top surface of the A-type JFET region 8 .

[0068] A type second source contact region 10 and a type B second ohmic contact region 11 are embedded in parallel on the top of the type B second well region 9; wherein the type A second source contact region is used to contact the source metal and is adjacent to the first trench; the side wall of the type B second well region directly below the type A second source contact region is formed into a second conductive channel.

[0069] like Figure 2 As shown, the length of the first conductive channel is L 1 and the second conductive channel length L 2 Preferably they are equal, both 0.4 mm.

[0070] The source metal is in an inverted U shape, with side leg one, side leg two and a horizontal cross section connecting side leg one and side leg two; wherein, side leg one extends into the first groove and can contact the A-type first source contact area 7 at the top of the B-type first well area 5 below, the outer side surface of side leg one is aligned with the outer side wall of the B-type first well area 5 below, the width of side leg one is smaller than the B-type first well area 5 below, and an insulating medium is filled between the inner side wall of side leg one and the B-type second well area 9 (that is, in the first groove inside side leg one); side leg two extends into the second groove and contacts the top of the Schottky metal 14.

[0071] Furthermore, a dielectric groove is preferably provided at the bottom of the horizontal cross section corresponding to the gate metal for filling with an insulating dielectric.

[0072] The gate metal is suspended in the insulating medium, located above the first conductive channel, and at least partially located above the A-type first source contact region 7. In this embodiment, the gate metal is preferably a whole piece of metal.

[0073] Furthermore, the thickness of the insulating medium between the gate metal and the first conductive channel is equal to the thickness of the insulating medium between the gate metal and the second conductive channel, and both are preferably 50 nm.

[0074] Furthermore, the top surface height of the gate metal is preferably higher than the top surface height of the B-type second well region 9 .

[0075] Working principle of this embodiment 1 In this embodiment 1, the Schottky metal is arranged on the side wall of the second trench, which saves the layout area and increases the Schottky contact area; when reverse conducting, the Schottky metal and the source metal are short-circuited to a high potential, which effectively inhibits the opening of the SiC MOSFET body diode. In this embodiment, the B-type first well region and the B-type columnar bar are introduced under the first trench and the second trench. In the reverse blocking state, the auxiliary depletion effect of the B-type columnar bar and the B-type first well region effectively improves the reverse withstand voltage of the device; in the reverse conducting state, the longitudinal Schottky metal contact on the side wall of the second trench can achieve good freewheeling capability, greatly improving the third quadrant performance of the device.

[0076] The conventional SiC MOSFET structure (hereinafter referred to as conventional device) is provided with a planar SBD, such as Fig.25 As shown, in comparison, the double-channel super-junction silicon carbide MOSFET provided in this embodiment 1 (hereinafter referred to as the device provided in this embodiment) has improved the blocking capability and forward conduction capability of the device due to the presence of the super-junction region. Figure 3As shown in the figure, as the thickness of the super junction region increases, the entire device can achieve better charge balance, so that the breakdown voltage gradually increases. At the same time, it is precisely because of the increase in the thickness of the super junction region that the current path is gradually compressed, causing the specific on-resistance to gradually increase. However, the super junction region itself increases the doping concentration of the drift region, so the specific on-resistance of the device is still at a low level. When the thickness of the super junction region is 7.5 mm, the device provided in this embodiment achieves the highest quality factor of 2630 MW / cm 2 At this time, the device breakdown voltage is 1871 V and the specific on-resistance is 1.331 mΩ–cm 2 .

[0077] like Figure 4 As shown, the device provided in this embodiment is additionally provided with a horizontal first conductive channel, which overcomes the problem of narrow current path caused by the super junction region to a certain extent, and compensates for the saturation current of the device during forward conduction, making it only slightly lower than the saturation current of the traditional device, and the saturation speed is faster than the traditional device. In contrast, if the first conductive channel of the device provided in this example is removed, the saturation current will be greatly reduced.

[0078] like Figure 5 As shown in the figure, both the conventional device and the device provided in this embodiment choose to integrate the SBD into the SiC MOSFET, which improves the device's freewheeling capability and the ability to inhibit the body diode from turning on, and greatly improves the device's third quadrant performance. When the gate-source voltage is -5 V and the drain-source current is -100 A / cm 2 Both devices have a low reverse voltage drop of 1.2 V.

[0079] like Figure 6 As shown, the device provided in this embodiment has a reduced depletion capacitance due to the provision of a second trench. At the same time, due to the shielding effect of the B-type columnar strip, the gate-drain capacitance (reverse recovery capacitance) of the device is greatly reduced, and as the drain-source voltage increases, the super junction region is gradually depleted, the shielding effect is weakened, and the gate-drain capacitance increases slowly. When the gate-drain voltage is 800 V, the gate-drain capacitance of the device provided in this embodiment is reduced by 79% compared to the conventional device.

[0080] like Figure 7 As shown, the device provided by this embodiment has lower depletion capacitance and gate-drain capacitance, so the switching loss of the device is lower. The switching energy loss of the device provided by this embodiment is compared with that of the traditional device, as shown in the following table:

[0081] It can be seen from the above table that, compared with traditional devices, the device provided in this embodiment has a turn-on energy loss reduced by 36%, and a turn-off energy loss reduced by 45%.

[0082] Example 2

[0083] like Figure 8 As shown, the difference between the second embodiment and the first embodiment is that in the second embodiment the gate metal 13 is separated into two parts by the insulating medium 12, that is, it is split into two split metals. The second embodiment can effectively reduce the gate-drain capacitance of the device and further improve the dynamic performance of the device.

[0084] Example 3

[0085] like Fig. 9 As shown, the only difference between this embodiment 3 and embodiment 1 is that in this embodiment, an A-type buffer layer 18 is inserted between the A-type substrate 2 and the super junction region 17 to further improve the static performance of the device, such as increasing the breakdown voltage and reducing the specific on-resistance.

[0086] The present invention takes Example 1 as an example to explain in detail the method for preparing a double-channel super junction silicon carbide MOSFET.

[0087] A method for preparing a double-channel super junction silicon carbide MOSFET comprises the following steps.

[0088] Step 1: growing part of the A-type epitaxial layer: Fig.10 As shown, an A-type epitaxial layer 3 of a set thickness is epitaxially grown on an A-type substrate 2 .

[0089] Step 2: Prepare super junction region: Fig.11 As shown, a super junction region of alternating A-type columnar strips and B-type columnar strips is formed on the A-type epitaxial layer through multiple epitaxial growth and ion implantation. For the convenience of subsequent description, the B-type columnar strip on the left is called the first B-type columnar strip, and the B-type columnar strip on the right is called the second B-type columnar strip.

[0090] Step 3: Continue to grow the A-type epitaxial layer and form a partial A-type JFET region: Fig.12 As shown, for the device prepared in step 2, a thin layer of SiC is first etched away, and then SiC continues to be epitaxially grown on the surface of the device. After that, a specific ion implantation mask layer is formed on the surface, ion implantation is performed to form a partial A-type JFET region, and high-temperature annealing is performed, and then the mask layer is removed.

[0091] Step 4: Prepare the B-type first well region: Fig.13As shown, a specific ion implantation mask layer is formed on both sides of the surface of the device prepared in step 3, ion implantation is performed to form a B-type first well region 5, and then high-temperature annealing is performed, and then the mask layer is removed. For the convenience of subsequent description, the B-type first well region located above the first B-type columnar strip is called the B-type first well region 1, and the B-type first well region located above the second B-type columnar strip is called the B-type first well region 2. Among them, the width of the B-type first well region 1 is equal to the width of the first B-type columnar strip, the width of the B-type first well region 2 is equal to the width of the second B-type columnar strip, and the width of the B-type first well region 1 is greater than the width of the B-type first well region 2.

[0092] Step 5: Prepare the first B-type ohmic contact region: Fig.14 As shown, a specific ion implantation mask layer is formed on the left side of the top surface of the B-type first well region 1 and the top surface of the B-type first well region 2, and then a high-dose ion implantation is performed to form the B-type first ohmic contact region 6, and then high-temperature annealing is performed and the mask layer is removed.

[0093] Step 6: Prepare the A-type first source contact region: Fig.15 As shown, a specific ion implantation mask layer is formed at the center of the top surface of the B-type first well region 1, and a high-dose ion implantation is performed to form the A-type first source contact region 7, and the A-type first source contact region and the B-type first ohmic contact region are located at the same height, and the ends are connected; then high-temperature annealing is performed and the mask layer is removed. At this time, the top surface of the B-type first well region 1 located on the right side of the A-type first source contact region is formed into a first conductive channel.

[0094] Step 7: Prepare A-type JFET region: Fig.16 As shown, for the device prepared in step 6, a thin layer of SiC is first etched away, and then SiC continues to be epitaxially grown on the surface of the device. Thereafter, ion implantation is performed in the epitaxially grown SiC layer above the partial A-type JFET region prepared in step 3 to form a complete A-type JFET region 8, and high-temperature annealing is performed.

[0095] Step 8: Prepare the B-type second well region: Fig.17 As shown, for the device prepared in step 7, a thin layer of SiC is first etched away, and then the epitaxial growth of SiC continues. Next, ion implantation is performed on the epitaxially grown SiC layer located directly above the A-type JFET region to form a B-type second well region 9, followed by high-temperature annealing.

[0096] Step 9: Prepare the A-type second source contact region: Fig.18 As shown, a specific ion implantation mask layer is formed on the surface of the device prepared in step 8, and a high-dose ion implantation is performed to form the A-type second source contact region 10, and then high-temperature annealing is performed and the mask layer is removed. Among them, the left side wall of the B-type second well region located below the A-type second source contact region forms a second conductive channel.

[0097] Step 10: Prepare the B-type second ohmic contact region: Fig.19 As shown, a specific ion implantation mask layer is formed on the top surface of the B-type second well region on the right side of the A-type second source contact region, and a high-dose ion implantation is performed to form the B-type second ohmic contact region 11, followed by high-temperature annealing, and then the mask layer is removed.

[0098] Step 11, preparing the first trench and the second trench: forming a specific etching mask layer on both sides of the B-type second well region, and using the etching mask layer to perform reactive ion etching on the left and right sides of the B-type second well region and the A-type JFET region to form Fig. 20 The first trench and the second trench are shown to have the same depth, and then the etching mask layer is removed.

[0099] Step 12, depositing Schottky metal: Schottky metal 14 is preferably deposited at the bottom of the second trench by chemical vapor deposition, such as Fig.21 shown.

[0100] Step 13, primary deposition of insulating medium: In the first trench, primary deposition of insulating medium 12 is completed by chemical vapor deposition, and then the insulating medium 12 is etched into an L-shaped shape, wherein the horizontal portion of the L-shaped insulating medium contacts the first conductive channel, and the vertical portion of the L-shaped insulating medium contacts the second conductive channel, as shown in FIG. Fig. 22 shown.

[0101] Step 14, depositing gate metal and insulating medium: depositing gate metal 13 on the L-shaped insulating medium, and then depositing insulating medium 12 for the second time, so that the gate metal is suspended in the insulating medium, as shown in the following example. Fig.23 Wherein, the gate metal is located above the first conductive channel and at least partially located above the A-type first source contact region.

[0102] Step 15, depositing source metal and drain metal: depositing source metal 15 on the outside of the insulating medium of the first trench, on the top surface of the B-type second well region and on the top surface of the second trench, and depositing drain metal 1 on the bottom surface of the A-type substrate, as shown in detail. Fig.24 shown.

[0103] The preferred embodiments of the present invention are described in detail above; however, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.

Claims

1. A dual-channel superjunction silicon carbide MOSFET, characterized in that: It includes an A-type substrate, an A-type epitaxial layer, a B-type second well region, a first trench, a second trench, a drain metal, a gate metal, a source metal and a Schottky metal; wherein the A-type is an N-type or P-type conductive semiconductor, the B-type is a P-type or N-type conductive semiconductor, and the conductivity types of A and B are different; The drain metal, the A-type substrate, the A-type epitaxial layer, the B-type second well region and the source metal are arranged in sequence from bottom to top; A super junction region and two B-type first well regions located on both sides of the top of the super junction region are provided in the A-type epitaxial layer; The super junction region includes an A-type columnar bar and two B-type columnar bars located on both sides of the A-type columnar bar; wherein the two B-type columnar bars are respectively a first B-type columnar bar and a second B-type columnar bar; Two B-type first well regions are respectively arranged on the tops of two B-type columnar strips; The first trench and the second trench are arranged on both sides of the B-type second well region; wherein the bottom of the first trench contacts the B-type first well region at the top of the first B-type columnar strip, and the bottom of the second trench contacts the B-type first well region at the top of the second B-type columnar strip; The Schottky metal is arranged at the bottom of the second trench; The source metal is in an inverted U shape, having a first leg and a second leg; wherein the first leg extends into the first trench and contacts the top of the B-type first well region below, and an insulating medium is filled between the inner side wall of the first leg and the B-type second well region; the second leg extends into the second trench and contacts the top of the Schottky metal; The gate metal is suspended in the insulating medium, a first conductive channel is formed on the top of the B-type first well region below the gate metal, and a second conductive channel is formed on the sidewall of the B-type second well region adjacent to the gate metal.

2. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: A B-type first ohmic contact region and an A-type first source contact region are embedded in parallel from outside to inside at the top of the B-type first well region located at the top of the first B-type columnar strip; wherein the A-type first source contact region is in contact with the side leg 1, and a portion of the A-type first source contact region is located directly below the gate metal; the top of the B-type first well region inside the A-type first source contact region forms the first conductive channel; A B-type first ohmic contact region is embedded at the top of the B-type first well region located at the top of the second B-type columnar strip; the B-type first ohmic contact region is in contact with the Schottky metal.

3. The double-channel super junction silicon carbide MOSFET according to claim 2, characterized in that: A type second source contact region and a type B second ohmic contact region are embedded in parallel on the top of the type B second well region; wherein the type A second source contact region is in contact with the source metal at the top and is adjacent to the gate metal; the side wall of the type B second well region directly below the type A second source contact region is formed as the second conductive channel.

4. The double-channel super junction silicon carbide MOSFET according to claim 1 or 3, characterized in that: The first conductive channel length L1 and the second conductive channel length L2 are equal.

5. The double-channel superjunction silicon carbide MOSFET according to claim 4, characterized in that: The thickness of the insulating medium between the gate metal and the first conductive channel is equal to the thickness of the insulating medium between the gate metal and the second conductive channel.

6. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: The invention also includes an A-type JFET region, which is arranged between the A-type epitaxial layer and the B-type second well region and between the first trench and the second trench.

7. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: The first trench and the second trench have the same bottom depth.

8. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: The invention also includes an A-type buffer layer, which is arranged between the A-type substrate and the super junction region.

9. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: The gate metal can be a solid piece of metal or a split metal.

10. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: The source metal also includes a horizontal cross section connecting side leg one and side leg two, and a dielectric groove is arranged at the bottom of the horizontal cross section corresponding to the gate metal for filling the insulating medium; the top surface height of the gate metal is higher than the top surface height of the B-type second well region.

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