Manufacturing method of semiconductor structure

Abstract

The invention discloses a manufacturing method of a semiconductor structure, and belongs to the technical field of semiconductors. The manufacturing method comprises the steps that a substrate is provided, a gate structure of a semiconductor device is arranged on the substrate, and the gate structure is arranged on the substrate in a protruding mode; forming side wall structures on two sides of the gate structure; forming a contact hole etching stop layer on the substrate, the gate structure and the side wall structure; the contact hole etching stop layer is cleaned; carrying out pretreatment on the contact hole etching stop layer; and forming a dielectric layer on the contact hole etching stop layer. According to the manufacturing method of the semiconductor structure provided by the invention, defects such as holes and gaps generated in the interlayer dielectric layer can be reduced, and the yield of the semiconductor structure is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a method for manufacturing a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, the density of circuit elements continues to increase. By filling dielectric layers between adjacent circuit elements to physically and electrically isolate the elements, improper interactions can usually be prevented. However, with the increasing demand for high integration and high performance of ultra-large-scale integrated circuits, the gap width of circuit elements has also been reduced accordingly, and the aspect ratio has also increased, which requires further improvement in the quality of the dielectric layer.

[0003] Currently, for example, before depositing the interlayer dielectric layer, a contact etch stop layer (CESL) is first deposited, and after the deposition is completed, a cleaning process is introduced to remove impurities on the surface of the contact etch stop layer. However, during the cleaning process, due to the uneven surface of the substrate, moisture remains between the gaps, and the moisture is chemically bonded to the contact etch stop layer, resulting in a slow bottom filling speed during the filling of the interlayer dielectric layer, and the dielectric layer is sealed prematurely, which is prone to defects such as voids or seams, which may cause leakage in the subsequent manufacturing process, thereby affecting the performance of the chip. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by the present invention can reduce defects such as voids and gaps in an interlayer dielectric layer, thereby improving the yield of the semiconductor structure.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, which at least comprises the following steps: Providing a substrate, on which a gate structure of a semiconductor device is disposed, and the gate structure is protrudingly disposed on the substrate; forming sidewall structures on both sides of the gate structure; forming a contact hole etching stop layer on the substrate, the gate structure and the sidewall structure; Cleaning the contact hole etching stop layer; Pre-treating the contact hole etch stop layer; and A dielectric layer is formed on the contact hole etch stop layer.

[0006] In one embodiment of the present invention, the pretreatment includes heating treatment and plasma treatment.

[0007] In one embodiment of the present invention, the temperature of the heating treatment is 180° C. to 240° C., and the time of the heating treatment is 20s to 40s.

[0008] In one embodiment of the present invention, the heat treatment is performed in an inert gas atmosphere, and the inert gas is helium or argon.

[0009] In one embodiment of the present invention, the plasma treatment step includes: placing the substrate after the heating treatment into a plasma chamber; and At the preset temperature and preset power, silicon hydride is introduced for a preset time.

[0010] In one embodiment of the present invention, the silicon hydride compound includes monosilane or disilane.

[0011] In an embodiment of the present invention, the preset temperature is 400° C. to 450° C., the preset power is 450W to 550W, and the preset time is 5s to 10s.

[0012] In one embodiment of the present invention, during the plasma processing, the distance between the substrate and the gas nozzle is controlled to be 1000 mils to 1200 mils.

[0013] In one embodiment of the present invention, after the contact hole etching stop layer is cleaned, a water-rich layer is formed at the bottom of the gap between adjacent gate structures.

[0014] In one embodiment of the present invention, the contact hole etching stop layer is pre-treated, and the water-rich layer at the bottom of the gap between adjacent gate structures is transformed into a silicon-rich layer.

[0015] In summary, the present invention provides a method for manufacturing a semiconductor structure. The unexpected technical effect of the present application is that it can solve the problem of residual moisture caused by the unevenness of the semiconductor structure on the substrate and chemically combined with the contact hole etching stop layer, so that the deposition rate of the interlayer dielectric layer at the bottom is not affected, and the interlayer dielectric layer will not be sealed in advance, thereby ensuring that the deposition of the interlayer dielectric layer on the substrate obtains a bottom-up filling effect, thereby reducing defects such as voids and gaps in the interlayer dielectric layer, avoiding leakage in subsequent processes, and improving the yield of semiconductor devices. While improving the quality of the interlayer dielectric layer, it reduces the loss of raw materials in the plasma treatment process and reduces production costs. The deposition method of the interlayer dielectric layer can be applied to different processes to improve the quality of the deposited dielectric layer and improve the manufacturing yield of semiconductor devices.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 FIG. 4 is a schematic diagram of a substrate and a gate structure on the substrate according to an embodiment of the present invention.

[0019] Figure 2 FIG. 4 is a schematic diagram of a substrate and a dummy gate structure on the substrate according to another embodiment of the present invention.

[0020] Figure 3 FIG. 4 is a schematic diagram of forming a self-aligned metal silicide according to an embodiment of the present invention.

[0021] Figure 4 FIG. 1 is a schematic diagram of forming a contact hole etching stop layer in one embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of a contact hole etching stop layer after cleaning in one embodiment of the present invention.

[0023] Figure 6 It is a schematic diagram of the contact hole etching stop layer after pretreatment in one embodiment of the present invention.

[0024] Figure 7 FIG. 1 is a schematic diagram of forming and planarizing an interlayer dielectric layer in one embodiment of the present invention.

[0025] Figure 8 FIG. 4 is an illustration of the effect of the preset time of plasma treatment on the quality of the interlayer dielectric layer in one embodiment of the present invention.

[0026] Fig. 9 It is a schematic diagram of forming a metal connection structure in an interlayer dielectric layer according to an embodiment of the present invention.

[0027] Fig.10 FIG. 4 is a schematic diagram of another embodiment of the present invention after planarizing the interlayer dielectric layer.

[0028] Description of labels: 10. Substrate; 11. Shallow trench isolation structure; 12. Gate dielectric layer; 13. Gate structure; 14. Sidewall structure; 15. Lightly doped region; 16. Heavily doped region; 17. Self-aligned metal silicide; 18. Contact hole etch stop layer; 19. Water-rich layer; 20. Silicon-rich layer; 21. Interlayer dielectric layer; 22. First metal connection structure; 23. Second metal connection structure; 121. First dielectric layer; 122. Second dielectric layer; 131. Pseudo gate structure; 132. First hard mask layer; 133. Second hard mask layer. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0031] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0032] See also Figure 1As shown, in one embodiment of the present invention, a substrate 10 is provided. The substrate 10 can be any material suitable for forming a semiconductor device, and the substrate 10 is, for example, silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, silicon wafer or other semiconductor materials formed by III / V compounds, etc., and also includes a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator. The present invention does not limit the type of substrate 10, and it can be selected according to the manufacturing requirements of the semiconductor device. In this embodiment, the substrate 10 is, for example, a doped silicon wafer, and the doping type can be P-type or N-type.

[0033] See also Figure 1As shown, in one embodiment of the present invention, a plurality of semiconductor devices are disposed on a substrate 10, and the present invention does not limit the types of semiconductor devices. The semiconductor device may be, for example, a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a thyristor, a charge coupled device (CCD), a constant voltage diode, a high frequency diode, a light-emitting diode (LED), a gate light-closed thyristor (GTO), a digital signal processor (DSP), a fast recovery diode (FRD), a high-speed and high-efficiency rectifier diode (HED), a light triggered thyristor (LTT), a photo relay or a microprocessor, etc., or more of the above, and the specific selection may be made according to the production requirements. In this embodiment, the semiconductor device is, for example, a multi-finger MOS transistor, and the multi-finger MOS transistor is isolated from other semiconductor devices by a shallow trench isolation structure 11. The shallow trench isolation structure 11 can be prepared by any formation method, and the present invention does not make any specific limitation.

[0034] See also Figure 1 As shown, in one embodiment of the present invention, the semiconductor device includes a plurality of gate structures 13, and the gate structures 13 are protrudingly arranged on the substrate 10. In one embodiment of the present invention, the distance between adjacent gate structures 13 is, for example, 30nm to 50nm. A gate dielectric layer 12 is arranged between the gate structure 13 and the substrate 10, wherein the gate dielectric layer 12 is, for example, a combination of silicon dioxide, a high dielectric constant dielectric layer, a low dielectric constant dielectric layer or a multi-layer dielectric layer, and the gate structure 13 is, for example, a polysilicon gate or a polysilicon pseudo gate. Sidewall structures 14 are arranged on both sides of the gate structure 13, and the sidewall structures 14 are, for example, silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride. In this embodiment, the sidewall structure 14 is, for example, a stacked structure of silicon oxide and silicon nitride.

[0035] See also Figure 2 As shown, in another embodiment of the present invention, when the gate of the semiconductor device is, for example, a metal gate, the gate dielectric layer includes, for example, a first dielectric layer 121 and a second dielectric layer 122, wherein the first dielectric layer 121 is, for example, silicon dioxide, and the second dielectric layer 122 is, for example, a high dielectric constant dielectric layer. A polysilicon pseudo gate structure 131 is provided on the second dielectric layer 122 to be removed in a subsequent process to form a metal gate. A hard mask layer is also provided on the polysilicon pseudo gate structure 131, and the hard mask layer includes a first hard mask layer 132 and a second hard mask layer 133, wherein the first hard mask layer 132 is, for example, a silicon nitride layer, and the second hard mask layer 133 is, for example, a silicon oxide layer, to protect the pseudo gate structure 131 during the formation of the interlayer dielectric layer and the planarization process, and to ensure the height of the metal gate finally formed. In this embodiment, for example, taking the gate dielectric layer 12 as silicon dioxide and the gate structure 13 as a polysilicon gate as an example, the method for manufacturing a semiconductor structure is described.

[0036] See also Figure 1 As shown, in one embodiment of the present invention, the semiconductor device further includes a lightly doped region 15 and a heavily doped region 16, wherein the doping type of the lightly doped region 15 and the heavily doped region 16 is the same and opposite to the doping type of the substrate 10. The edge of the lightly doped region 15 partially overlaps with the gate structure 13, the edge of the heavily doped region 16 is aligned with the edge of the sidewall structure 14 away from the gate structure 13, and the depth of the heavily doped region 16 is greater than the depth of the lightly doped region 15, so as to serve as the source and drain of the semiconductor device.

[0037] See also Figure 1 and Figure 3 As shown, in one embodiment of the present invention, after forming the semiconductor device, a self-aligned metal silicide 17 is formed on the heavily doped region 16 and the gate structure 13 of the semiconductor device. The self-aligned metal silicide 17 is, for example, nickel silicide (NiSi), cobalt silicide (CoSi2) or titanium silicide (TiSi2) with low resistance. By forming the self-aligned metal silicide 17, the contact resistance between the subsequently formed metal connection structure and the semiconductor device is reduced, the performance of the semiconductor device is improved, and the heavily doped region is prevented from being broken down or leaking electricity, thereby improving the stability of the semiconductor device. The self-aligned metal silicide 17 can also be used as a contact structure of the semiconductor device to lead out the source, drain and gate of the semiconductor device.

[0038] See also Figure 3 to Figure 4As shown, in one embodiment of the present invention, after forming the self-aligned metal silicide 17, a contact hole etch stop layer 18 is formed on the substrate 10. The contact hole etch stop layer 18 covers the substrate 10, the gate structure 13 and the sidewall structure 14, and the contact hole etch stop layer 18 is, for example, a silicon nitride layer, and the thickness is, for example, 80Å~200Å. In one embodiment of the present invention, the contact hole etch stop layer 18 is prepared by a low-temperature deposition method such as plasma enhanced chemical vapor deposition (PECVD), and the deposition source includes a nitrogen source and a silicon source, wherein the nitrogen source is selected from one or a combination of nitrogen (N2) or ammonia (NH3), and the silicon source is selected from one or a combination of silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4) or hexachlorodisilane (Si2Cl6).

[0039] See also Figures 4 to 5 As shown, in one embodiment of the present invention, after the contact hole etch stop layer 18 is formed, the contact hole etch stop layer 18 is cleaned to remove the particle impurities and the like that may exist on the contact hole etch stop layer 18, so as to improve the interface performance between the interlayer dielectric layer and the contact hole etch stop layer 18 that is subsequently formed. Specifically, under room temperature conditions, the substrate on which the contact hole etch stop layer 18 is formed is placed in a cleaning chamber, and nitrogen and water are introduced at the same time. The nitrogen and water are sprayed from the same outlet, and the nitrogen atomizes the water to improve the cleaning effect and avoid damage to the contact hole etch stop layer 18, wherein the flow rate of the nitrogen is, for example, 40L / min~120L / min, the flow rate of the water is, for example, 60L / min~200L / min, and the cleaning time is, for example, 10s~40s. After cleaning the contact hole etch stop layer 18, the residual moisture on the surface of the substrate is removed by a wafer spin dryer, but due to the presence of a protruding gate structure and the like on the substrate 10, moisture remains between the gaps of adjacent gate structures 13, forming a water-rich layer 19. If the interlayer dielectric layer is deposited directly, the deposition temperature is high, resulting in residual moisture chemically connecting with the contact hole etch stop layer 18 to form Si-OH bonds, while the surface of the contact hole etch stop layer 18 at the top is rich in NH bonds, the electronegativity of NH bonds is small, while the electronegativity of Si-OH is large. The nucleation reaction speed on the NH bonds during the deposition of the interlayer dielectric layer is greater than that on the Si-OH bonds, resulting in a faster deposition speed at the top of the gap of the gate structure 13 during the deposition of the interlayer dielectric layer, so that the interlayer dielectric layer is sealed prematurely, resulting in defects such as gaps or seams.

[0040] See also Figures 5 and 6As shown, in one embodiment of the present invention, after cleaning the contact hole etch stop layer 18, the substrate contact hole etch stop layer 18 is pretreated, and the pretreatment includes, for example, heat treatment and plasma treatment. The temperature of the heat treatment is, for example, 180°C to 240°C, the time of the heat treatment is, for example, 20s to 40s, and the heat treatment is, for example, performed in an inert gas atmosphere, the inert gas is, for example, helium or argon, etc., and the flow rate of the inert gas is, for example, 1800sccm to 2500sccm, so as to prevent oxidation of the contact hole etch stop layer 18 during the process of removing moisture. Most of the moisture in the water-rich layer 19 can be removed by heat treatment, while a small amount of moisture is combined with the contact hole etch stop layer 18 in the form of Si-OH valence bonds, which is difficult to remove by heat treatment.

[0041] See also Figures 5 and 6 As shown, in one embodiment of the present invention, after the heat treatment, plasma treatment is performed, wherein the plasma includes, for example, hydrogen plasma and silicon plasma. In this embodiment, the substrate 10 after the heat treatment is placed in the plasma chamber, and silicon hydride compounds such as monosilane (SiH4) or disilane (Si2H6) are introduced for a preset time at a preset temperature and preset power, and the distance between the substrate 10 and the gas nozzle is controlled to be, for example, 1000mils~1200mils, so as to improve the uniformity of the plasma treatment. In this embodiment, the preset temperature is, for example, 400℃~450℃, the preset power is, for example, 450W~550W, the preset time is, for example, 5s~10s, and the flow rate of silicon hydride compounds is, for example, 400sccm~600sccm. Silicon hydride compounds generate hydrogen plasma and silicon plasma in the plasma chamber. The generated hydrogen plasma reacts with -OH to consume the -OH bonds. The synchronous silicon plasma combines with Si- in the water-rich layer to generate Si-Si, forming a silicon-rich layer 20, wherein the silicon-rich layer 20 is formed at the bottom of the gap between adjacent gate structures 13, and the thickness of the silicon-rich layer 20 is, for example, at the atomic level, and the thickness in the accompanying drawings is only for example.

[0042] See also Figure 6 to Figure 7As shown, in one embodiment of the present invention, after pre-treating the contact hole etch stop layer 18, an interlayer dielectric layer 21 is formed on the contact hole etch stop layer 18, wherein the interlayer dielectric layer 21 is, for example, silicon dioxide or a low dielectric constant (Low-K) material to improve the reliability of the semiconductor structure. And the interlayer dielectric layer 21 is deposited, for example, by a high aspect ratio process (High Aspect Ratio Process, HRAP) to improve the filling capacity of the interlayer dielectric layer 21. By plasma treatment, the water-rich layer 19 is converted into a silicon-rich layer 20, and when the interlayer dielectric layer is deposited by HRAP, there is no dependence on Si-Si bonds, so the deposition rate of the interlayer dielectric layer at the bottom is greater than the deposition rate at the top, so that defects such as voids will not be caused. In this embodiment, specifically, a silicon-containing precursor and an oxygen-containing precursor are used for deposition at a temperature range of, for example, 400°C to 500°C, and at a pressure of, for example, 30torr to 760torr. Among them, the silicon-containing precursor includes, for example, one of silane or tetraethoxysilane (TEOS), and the oxygen-containing precursor includes, for example, one of O2 or O3. In the present embodiment, the silicon-containing precursor is, for example, TEOS, and the oxygen-containing precursor is, for example, O3. The dielectric layer is deposited at a temperature of, for example, 430°C and a pressure of 500 torr, and the deposition time is, for example, 100s to 200s. When depositing the interlayer dielectric layer 21, the interlayer dielectric layer 21 covers the shallow trench isolation structure 11 and the contact hole etching stop layer 18. After the interlayer dielectric layer 21 is formed, a planarization process is performed on the interlayer dielectric layer 21, for example, a chemical mechanical polishing (CMP) process is used to remove part of the interlayer dielectric layer 21 to ensure that the surface of the interlayer dielectric layer 21 is flat, thereby improving the convenience of subsequent operations.

[0043] See also Figures 7 and 8As shown, in one embodiment of the present invention, the influence of the conditions of the plasma treatment of the contact hole etching stop layer 18 on the deposition of the interlayer dielectric layer 21 in the HARP process is studied. In this embodiment, the silicon hydride is controlled to be, for example, monosilane, and the flow rate of the silicon hydride is fixed, the preset temperature is consistent, the spacing between the substrate 10 and the gas nozzle is consistent, the preset time of the plasma treatment is controlled to change, and the influence of the plasma treatment time on the subsequent deposition of the interlayer dielectric layer is confirmed. Among them, when the interlayer dielectric layer 21 is deposited on the substrate 10 that has not been plasma treated, more defects appear, especially at the edge of the substrate 10. This is because after cleaning, during the drying process, the residual moisture around the substrate 10 is more than the center. Therefore, the interlayer dielectric layer 21 formed at the edge of the substrate 10 has more defects. As the preset time of the plasma treatment increases, the defects in the interlayer dielectric layer 21 gradually decrease until the preset time is 7s, and there are basically no defects. As time increases, the treatment effect is not further improved. Therefore, by controlling the plasma treatment time within a preset range, the deposition quality of the interlayer dielectric layer can be ensured to be good, and the interlayer dielectric layer will not be sealed prematurely, thereby improving the filling effect of the interlayer dielectric layer and preventing defects such as voids and gaps. Similarly, by changing the preset temperature, preset power, flow rate, etc., obtaining the optimal range of the preset temperature, preset power, flow rate, etc., while improving the quality of the interlayer dielectric layer, reducing the loss of raw materials or time during the plasma treatment process, and reducing production costs.

[0044] See also Figure 7 and Fig. 9As shown, in one embodiment of the present invention, after the interlayer dielectric layer 21 is planarized, a metal connection structure is formed in the interlayer dielectric layer 21. In this embodiment, the remaining thickness of the interlayer dielectric layer 21 on the gate structure 13 is, for example, 60nm to 100nm. In other embodiments, the remaining thickness of the interlayer dielectric layer 21 on the gate structure 13 can be selected according to the manufacturing requirements. Specifically, after the interlayer dielectric layer 21 is formed, a plurality of openings (not shown in the figure) are formed in the interlayer dielectric layer 21. In this embodiment, the openings are, for example, respectively arranged on the gate structure 13 and the heavily doped region 16, and the openings are completed by two-step etching. Specifically, a patterned photoresist layer (not shown in the figure) is formed on the interlayer dielectric layer 21 to locate the position of the opening, the patterned photoresist layer is used as a mask, the contact hole etching stop layer 18 is used as an etching stop layer, the interlayer dielectric layer 21 is etched to the contact hole etching stop layer 18 and stops, the etching conditions are changed to remove the exposed contact hole etching stop layer 18, and an opening is formed, the opening exposes the self-aligned metal silicide 17 on the gate structure 13 and the heavily doped region 16, so as to lead out the gate, source and drain. The opening is formed, for example, by dry etching, and the etching gas can be, for example, one or a combination of several gases such as trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or nitrogen (N2), or a combination of them and oxygen (O2). In other embodiments, the opening can be formed by a combination of dry etching and wet etching or a wet etching process.

[0045] See also Fig. 9As shown, in one embodiment of the present invention, after the opening is formed, a conductive material is deposited in the opening to form a plurality of metal connection structures. When depositing the conductive material, a barrier layer (not shown in the figure) may be first deposited in the opening, and the barrier layer may be, for example, a material with good adhesion such as tantalum (Ta), titanium (Ti), tantalum nitride (TaN) or titanium nitride (TiN), and the thickness of the barrier layer may be, for example, 2nm to 8nm. By setting the barrier layer, the adhesion between the conductive material and the side wall of the opening is enhanced, and at the same time, the diffusion of the conductive material to the dielectric layer is reduced, the electromigration phenomenon is reduced, and the electrical performance of the semiconductor structure is improved. Among them, the conductive material may be, for example, a low-resistance material such as metal copper, metal aluminum or metal tungsten. In this embodiment, the conductive material may be, for example, metal tungsten. Metal tungsten is formed, for example, by physical vapor deposition or electroplating, and the metal tungsten is filled in the opening until it covers the interlayer dielectric layer 21, and then the metal tungsten is planarized so that the metal tungsten is flush with the interlayer dielectric layer 21 on both sides. The metal connection structure includes a first metal connection structure 22 and a second metal connection structure 23. The first metal connection structure 22 is connected to the self-aligned metal silicide 17 on the gate structure 13, and the second metal connection structure 23 is connected to the self-aligned metal silicide 17 on the heavily doped region 16. By controlling the quality of the interlayer dielectric layer 21, defects such as voids or gaps in the interlayer dielectric layer 21 are avoided, thereby preventing the metal connection structure from being filled in the void or gap, thereby reducing the defects of the formed metal connection structure, reducing leakage, and improving the reliability of the semiconductor structure.

[0046] See also Figure 2 and Fig.10 As shown, in another embodiment of the present invention, during the process of forming a metal gate, when planarizing the interlayer dielectric layer 21, non-selective grinding is used, and the contact hole etching stop layer 18, the second hard mask layer 133 and the first hard mask layer 132 on the pseudo gate structure 131 are removed at the same time to expose the surface of the pseudo gate structure 131. The pseudo gate structure 131 is flush with the interlayer dielectric layer 21 on both sides. After planarization, the pseudo gate structure 131 is removed to form a metal gate. By controlling the quality of the interlayer dielectric layer 21, defects such as voids or gaps in the interlayer dielectric layer 21 are avoided, thereby avoiding the residual metal material in the interlayer dielectric layer 21 due to the exposure of voids or gaps when forming a metal gate, and avoiding the problems of insufficient metal gate height, short circuit or open circuit. That is, the method for preparing the dielectric layer in the present application can be applied to different links of the semiconductor process to improve the manufacturing yield of semiconductor devices. In other embodiments, the method for improving the deposition process of the dielectric layer may also be applied to filling processes such as shallow trench isolation (Shallow Trench Isolation) or deep trench isolation (DTI) to improve the filling effect.

[0047] In summary, the present invention provides a method for manufacturing a semiconductor structure. The unexpected technical effect of the present application is: by pre-treating the contact hole etch stop layer, the problem of residual moisture caused by the unevenness of the semiconductor structure on the substrate and chemically combining with the contact hole etch stop layer is solved, so that the deposition rate of the bottom interlayer dielectric layer is not affected, and the interlayer dielectric layer will not be sealed in advance, thereby ensuring that the deposition of the interlayer dielectric layer on the substrate obtains a bottom-up filling effect, thereby reducing the generation of defects such as voids and gaps in the interlayer dielectric layer, avoiding leakage in subsequent processes, and improving the yield of semiconductor devices. While improving the quality of the interlayer dielectric layer, it reduces the loss of raw materials in the plasma treatment process and reduces production costs. The deposition method of the interlayer dielectric layer can be applied to different processes to improve the quality of the deposited dielectric layer and improve the manufacturing yield of semiconductor devices.

[0048] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: At least the following steps are included: Providing a substrate, on which a gate structure of a semiconductor device is disposed, and the gate structure is protrudingly disposed on the substrate; forming sidewall structures on both sides of the gate structure; forming a contact hole etching stop layer on the substrate, the gate structure and the sidewall structure; Cleaning the contact hole etching stop layer; Pre-treating the contact hole etching stop layer; as well as A dielectric layer is formed on the contact hole etch stop layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The pretreatment includes heating treatment and plasma treatment.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The temperature of the heating treatment is 180° C. to 240° C., and the time of the heating treatment is 20s to 40s.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The heat treatment is performed in an inert gas atmosphere, and the inert gas is helium or argon.

5. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The steps of plasma treatment include: placing the substrate after the heating treatment into a plasma chamber; and At the preset temperature and preset power, silicon hydride is introduced for a preset time.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The silicon hydride compound includes monosilane or disilane.

7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The preset temperature is 400° C. to 450° C., the preset power is 450W to 550W, and the preset time is 5s to 10s.

8. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: During the plasma treatment, the distance between the substrate and the gas nozzle is controlled to be 1000 mils to 1200 mils.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After the contact hole etching stop layer is cleaned, a water-rich layer is formed at the bottom of the gap between adjacent gate structures.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The contact hole etching stop layer is pre-treated so that the water-rich layer at the bottom of the gap between adjacent gate structures is transformed into a silicon-rich layer.

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