Preparation method of self-stratifying addressable three-dimensional stacked nanowire integration and CFET structure and preparation method of logic device

Abstract

The present invention relates to the field of microelectronic manufacturing technology. The present invention utilizes the preparation of stepped stacked trenches and the growth method of IPSLS nanowires to achieve self-layered addressable three-dimensional stacked nanowire integration and is beneficial to the preparation of addressable three-dimensional integrated devices, which can greatly improve the integration density and enhance the device performance. At the same time, based on the stepped three-dimensional stacked nanowires, the present invention proposes a preparation method for a CFET structure. Different types of nanowires are grown in different stepped layers using different catalytic metals, and then the source and drain metals are defined and prepared by lithography for each step, and the gate dielectric layer and the gate thin film layer are deposited. Multiple channels can be prepared through one growth, so as to achieve multi-layer stacking of CFETs in the three-dimensional direction and achieve addressability, greatly improving the integration density of the device, simplifying the preparation process, process stability and reliability.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology. Further, it relates to self-stratifying addressable three-dimensional stacked nanowire integration based on stepped stacked trenches, which can be used in high-density integrated devices with three-dimensional stacking. In particular, it relates to a method for preparing a CFET device structure and a logic device of self-stratifying addressable three-dimensional nanowires based on stepped stacked trenches, which can be applied to three-dimensional stacked logic device integration and the manufacture of a new generation of chips. Background Art

[0002] Semiconductor nanowires are the core materials of modern microelectronics technology due to their high ultra-high specific surface area, carrier mobility, high efficiency, stability, and reliable doping process. The inventors of this application first proposed a planar solid-liquid-solid (IPSLS) growth mode: among them, crystalline nanowire structures are grown by low-melting-point metal nanoparticles absorbing amorphous precursor films. At the same time, the inventors of this application also proposed a method using a positive photoresist process to prepare a multi-step guiding structure through cycles of anisotropic etching and isotropic etching reduction, and grow a positionable planar nanowire array. The previous research results of this team are based on nanowires obtained by the "planar solid-liquid-solid" growth method, which have the advantages of planar or three-dimensional positionability, programmable morphology, controllable diameter, and low cost, and can easily obtain three-dimensional nanowires based on various structures.

[0003] With the sharp increase in the requirements for computing power, storage density, and energy efficiency in fields such as artificial intelligence, big data, and 5G communication, the device size in the plane has been continuously miniaturized to the physical limit, and Moore's law is difficult to continue. As the feature size is reduced to the nanometer level, the interconnect delay and power consumption increase significantly, becoming the key factors restricting performance improvement. In order to continue Moore's law, shorten the interconnect path to reduce delay and power consumption, and achieve higher integration density, it is necessary to develop towards three-dimensional integration, that is, continuously stack devices in the vertical direction. Now, technologies such as through-silicon vias (TSV) and hybrid bonding have been developed, and concepts such as stacked complementary transistors (CFET) have been proposed for the development of three-dimensional device integration. However, the current technology has a low integration density, complex manufacturing processes, and low reliability and stability.

[0004] To solve the above problems, based on the stacked etching technology and the IPSLS growth technology, this team proposes a new technical path and complementary method for the existing three-dimensional integration, that is, designs a brand-new structure and preparation method for three-dimensional stacked nanowire integration and realizes the addressability of devices. Summary of the Invention

[0005] The present application provides a method for self-stratifying addressable three-dimensional stacked nanowire integration and CFET fabrication based on stepped stacked trenches, which can fabricate multiple layers of nanowires through a single growth. Moreover, the nanowires can be guided by stepped trenches to gradually achieve self-stratification from parallel growth, thus achieving an addressable effect, simplifying the fabrication method and improving the integration density. Additionally, based on the nanowires grown on stepped stacked trenches, the present invention also proposes a method for fabricating a CFET and an inverter, realizing the integration of N-type field-effect transistors (NFETs) and P-type field-effect transistors (PFETs) in the three-dimensional direction, improving the integration density of the CFET, and having the potential to be applied to three-dimensional logic, memory, sensing and other devices.

[0006] The present application provides a method for fabricating self-stratifying addressable three-dimensional stacked nanowire integration, including the following steps:

[0007] 1) Using a photoresist process, transfer the mask channel pattern onto a substrate with an alternately cyclically deposited periodic heterostructure stack.

[0008] 2) Through cyclic or angled plasma etching of anisotropic etching and isotropic etching back, etch the heterostructure stack into a stepped or ramped stacked structure.

[0009] 3) Selectively etch one of the dielectric layers to form a stepped guiding trench structure.

[0010] 4) Deposit a strip-shaped catalytic metal layer at the end of the side with the largest number of vertical trenches in the guiding trench structure.

[0011] 5) In a system such as PECVD, raise the temperature above the melting point of the catalytic metal, and use a reducing gas for plasma treatment to remove the oxide layer on the surface of the catalytic metal and form metal nanoparticles from the catalytic metal.

[0012] 6) Lower the temperature below the melting point of the catalytic metal particles, cover the entire sample surface with an amorphous semiconductor precursor thin film; then perform annealing treatment. The front end of the catalytic metal droplet begins to absorb the amorphous semiconductor precursor thin film layer, and the back end deposits crystalline doped nanowires. When the catalytic metal moves to the stepped corner of the side of the guiding trench structure, the catalytic metal sphere turns and continues to absorb the amorphous semiconductor precursor thin film, thereby realizing the self-stratification of the crystalline doped nanowires.

[0013] 7) After removing the remaining amorphous semiconductor precursor thin film layer on the sample surface, passivate the surface of the crystalline doped nanowires.

[0014] 8) Deposit a gate dielectric layer on the entire sample surface, and connect to the crystalline doped nanowires by injecting metal through openings at each step, thereby realizing the integration and addressability of the nanowire devices on each step.

[0015] Further, in step 1), the material of the substrate is crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire or polyimide, etc.; the hetero-stacked structure is a dielectric layer with different etching selectivity ratios such as silicon nitride / silicon oxide, aluminum oxide / silicon oxide, zinc oxide / silicon oxide, hafnium oxide / silicon nitride, etc.

[0016] Further, in step 1), the photolithography is contact photolithography, laser direct writing, electron beam lithography, deep ultraviolet lithography, extreme ultraviolet lithography, etc., and is also applicable to the photolithography in subsequent steps.

[0017] Further, in step 2), the anisotropic etching gas is CF4, C4F8, CHF3, SF6, Ar, Cl2, BCl3, etc. for physical or chemical etching, and the isotropic etching gas is O2, O3, SO2, etc. for etching the size of the photoresist. The step width and height are determined by the power and time of the plasma, which is used to control the number of nanowires in each step and the horizontal projection distance between nanowires; the inclination angle θ of the ramped stacked layer is determined by the angle of plasma etching.

[0018] Further, in step 3), the etching method of the stepped guiding trench is dry etching with gases such as CF4, C4F8, CHF3, SF6, Cl2, BCl3, etc. or wet etching with acid-base solutions such as HCl, HF, H3PO4, HNO3, NaOH, NH4OH, TMAH, etc. The parameters such as etching power, concentration and time jointly determine the depth of the trench. The etching method should have a high etching selectivity ratio for the two dielectric layer structures, and the selectivity ratio is greater than 5:1.

[0019] Further, in step 1), the hetero-stacked structure is two dielectric layers B and A with different etching selectivity ratios. The etching selectivity ratio of dielectric layer B to dielectric layer A is greater than 5:1, and the thickness of dielectric layer A is d A , and the thickness of dielectric layer B is d B .

[0020] Further, in step 2), the preparation steps of the stepped stacked structure include:

[0021] 1) Anisotropic etching, defining the height h of each step, where h is the thickness of the stacked layer of n cycles, that is, h = n·(d A + d B), which is subsequently used for growing nanowires. Each step height h corresponds to n nanowires therein;

[0022] 2) Isotropic etching is used to etch the size of the photoresist, exposing the step width w to be etched. The step width w corresponds to the horizontal projection spacing of the nanowires in different steps.

[0023] Furthermore, the ramp-type stack is obtained by angled plasma etching. The etched ramp angle is θ, and the horizontal projection spacing spacing between adjacent homogeneous dielectric layers is arctanθ·(dA + dB), which is used to define the horizontal projection spacing between subsequent adjacent nanowires. Using angled plasma etching can further increase the step density, that is, increase the density of subsequent addressable nanowire devices.

[0024] Furthermore, in step 4), the catalytic metal layer is deposited on the end of the side of the stepped guiding groove structure away from the step. The catalytic metal is one of In, Sn, Bi, Ga metals or their metal alloys, and the catalytic metal can also be deposited on the side by angled deposition.

[0025] Furthermore, in step 6), the amorphous semiconductor precursor film is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or a-Ge / a-Si heterostructure, etc.

[0026] Furthermore, in step 7), the amorphous semiconductor precursor film layer is removed by etching processes such as hydrogen plasma, RIE dry etching or wet etching, etc. The wet etching solution is an alkaline etching system such as potassium hydroxide (KOH), ammonia water (NH4OH), tetramethylammonium hydroxide (TMAH), etc. The RIE dry etching gas is a fluorine-containing gas such as carbon tetrafluoride (CF4), tetrafluoride octacarbon (C4F8), etc. The passivation method can be passivation with strongly oxidizing solutions such as HNO3, H2O2, KMnO4, etc., passivation with oxidizing plasmas such as low-temperature O2, O3, etc., or high-temperature (>750 °C) passivation, etc.

[0027] Furthermore, in step 8), the gate dielectric layer is alumina, hafnium oxide, silicon nitride, silicon oxide, titanium oxide, lanthanum oxide or heterostructure, etc. The opening method is RIE, DRIE, ICP, wet etching, laser drilling, etc. The method of injecting metal is physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, electroless plating, damascene process, metal reflow process, etc.

[0028] The present invention also provides a method for preparing a CFET structure by using the above self-stratifying addressable three-dimensional stacked nanowire integration, which is characterized by including the following steps:

[0029] 1) Adopt the photoresist process to transfer the mask channel pattern onto the substrate with periodically alternating heterostructures deposited in cycles. The number of steps is theoretically unrestricted.

[0030] 2) Through cycles of anisotropic etching and isotropic etching or angled plasma etching, etch the heterostructure into a stepped or ramped heterostructure.

[0031] 3) Selectively etch one of the dielectric layers to form a stepped guiding trench structure.

[0032] 4) Sequentially perform photolithographic definition and evaporate different catalytic metals at the connection between one end and the side of each step. The same catalytic metal can be defined and evaporated by photolithography at one time at different step positions.

[0033] 5) In a PECVD system or the like, synchronously raise the temperature above the melting point of the catalytic metal with the highest melting point value, and perform plasma treatment with a reducing gas to remove the surface oxide layer and form metal nanoparticles of the catalytic metal at the same time.

[0034] 6) Then synchronously lower the temperature below the melting point of the catalytic metal particles with the lowest melting point value, and cover the entire sample surface with an amorphous semiconductor precursor film; then perform annealing treatment. The front end of the catalytic metal droplets begins to absorb the amorphous semiconductor precursor film layer. Due to the self-doping effect of the catalytic metal, some catalytic metal atoms will enter the nanowire, and crystalline doped nanowires will be deposited at the back end. Since the catalytic metal grows simultaneously in different steps, the self-stratification of the crystalline doped nanowires is automatically achieved. The nanowires generated here will automatically turn when encountering the corners of the side and the steps, so as to change from the stratified growth in different steps to the parallel growth in the same vertical plane, realizing the vertical three-dimensional stacking of different types of nanowires.

[0035] 7) After removing the remaining amorphous semiconductor precursor film layer on the sample surface, passivate the surface of the crystalline doped nanowires.

[0036] 8) Photolithographically define the source and drain metal patterns on the independent vertical surface of each step, remove the surface oxide layer and evaporate the separated source and drain metals to connect different types of nanowires.

[0037] 9) Deposit a gate dielectric layer on the entire sample surface, define the gate pattern by photolithography and deposit separated gate films on the independent vertical surface of each step, and perform vacuum low-temperature annealing after the overall device preparation as needed to improve the contact and eliminate interface defects, completing the preparation of the CFET structure.

[0038] Preferably, in step 4), the types of catalytic metals are t, where t ≥ 2. Different catalytic metals are separately vapor-deposited on the vertical surfaces at the ends of each step. At least one catalytic metal serves as a donor impurity to provide electrons, generating N-type nanowires to form the channels of NFETs. At least one catalytic metal serves as an acceptor impurity to provide holes, generating P-type nanowires to form the channels of PFETs.

[0039] Preferably, the catalytic metals serving as donor impurities are Bi, Sr, Na, K, or their metal alloys, etc., which can provide electrons to make the nanowires form the channels of NFETs; the catalytic metals serving as acceptor impurities are In, Ga, Al, Cu, or Au metals and their metal alloys, etc., which can provide holes to make the nanowires form the channels of P-type nanowires to become PFETs.

[0040] Preferably, the source and drain metals in step 8) need to form a relatively small Schottky barrier with the nanowires. The metals connected to N-type nanowires are Ti, Al, Ag, Pb, or Ga and their metal alloys, etc. The metals connected to P-type nanowires are Pt, Au, Ni, Pd, or Co and their metal alloys, etc.; different types of nanowires can change the channel length according to the distance between the source and drain metals, thereby adjusting the performance of different types of devices to achieve matching.

[0041] Preferably, the gate film in step 9) is Al, Ni, Ti, Au, Pt, or Cr and their metal alloys, or polysilicon, etc.

[0042] The present invention also provides a logic device composed of the CFET structure prepared by the above method, characterized in that: it includes an NMOS composed of the NFETs and a PMOS composed of the PFETs. The NMOS and PMOS are provided with a common gate electrode constituting the input end of the logic device. The NMOS is provided with a first separate electrode for grounding, the PMOS is provided with a second separate electrode for connecting to the power supply, and a common electrode of the logic device output end is provided between the NMOS and PMOS.

[0043] The present invention also provides a preparation method of the above logic device, characterized in that:

[0044] 1) Prepare a CFET structure with 2 steps and 2 types of catalysts;

[0045] 2) Connect the same-type nanowires within the same step with separate electrodes, and connect the side surfaces of different steps with a common electrode to connect different types of crystalline doped nanowires to form the output end of the logic device;

[0046] Alternatively, at each step and the side corner, a separation electrode is defined by photolithography and a separation metal is deposited. At the place where all the nanowires on the side of the step are parallelly stacked, a common electrode is defined by photolithography and a metal is deposited, which is beneficial to reducing the projected area of the device in the horizontal direction and improving the integration density of the device.

[0047] 3) Deposit a gate dielectric layer on the entire sample surface, define the gate patterns connected on all steps by photolithography, and evaporate metal to form a common gate for the input end of the logic device.

[0048] The multiple technical solutions provided by this application have at least the following technical effects or advantages:

[0049] 1. The present invention uses modern microfabrication technology to prepare a stepped stack, and uses methods such as IPSLS to grow a trench-guided ultra-fine doped crystalline nanowire three-dimensional stacked array at a low temperature (< 350 °C) without a wafer substrate. The size of the nanowires is jointly limited by the thickness d of the deposited dielectric layer B B and the etched trench depth t. The thickness d B and the depth t can both be controlled at the nanometer level, and ultra-fine crystalline nanowire channels can be prepared without relying on high-precision photolithography.

[0050] 2. The present invention realizes self-stratifying and addressable three-dimensional stacked silicon nanowire integration, which can improve the integration density. Initially, all the nanowires are parallelly stacked in the same plane and turn when encountering a stepped corner, thus realizing the self-stratification of the nanowires. The vertical projection distance between adjacent nanowires is defined by the thickness d of the deposited dielectric layer A A The horizontal projection distance between the nanowires between adjacent steps is defined by the step width w, and the number of nanowires in each step is defined by the step height h. These parameters can all be controlled at the level of dozens of nanometers, greatly improving the integration density of the device. For the stepped trench obtained by etching the ramped stack, the horizontal projection distance between the nanowires between adjacent steps is defined by spacing, and the number of nanowires in each step is 1, which can further improve the integration density of the three-dimensional stacked nanowires and the density of addressable devices.

[0051] 3. The CFET preparation method proposed by the present invention can adjust the device performance in different steps to meet different requirements by controlling the number of nanowires, channel length, source-drain metal type, and gate film type in each step. At the same time, by adjusting the deposition period of the stack and the way of etching the stepped stack trench, the three-dimensional space can be fully utilized to realize the stacking of PFET and NFET, further increasing the number of CFET devices and device density in three-dimensional integration.

[0052] 4. The inverter prepared based on CFET in the present invention can fabricate the inverter in the same vertical plane, reducing the floor projection area, simplifying the fabrication process while greatly improving the integration density and reducing the power consumption.

[0053] 5. The present invention is conducive to the realization of monolithic three-dimensional integration. Whether it is the fabrication of CFET or various three-dimensional integrated devices fabricated based on self-stratifying addressable three-dimensional stacked nanowires, different types of channels of all devices can be grown and fabricated at one time in PECVD, so as to achieve multi-layer stacking of CFETs and addressability in the three-dimensional direction. Since the channels of all devices can be fabricated and passivated at one time, there is no need to bond and connect different chips / wafers through techniques such as hybrid bonding to increase the stacking layers, nor is it necessary to transfer or cyclically deposit dielectric layers to fabricate devices layer by layer. It effectively avoids the influence of the thermal effect of the upper device on the lower device, simplifies the fabrication process greatly while reducing the thermal budget, and greatly improves the stability and reliability of the process, and can be applied to monolithic three-dimensional integration as an efficient method. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0055] Figure 1 It is a schematic diagram of the process and structure for forming a stepped stacked trench based on step etching in an embodiment of the present invention and realizing self-stratifying addressability of three-dimensional stacked nanowires;

[0056] Figure 2 It is a schematic diagram of the process and structure for forming a stepped stacked trench based on ramp etching in an embodiment of the present invention and realizing self-stratifying addressability of three-dimensional stacked nanowires;

[0057] Figure 3 It is a schematic diagram of the process and structure for fabricating CFET and inverter devices based on the stepped stacked trench in an embodiment of the present invention;

[0058] Figure 4 It is a schematic diagram of the principle and side structure for integrating NFET and PFET in the vertical plane to fabricate an inverter in an embodiment of the present invention;

[0059] In the figure: 101, substrate; 102, silicon oxide; 103, silicon nitride; 104, etched silicon nitride guiding trench; 105, catalytic metal indium ball; 106, crystalline nanowire; 107, silicon oxide gate dielectric layer; 108, metal connection for addressing; 201, catalytic metal bismuth for N-type nanowire growth; 202, catalytic metal indium for P-type nanowire growth; 203, N-type nanowire; 204, P-type nanowire; 205, source and drain metal for connecting nanowires; 206, gate dielectric layer; 207, gate thin film; 208, common electrode; 209, separation electrode. Detailed implementation mode

[0060] Aiming at the deficiencies or drawbacks of the prior art, the present invention uses the preparation of stepped stacked trenches and the nanowire growth mode of IPSLS to realize self-stratified addressable three-dimensional stacked nanowire integration and is conducive to the preparation of addressable three-dimensional integrated devices, which can greatly improve the integration density and enhance the device performance. At the same time, based on the stepped three-dimensional stacked nanowires, the present invention proposes a preparation method of CFET. Different types of nanowires are grown in different stepped layers by using different catalytic metals, and then the source and drain metals are defined by photolithography and prepared for each step, and the gate dielectric layer and the gate thin film layer are deposited. Multiple channel layers can be prepared by one growth, so as to realize the multi-layer stacking of CFET in the three-dimensional direction and achieve addressability, greatly improving the integration density of the device and simplifying the preparation process, process stability and reliability. Further, by connecting the same-side source and drain metals and the gate thin film layer in the adjacent upper and lower steps, an inverter device based on CFET can be prepared; further, an inverter can be prepared at the place where all the nanowires on the side of the step are parallelly stacked, that is, where the number of trenches in the vertical direction is the largest, which is conducive to reducing the projection area of the device in the horizontal direction and enhancing the integration density of the device.

[0061] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with the specification drawings and specific implementation modes. Embodiment

[0062] This embodiment provides a self-stratified addressable three-dimensional stacked nanowire integration based on stepped stacked trenches, including a preparation method of CFET, as Figure 1 shown, which includes the following steps:

[0063] In the first step, on the silicon oxide wafer substrate 101, a stack of silicon oxide 102 and silicon nitride 103 is sequentially and alternately deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) technology. In this embodiment, 6 cycles are taken as an example, that is, there are 6 layers of silicon oxide 102 and 6 layers of silicon nitride 103 from top to bottom (excluding the silicon oxide deposited at the bottom layer).

[0064] In this embodiment, to obtain nanowires with a diameter less than 20 nm, the thickness d of the silicon nitride 103 B is set to 20 nm, and the thickness d of the silicon oxide 102 A is set to 20 nm according to the preparation requirements, as shown in Figure 1 Figure (a).

[0065] In the second step, the mask pattern is transferred to the stack using photolithography technology. The heterostructure stack is anisotropically etched with C4F8 by Inductively Coupled Plasma (ICP). The etching depth per time includes 2 stack cycles, and the step height is about 80 nm. O2 is used to isotropically etch the photoresist to make the photoresist etch back. The etch back is about 50 nm each time, that is, the step width is 50 nm. After 3 cycles, the photoresist is removed, forming a stepped silicon oxide and silicon nitride stack and exposing the side structure, as shown in Figure 1 Figure (b).

[0066] In the third step, the obtained stepped stack structure is placed in a hot phosphoric acid solution. The content of phosphoric acid > 85%, the temperature of the hot phosphoric acid is 140 °C. The etching ratio of hot phosphoric acid to silicon nitride and silicon oxide is about 50:1. After being placed in the hot phosphoric acid solution for 5 min, the etched groove depth t is about 30 nm, obtaining the etched silicon nitride guiding groove 104, thus obtaining a stepped stack groove, as shown in Figure 1 Figure (c).

[0067] In the fourth step, using photolithography technology, the catalytic metal region is positioned at one end of the side of the stepped stack groove (the side with the largest number of vertical grooves). A 5 nm thick catalytic metal indium In film is deposited by thermal evaporation; in PECVD, the temperature is raised above the melting point of the catalytic metal, and a reducing hydrogen plasma is introduced for treatment to transform the metal indium In film into separated catalytic metal indium spheres 105, as shown in Figure 1 Figure (d).

[0068] Step 5: Lower the temperature in the PECVD system below the melting point of the catalytic metal particles, and cover the entire structure surface with a 10-nm-thick amorphous silicon (a-Si) thin film layer; then raise the temperature above the eutectic point of the catalytic metal and the amorphous thin film layer. The catalytic metal droplets start to absorb amorphous silicon at their front ends, and crystalline nanowires 106 are deposited at their rear ends. Since the catalytic metal indium spheres need to absorb the amorphous silicon in the trenches, the catalytically grown crystalline silicon nanowires are also confined within the trenches. When encountering the corners of the stepped stacked trenches, the nanowires will turn and enter the trenches of each step to continue growing, achieving self-stratification of the nanowires, which facilitates subsequent discrete connection and addressing of the nanowires and devices on each step. As shown in Figure 1 Figure (e) in

[0069] Step 6: Use carbon tetrafluoride (CF4) in RIE for dry etching to remove the amorphous silicon, and then anneal in an O2 atmosphere at 850 °C for 8 min in a tube annealing furnace to passivate the crystalline nanowires with high quality.

[0070] Step 7: Devices can be fabricated on the nanowires on each step. The steps for fabricating the devices are shown in the subsequent embodiments and are omitted here; cover the entire sample surface with a 300-nm-thick silicon oxide gate dielectric layer 107, and fabricate metal connections 108 for addressing by using TSV through-silicon vias and injecting metal to connect the nanowires within each step, thereby enabling addressability of the nanowires and devices on each step. As shown in Figure 1 Figure (f) in Embodiment

[0071] This embodiment provides a self-stratifying and addressable three-dimensional stacked nanowire integration based on stepped stacked trenches, including a preparation method for CFETs. As shown in Figure 2 the following steps are included:

[0072] Step 1: Use Plasma-Enhanced Chemical Vapor Deposition (PECVD) technology to alternately deposit a stack of silicon oxide 102 and silicon nitride 103 on a substrate 101 (such as a silicon oxide wafer). In this embodiment, 6 cycles are taken as an example, that is, there are 6 layers of silicon oxide 102 and 6 layers of silicon nitride 103 from top to bottom (excluding the silicon oxide deposited at the bottom layer).

[0073] In this embodiment, to obtain nanowires with a diameter less than 20 nm, the thickness d B of the silicon nitride 103 is set to 20 nm, and the thickness d A of the silicon oxide 102 is set to 20 nm according to the preparation requirements.

[0074] In the second step, the pattern on the mask is transferred to the stack by photolithography. Angle etching is performed using Ar plasma through ion beam etching (IBE) to form a ramp-shaped stack and expose the side structures, as shown in Figure 2 Figure a) in A + d B ). The horizontal projection spacing of adjacent homogeneous dielectric layers (i.e., the horizontal projection spacing of adjacent nanowires) spacing is arctanθ·(d Figure 2 ), as shown in the side view of the ramp-shaped stack in Figure (b) of

[0075] In the third step, the obtained ramp-shaped stack structure is placed in a hot phosphoric acid solution. The content of phosphoric acid is > 85%, the temperature of the hot phosphoric acid is 140 °C, and the etching ratio of hot phosphoric acid to silicon nitride and silicon oxide is about 50:1. After being placed in the hot phosphoric acid solution for 5 minutes, the etched trench depth t is about 30 nm, and the etched silicon nitride guiding trench 104 is obtained, thereby obtaining a stepped stack trench, as shown in Figure 2 Figure (c) in Figure 2 Figure (d) in

[0076] In the fourth step, the catalytic metal region is positioned at one end of the side of the stepped stack trench (the side with the largest number of vertical trenches) by photolithography, and a 5-nm-thick catalytic metal indium In thin film is deposited by thermal evaporation. In the PECVD, the temperature is raised above the melting point of the catalytic metal, and a reducing hydrogen plasma is introduced for treatment to convert the In thin film into separated catalytic metal indium spheres.

[0077] In the fifth step, in the PECVD system, the temperature is lowered below the melting point of the catalytic metal particles, and a 10-nm-thick amorphous silicon (a-Si) thin film layer is covered on the entire structure surface; then the temperature is raised above the eutectic point of the catalytic metal and the amorphous thin film layer. The catalytic metal indium sphere droplets start to absorb amorphous silicon at their front end, and crystalline nanowires 106 are deposited at their rear end. Since the catalytic metal indium spheres need to absorb the amorphous silicon in the trenches, the catalytically grown crystalline nanowires are also restricted in the trenches. When encountering the corner of the stepped stack trench, the nanowires will turn and enter the trenches of each step to continue growing, realizing the self-stratification of the nanowires, which is convenient for subsequent discrete connection and addressing of the nanowires and devices on each step, as shown in Figure 2 Figure (e) in

[0078] In the sixth step, dry etching is performed using carbon tetrafluoride (CF4) in RIE to remove amorphous silicon, and then annealing is carried out at 850 °C for 8 min in an O2 atmosphere in a tube annealing furnace to passivate the crystalline nanowires with high quality.

[0079] In the seventh step, devices can be fabricated for the nanowires on each step. The steps for fabricating the devices are shown in the subsequent embodiments and are omitted here; A 300-nm-thick silicon oxide gate dielectric layer 107 is covered on the entire sample surface, and the through-silicon via (TSV) and metal injection methods are used to connect the nanowires within each step, thereby enabling the addressing of the nanowires and devices in each layer of the step, as Figure 2 shown in Figure (f) of [reference]. The self-stratifying addressable three-dimensional stacked nanowire integration based on the ramp-type stack can greatly improve the integration density of the device and can be used in high-density three-dimensional integrated devices such as logic, sensing, and storage. Embodiment

[0080] This embodiment provides a method for fabricating a CFET based on a stepped stacked trench, and the structure is as Figure 3 shown. This embodiment uses a stepped trench fabrication method similar to the stepped type in Embodiment 1, and specifically includes the following steps:

[0081] 1) The number of steps of the stepped trench fabricated in this embodiment is 2, and each step contains 3 cycles of the stack, that is, the step height is 3·(d A +d B ). The width of the step is set to 200 nm, as Figure 3 shown in Figure (a) of [reference]. Then, the stacked trench with 2 layers of steps is also fabricated using the hot phosphoric acid etching method, as Figure 3 shown in Figure (b) of [reference];

[0082] 2) Photolithography is used to define the catalytic metal regions at the protrusions of each step (the side and the corner of the step), and different catalytic metals are evaporated in batches. Indium 202, the catalytic metal for P-type nanowire growth, is evaporated at the corner of the first step and the side, and bismuth 201, the catalytic metal for N-type nanowire growth, is evaporated at the corner of the second step and the side. The temperature is raised above the melting point of bismuth metal in PECVD, and a reducing hydrogen plasma is introduced for treatment to transform the catalytic metal into separated metal droplets, as Figure 3 shown in Figure (c) of [reference];

[0083] 3) The temperature in the PECVD system is reduced below the melting point of indium metal, and a 10-nm-thick amorphous silicon (a-Si) thin film layer is deposited on the entire structure surface. Then, the temperature is increased to cause the catalytic metal droplets to start absorbing amorphous silicon at their front ends, while crystalline silicon nanowires are deposited at their rear ends. Due to the self-doping effect of the catalytic metal in the nanowires, indium acts as an acceptor impurity in the silicon nanowires, so the catalytic metal In spheres will grow P-type nanowires 204 in the sidewall trenches, and metal bismuth Bi acts as a donor impurity in the silicon nanowires, so the catalytic metal Bi spheres will grow N-type nanowires 203 in the sidewall trenches. When encountering the corners of the stepped stacked trenches, they will turn, thus changing from the hierarchical growth in different steps to the parallel growth in the same vertical plane, realizing the vertical three-dimensional stacking of different types of nanowires, as Figure 3 shown in Figure (d) below. P-type silicon nanowires are grown in the three trenches of the lower step, and N-type silicon nanowires are grown in the three trenches of the upper step. The arrows in the figure indicate the growth directions of the nanowires.

[0084] 4) Dry etching is carried out using carbon tetrafluoride (CF4) in RIE to remove the amorphous silicon. After that, annealing is performed in an O2 atmosphere at 850 °C for 8 min in a tube annealing furnace to passivate the nanowires with high quality.

[0085] 5) Photolithography is used to define the source and drain metal patterns at each step. BOE or an HF solution with an appropriate concentration (such as 4%) is used to remove the surface oxide layer and deposit the source and drain metals 205 for connecting the nanowires to connect different types of nanowires, as Figure 3 shown in Figure (e) below. Here, the source and drain metals 205 for connecting the nanowires are just a unified label for the metals used as the source and drain. If different metals need to be deposited to reduce the Schottky barrier in contact with the nanowires, photolithography, oxide layer removal, and metal deposition can be carried out in batches. In this embodiment, Ti with a thickness of 12 nm and Al with a thickness of 40 nm can be used to connect the N-type nanowires in the three trenches of the upper step, so that NFETs can be fabricated on the upper step. Pt with a thickness of 12 nm and Au with a thickness of 40 nm can be used to connect the P-type nanowires in the three trenches of the lower step, so that PFETs can be fabricated on the lower step, realizing the three-dimensional stacking of NFETs and PFETs, which is beneficial to the integration of CFETs.

[0086] 6) A gate dielectric layer 206 is covered on the entire sample surface. The gate pattern is defined by photolithography at each step, and separated gate thin films 207 are locally deposited through evaporation or sputtering processes. Here, the gate dielectric layer 206 and the gate thin films 207 are just unified labels for the gate dielectric and the gate thin films. In this embodiment, a 3nm alumina and 8nm hafnium oxide heterostructure can be used as the gate dielectric, and a 60nm Al or Ni metal thin film can be used as the gate, as Figure 3 shown in Figure (f) of

[0087] In this embodiment, different doped nanowires in different stepped layers are utilized to separately fabricate NFETs and PFETs on the steps, realizing the three-dimensional stacked integration of CFETs. At the same time, different types of nanowires will turn at the step corners and converge in the same vertical plane, which is beneficial to improving the integration density and further enhancing the device performance of CFETs, and is expected to be applied to three-dimensional logic devices and the manufacture of new-generation chips. Embodiment

[0088] This embodiment provides a method for fabricating an inverter based on a stepped stack-type CFET, as Figure 3 shown in Figures (g) and (h) of Figure 4 and

[0089] In this embodiment, the inverter is fabricated at the side position of the stepped stack trench. The nanowires grown in different layers in different steps are transformed into parallel growth in the same vertical plane, which is beneficial to reducing the horizontal projection area of the device and improving the integration density of the device. Based on the different types of nanowires fabricated and grown in Embodiment 3.

[0090] In step 5) of Embodiment 3 of this embodiment, the metals on one side of the upper and lower steps are connected to form a common electrode 208, and the other side is still connected with separated metals to form separated electrodes 209, as Figure 3 shown in Figure (g) of

[0091] Then, in step 6) of Embodiment 3, the gate pattern connected on the side is defined by photolithography and the gate thin film 207 is evaporated to form a common gate as the input end of the inverter, as Figure 3 shown in Figure (h) of

[0092] Figure 4Figure (a) in [[ ]] shows a simplified schematic diagram of the inverter prepared in this embodiment, which is used for comparison with Figure (b) on the right. Figure (b) is a side view of the inverter prepared in this embodiment. The PFET in the lower stepped layer is used as the PMOS in the schematic diagram of Figure (a), and the NFET in the upper stepped layer is used as the NMOS in the schematic diagram of Figure (a). The separated electrode in the PFET is used as the working voltage VDD of the inverter, the separated electrode in the NFET is used as the ground terminal GND of the inverter, the common electrode in the CFET is used as the output terminal Vout of the inverter, and the common gate in the CFET is used as the input terminal Vin of the inverter.

[0093] If the Gate all around (GAA) structure is adopted, the performance of the nanowire devices in the stepped layer can be further improved. However, this is not the core idea and innovation point of the present invention. It is only an improvement based on the structure of the present invention. The above embodiments are described to help understand the method and its core idea of this application. At the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes, and these improvements should also be regarded as the protection scope of the present invention.

Claims

1. A preparation method for self-stratifying and addressable three-dimensional stacked nanowire integration, characterized in that: It includes the following steps: 1) Adopt a photoresist process to transfer the mask channel pattern onto a substrate with a periodically alternating heterostructure deposited in a cyclic manner; 2) Through cycles of anisotropic etching and isotropic etching, etch the heterostructure into a stepped heterostructure; 3) Place the obtained stepped heterostructure in a hot phosphoric acid solution and selectively etch one of the dielectric layers to form a stepped guiding trench structure; 4) Deposit a strip-shaped catalytic metal layer at one end of the side with the largest number of vertical trenches in the guiding trench structure; 5) In a system such as PECVD, raise the temperature above the melting point of the catalytic metal and perform plasma treatment with a reducing gas to remove the oxide layer on the surface of the catalytic metal and form metal nanoparticles at the same time; 6) Lower the temperature below the melting point of the catalytic metal particles, cover the entire sample surface with an amorphous semiconductor precursor thin film; then perform annealing treatment. The front end of the catalytic metal droplet begins to absorb the amorphous semiconductor precursor thin film layer, and the back end deposits crystalline doped nanowires. When the catalytic metal moves to the stepped corner on the side of the guiding trench structure, the catalytic metal sphere turns and continues to absorb the amorphous semiconductor precursor thin film, thus realizing the self-stratification of the crystalline doped nanowires; 7) After removing the remaining amorphous semiconductor precursor thin film layer on the sample surface, passivate the surface of the crystalline doped nanowires; 8) Deposit a gate dielectric layer on the entire sample surface and achieve connection with the crystalline doped nanowires by opening holes and injecting metal at each step, thereby realizing the integration and addressability of the nanowire devices on each step; In step 1), the heterostructure is composed of two dielectric layers B and A with different etching selectivity ratios. The etching selectivity ratio of dielectric layer B to dielectric layer A is greater than 5:1, and the thickness of dielectric layer A is d A , and the thickness of dielectric layer B is d B ; In step 2), the preparation steps of the stepped heterostructure include: 1) Anisotropic etching is used to define the height h of each step. h is the thickness of the stacked layer of n cycles, that is, h = n·(d A + d B ), which is used for subsequent growth of nanowires. Each step height h corresponds to n nanowires therein; 2) Isotropic etching, used to etch the size of the photoresist and expose the required etched step width w, and the step width w corresponds to the horizontal projection spacing of the nanowires in different steps.

2. The preparation method of the self-stratifying addressable three-dimensional stacked nanowire integration according to claim 1, characterized in that: In step 4), the catalytic metal layer is evaporated at the end of the side of the stepped guiding trench structure away from the step, and the catalytic metal is one of In, Sn, Bi, Ga metals or their metal alloys.

3. The preparation method of self-stratifying addressable three-dimensional stacked nanowire integration according to claim 1, characterized in that: In step 6), the amorphous semiconductor precursor thin film is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or a-Ge / a-Si heterostructure.

4. A method for fabricating a three-dimensional stacked nanowire integrated CFET structure prepared by the method described in claim 1, characterized in that, It includes the following steps: 1) Adopt a photoresist process to transfer the mask channel pattern onto a substrate with a periodically alternating heterostructure deposited in a cyclic manner; 2) Through cycles of anisotropic etching and isotropic etching or angled plasma etching, etch the heterostructure into a stepped or ramped heterostructure; 3) Place the obtained stepped or ramped heterostructure in a hot phosphoric acid solution and selectively etch one of the dielectric layers to form a stepped guiding trench structure; 4) Perform photolithographic definition and evaporate different catalytic metals step by step at the connection between one end and the side of each step; 5) In systems such as PECVD, synchronously raise the temperature to above the melting point of the catalytic metal up to the highest melting point value, and perform plasma treatment using a reducing gas to remove the surface oxide layer while forming metal nanoparticles of the catalytic metal. 6) Then synchronously lower the temperature to below the melting point of the catalytic metal particles at the lowest melting point value, and cover the entire sample surface with an amorphous semiconductor precursor film; then perform an annealing treatment. The front end of the catalytic metal droplets begins to absorb the amorphous semiconductor precursor film layer. Due to the self-doping effect of the catalytic metal, some catalytic metal atoms enter the nanowires, and crystalline doped nanowires are deposited at the back end. Since the catalytic metal grows simultaneously in different steps, the self-stratification of the crystalline doped nanowires is automatically achieved. When the catalytic metal moves to the end of the step and the side corner, the catalytic metal spheres turn to realize the parallel stacked growth of different types of crystalline doped nanowires on the same side. 7) After removing the remaining amorphous semiconductor precursor film layer on the sample surface, passivate the surface of the crystalline doped nanowires. 8) Photolithographically define the source and drain metal patterns on each stepped independent vertical surface, remove the surface oxide layer and evaporate the separated source and drain metals to connect different types of crystalline doped nanowires. 9) Deposit a gate dielectric layer on the entire sample surface, define the gate pattern by photolithography, and deposit separated gate films on each stepped independent vertical surface to complete the preparation of the CFET structure.

5. The method for preparing a CFET structure according to claim 4, wherein: In step 4), the types of the catalytic metals are t, where t ≥ 2. Different catalytic metals are separately evaporated on the vertical surface at the end of each step, and at least one catalytic metal provides electrons as a donor impurity to generate N-type nanowires to form the channel of the NFET, and at least one catalytic metal provides holes as an acceptor impurity to generate P-type nanowires to form the channel of the PFET.

6. The method for preparing a CFET structure according to claim 4, wherein: The source and drain metals are electrically connected to the external circuit by injecting metals after opening holes to achieve addressability of the devices on each step; set different source and drain metal distances to adjust the channel lengths of different types of crystalline doped nanowires to adjust the performance of different types of devices to achieve matching.

7. A logic device, which is composed of the CFET structure prepared by claim 5, characterized in that: It includes an NMOS composed of the NFETs and a PMOS composed of the PFETs. The NMOS and PMOS are provided with a common gate constituting the input end of the logic device. The NMOS is provided with a first separated electrode for grounding, the PMOS is provided with a second separated electrode for connecting to the power supply, and a common electrode of the logic device output end is provided between the NMOS and PMOS. The NMOS and PMOS are respectively prepared from N-type nanowires in three grooves on the side of the upper stepped surface and P-type nanowires in three grooves on the side of the lower stepped surface grown at one time, and the NMOS and PMOS are three-dimensionally stacked and integrated in a staggered stepped structure.

8. A method for preparing a logic device, applicable to the logic device according to claim 7, characterized in that: 1) Prepare a CFET structure with 2 steps and 2 types of catalysts. 2) The same type of nanowires within the same ladder are connected by separate electrodes, and the sides of different ladders are connected by a common electrode to form the output terminal of the logic device with different types of crystalline doped nanowires; Alternatively, at each corner of the ladder and the side, a separate metal is defined by photolithography and evaporated to form a separate electrode, and at the parallel stacking of all nanowires on the side of the ladder, a metal is defined by photolithography and evaporated to form a common electrode; 3) Deposit a gate dielectric layer on the entire sample surface, and define the gate patterns connected on all ladders by photolithography and evaporate metal to form a common gate for the input terminal of the logic device.

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