Gate structure profiles in semiconductor devices

Abstract

The invention discloses a gate structure profile in a semiconductor device. The invention discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; an isolation region disposed on the substrate and adjacent to the base structure; a nanostructure channel region disposed on the first substrate portion; a source / drain region disposed on the second substrate portion; a gate structure; and a gate spacer disposed along a sidewall of the gate structure and between the gate structure and the isolation region. The gate structure includes an outer gate portion and an inner gate portion, the outer gate portion including an outer gate portion including a tapered cross-sectional profile and disposed on the isolation region, and the inner gate portion including a non-tapered cross-sectional profile and disposed on the nanostructure channel region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to gate structure profiles in semiconductor devices. Background Art

[0002] As semiconductor technology develops, there is a growing demand for greater storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and gate-all-around field effect transistors (GAA FETs). This size reduction increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a base structure having a first base portion and a second base portion arranged on the substrate; an isolation region arranged on the substrate and adjacent to the base structure; a nanostructure channel region arranged on the first base portion; a source / drain region arranged on the second base portion; a gate structure comprising: an external gate portion comprising a tapered cross-sectional profile and arranged on the isolation region, and an internal gate portion comprising a non-tapered cross-sectional profile and arranged on the nanostructure channel region; and a gate spacer arranged along a sidewall of the gate structure and between the gate structure and the isolation region.

[0004] According to a second aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a base structure having a first base portion and a second base portion arranged on the substrate; a shallow trench isolation (STI) region arranged on the substrate; a nanostructure channel region arranged on the first base portion; a source / drain region arranged on the second base portion; and a gate structure comprising: a top gate portion arranged on the nanostructure channel region, and a bottom gate portion comprising: a first gate portion having a rectangular cross-sectional profile arranged on the first base portion; and a second gate portion having a conical cross-sectional profile arranged on the first base portion.

[0005] According to a third aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a base structure on a substrate; forming a shallow trench isolation (STI) region on the substrate; forming a sacrificial gate structure on the superlattice structure, the sacrificial gate structure having a second gate portion and a first gate portion suspended on the STI region; forming a gate spacer along a sidewall of the sacrificial gate structure and between the sacrificial gate structure and the STI region; and replacing the sacrificial gate structure and the sacrificial nanostructure layer with a gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1A An isometric view of a semiconductor device having a gate structure with a tapered cross-sectional profile is shown in accordance with some embodiments.

[0008] Figure 1B A top view of a semiconductor device having a gate structure with a tapered cross-sectional profile is shown in accordance with some embodiments.

[0009] Figure 2A-2C , Figures 3A-3C and Figures 4A-4C Different cross-sectional views of a semiconductor device including a gate structure having a tapered cross-sectional profile are illustrated in accordance with some embodiments.

[0010] Figure 5 is a flow chart of a method of fabricating a semiconductor device having a gate structure with a tapered cross-sectional profile according to some embodiments.

[0011] Figure 6 , Figures 7A-7D , Figures 8A-8D , Figures 9A-9D , Figures 10A-10D , Figures 11A-11D , Figures 12A-12C , Figures 13A-13C , Figures 14A-14C and Figures 15A-15C Isometric and cross-sectional views of a semiconductor device including a gate structure having a tapered cross-sectional profile at different stages of its fabrication process are shown in accordance with some embodiments.

[0012] Fig.16 is a flow chart of a method of fabricating another semiconductor device including a gate structure having a tapered cross-sectional profile, according to some embodiments.

[0013] Figures 17A-17D , Figures 18A-18D , Figures 19A-19D , Figures 20A-20D , Figures 21A-21C , Figures 22A-22C , Figures 23A-23C , Figures 24A-24C and Figures 25A-25C Isometric and cross-sectional views of a semiconductor device including a gate structure having a tapered cross-sectional profile at different stages of its fabrication process are shown in accordance with some embodiments.

[0014] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature and the second feature are formed in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, spatially relative terms (e.g., "below," "beneath," "lower," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0017] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0018] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of the specification is interpreted by persons skilled in the relevant art(s) based on the teachings herein.

[0019] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0020] The GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning processes or multiple patterning processes. The double patterning process or multiple patterning process can combine the photolithography process and the self-alignment process, thereby allowing a pattern to be created with a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA transistor structure.

[0021] The fin structure disclosed herein can be patterned by any suitable method. For example, the fin structure can be patterned using one or more photolithography processes (including double patterning processes or multiple patterning processes). The double patterning process or the multiple patterning process can combine the photolithography process and the self-alignment process, thereby allowing the pattern to be created with a pitch smaller than the pitch obtainable using a single direct photolithography process. For example, a sacrificial layer is formed on top of the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fin structure.

[0022] The GAA FET may include: a base structure (also referred to as a "sheet base" and a "fin base") disposed on a substrate, a shallow trench isolation (STI) region disposed adjacent to the base structure and on the substrate, a source / drain (S / D) region disposed on the substrate, a nanostructure channel region disposed on the base structure and between the S / D regions, and a gate structure (also referred to as a "GAA structure") surrounding each nanostructure channel region. The GAA structure includes an external gate portion disposed on the STI region and an internal gate portion disposed on the nanostructure channel region. The internal gate portion includes a top gate portion disposed on the topmost nanostructure channel region and a bottom gate portion disposed between the base structure and the bottommost nanostructure channel region.

[0023] One of the challenges in forming a GAA structure is to prevent the bottom gate portion from extending into the substrate structure during the formation of the GAA structure, which causes the bottom gate portion to be close to the S / D region and increases the parasitic capacitance in the GAA FET. Since a trench is formed in the substrate structure during the formation of the GAA structure in the gate replacement process, the bottom gate portion extends into the substrate structure. The gate replacement process includes: forming a sacrificial gate structure (also called a "dummy gate structure"), a portion of which is located on the STI region; etching the sacrificial gate structure to form a gate opening; and forming the GAA structure in the gate opening. During the etching of the sacrificial gate structure, the STI region below the sacrificial gate structure is etched, which causes the substrate structure adjacent to the STI region to be etched and a trench is formed in the substrate structure.

[0024] To overcome the above challenges, the present disclosure provides an example structure and method for improving the bottom surface profile of the bottom gate portion of the GAA structure, which increases the spacing between the bottom gate portion and the S / D region. Increasing the spacing between the bottom gate portion and the S / D region can reduce or minimize the parasitic capacitance in the GAA FET, which can improve the reliability and performance of the GAA FET. In some embodiments, the portion of the sacrificial gate structure on the STI region can be separated by a spacer to prevent etching of the STI region during the removal of the sacrificial gate structure. Preventing etching of the STI region can prevent etching of the substrate structure and the formation of trenches in the substrate structure. Therefore, the bottom gate portion can form a substantially flat bottom surface profile. In some embodiments, the portion of the sacrificial gate structure directly located on the STI region can form a tapered cross-sectional profile to prevent or minimize etching of the STI region when removing the sacrificial gate structure. Therefore, it is possible to prevent the formation of trenches in the substrate structure, or to form narrow trenches in the substrate structure. In some embodiments, the trench can be narrower than the trench formed by the sacrificial gate structure having a non-tapered (e.g., rectangular) cross-sectional profile on the STI region. Therefore, by modifying the profile of the sacrificial gate structure portion on the STI region, the bottom surface profile of the bottom gate portion can be improved to reduce or minimize the parasitic capacitance in the GAA FET.

[0025] Figure 1A An isometric view of a semiconductor device 100 is shown, which may represent a GAA FET 100 , in accordance with some embodiments. Figure 1B A top view of a GAA FET 100 is shown, in accordance with some embodiments. Figure 2A , Figure 3A and Figure 4A GAA FET 100 is shown along the Figure 1A and Figure 1B Different cross-sectional views of the line AA of FIG. 1 , which have been shown for simplicity in FIG. Figure 1A and Figure 1B Additional structure not shown. Figure 2B , 3B 4B shows a GAAFET 100 along the Figure 1A and Figure 1B Different cross-sectional views of the line BB, which have been Figure 1A and Figure 1B Additional structure not shown. Figure 2C , Figure 3C and Figure 4C GAA FET 100 is shown along the Figure 1A and Figure 1B Different cross-sectional views of line CC, with the Figure 1A and Figure 1B Unless otherwise mentioned, the Figure 1A , Figure 1B , Figure 2A-2C , Figures 3A-3C and Figures 4A-4C Discussions of elements with the same annotation apply to each other.

[0026] refer to Figure 1A , Figure 1B and Figure 2A-2C In some embodiments, the GAA FET 100 may include (i) a substrate 102, (ii) an STI region 104 disposed on the substrate 102, (iii) a fin-shaped base structure 106 (also referred to as a "sheet base 106" or a "fin base 106") disposed on the substrate 102, (iv) a nanostructure channel region 208 disposed on the base structure 106, (v) an S / D region 110 disposed adjacent to the nanostructure channel region 208, (vi) an isolation structure 111, (vii) a gate structure 112 (also referred to as a "GAA structure 112") surrounding the nanostructure channel region 208, (viii) an external gate spacer 114, (ix) a barrier layer 115, (x) an internal gate spacer 216, (xi) an etch stop layer (ESL) 118 disposed directly on the S / D region 110, and (xii) an interlayer dielectric (ILD) layer 120 disposed directly on the ESL 118. Depending on the context, each region in the S / D region 110 may be referred to individually or collectively as a source or a drain. For simplicity, Figure 1B The barrier layer 115 , the ESL 118 , and the ILD layer 120 are not shown.

[0027] In some embodiments, the substrate 102 may be a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, the substrate 102 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, the STI region 104 may include an insulating material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide (SiGeO2). x ). In some embodiments, base structure 106 may include a similar material as substrate 102. Base structure 106 may have elongated sides extending along the X-axis.

[0028] In some embodiments, the nanostructure channel region 208 can be a nanosheet, nanowire, nanorod, nanotube or other suitable nanostructure shape. As used herein, the term "nanostructure" defines a structure, layer and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm or other values ​​less than about 100 nm. The nanostructure channel region 208 can include a semiconductor material similar to or different from the substrate 102. In some embodiments, the nanostructure channel region 208 can include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium antimony boron (SiGeSnB), III-V semiconductor compounds or other suitable semiconductor materials. In some embodiments, the thickness of each nanostructure channel region 208 along the Z-axis can be about 3 nm to about 15 nm. Although three nanostructure channel regions 208 are shown below each gate structure 112, the GAA FET 100 may have any number of nanostructure channel regions 208. Although rectangular cross-sections of the nanostructure channel regions 208 are shown, the cross-sections of the nanostructure channel regions 208 may be other geometric shapes (e.g., circular, elliptical, triangular, or polygonal).

[0029] In some embodiments, the S / D region 110 may be disposed above the substrate structure 106 and electrically isolated from the substrate structure 106 by the isolation structure 111. In some embodiments, each S / D region 110 may include S / D sub-regions 110A and 110B. , and may also be epitaxially grown on the sidewalls of the nanostructure channel region 208. In some embodiments, each S / D sub-region 110A may have a D-shaped cross-sectional profile and a curved sidewall in contact with the S / D sub-region 110B. The number of S / D sub-regions 110A in each S / D region 110 may be equal to the number of nanostructure channel regions 208 facing each S / D region 110. For example, as Figure 2A As shown, each S / D region 110 includes six S / D sub-regions 110A, which is equivalent to six nanostructure channel regions 208 facing each S / D region 110 .

[0030] In some embodiments, each S / D sub-region 110B may include: (i) a first portion disposed directly on the S / D sub-region 110A and epitaxially grown, and (ii) a second portion disposed directly on the sidewall of the internal gate spacer 216 and located between adjacent S / D sub-regions 110A. The second portion of the S / D sub-region 110B may be formed by merging the first portions of adjacent S / D sub-regions 110B. In some embodiments, an air gap (not shown) may exist between the sidewall of the internal gate spacer 216 and the second portion of the S / D sub-region 110B.

[0031] In some embodiments, for n-type GAA FET 100, S / D sub-regions 110A and 110B may include epitaxially grown Si without any Ge atoms and may differ from each other based on n-type dopant (e.g., phosphorus atoms) concentration. For example, the n-type dopant concentration in S / D sub-region 110B may be higher than the n-type dopant concentration in S / D sub-region 110A. The higher dopant concentration in S / D sub-region 110B may reduce the contact resistance between S / D region 110 and S / D contact structure (not shown). In some embodiments, S / D sub-region 110A may be undoped. In some embodiments, S / D sub-region 110B may include approximately 1×10 21 Atom / cm 3 About 4×10 21 Atom / cm 3 of phosphorus doping concentration.

[0032] In some embodiments, for a p-type GAA FET 100, the S / D sub-region 110A may include epitaxially grown Si without any Ge atoms, and the S / D sub-region 110B may include epitaxially grown SiGe. In some embodiments, the S / D sub-region 110B may include a Ge atomic concentration of about 45 atomic % to about 60 atomic %, with any remaining atomic % being Si atoms. In some embodiments, for a p-type GAA FET 100, the S / D sub-regions 110A and 110B may differ from each other based on a p-type dopant (e.g., boron atoms) concentration. For example, the p-type dopant concentration of the S / D sub-region 110B may be higher than the p-type dopant concentration in the S / D sub-region 110A. In some embodiments, the S / D sub-region 110A may be undoped. In some embodiments, the S / D sub-region 110B may include about 8×10 20 Atom / cm 3 About 3×10 21 Atom / cm 3 of boron doping concentration.

[0033] In some embodiments, the isolation structure 111 may be disposed below the S / D region 110 and in a recessed region of the substrate structure 106. The recessed region in the substrate structure 106 may be formed during the formation of the S / D region 110, as described in detail below. The isolation structure 111 may prevent the S / D region 110 from epitaxially growing on the substrate structure 106 and prevent dopants from diffusing from the S / D region 110 to the substrate structure 106, thereby preventing current leakage between adjacent S / D regions 110 and short channel effects in the GAA FET 100. In some embodiments, each isolation structure 111 may include an undoped semiconductor layer 111A and a dielectric layer 111B.

[0034] In some embodiments, the undoped semiconductor layer 111A may be disposed in a recessed region of the base structure 106. In some embodiments, the undoped semiconductor layer 110A may include undoped silicon or other suitable undoped semiconductor materials. In some embodiments, the undoped semiconductor layer 111A may extend into the base structure 106 by a distance of about 20 nm to about 40 nm. In some embodiments, if the distance is less than about 20 nm, the undoped semiconductor layer 111A may not adequately prevent dopants from diffusing from the S / D region 110 to the base structure 106. On the other hand, if the distance is greater than about 40 nm, the processing time (e.g., etching time, deposition time) for forming the undoped semiconductor layer 111A may increase, thereby increasing the manufacturing cost of the GAA FET 100.

[0035] In some embodiments, the dielectric layer 111B may be directly disposed on the undoped semiconductor layer 111A and disposed along the sidewalls of the recessed region in the base structure 106. In some embodiments, each dielectric layer 111B may include a nitride material, such as SiN, SiON, SiCON, and SiCN. In some embodiments, each dielectric layer 111B may include a silicon-rich dielectric material. In some embodiments, the silicon-rich dielectric material may include: (i) a silicon-rich nitride (SiN) having a silicon atomic concentration higher than a nitrogen atomic concentration; x N y ); (ii) silicon-rich oxynitride (Si x O y N z ); (iii) silicon-rich carbon oxides (Si x O y C z ); (iv) silicon-rich carbon nitride oxides (Si w O x C yN z (v) silicon-rich boron oxynitride (Si w B x O y N z ), (vi) silicon-rich carbon-boron oxide (Si w B x O y C z ), or (vii) other suitable silicon-rich nitride or carbide-based dielectric materials. The silicon-rich dielectric material of the dielectric layer 111B may provide high etching resistance to the dielectric layer 111B during the formation of the dielectric layer 111B.

[0036] Each gate structure 112 may be a multi-layer structure and may include: (i) an interface oxide (IL) layer 112A, (ii) a high-K (HK) gate dielectric layer 112B, (iii) a work function metal (WFM) layer 112C, and (iv) a gate metal fill layer 112D. In some embodiments, the IL layer 112A may be directly disposed on the topmost nanostructure channel region 208. In some embodiments, the IL layer 112A may include SiO2, SiGeO x or germanium oxide (GeO x ), and may have a thickness of about 0.5 nm to about 1 nm. In some embodiments, the HK gate dielectric layer 112B may be directly disposed on the IL layer 112A, and may include a high-K dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). In some embodiments, the sidewalls of the HK gate dielectric layer 112B may contact the sidewalls of the external gate spacer 114.

[0037] The WFM layer 112C may be disposed on the HK gate dielectric layer 112B. In some embodiments, for a p-type GAA FET 100, the WFM layer 112C may include a Ti-based or Ta-based nitride or alloy that is substantially free of Al (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu) alloy. In some embodiments, for an n-type GAA FET 100, the WFM layer 112C may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), titanium aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. The gate metal fill layer 112D may be disposed on the WFM layer 112C. In some embodiments, the gate metal filling layer 112D may include a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), metal alloys and combinations thereof.

[0038] Each gate structure 112 may have a pair of outer gate portions 112S (eg, Figure 1A , Figure 1B , Figure 2B and Figure 2C shown in Figure 2A ) and an internal gate portion 112N (not visible in the cross-sectional view of FIG. 1 ) between a pair of external gate portions 112S (as shown in FIG. 1 ). Figure 1A , Figure 1B , Figure 2A and Figure 2C shown in Figure 2B In some embodiments, each external gate portion 112S may be disposed on the STI region 104 but not in direct contact with the STI region 104. The external gate portion 112S may be separated from the STI region 104 by a portion of the external gate spacer 114. Each external gate portion 112S may have an upper gate portion 112SU and a lower gate portion 112SL. In some embodiments, each upper gate portion 112SU may have: (i) a rectangular cross-sectional profile along the X-axis (e.g., Figure 2B); (ii) substantially linear sidewalls; (iii) a width W1 of about 9 nm to about 12 nm. In some embodiments, each lower gate portion 112SL may have: (i) a tapered cross-sectional profile (e.g., a V-shaped cross-sectional profile) along the X-axis; (ii) an inclined sidewall; (iii) an angle between the inclined sidewall and the top surface 104t of the STI region 104 of about 70 degrees to about 80 degrees; (iv) a width W2 of about 5 nm to about 8 nm in the middle region of the lower gate portion 112SL. In some embodiments, a portion of the HK gate dielectric layer 112B in the upper gate portion 112SU may have substantially linear sidewalls, and a portion of the HK gate dielectric layer 112B in the lower gate portion 112SL may have an inclined sidewall and a V-shaped cross-sectional profile along the X-axis.

[0039] In some embodiments, Figure 2A As shown, each internal gate portion 112N may have a top gate portion 212Nt and a bottom gate portion 212Nb. The top gate portion 212Nt may be disposed on and in contact with the topmost nanostructure channel region 208. In some embodiments, each top gate portion 212Nt may have (i) a rectangular cross-sectional profile along the X-axis, (ii) a substantially linear sidewall, and (iii) a width W1 of about 9 nm to about 12 nm. The bottom gate portion 212Nb may be disposed between the bottommost nanostructure channel region 208 and the base structure 106. In some embodiments, each bottom gate portion 212Nb may have (i) a rectangular cross-sectional profile along the X-axis and (ii) a substantially linear bottom surface in contact with the top surface of the base structure 106. The substantially linear profile of the bottom surface of the bottom gate portion 212Nb may depend on the structural profile of the lower gate portion 112SL.

[0040] Forming the lower gate portion 112SL having a tapered cross-sectional profile and being separated from the STI region 104 can prevent a trench (eg, Figure 2A104 ), as discussed in detail below. The trench (e.g., trench 122 in the substrate structure of other GAA FETs) is formed during the formation of a gate portion having a non-tapered cross-sectional profile (e.g., a rectangular cross-sectional profile) on the STI region. Preventing the formation of such a trench in the region of the substrate structure 106 below the nanostructure channel region 208 can prevent the bottom gate portion 212Nb from extending into the substrate structure 106, thereby reducing the spacing between the gate structure 112 and the S / D region 110 and increasing the parasitic capacitance of the GAA FET 100. Therefore, forming the lower gate portion 112SL having a tapered cross-sectional profile and separated from the STI region 104 facilitates forming a substantially linear profile of the bottom surface of the bottom gate portion 212Nb.

[0041] In some embodiments, the portion of the HK gate dielectric layer 112B in the top gate portion 212Nt may have a U-shaped cross-sectional profile along the X-axis. In some embodiments, the portion of the HK gate dielectric layer 112B in the bottom gate portion 212Nb may have a rectangular ring-shaped cross-sectional profile along the X-axis. In some embodiments, the portion of the HK gate dielectric layer 112B in the inner gate portion 212Nb may have a rectangular ring-shaped cross-sectional profile along the Y-axis. Figure 2C As shown, the portion of the HK gate dielectric layer 112B on the base structure 106 in the inner gate portion 112N may be disposed at a lower surface plane than the portion of the HK gate dielectric layer 112B disposed on the STI region 104 in the outer gate portion 112S. Figure 2C As shown, a top surface of a region of the base structure 106 beneath the nanostructure channel region 208 and a top surface 104 t of the STI region 104 may be substantially coplanar with one another.

[0042] The external gate spacers 114 electrically isolate the gate structure 112 from the adjacent S / D regions 110 and other adjacent structures (e.g., S / D contact structures (not shown)). In some embodiments, each external gate spacer 114 may include a dielectric material, such as SiO2, SiN, SiON, SiCN, and SiOCN. In some embodiments, each external gate spacer 114 may have an outer sidewall having a substantially linear profile facing away from the gate structure 112 and an inner sidewall having a V-shaped cross-sectional profile facing the gate structure 112. In some embodiments, each external gate spacer 114 may have a pair of external spacer portions 114S (e.g., Figure 1A , Figure 1B , Figure 2B and Figure 2C shown in Figure 2A) and an inner spacer portion 114N (not visible in the cross-sectional view of FIG. 1 ) located between a pair of outer spacer portions 112S (as shown in FIG. 1 ). Figure 1A , Figure 1B , Figure 2A and Figure 2C shown in Figure 2B not visible in the cross-section view).

[0043] In some embodiments, each inner spacer portion 114N may be disposed along the sidewall of the top gate portion 212Nt and on the topmost nanostructure channel region 208, and may have a thickness T1 of about 6 nm to about 8 nm. In some embodiments, each outer spacer portion 114S may be disposed directly on the STI region 104 and may surround the outer gate portion 112S. Each outer spacer portion 114S may have an upper spacer portion 114SU and a lower spacer portion 114SL. In some embodiments, each upper spacer portion 114SU may have: (i) a rectangular cross-sectional profile along the X-axis (e.g., Figure 2B 112SL); (ii) a substantially linear sidewall disposed along the sidewall of the upper gate portion 112SU; and (iii) a thickness T1 of about 6 nm to about 8 nm. In some embodiments, each lower spacer portion 114SL may have (i) a substantially linear outer sidewall facing away from the lower gate portion 112SL, (ii) an inclined inner sidewall facing and contacting the lower gate portion 112SL, and (iii) a thickness T2 of about 30 nm to about 35 nm. Such a profile and size of the outer spacer portion 114S facilitates forming a lower gate portion 112SL having a tapered cross-sectional profile, as discussed in detail below.

[0044] The internal gate spacers 216 can electrically isolate the gate portion between the nanostructure channel regions 208 and the bottom gate portion 212Nb from the adjacent S / D regions 110. In some embodiments, each internal gate spacer 216 can have a height of about 3 nm to about 20 nm and a thickness of about 1 nm to about 10 nm. Within these height and thickness ranges, the internal gate spacers 216 can sufficiently electrically isolate the gate portion from the adjacent S / D regions 110 without affecting device size and manufacturing cost.

[0045] In some embodiments, the ESL 118 may be disposed directly on the S / D region 110. In some embodiments, the ESL 118 may have a dielectric constant of about 4 to about 7 and may include dielectric materials such as lanthanum oxide (LaO), aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum carbon nitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), aluminum oxynitride (AlON), SiO2, SiC, SiN, and zinc oxide (ZnO). In some embodiments, the ILD layer 120 may be disposed directly on the ESL 118. In some embodiments, the ILD layer 120 may include insulating materials such as SiO2, SiN, SiON, SiCN, and SiOCN.

[0046] refer to Figures 3A-3C In some embodiments, the GAA FET 100 may have a gate structure 312 and an external gate spacer 314 instead of the gate structure 112 and the external gate spacer 114. Unless otherwise mentioned, the discussion about the gate structure 112 and the external gate spacer 114 applies to the gate structure 312 and the external gate spacer 314. Similar to the gate structure 112, each gate structure 312 may be a multi-layer structure and may include (i) an IL layer 312A, (ii) a HK gate dielectric layer 312B, (iii) a WFM layer 312C, and (iv) a gate metal filling layer 312D. Unless otherwise mentioned, the discussion about the IL layer 112A, the HK gate dielectric layer 112B, the WFM layer 112C, and the gate metal filling layer 112D applies to the IL layer 312A, the HK gate dielectric layer 312B, the WFM layer 312C, and the gate metal filling layer 312D, respectively.

[0047] Each gate structure 312 may have a pair of outer gate portions 312S and an inner gate portion 312N located between the pair of outer gate portions 312S. In some embodiments, each outer gate portion 312S may be disposed directly on the STI region 104. Each outer gate portion 312S may have an upper gate portion 312SU and a lower gate portion 312SL. In some embodiments, each upper gate portion 312SU may have (i) a rectangular cross-sectional profile along the X-axis (e.g., Figure 3B), (ii) substantially linear sidewalls, and (iii) a width W1 of about 9 nm to about 12 nm. In some embodiments, each lower gate portion 312SL may have: (i) a tapered cross-sectional profile along the X-axis; (ii) an inclined sidewall; (iii) an angle between the inclined sidewall and the top surface 104t of the STI region 104 of about 70 degrees to about 80 degrees, (iv) a substantially linear bottom surface 312Bs in contact with the top surface 104t of the STI region 104, (v) a width W2 of about 5 nm to about 8 nm in a middle region of the lower gate portion 312SL, and (vi) a width W3 of about 0 nm to about 3 nm of the bottom surface 312Bs. In some embodiments, a portion of the HK gate dielectric layer 312B in the upper gate portion 312SU may have substantially linear sidewalls, and a portion of the HK gate dielectric layer 312B in the lower gate portion 312SL may have inclined sidewalls and a substantially linear bottom surface in contact with the top surface 104t of the STI region 104.

[0048] In some embodiments, each internal gate portion 312N may have a top gate portion 312Nt and a bottom gate portion 312Nb. Unless otherwise noted, the discussion regarding the top gate portion 212Nt and the bottom gate portion 212Nb applies to the top gate portion 312Nt and the bottom gate portion 312Nb. Similar to the bottom gate portion 212Nb, the substantially linear profile of the bottom surface of the bottom gate portion 312Nb may depend on the structural profile of the lower gate portion 312SL. Even though the lower gate portion 312SL contacts the STI region 104, unlike the lower gate portion 112SL, the tapered cross-sectional profile of the lower gate portion 312SL may prevent the formation of trenches (e.g., Figure 3A In some embodiments, a gate structure 312 having a lower gate portion 312SL in contact with the STI region 104 may be formed in the GAA FET 100 instead of the gate structure 112 to reduce the etching time during the gate replacement process, thereby reducing the manufacturing cost of the GAA FET 100, as discussed in detail below.

[0049] In some embodiments, Figure 3C As shown, the portion of the HK gate dielectric layer 312B on the base structure 106 in the inner gate portion 312N and the portion of the HK gate dielectric layer 312B on the STI region 104 in the outer gate portion 312S may be substantially coplanar with each other. Figure 3CAs shown, a top surface of a region of the base structure 106 beneath the nanostructure channel region 208 and a top surface 104 t of the STI region 104 may be substantially coplanar.

[0050] In some embodiments, each external gate spacer 314 may have a pair of external spacer portions 314S and an internal spacer portion 314N between the pair of external spacer portions 312S. In some embodiments, each internal spacer portion 314N may be disposed along the sidewall of the top gate portion 312Nt and in the topmost nanostructure channel region 208, and may have a thickness T1 of about 6 nm to about 8 nm. In some embodiments, each external spacer portion 314S may be disposed directly on the STI region 104 and along the sidewall of the external gate portion 312S. Each external spacer portion 314S may have an upper spacer portion 314SU and a lower spacer portion 314SL. In some embodiments, each upper spacer portion 314SU may have (i) a rectangular cross-sectional profile along the X-axis (e.g., Figure 3B 312SL), (ii) a substantially linear sidewall disposed along the sidewall of the upper gate portion 312SU, and (iii) a thickness T1 of about 6 nm to about 8 nm. In some embodiments, each lower spacer portion 314SL may have (i) a substantially linear outer sidewall facing away from the lower gate portion 312SL, (ii) an inclined inner sidewall facing and contacting the lower gate portion 312SL, and (iii) a thickness T3 of about 15 nm to about 17 nm. Such a profile and size of the outer spacer portion 314S facilitates forming a lower gate portion 312SL having a tapered cross-sectional profile, as described in detail below.

[0051] refer to Figures 4A-4C In some embodiments, the GAA FET 100 may have a gate structure 412 instead of the gate structures 112 or 312. Unless otherwise mentioned, the discussion about the gate structure 112 applies to the gate structure 412 and the external gate spacer 314. Similar to the gate structure 112, each gate structure 412 may be a multi-layer structure and may include: (i) an IL layer 412A, (ii) a HK gate dielectric layer 412B, (iii) a WFM layer 412C, and (iv) a gate metal filling layer 412D. Unless otherwise mentioned, the discussion of the IL layer 112A, the HK gate dielectric layer 112B, the WFM layer 112C, and the gate metal filling layer 112D applies to the IL layer 412A, the HK gate dielectric layer 412B, the WFM layer 412C, and the gate metal filling layer 412D, respectively.

[0052] Each gate structure 412 may have a pair of outer gate portions 412S and an inner gate portion 412N between the pair of outer gate portions 412S. Figure 4B As shown, each external gate portion 412S may extend into the STI region 104 by a distance D1. Each external gate portion 412S may have an upper gate portion 412SU and a lower gate portion 412SL. In some embodiments, each upper gate portion 412SU may have: (i) a rectangular cross-sectional profile along the X-axis (e.g., Figure 4B 104 ); (ii) substantially linear sidewalls; and (iii) a width W1 of about 9 nm to about 12 nm. In some embodiments, each lower gate portion 412SL may have a V-shaped cross-sectional profile along the X-axis that extends a distance D1 into the STI region 104. In some embodiments, each lower gate portion 412SL may have: (i) a first portion 412S1 having a tapered cross-sectional profile along the X-axis, the first portion 412S1 being disposed on the top surface 104t of the STI region 104; (ii) a second portion 412S2 having a V-shaped cross-sectional profile along the X-axis; (iii) inclined sidewalls of the first portion 412S1 and the second portion 412S2, (iv) an angle between the inclined sidewalls and the top surface 104t of the STI region 104 of about 70 degrees to about 80 degrees, and (iv) a width W2 of about 5 nm to about 8 nm in a middle region of the lower gate portion 412SL. In some embodiments, a portion of the HK gate dielectric layer 412B in the upper gate portion 412SU may have substantially linear sidewalls, and a portion of the HK gate dielectric layer 412B in the lower gate portion 412SL may have sloped sidewalls and may extend a distance D1 into the STI region 104 .

[0053] In some embodiments, each internal gate portion 412N may have a top gate portion 412Nt and a bottom gate portion 412Nb. Unless otherwise mentioned, the discussion about the top gate portion 212Nt applies to the top gate portion 412Nt. Unlike the bottom gate portion 212Nb, each bottom gate portion 412Nb may have: (i) a first portion 412Nb1 having a rectangular cross-sectional profile along the X-axis, the first portion 412Nb1 being disposed on the top surface of the base structure 106; (ii) a U-shaped cross-sectional profile along the X-axis (such as Figure 4A The second portion 412Nb2 may have a V-shaped cross-sectional profile (not shown) or a V-shaped cross-sectional profile (not shown), and the second portion 412Nb2 extends below the top surface of the substrate structure 106 to a distance D2 of about 2 nm to about 4 nm. In some embodiments, the distance D2 may be equal to or greater than the distance D1. The structural profile of the second portion 412Nb2 may depend on the structural profile of the lower gate portion 412SL.

[0054] Since the lower gate portion 412SL is formed to have a tapered cross-sectional profile, it is different from the gate portion (e.g., Figure 4A Compared with the gate portion 422 shown by the dashed line in the middle, the second portion 412Nb2 formed in the substrate structure 106 has a narrower cross-sectional profile along the X axis (eg, Figure 4A ). The narrower cross-sectional profile of the second portion 412Nb2 can enable the horizontal spacing S1 between the second portion 412Nb2 and the adjacent S / D region to reach about 9 nm to about 14 nm, which is greater than the horizontal spacing S1 of about 3 nm to about 8 nm achieved between the gate portion 422 and the S / D region in other GAA FETs. This increase in the horizontal spacing S1 can lead to a reduction in parasitic capacitance in the GAA FET 100.

[0055] In addition to the narrower cross-sectional profile, due to the formation of the lower gate portion 412SL having a tapered cross-sectional profile, the second portion 412Nb2 in the base structure 106 can form a shallower depth profile than the gate portion 422. The distance D2 that the second portion 412Nb2 extends into the base structure 106 is about 2nm to about 4nm, while the distance that the gate portion 422 extends into the base structure of other GAA FETs is about 8nm to about 10nm. Therefore, using the gate structure 412 having a tapered gate portion (e.g., the lower gate portion 412SL) on the STI region 104 can reduce the volume of the gate portion (e.g., the second portion 412Nb2) in the base structure 106, thereby reducing the parasitic capacitance of the GAA FET 100. In some embodiments, a gate structure 412 having a lower gate portion 412SL extending into the STI region 104 may be formed in the GAA FET 100 instead of the gate structure 112 or 312, as a result of forming the gate structure 412 having a higher aspect ratio than the gate structure 112 or 312, as discussed in detail below. Figure 4A As shown, the IL layer 412A, the HK gate dielectric layer 412B, the WFM layer 412C, and the gate metal filling layer 412D in the second portion 412Nb2 may have a U-shaped or V-shaped cross-sectional profile along the X-axis.

[0056] Figure 5 According to some embodiments, a method for manufacturing a Figure 1A , Figure 1B and Figure 2A-2C Flowchart of an example method 500 of GAA FET 100 with isometric, top, and cross-sectional views. For illustration purposes, reference will be made to Figure 6 , Figures 7A-7D , Figures 8A-8D , Figures 9A-9D , Figures 10A-10D , Figures 11A-11D , Figures 12A-12C , Figures 13A-13C , Figures 14A-14C and Figures 15A-15C The example manufacturing process for manufacturing the GAA FET 100 is described in detail in Figure 5 The operations shown in . Figure 6 , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A and Fig.11A is an isometric view of a GAA FET 100 at various stages of its fabrication, according to some embodiments. Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12A , Fig.13A , Fig.14A and Fig.15A is a GAA FET 100 at different stages of its fabrication according to some embodiments. Figure 1A , Figure 1B , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A and Fig.11A Cross-sectional view along line AA. Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B The GAAFET 100 according to some embodiments is a GAAFET 100 at different stages of its manufacture. Figure 1A , Figure 1B , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A and Fig.11A A cross-sectional view along line BB. Fig.7D , Fig.8D , Fig.9D , Fig. 10D , Fig.11D , Fig. 12C , Fig. 13C , Fig. 14C and Fig. 15C The GAAFET 100 according to some embodiments is a GAAFET 100 at different stages of its manufacture. Figure 1A , Figure 1B , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A and Fig.11A 500 is a cross-sectional view of line CC. Depending on the specific application, the operations may be performed in a different order or not performed. It should be noted that method 500 may not produce a complete GAA FET 100. Therefore, it is understood that other processes may be provided before, during, and after method 500, and some of the other processes may only be briefly described here. Unless otherwise mentioned, Figure 1A , Figure 1B , Figure 2A-2C , Figure 6 , Figures 7A-7D , Figures 8A-8D , Figures 9A-9D , Figures 10A-10D , Figures 11A-11D , Figures 12A-12C , Figures 13A-13C , Figures 14A-14C and Figures 15A-15C Discussions of elements with the same annotation apply to each other.

[0057] refer to Figure 5 In operation 505, a superlattice structure having a nanostructure layer and a nanostructure sacrificial layer is formed on a base structure on a substrate. Figure 6 As described, a superlattice structure 607 (also referred to as a "nanosheet stack 607") is formed on the fin-like base structure 106, which is formed on the substrate 102. The superlattice structure 607 may include nanostructure layers 208 and nanostructure sacrificial layers 608 arranged in an alternating configuration. In some embodiments, the nanostructure layer 208 may include Si, and the nanostructure sacrificial layer 608 may include SiGe.

[0058] refer to Figure 5 In operation 510, an STI region is formed on the substrate adjacent to the base structure. Figure 6 As described above, an STI region 104 is formed on the substrate 102 adjacent to the base structure 106. In some embodiments, the formation of the STI region 104 may include the following sequential operations: (i) depositing a dielectric layer (not shown) having a material of the STI region 104 on the substrate 102 and the superlattice structure 607; (ii) performing a chemical mechanical polishing (CMP) process to coplanarize (not shown) the top surface of the dielectric layer and the superlattice structure 607; (iii) performing an etching process on the dielectric layer to form Figure 6 In some embodiments, top surfaces of the STI region 104 and the base structure 106 may be substantially coplanar.

[0059] refer to Figure 5In operation 515, a sacrificial gate structure is formed, wherein a first portion is located on the superlattice structure and a second portion is suspended on the STI region. Figures 7A-7D , Figures 8A-8D and Figures 9A-9D As described above, a sacrificial gate structure 812 is formed, the sacrificial gate structure 812 having an outer gate portion 812S suspended on the STI region 104 and an inner gate portion 812N on the superlattice structure 607. In some embodiments, the formation of the sacrificial gate structure 812 may include the following sequential operations: (i) Figure 6 The oxide layer 712A is deposited substantially as desired on the STI region 104 and the superlattice structure 607, as shown in FIG. Figures 7A-7D (ii) depositing an amorphous, polycrystalline or single crystal polysilicon layer 712B on the oxide layer 712A, as Figures 7A-7D (iii) depositing a nitride mask layer 712C on the polysilicon layer 712B, as shown; Figures 7A-7D iv) depositing an oxide mask layer 712D (eg, a SiO2 layer) on the nitride mask layer 712C, as shown Figures 7A-7D As shown; v) in Figures 7A-7D vi) performing photolithographic patterning on the structure (not shown); vi) Figures 7A-7D A first etching process is performed on the structure of to form a sacrificial gate structure 812 having an IL layer 812A, a polysilicon structure 812B, a nitride layer 812C and an oxide layer 812D, and a byproduct layer 824, as shown in FIG. Figures 8A-8D As shown; and vii) using hydrofluoric acid gas or solution Figures 8A-8D The structure of FIG. 1 is subjected to a second etching process (also referred to as a “cleaning process”) to remove the byproduct layer 824, forming a sacrificial gate structure 812, wherein the outer gate portion 812S is suspended on the STI region 104, and the inner gate portion 812N is directly located on the superlattice structure 607, as shown in FIG. Figures 9A-9D shown.

[0060] refer to Figures 8A-8D and Figures 9A-9DIn some embodiments, each external gate portion 812S may have (i) an upper gate portion 812SU having a first portion of a polysilicon structure 812B, a nitride layer 812C, and an oxide layer 812D; and (ii) a lower gate portion 812SL having a second portion of the polysilicon structure 812B. In some embodiments, the upper portion of the polysilicon structure 812B, the nitride layer 812C, and the oxide layer 812D in each upper gate portion 812SU may have (i) a rectangular cross-sectional profile along the X-axis; (ii) a substantially linear sidewall; and (iii) a width W1 of about 9 nm to about 12 nm. In some embodiments, the lower portion of the polysilicon structure 812B in each lower gate portion 812SL may have (i) a tapered cross-sectional profile (e.g., a V-shaped cross-sectional profile) along the X-axis; (ii) a sloped sidewall; (iii) an angle between the sloped sidewall and the top surface 104t of the STI region 104 of about 70 degrees to about 80 degrees; and (iv) a width W2 of about 5 nm to about 8 nm in the middle region of the lower portion of the polysilicon structure 812B. In some embodiments, each internal gate portion 812N may be disposed on and in contact with the topmost nanostructure layer 208 of the superlattice structure 607. In some embodiments, each internal gate portion 812N may have (i) a rectangular cross-sectional profile along the X-axis; (ii) a substantially linear sidewall; and (iii) a width W1 of about 9 nm to about 12 nm.

[0061] In some embodiments, depositing the oxide layer 712A in operation 515 may include: depositing the oxide layer 712A in a chemical vapor deposition (CVD) process at a temperature of about 650° C. to about 750° C. Figure 6 The structure is exposed to a precursor, such as tetraethylorthosilicate (TEOS), to deposit an oxide layer 712A (eg, SiO 2 ) of about 2 nm to about 4 nm.

[0062] In some embodiments, after the first etching process in operation 515, as shown in FIG. Fig. 8A , 8C 8D, the portion of the oxide layer 712A under the outer gate portion 812S can be completely removed, while the portion of the oxide layer 712A at the interface between the polysilicon structure 812B and the superlattice structure 607 is retained to form the IL layer 812A, as shown in FIG. Figure 8B and 8D In some embodiments, during the first etching process, a byproduct layer 824 may be formed on the exposed surfaces of the superlattice structure 607 and the STI region 104 and the sacrificial gate structure 812, as shown in FIG. Figures 8A-8DAs shown. In some embodiments, byproduct layer 824 may be formed as an etching byproduct, and the etching byproduct is generated by the reaction between the etching peeling material of oxide layer 712A, polysilicon layer 712B, nitride mask layer 712C, oxide mask layer 712D and the gas mixture used in the first etching process. In some embodiments, byproduct layer 824 may include silicon monoxide (SiO), byproducts of SiO and chlorine (Cl), byproducts of SiO and nitrogen (N), byproducts of SiO and argon (Ar), and / or products of SiO and hydrogen bromide (HBr). In some embodiments, as Fig. 9C and 9D As shown, after the byproduct layer 824 is removed during the second etching process, a gap 926 having a height H1 of about 2 nm to about 5 nm may be formed between the polysilicon structure 812B and the STI region 104 .

[0063] In some embodiments, the first etching process may include a plasma etching process using a mixed gas of an etching gas and a diluted carrier gas. In some embodiments, the etching gas may include Cl2, HBr, difluoromethane (CH2F2), fluoroform (CHF3), carbon tetrafluoride (CF4), chlorodifluoromethane (CHClF2), fluoromethane (CH3F), hexafluorocyclobutene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6) or hydrogen (H2). In some embodiments, the carrier gas may include an inert gas such as Ar, N2, helium (He) and neon (Ne). In addition, the mixed gas used in the plasma etching process may also include a passivation gas. In some embodiments, the passivation gas may include N2, O2, CO2, CH4, SO2, CO and / or SiCl4. The passivation gas may be used to change the etching selectivity of the polysilicon layer 712B along the height of the sacrificial gate structure 812 to achieve Figure 8C A cross-sectional profile of a polysilicon structure 812B having different widths (e.g., widths W1 and W2) along the height of the polysilicon structure 812B is shown. In some embodiments, the plasma etching process can be performed at a temperature of about 25° C. to about 200° C. and a pressure of about 1 mTorr to about 800 mTorr. The flow rates of the etching gas, the carrier gas, and the passivation gas can be about 20 standard cubic centimeters (sccm) per minute to about 3000 standard cubic centimeters (sccm). A plasma power of about 10 W to about 4000 W and a bias power of about 300 W to about 600 W can be used in the plasma etching process.

[0064] refer to Figure 5 In operation 520, an external gate spacer is formed on the sacrificial gate structure. Figures 10A-10D and Figures 11A-11DAs described, an external gate spacer 114 is formed on the sacrificial gate structure 812. In some embodiments, the formation of the external gate spacer 114 may include the following sequential operations: (i) Figures 9A-9D A dielectric layer 1014 having an external gate spacer 114 material is deposited on the structure, such as Figures 10A-10D (ii) performing an annealing process to densify the dielectric layer 1014; and (iii) performing an etching process on the densified dielectric layer 1014 to form an external gate spacer 114 having a structural profile, such as Figures 11A-11D shown.

[0065] In some embodiments, dielectric layer 1014 may be deposited in a plasma enhanced CVD (PECVD) process using a gas mixture of TEOS, H2, ammonia (NH3), N2, and / or O2 at a temperature of about 500° C. to about 600° C. During the PECVD process, a plasma power of about 100 W to about 300 W and a bias power of about 200 W to about 500 W may be used. In some embodiments, the bias voltage applied to substrate 102 during the PECVD process may be controlled to vary the deposition selectivity of dielectric layer 1014 along the height of sacrificial gate structure 812, thereby achieving Fig. 10C 812B. In some embodiments, the dielectric layer 1014 may have a thickness T1 around the upper portion of the polysilicon structure 812B in each upper gate portion 812SU. In some embodiments, as shown in FIG. Fig. 10A and 10C As shown, the thickness T4 of the dielectric layer 1014 around the lower portion of the polysilicon structure 812B in the lower gate portion 812SL may be greater than the thickness T1. In some embodiments, the dielectric layer 1014 around the tip of the polysilicon structure 812B in the lower gate portion 812SL may have a thickness T2 greater than the thicknesses T1 and T4, as shown in FIG. Fig. 10A and Fig. 10C In some embodiments, the bias voltage applied to the substrate 102 during the PECVD process can be controlled to fill the gap 926 (eg, Fig. 9C and 9D As shown), Fig. 10C and 10D shown.

[0066] refer to Figure 5 In operation 525, S / D openings and internal gate spacers are formed in the superlattice structure. Figures 12A-12CAs described, S / D openings 1210 and internal gate spacers 216 are formed in the superlattice structure 607. The formation of the internal gate spacers 216 may include the following sequential operations: (i) Figures 11A-11D An etching process is performed on the structure of the superlattice structure 607 to etch the portion of the superlattice structure 607 that is not covered by the sacrificial gate structure 812 and the external gate spacer 114, and form an opening 1210, such as Fig. 12A As shown (in Fig. 12B and 12C 1210); (ii) performing an etching process on the sidewalls of the nanostructure sacrificial layer 608 facing the opening 1210 to form an inner gate spacer opening (not shown); (iii) depositing a dielectric layer (not shown) to fill the inner gate spacer opening (on the sidewalls of the outer gate spacer 114 and the nanostructure layer 208, and on the top surfaces of the sacrificial gate structure 812, the outer gate spacer 114, and the base structure 106); and (iv) performing an etching process on the dielectric layer to form the inner gate spacer 216 and the barrier layer 115, as shown in FIG. Fig. 12A and 12B As shown ( Fig. 12C cross-section is not visible).

[0067] refer to Figure 5 In operation 530, an isolation structure and an S / D region are formed in the S / D opening. Figures 13A-13C As described, the isolation structure 111 and the S / D region 110 are formed in the S / D opening 1210. In some embodiments, the formation of the isolation structure 111 may include the following sequential operations: (i) epitaxially growing an undoped silicon layer on the exposed surface of the base structure 106 in the S / D opening 1210 to form an undoped semiconductor layer 111A, such as Fig.13A As shown (in Fig. 13B and Fig. 13C (ii) forming a dielectric layer 111A on the undoped semiconductor layer 111A, such as Fig.13A As shown (in Fig. 13B and 13C In some embodiments, the formation of the S / D region 110 may include: (i) epitaxially growing the S / D sub-region 110A on the sidewalls of the nanostructure layer 208, such as Fig.13A As shown (in Fig. 13B and 13C (ii) epitaxially growing the S / D sub-region 110B on the S / D sub-region 110A, as shown in FIG. Fig.13A After the S / D region 110 is formed, an ESL 118 and an ILD layer 120 may be formed, as shown in FIG. Fig.13A and13B As shown (in Fig. 13C not visible in the cross-section view).

[0068] refer to Figure 5 In operation 535, the sacrificial gate structure and the nanostructure sacrificial layer are replaced with a GAA structure. Figures 14A-14C As described in FIGS. 15A-15C , the sacrificial gate structure 812 and the nanostructure sacrificial layer 608 are replaced with the GAA structure 112. The formation of the GAA structure 112 may include the following sequential operations: (i) etching the sacrificial gate structure 812 and the nanostructure sacrificial layer 608 to form a gate opening 1412, as shown in FIGS. Figures 14A-14C (ii) the exposed region of the nanostructure layer 208 in the gate opening 1412 is oxidized to form an IL layer 112A, as shown in FIG. Fig.15A and 15C As shown (in Fig. 15B (iii) forming a HK gate dielectric layer 112B on the IL layer 112A, as shown in FIG. Figures 15A-15C (iv) forming a WFM layer 112C on the HK gate dielectric layer 112B, as shown Figures 15A-15C and (v) forming a conductive layer 112D on the WFM layer 112C, as shown; Figures 15A-15C shown.

[0069] In some embodiments, Fig. 14B As shown, the cross-sectional profile of the gate opening 1412 on the STI region 104 can be similar to the cross-sectional profile of the polysilicon structure 812B. Because the cross-sectional profile of the polysilicon structure 812B is tapered, the volume of the polysilicon structure 812B removed near the STI region 104 is smaller than that of the polysilicon structures in other GAAFETS whose cross-sectional profiles are not tapered. Therefore, unlike the etching process of the non-tapered polysilicon structure, the polysilicon structure 812B is not over-etched to ensure that the polysilicon structure 812B is completely removed. Over-etching of the non-tapered polysilicon structure results in the formation of trenches (such as Fig.14A The trench 122 shown in the dashed line in the middle) increases the parasitic capacitance in the GAA FET, as described above. Therefore, due to the tapered cross-sectional profile of the polysilicon structure 812B and the lower portion of the polysilicon structure 812B being separated from the STI region 104 by the external gate spacer 114, the gate opening 1412 can be prevented from extending into the STI region 104 and the base structure 106 during the etching process of the sacrificial gate structure 812.

[0070] Fig.16 According to some embodiments, a method for manufacturing a Figure 1A , 1B, 3A-3C and 4A-4C of the top view and cross-sectional view of the GAA FET 100. For the purpose of explanation, reference will be made to Figure 6 , 7A -7D, 17A-17D, 18A-18D, 19A-19D, 20A-20D, 21A-21C, 22A-22C, 23A-23C, 24A-24C, and 25A-25C are described with reference to an exemplary manufacturing process for manufacturing Fig.16 The operation shown. Figure 6 , 7A , 17A, 18A, 19A, and 20A are isometric views of a GAAFET 100 at different stages of its fabrication according to some embodiments. Figure 7B , 17B , 18B, 19B, 20B, 21A, 22A, 23A, 24A, and 25A are diagrams of GAA FET 100 at different stages of its manufacture according to some embodiments. Figure 1A , 1B , 7A, 17A, 18A, 19A and 20A, cross-sectional views along line AA. Figure 7C , 17C , 18C, 19C, 20C, 21B, 22B, 23B, 24B, and 25B are diagrams of GAA FET 100 at different stages of its manufacture according to some embodiments. Fig. 7A , 17A , 18A, 19A and 20A, cross-sectional views along line BB. Fig.7D , 17D , 18D, 19D, 20D, 21C, 22C, 23C, 24C, and 25C are diagrams of GAA FET 100 at different stages of its manufacture according to some embodiments. Fig. 7A , 17A , 18A, 19A and 20A. The operations may be performed in different orders or not performed depending on the specific application. It should be noted that method 1600 may not be able to manufacture a complete GAA FET 100. Therefore, it is understood that other processes may be provided before, during and after method 1600, and some of the other processes may only be briefly described here. Figure 1A , 1B, 2A-2C, 3A-3C, 4A-4C, 2A-2C, 6, 7A-7D, 8A-8D, 9A-9D, 10A-10D, 11A-11D, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 17A-17D, 18A-18D, 19A-19D, 20A-20D, 21A-21C, 22A-22C, 23A-23C, 24A-24C, and 25A-25C. Discussion of the same elements in the notes is applicable to each other unless otherwise noted.

[0071] See also Fig.16 , operations 1605 and 1610 with Figure 5 Operations 505 and 510 are similar. After operation 1610, the Figure 6 The structure is similar to the structure. As shown below Figures 7A-7D , 17A-17D and 18A-18D, in Figure 6 Executed on the structure Fig.16 Subsequent operations 1615.

[0072] refer to Fig.16 In operation 1615, a sacrificial gate structure is formed having a first portion directly on the superlattice structure and a second portion directly on the STI region. Figures 7A-7D , 17A-17D and 18A-18D, a sacrificial gate structure 1712 is formed, wherein an outer gate portion 1712S is directly located on the STI region 104 and an inner gate portion 1712N is located on the superlattice structure 607. In some embodiments, the formation of the sacrificial gate structure 1712 may include the following sequential operations: (i) Figure 6 The oxide layer 712A is deposited substantially as desired on the STI region 104 and the superlattice structure 607, such as Figures 7A-7D (ii) depositing an amorphous, polycrystalline or single crystal polysilicon layer 712B on the oxide layer 712A, as Figures 7A-7D (iii) depositing a nitride mask layer 712C (eg, a SiN layer) on the polysilicon layer 712B, as shown; Figures 7A-7D (iv) depositing an oxide mask layer 712D (eg, a SiO2 layer) on the nitride mask layer 712C, as shown; Figures 7A-7D shown; (v) in Figures 7A-7D vi) performing photolithographic patterning on the structure (not shown); vi) Figures 7A-7D A first etching process is performed on the structure of to form a sacrificial gate structure 1712 having an IL layer 1712A, a polysilicon structure 1712B, a nitride layer 1712C and an oxide layer 1712D, and a byproduct layer 1724, as shown in FIG. Figures 17A-17D as shown; and (vii) in Figures 17A-17D A second etching process is performed on the structure of HF acid gas or solution to remove the byproduct layer 1724 and form a sacrificial gate structure 1712, such as Figures 18A-18D As shown, the external gate portion 1712S is directly located on the STI region 104, and the internal gate portion 1712N is directly located on the superlattice structure 607, as shown in FIG. Figures 17A-17D shown.

[0073] refer to Figures 17A-17D and Figures 18A-18D In some embodiments, each external gate portion 1712S may have (i) an upper gate portion 1712SU having a first portion of a polysilicon structure 1712B, a nitride layer 1712C, and an oxide layer 1712D, and (ii) a lower gate portion 1712SL having a second portion of the polysilicon structure 1712B. In some embodiments, an upper portion of the polysilicon structure 1712B, the nitride layer 1712C, and the oxide layer 1712D in each upper gate portion 812SU may have (i) a rectangular cross-sectional profile along the X-axis, (ii) a substantially linear sidewall, and (iii) a width W1 of about 9 nm to about 12 nm. In some embodiments, the lower portion of the polysilicon structure 1712B in each lower gate portion 1712SL may have: (i) a tapered cross-sectional profile along the X-axis; (ii) an inclined sidewall; (iii) an angle between the inclined sidewall and the top surface 104t of the STI region 104 of about 70 degrees to about 80 degrees; (iv) a substantially linear bottom surface 1712Bs in contact with the top surface 104t of the STI region 104; (v) a width W2 of about 5 nm to about 8 nm in the middle region of the lower gate portion 1712SL; and (vi) a width W3 of about 0 nm to about 3 nm of the bottom surface 1712Bs. In some embodiments, each internal gate portion 1712N may be disposed on and in contact with the topmost nanostructure layer 208 of the superlattice structure 607. In some embodiments, each internal gate portion 1712N may have (i) a rectangular cross-sectional profile along the X-axis, (ii) a substantially linear sidewall, and (iii) a width W1 of about 9 nm to about 12 nm.

[0074] In some embodiments, unlike the first etching process in operation 515, portions of the oxide layer 712A are retained at the interfaces between the polysilicon structure 812B and the STI region 104 and between the polysilicon structure 812B and the superlattice structure 607 to form an IL layer 1712A after the first etching process in operation 1615, as shown in FIG. Figures 17A-17DIn some embodiments, similar to the byproduct layer 824, the byproduct layer 1724 may be formed on the exposed surfaces of the sacrificial gate structure 1712 and the superlattice structure 607 and the STI region 104 during the first etching process, as shown in FIG. Figures 17A-17D The first etching process in operation 1615 may be similar to the first etching process in operation 515 , except that the etching duration in the first etching process in operation 1615 may be shorter than that in the first etching process in operation 515 .

[0075] refer to Fig.16 In operation 1620, an external gate spacer is formed on the sidewall of the sacrificial gate structure. Figures 19A-19D and Figures 20A-20D As described, an external gate spacer 314 is formed on the sidewall of the sacrificial gate structure 1712. In some embodiments, the formation of the external gate spacer 314 may include the following sequential operations: (i) Figures 18A-18D A dielectric layer 1914 having an external gate spacer 314 material is deposited on the structure, such as Figures 19A-19D (ii) performing an annealing process to densify the dielectric layer 1914; and (iii) performing an etching process on the densified dielectric layer 1014 to form an external gate spacer 314 having a structural profile, such as Figures 20A-20D shown.

[0076] In some embodiments, dielectric layer 1914 can be deposited in a PECVD process similar to dielectric layer 1014. In some embodiments, the bias voltage applied to substrate 102 during the PECVD process can be controlled to change the deposition selectivity of dielectric layer 1914 along the height of sacrificial gate structure 1712, thereby achieving Fig.19C 1 and 1 . A cross-sectional profile of a dielectric layer 1914 having different thicknesses (eg, thicknesses T1 and T3) along the height of the polysilicon structure 1712B is shown in FIG. Fig.19C As shown, dielectric layer 1914 may have a thickness T1 around the upper portion of polysilicon structure 1712B in upper gate portion 1712SU. In some embodiments, dielectric layer 1914 may have a thickness T3 greater than thickness T1, surrounding the lower portion of polysilicon structure 1712B in lower gate portion 1712SL, as shown in FIG. Fig.19A and Fig.19C shown.

[0077] refer to Fig.16 , operations 1625 and 1630 with Figure 5 The operations 525 and 530 are similar and Figures 20A-20D After operation 1630, the Figures 21A-21C The structure of Figures 22A-22C and Figures 23A-23C As stated, Fig.16 Subsequent operations 1635 in Figures 21A-21C is executed on the structure.

[0078] refer to Fig.16 In operation 1635, the sacrificial gate structure and the nanostructure sacrificial layer are replaced with a GAA structure. Figures 22A-22C and Figures 23A-23C As depicted, the sacrificial gate structure 1712 and the nanostructure sacrificial layer 608 are replaced by the GAA structure 312. The formation of the GAA structure 312 may include the following sequential operations: (i) etching the sacrificial gate structure 1712 and the nanostructure sacrificial layer 608 to form the gate opening 2212, as shown in FIG. Figures 22A-22C (ii) the exposed region of the nanostructure layer 208 in the gate opening 2212 is oxidized to form an IL layer 312A, as shown Fig.23A and 23C As shown (in Fig. 23B (iii) forming a HK gate dielectric layer 312B on the IL layer 312A, as shown in FIG. Figures 23A-23C (iv) forming a WFM layer 312C on the HK gate dielectric layer 312B, as shown Figures 23A-23C and (v) forming a conductive layer 312D on the WFM layer 312C, as shown; Figures 23A-23C shown.

[0079] In some embodiments, Fig. 14B As shown, the cross-sectional profile of the gate opening 2212 on the STI region 104 can be similar to the cross-sectional profile of the polysilicon structure 1712B. Similar to the polysilicon structure 812B, due to the tapered cross-sectional profile of the polysilicon structure 1712B, the gate opening 2212 can be prevented from extending to the STI region 104 and the base structure 106 during the etching process of the sacrificial gate structure 1712.

[0080] In some embodiments, in operation 1635, sacrificial gate structure 1712 and nanostructure sacrificial layer 608 may be replaced with GAA structure 412, such as Figures 25A-25C As shown, instead of replacing it with GAA structure 312. The formation of GAA structure 412 may include the following sequential operations: (i) etching sacrificial gate structure 1712 and nanostructure sacrificial layer 608 to form gate opening 2412, as shown in FIG. Figures 24A-24C (ii) the exposed region of the nanostructure layer 208 in the gate opening 2412 is oxidized to form an IL layer 412A, as shown Fig.25A and 25C As shown (in Fig.25B(iii) forming a HK gate dielectric layer 412B on the IL layer 412A, such as Figures 25A-25C (iv) forming a WFM layer 412C on the HK gate dielectric layer 412B, as shown Figures 25A-25C and (v) forming a conductive layer 412D on the WFM layer 412C, as shown; Figures 25A-25C shown.

[0081] In some embodiments, since the sacrificial gate structure 1712 has a high aspect ratio (e.g., an aspect ratio of about 3 to about 20), the sacrificial gate structure 1712 may be overetched to ensure that a narrower portion of the sacrificial gate structure 1712 near the STI region 104 is removed. As a result of the overetching, the gate opening 2412 is a distance away from the STI region 104 and a distance D2 from the base structure 106, thereby forming a trench 2412Nt in the base structure 106, as shown in FIG. Fig.24A As shown in FIG. 1 , since the cross section of the polysilicon structure 1712B is tapered, it is different from the trenches formed by overetching of the polysilicon structure with non-tapered cross section in other GAA FETs (such as Fig.24A The trench 2412Nt is narrower than the trench 422 shown in the dotted line. Similarly, since the cross-sectional profile of the polysilicon structure 1712B is tapered, the depth profile of the trench 2412Nt is shallower than that of the trench 422.

[0082] The present disclosure provides example structures and methods for improving the bottom surface profile of the bottom gate portion (e.g., bottom gate portions 212Nb, 312Nb, and 412Nb) of a GAA structure (e.g., GAA structures 112, 312, and 412), which increases the spacing (e.g., spacing S1) between the bottom gate portion and the S / D region (e.g., S / D region 110). Increasing the spacing between the bottom gate portion and the S / D region can reduce or minimize parasitic capacitance in the GAA FET (e.g., GAA FET 100), thereby improving the reliability and performance of the GAA FET. In some embodiments, the portion of the sacrificial gate structure (e.g., external gate portion 812S) on the STI region (e.g., STI region 104) can be separated by spacers (e.g., external gate spacers 114 and 314) to prevent etching of the STI region during removal of the sacrificial gate structure. Preventing etching of the STI region can prevent etching of the substrate structure (e.g., substrate structure 106) and the formation of trenches in the substrate structure. Thus, the bottom gate portion can form a bottom surface profile that is substantially planar. In some embodiments, the portion of the sacrificial gate structure directly located on the STI region (e.g., the outer gate portion 1712S) can form a tapered cross-sectional profile to prevent or minimize etching of the STI region during removal of the sacrificial gate structure. Thus, trenches can be prevented from forming in the substrate structure, or narrow trenches (e.g., trench 2412Nt) can be formed in the substrate structure. In some embodiments, the trenches can be narrower than trenches formed by sacrificial gate structures having non-tapered (e.g., rectangular) cross-sectional profiles on the STI region. Therefore, by modifying the profile of the sacrificial gate structure, the bottom surface profile of the bottom gate portion can be improved to reduce or minimize parasitic capacitance in the GAA FET.

[0083] In some embodiments, a semiconductor device includes: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; an isolation region disposed on the substrate and adjacent to the base structure; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion; a gate structure; and a gate spacer disposed along a sidewall of the gate structure and between the gate structure and the isolation region. The gate structure includes an outer gate portion and an inner gate portion, the outer gate portion including: an outer gate portion including a tapered cross-sectional profile and disposed on the isolation region, and an inner gate portion including a non-tapered cross-sectional profile and disposed on the nanostructure channel region.

[0084] In some embodiments, a semiconductor device includes: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; a shallow trench isolation (STI) region disposed on the substrate; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion and a gate structure. The gate structure includes a top gate portion disposed on the nanostructure channel region; and a bottom gate portion. The bottom gate portion includes: a first gate portion having a rectangular cross-sectional profile disposed on the first base portion; and a second gate portion having a tapered cross-sectional profile disposed on the first base portion.

[0085] In some embodiments, a method includes: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a base structure on a substrate; forming a shallow trench isolation (STI) region on the substrate; forming a sacrificial gate structure on the superlattice structure, the sacrificial gate structure having a second gate portion and a first gate portion suspended on the STI region; forming a gate spacer along a sidewall of the sacrificial gate structure and between the sacrificial gate structure and the STI region; and replacing the sacrificial gate structure and the sacrificial nanostructure layer with a gate structure.

[0086] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0087] Example

[0088] 1. A semiconductor device, comprising: a substrate; a base structure, the base structure having a first base portion and a second base portion disposed on the substrate; an isolation region disposed on the substrate and adjacent to the base structure; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion; a gate structure, comprising: an outer gate portion, comprising a tapered cross-sectional profile, and disposed on the isolation region, and an inner gate portion, comprising a non-tapered cross-sectional profile, and disposed on the nanostructure channel region; and a gate spacer disposed along a sidewall of the gate structure and between the gate structure and the isolation region.

[0089] 2 . The semiconductor device of claim 1 , wherein the outer gate portion comprises: an upper gate portion having a rectangular cross-sectional profile; and a lower gate portion having the tapered cross-sectional profile.

[0090] 3 . The semiconductor device of claim 1 , wherein the outer gate portion comprises: an upper gate portion having a first width; and a lower gate portion having a second width smaller than the first width.

[0091] 4 . The semiconductor device according to claim 1 , wherein the gate structure comprises a gate dielectric layer having a V-shaped cross-sectional profile and disposed on the isolation region.

[0092] 5 . The semiconductor device of claim 1 , wherein the gate structure comprises a conductive layer, and wherein a portion of the gate spacer is disposed between a bottom surface of the conductive layer and a top surface of the isolation region.

[0093] 6 . The semiconductor device of claim 1 , wherein the gate spacer comprises: an upper spacer portion having a first thickness; and a lower spacer portion having a second thickness greater than the first thickness.

[0094] 7. The semiconductor device of claim 1, wherein the gate spacer comprises: an outer sidewall having a substantially linear profile, the outer sidewall facing away from the gate structure; and an inner sidewall having a V-shaped cross-sectional profile, the inner sidewall facing the gate structure.

[0095] 8 . The semiconductor device of claim 1 , wherein a first portion of the gate structure disposed on the gate spacer is at a higher surface plane than a second portion of the gate structure disposed on the first base portion of the base structure.

[0096] 9 . The semiconductor device of claim 1 , wherein the gate spacer is disposed under a tapered portion of the outer gate portion.

[0097] 10 . The semiconductor device of claim 1 , further comprising an isolation structure disposed between the source / drain regions and the second substrate portion.

[0098] 11. A semiconductor device, comprising: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; a shallow trench isolation (STI) region disposed on the substrate; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion; and a gate structure, comprising: a top gate portion disposed on the nanostructure channel region, and a bottom gate portion, comprising: a first gate portion having a rectangular cross-sectional profile disposed on the first base portion; and a second gate portion having a conical cross-sectional profile disposed on the first base portion.

[0099] 12 . The semiconductor device according to claim 11 , wherein the gate structure further comprises an external gate portion, the external gate portion comprising: an upper gate portion disposed on the STI region; and a lower gate portion disposed in the STI region.

[0100] 13 . The semiconductor device of claim 11 , wherein the gate structure further comprises an outer gate portion, the outer gate portion comprising: an upper gate portion having a rectangular cross-sectional profile; and a lower gate portion having a V-shaped cross-sectional profile.

[0101] 14. The semiconductor device of claim 11, wherein the gate structure further comprises an external gate portion extending to the STI region at a first distance; and wherein the second gate portion extends to the first substrate portion at a second distance greater than the first distance.

[0102] 15. The semiconductor device according to claim 11 further comprises a gate spacer disposed on the STI region, the gate spacer comprising: an outer sidewall having a substantially linear profile, the outer sidewall facing away from the gate structure; and an inner sidewall having an inclined profile, the inner sidewall facing the gate structure.

[0103] 16 . The semiconductor device of claim 11 , wherein the second gate portion extends toward the first base portion by a distance of about 2 nm to about 4 nm.

[0104] 17. A method for forming a semiconductor device, comprising: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a base structure on a substrate; forming a shallow trench isolation (STI) region on the substrate; forming a sacrificial gate structure on the superlattice structure, the sacrificial gate structure having a second gate portion and a first gate portion suspended on the STI region; forming a gate spacer along the sidewall of the sacrificial gate structure and between the sacrificial gate structure and the STI region; and replacing the sacrificial gate structure and the sacrificial nanostructure layer with a gate structure.

[0105] 18 . The method of claim 17 , wherein forming the sacrificial gate structure comprises: forming the first gate portion having a tapered cross-sectional profile; and forming the second gate portion having a rectangular cross-sectional profile.

[0106] 19 . The method of claim 17 , wherein forming the sacrificial gate structure comprises: forming a first gate portion having a first width; and forming the second gate portion having a second width less than the first width.

[0107] 20 . The method of claim 17 , wherein forming the gate spacer comprises depositing a dielectric layer to cover a top surface and sidewalls of the sacrificial gate structure and fill a gap between the sacrificial gate structure and the STI region.

Claims

1. A semiconductor device, comprising: substrate; a base structure having a first base portion and a second base portion disposed on the substrate; an isolation region disposed on the substrate and adjacent to the base structure; A nanostructured channel region is disposed on the first substrate portion; a source / drain region disposed on the second substrate portion; The gate structure includes: an external gate portion including a tapered cross-sectional profile and disposed on the isolation region, and an internal gate portion including a non-tapered cross-sectional profile and disposed on the nanostructured channel region; as well as A gate spacer is disposed along a sidewall of the gate structure and between the gate structure and the isolation region.

2. The semiconductor device according to claim 1, wherein The external gate portion comprises: an upper gate portion having a rectangular cross-sectional profile; and The lower gate portion has the tapered cross-sectional profile.

3. The semiconductor device according to claim 1, wherein The external gate portion comprises: an upper gate portion having a first width; and The lower gate portion has a second width that is smaller than the first width.

4. The semiconductor device according to claim 1, wherein: The gate structure includes a gate dielectric layer having a V-shaped cross-sectional profile and disposed on the isolation region.

5. The semiconductor device according to claim 1, wherein The gate structure includes a conductive layer, and A portion of the gate spacer is disposed between a bottom surface of the conductive layer and a top surface of the isolation region.

6. The semiconductor device according to claim 1, wherein The gate spacer comprises: an upper spacer portion having a first thickness; and A lower spacer portion has a second thickness greater than the first thickness.

7. The semiconductor device according to claim 1, wherein: The gate spacer comprises: an outer sidewall having a substantially linear profile, the outer sidewall facing away from the gate structure; and The inner sidewall has a V-shaped cross-sectional profile, and the inner sidewall faces the gate structure.

8. The semiconductor device according to claim 1, wherein A first portion of the gate structure disposed on the gate spacer is at a higher surface plane than a second portion of the gate structure disposed on the first base portion of the base structure.

9. A semiconductor device comprising: substrate; a base structure having a first base portion and a second base portion disposed on the substrate; A shallow trench isolation (STI) region is disposed on the substrate; A nanostructure channel region is disposed on the first substrate portion; a source / drain region disposed on the second substrate portion; as well as The gate structure includes: a top gate portion disposed on the nanostructure channel region, and The bottom gate section includes: a first gate portion having a rectangular cross-sectional profile disposed on the first substrate portion; and A second gate portion, having a tapered cross-sectional profile, is disposed on the first substrate portion.

10. A method for forming a semiconductor device, comprising: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a base structure on a substrate; forming a shallow trench isolation (STI) region on the substrate; forming a sacrificial gate structure on the superlattice structure, the sacrificial gate structure having a second gate portion and a first gate portion suspended over the STI region; forming a gate spacer along a sidewall of the sacrificial gate structure and between the sacrificial gate structure and the STI region; as well as The sacrificial gate structure and the sacrificial nanostructure layer are replaced with a gate structure.

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