Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a first semiconductor layer, a first dielectric layer, a second dielectric layer, a third dielectric layer and a second semiconductor layer which are stacked, and the first semiconductor layer and the second semiconductor layer are separated through the first dielectric layer, the second dielectric layer and the third dielectric layer. The second semiconductor layer is used for forming a semiconductor device; the plurality of conductive structures are arranged in the second dielectric layer, each conductive structure comprises a first end and a second end which are opposite to each other along the stacking direction, the first end is in contact with the first dielectric layer, and the second end is in contact with the third dielectric layer; wherein the second dielectric layer and the first dielectric layer are made of different materials, and the second dielectric layer and the third dielectric layer are made of different materials; and the semiconductor device carries out heat dissipation through the third dielectric layer, the conductive structure and the first dielectric layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, including but not limited to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the technological development of the semiconductor industry, the device density per unit area is getting higher and higher, and the size of the device is constantly shrinking, which inevitably brings various problems. Among them, the silicon-on-insulator (SOI) technology on insulating substrates has attracted widespread attention due to its excellent performance such as anti-interference and low leakage. However, there is a self-heating effect in semiconductor devices in SOI technology, that is, when the semiconductor device is working, the channel current generates heat, causing the internal temperature of the semiconductor device to rise, resulting in the degradation of the characteristics of the semiconductor device. The self-heating effect will not only affect the stability and reliability of the operation of the semiconductor device, but also lead to poor uniformity of the thermal process, becoming an important factor restricting the development of semiconductor technology. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0004] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising: a first semiconductor layer, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a second semiconductor layer that are stacked, wherein the first semiconductor layer and the second semiconductor layer are isolated from each other by the first dielectric layer, the second dielectric layer, and the third dielectric layer, and the second semiconductor layer is used to form a semiconductor device; a plurality of conductive structures are arranged in the second dielectric layer, wherein the conductive structures comprise a first end and a second end opposite to each other along a stacking direction, the first end contacts the first dielectric layer, and the second end contacts the third dielectric layer; wherein the materials of the second dielectric layer and the first dielectric layer are different, and the materials of the second dielectric layer and the third dielectric layer are different; and the semiconductor device dissipates heat through the third dielectric layer, the conductive structures, and the first dielectric layer.

[0005] In some embodiments, the thermal conductivity of the second dielectric layer is smaller than that of the first dielectric layer, and the thermal conductivity of the second dielectric layer is smaller than that of the third dielectric layer; the thermal conductivity of the first dielectric layer is smaller than that of the conductive structure, and the thermal conductivity of the third dielectric layer is smaller than that of the conductive structure.

[0006] In some embodiments, a size of the second semiconductor layer along the stacking direction is smaller than a size of the first semiconductor layer along the stacking direction; a sum of sizes of the first dielectric layer, the second dielectric layer, and the third dielectric layer along the stacking direction is smaller than a size of the first semiconductor layer along the stacking direction.

[0007] In some embodiments, the second dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked together, the first sub-dielectric layer being disposed between the first dielectric layer and the second sub-dielectric layer; the conductive structure includes a first sub-conductive structure disposed in the first sub-dielectric layer and a second sub-conductive structure disposed in the second sub-dielectric layer, the first sub-conductive structure includes the first end and the third end opposite to each other along the stacking direction, the second sub-conductive structure includes the second end and the fourth end opposite to each other along the stacking direction, and the third end is in contact with the fourth end.

[0008] In some embodiments, a first contact interface is provided between the first sub-dielectric layer and the second sub-dielectric layer, a second contact interface is provided between the first sub-conductive structure and the second sub-conductive structure, and the first contact interface and the second contact interface are in the same plane; the first dielectric layer and the third dielectric layer are plane-symmetrical about the first contact interface or the second contact interface.

[0009] In some embodiments, the semiconductor device includes: a gate structure disposed on a side of the second semiconductor layer away from the third dielectric layer, the gate structure including a gate electrode layer and a gate dielectric layer disposed between the second semiconductor layer and the gate electrode layer; a source region and a drain region disposed in the second semiconductor layer and respectively disposed on opposite sides of the gate structure.

[0010] In some embodiments, the material of the second dielectric layer includes silicon oxide material; and / or the material of the conductive structure includes metal material.

[0011] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: providing a first semiconductor layer and an initial second semiconductor layer respectively; forming a first dielectric layer and a first sub-dielectric layer covering the first semiconductor layer in sequence, and forming a third dielectric layer and a second sub-dielectric layer covering the initial second semiconductor layer in sequence; etching the first sub-dielectric layer to form a first groove, and etching the second sub-dielectric layer to form a second groove; forming a first sub-conductive structure in the first groove, and forming a second sub-conductive structure in the second groove; bonding the first semiconductor layer and the initial second semiconductor layer so that the first sub-conductive structure and the second sub-conductive structure are in corresponding contact to form a conductive structure, and the first sub-dielectric layer and the second sub-dielectric layer are in corresponding contact to form a second dielectric layer; wherein the first semiconductor layer and the initial second semiconductor layer are isolated from each other by the first dielectric layer, the second dielectric layer and the third dielectric layer, the second dielectric layer and the first dielectric layer are made of different materials, and the second dielectric layer and the third dielectric layer are made of different materials.

[0012] In some embodiments, after bonding the first semiconductor layer and the initial second semiconductor layer, the method further includes: thinning the initial second semiconductor layer to form a second semiconductor layer, the second semiconductor layer being used to form a semiconductor device; wherein the semiconductor device dissipates heat through the third dielectric layer, the conductive structure and the first dielectric layer.

[0013] In some embodiments, after the initial second semiconductor layer is thinned to form a second semiconductor layer, the method further includes: forming a gate structure on a side of the second semiconductor layer away from the third dielectric layer, the gate structure including a gate electrode layer and a gate dielectric layer disposed between the second semiconductor layer and the gate electrode layer; and respectively forming a source region and a drain region in the second semiconductor layer on opposite sides of the gate structure.

[0014] The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof. In the embodiment of the present disclosure, the first semiconductor layer and the second semiconductor layer are separated by the first dielectric layer, the second dielectric layer and the third dielectric layer, the second semiconductor layer is used to form a semiconductor device, and the second dielectric layer is also provided with a plurality of conductive structures, and the semiconductor device can sequentially conduct the heat generated during operation through the third dielectric layer, the conductive structure and the first dielectric layer to avoid the internal temperature of the semiconductor device from rising, so that the performance attenuation and reliability reduction of the semiconductor device caused by the self-heating effect can be improved, and the uniformity of the thermal process can also be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A schematic partial cross-sectional view of a semiconductor structure is provided for some examples;

[0016] Figure 2 A schematic diagram of a partial cross-section of a semiconductor structure provided by an embodiment of the present disclosure;

[0017] Figure 3 A flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0018] Figures 4 to 9 A schematic partial cross-sectional view of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0020] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0021] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0023] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0024] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0026] Before introducing the embodiments of the present disclosure, various directions that may be involved in the following are defined. The stacking direction of each material layer is defined as the Z direction, and the intersecting X direction and Y direction are defined in a plane perpendicular to the Z direction. In some embodiments, the X direction and the Y direction may be perpendicular to each other. In other embodiments, the X direction and the Y direction may not be perpendicular. The following will be described as an example in which any two of the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0027] refer to Figure 1 , Figure 1 A schematic diagram of a partial cross-section of a semiconductor structure is provided for some examples. Figure 1 As shown, the semiconductor structure 100 includes: a bottom silicon 102, a buried oxide layer 104 and a top silicon 106 stacked along the Z direction; the top silicon 106 is used to form a transistor 108. The transistor 108 includes: a gate structure 110 disposed on the top silicon 106, the gate structure 110 includes a gate dielectric layer 112 in contact with the top silicon 106 and a gate electrode layer 114 in contact with the gate dielectric layer 112; a source region 116 and a drain region 118 respectively disposed in the top silicon 106 on opposite sides of the gate structure 110 along the X direction; and a channel region disposed between the source region 116 and the drain region 118 and disposed in the top silicon 106.

[0028] Here, the bottom silicon 102 , the buried oxide layer 104 and the top silicon 106 stacked along the Z direction together form an SOI structure. The heat generated by the transistor 108 when working is conducted downward to the buried oxide layer 104 and dissipated through the buried oxide layer 104 .

[0029] However, since the thermal conductivity of the buried oxide layer 104 is relatively small, the heat generated by the transistor 108 during operation is difficult to conduct away, and the self-heating effect will cause the internal temperature of the transistor 108 to rise, which will not only affect the stability and reliability of the operation of the transistor 108, but also lead to poor uniformity of the thermal process.

[0030] In view of this, an embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0031] refer to Figure 2 , Figure 2 A partial cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 2As shown, an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure 200 includes: a first semiconductor layer 202, a first dielectric layer 206, a second dielectric layer 214, a third dielectric layer 210 and a second semiconductor layer 204 stacked along the Z direction, the first semiconductor layer 202 and the second semiconductor layer 204 are isolated by the first dielectric layer 206, the second dielectric layer 214 and the third dielectric layer 210, the second semiconductor layer 204 is used to form a semiconductor device 216; a plurality of conductive structures 218 are provided in the second dielectric layer 214, the conductive structure 218 includes a first end 222 and a second end 228 opposite to each other along the Z direction, the first end 222 is in contact with the first dielectric layer 206, and the second end 228 is in contact with the third dielectric layer 210; wherein the second dielectric layer 214 and the first dielectric layer 206 are made of different materials, and the second dielectric layer 214 and the third dielectric layer 210 are made of different materials; the semiconductor device 216 dissipates heat through the third dielectric layer 210, the conductive structure 218 and the first dielectric layer 206.

[0032] Here, the first semiconductor layer 202 may play a supporting role, and the second semiconductor layer 204 may be used to form a semiconductor device 216. The materials of the first semiconductor layer 202 and the second semiconductor layer 204 may include at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0033] Here, the first dielectric layer 206, the second dielectric layer 214, and the third dielectric layer 210 can realize electrical isolation between the first semiconductor layer 202 and the second semiconductor layer 204, wherein the first dielectric layer 206 and the third dielectric layer 210 can also play a role in heat conduction. The materials of the first dielectric layer 206, the second dielectric layer 214, and the third dielectric layer 210 can all include insulating materials. The materials of the second dielectric layer 214 and the first dielectric layer 206 are different, and a contact interface can be formed between the second dielectric layer 214 and the first dielectric layer 206. The materials of the second dielectric layer 214 and the third dielectric layer 210 are different, and a contact interface can also be formed between the second dielectric layer 214 and the third dielectric layer 210.

[0034] Here, the conductive structure 218 is disposed in the second dielectric layer 214, and the conductive structure 218 can extend along the Z direction. The conductive structure 218 includes a first end 222 and a second end 228 that are opposite to each other along the extension direction. The first end 222 and the second end 228 of the conductive structure 218 are in contact with the first dielectric layer 206 and the third dielectric layer 210, respectively. It should be noted that, although the conductive structure 218 is made of a conductive material, the conductive structure 218 does not play a role in conducting electrical signals at this time. The conductive structure 218 is electrically isolated from the first semiconductor layer 202 through the first dielectric layer 206, and the conductive structure 218 is electrically isolated from the second semiconductor layer 204 through the third dielectric layer 210, so as to avoid affecting the electrical performance of the semiconductor device 216.

[0035] Here, the orthographic projection shape of the conductive structure 218 on the XY plane may include but is not limited to a circle, a square, a diamond or other shapes, etc. The orthographic projection shape of the conductive structure 218 on the XZ plane may include but is not limited to a rectangle, a trapezoid or other shapes, etc. The present disclosure has no special restrictions on the orthographic projection shape of the conductive structure 218 on the XY plane and the XZ plane and the size of the conductive structure 218 along the X direction or the Y direction, and can be flexibly selected according to actual conditions.

[0036] Here, a plurality of conductive structures 218 may be provided in the second dielectric layer 214, and the plurality of conductive structures 218 may be arranged uniformly or non-uniformly in the second dielectric layer 214. Here, uniform arrangement means that the distance between any two adjacent conductive structures 218 along the X direction is the same; and / or, the distance between any two adjacent conductive structures 218 along the Y direction is the same. Non-uniform arrangement means that the distance between any two adjacent conductive structures 218 along the X direction is different, and the distance between any two adjacent conductive structures 218 along the Y direction is different. The present disclosure has no special limitation on the number and arrangement of the conductive structures 218 in the second dielectric layer 214, and can be flexibly selected according to actual conditions. When the conductive structures 218 are arranged uniformly, it is more conducive to the uniformity of heat conduction.

[0037] Here, the material of the conductive structure 218 may include a conductive material.

[0038] In the embodiment of the present disclosure, the third dielectric layer 210, the conductive structure 218 and the first dielectric layer 206 form a heat conduction path, and the heat generated by the semiconductor device 216 when working is sequentially conducted through the third dielectric layer 210, the conductive structure 218 and the first dielectric layer 206, thereby preventing the internal temperature of the semiconductor device 216 from rising, thereby improving the performance degradation and reliability reduction of the semiconductor device 216 caused by the self-heating effect. In addition, the conductive structure 218 can also be evenly arranged in the second dielectric layer 214 to form an evenly arranged heat conduction path, thereby improving the uniformity (or uniformity) of heat conduction in the thermal process.

[0039] In some embodiments, the thermal conductivity of the second dielectric layer 214 is smaller than the thermal conductivity of the first dielectric layer 206 , and the thermal conductivity of the second dielectric layer 214 is smaller than the thermal conductivity of the third dielectric layer 210 ; the thermal conductivity of the first dielectric layer 206 is smaller than the thermal conductivity of the conductive structure 218 , and the thermal conductivity of the third dielectric layer 210 is smaller than the thermal conductivity of the conductive structure 218 .

[0040] Here, the thermal conductivity of the second dielectric layer 214 is less than the thermal conductivity of the first dielectric layer 206 (or the third dielectric layer 210) and less than the thermal conductivity of the conductive structure 218, that is, the second dielectric layer 214 has the worst heat conduction capability, the first dielectric layer 206 and the third dielectric layer 210 have the second worst heat conduction capability, and the conductive structure 218 has the best heat conduction capability. The third dielectric layer 210 is in direct contact with the second semiconductor layer 204, and the heat generated by the semiconductor device 216 when working is first conducted to the third dielectric layer 210, and the conductive structure 218 has the best heat conduction capability to form a heat conduction channel, thereby conducting the heat from the third dielectric layer 210 to the conductive structure 218, and finally conducting the heat from the conductive structure 218 to the first dielectric layer 206.

[0041] In some embodiments, the material of the second dielectric layer 214 includes silicon oxide material; and / or, the materials of the first dielectric layer 206 and the third dielectric layer 210 may include silicon carbide material, ceramic material or silicone grease material; and / or, the material of the conductive structure 218 includes metal material.

[0042] In some embodiments, the materials of the first dielectric layer 206 and the third dielectric layer 210 may be the same or different. In some embodiments, the thicknesses of the first dielectric layer 206 and the third dielectric layer 210 may be the same or different. When the materials and / or thicknesses of the first dielectric layer 206 and the third dielectric layer 210 are the same, the processes of forming the first dielectric layer 206 and the third dielectric layer 210 may be performed simultaneously, which is beneficial to saving manufacturing processes.

[0043] In some embodiments, the size of the second semiconductor layer 204 along the Z direction is smaller than the size of the first semiconductor layer 202 along the Z direction; the sum of the sizes of the first dielectric layer 206, the second dielectric layer 214, and the third dielectric layer 210 along the Z direction is smaller than the size of the first semiconductor layer 202 along the Z direction. The size of each material layer along the Z direction may also be referred to as the thickness of each material layer or the height of each material layer.

[0044] Here, the thickness of the first semiconductor layer 202 is relatively large, and the first semiconductor layer 202 can play a supporting role. Compared with the thickness of the first semiconductor layer 202, the thickness of the second semiconductor layer 204 is relatively small, and can be used to form a semiconductor device 216. Compared with the thickness of the first semiconductor layer 202, the sum of the thicknesses of the first dielectric layer 206, the second dielectric layer 214, and the third dielectric layer 210 is relatively small, and can be used to play an electrical isolation role. The present disclosure does not have any special restrictions on the specific thickness values ​​of the first semiconductor layer 202, the second semiconductor layer 204, the first dielectric layer 206, the second dielectric layer 214, and the third dielectric layer 210, and can be flexibly selected according to actual conditions.

[0045] In some embodiments, the semiconductor structure 200 may include a fully depleted SOI (FD-SOI) structure. Here, the thickness of the second semiconductor layer 204 is relatively small, and the sum of the thicknesses of the first dielectric layer 206, the second dielectric layer 214, and the third dielectric layer 210 is relatively small.

[0046] In some embodiments, the semiconductor structure 200 may include a partially depleted SOI (PD-SOI) structure. Here, the second semiconductor layer 204 has a relatively large thickness, and the sum of the thicknesses of the first dielectric layer 206, the second dielectric layer 214, and the third dielectric layer 210 is relatively large.

[0047] Figure 2The middle dotted box illustrates an enlarged schematic diagram of the conductive structure 218. In some embodiments, the second dielectric layer 214 includes a first sub-dielectric layer 208 and a second sub-dielectric layer 212 stacked along the Z direction, the first sub-dielectric layer 208 is in contact with the first dielectric layer 206, the second sub-dielectric layer 212 is in contact with the third dielectric layer 210, the first sub-dielectric layer 208 is disposed between the first dielectric layer 206 and the second sub-dielectric layer 212, and the second sub-dielectric layer 212 is disposed between the first sub-dielectric layer 208 and the third dielectric layer 210; the conductive structure 218 includes a first sub-conductive structure 220 disposed in the first sub-dielectric layer 208 and a second sub-conductive structure 226 disposed in the second sub-dielectric layer 212, the first sub-conductive structure 220 includes a first end 222 and a third end 224 opposite to each other along the Z direction, the second sub-conductive structure 226 includes a second end 228 and a fourth end 230 opposite to each other along the Z direction, and the third end 224 is in contact with the fourth end 230.

[0048] Here, the first sub-dielectric layer 208 is in contact with the second sub-dielectric layer 212, for example, the first sub-dielectric layer 208 and the second sub-dielectric layer 212 may be connected by bonding. A first contact interface 232 is provided between the first sub-dielectric layer 208 and the second sub-dielectric layer 212. The first sub-conductive structure 220 is in contact with the second sub-conductive structure 226, for example, the first sub-conductive structure 220 and the second sub-conductive structure 226 may be connected by bonding. A second contact interface 234 is provided between the first sub-conductive structure 220 and the second sub-conductive structure 226. Since the thickness of the first sub-dielectric layer 208 is the same as the thickness of the first sub-conductive structure 220, the surfaces of the first sub-dielectric layer 208 and the first sub-conductive structure 220 away from the first dielectric layer 206 are coplanar; since the thickness of the second sub-dielectric layer 212 and the second sub-conductive structure 226 is the same, the surfaces of the second sub-dielectric layer 212 and the second sub-conductive structure 226 away from the third dielectric layer 210 are coplanar; wherein the first contact interface 232 and the second contact interface 234 are in the same plane, that is, the first contact interface 232 and the second contact interface 234 can both be bonding interfaces. Figure 2 The first contact interface 232 and the second contact interface 234 are indicated by dashed lines.

[0049] In some embodiments, the materials of the first sub-dielectric layer 208 and the second sub-dielectric layer 212 may be the same or different, and the materials of the first sub-conductive structure 220 and the second sub-conductive structure 226 may be the same or different. In some embodiments, the thicknesses of the first sub-dielectric layer 208 and the second sub-dielectric layer 212 may be the same or different, and the thicknesses of the first sub-conductive structure 220 and the second sub-conductive structure 226 may be the same or different. When the materials and / or thicknesses of the first sub-dielectric layer 208 and the second sub-dielectric layer 212 are the same, the processes of forming the first sub-dielectric layer 208 and the second sub-dielectric layer 212 may be performed simultaneously, which is beneficial to saving manufacturing processes. When the materials and / or thicknesses of the first sub-conductive structure 220 and the second sub-conductive structure 226 are the same, the processes of forming the first sub-conductive structure 220 and the second sub-conductive structure 226 may be performed simultaneously, which is beneficial to saving manufacturing processes.

[0050] In some embodiments, the sizes of the first sub-conductive structure 220 and the second sub-conductive structure 226 along the X direction and / or the Y direction may be the same or different. Here, after the bonding connection is performed, the axes of the first sub-conductive structure 220 and the second sub-conductive structure 226 coincide with each other. Further, after the bonding connection is performed, the orthographic projections of the first sub-conductive structure 220 and the second sub-conductive structure 226 on the XY plane coincide with each other.

[0051] It should be noted that, when the materials of the first sub-dielectric layer 208 and the second sub-dielectric layer 212 are the same, no actual interface is formed between the first sub-dielectric layer 208 and the second sub-dielectric layer 212, and the first contact interface 232 is only used to exemplify the relative positional relationship between the first sub-dielectric layer 208 and the second sub-dielectric layer 212. When the materials of the first sub-conductive structure 220 and the second sub-conductive structure 226 are the same, no actual interface is formed between the first sub-conductive structure 220 and the second sub-conductive structure 226, and the second contact interface 234 is only used to exemplify the relative positional relationship between the first sub-conductive structure 220 and the second sub-conductive structure 226.

[0052] In some embodiments, the first dielectric layer 206 and the third dielectric layer 210 are planar symmetric about the first contact interface 232 or the second contact interface 234. Here, the first dielectric layer 206 and the third dielectric layer 210 may be made of the same material and have the same thickness.

[0053] In some embodiments, the semiconductor structure may further include: a shallow trench isolation structure provided in the second semiconductor layer, the shallow trench isolation structure isolates an active area in the second semiconductor layer, that is, the second semiconductor layer between adjacent shallow trench isolation structures may form an active area; wherein, electrical isolation between semiconductor devices may be achieved through the shallow trench isolation structure.

[0054] In some embodiments, the semiconductor device 216 includes: a gate structure 236 (eg, Figure 2 As shown in the dotted circle, the gate structure 236 includes a gate electrode layer 240 and a gate dielectric layer 238 disposed between the second semiconductor layer 204 and the gate electrode layer 240; a source region 242 and a drain region 244 disposed in the second semiconductor layer 204 and respectively disposed on opposite sides of the gate structure 236; and a channel region disposed in the second semiconductor layer 204 and between the source region 242 and the drain region 244.

[0055] Here, the semiconductor device 216 may include a metal-oxide-semiconductor field-effect transistor (MOSFET). Exemplarily, the semiconductor device 216 may include an NMOS transistor, and an N-type doped source region 242 and a drain region 244 are formed in the P-type doped second semiconductor layer 204. The semiconductor device may also include a PMOS transistor, and a P-type doped source region 242 and a drain region 244 are formed in the N-type doped second semiconductor layer 204. The present disclosure has no special restrictions on the type and number of transistors included in the semiconductor device 216, and may include NMOS transistors, PMOS transistors, or both NMOS transistors and PMOS transistors. The second semiconductor layer 204 provided in the embodiment of the present disclosure can be used to form the semiconductor device 216, and is not limited to the above-mentioned MOSFET. The second semiconductor layer 204 can also be used to manufacture digital circuits, analog circuits, or radio frequency circuits, etc., and the present disclosure does not make any special restrictions on this.

[0056] refer to Figure 3 , Figure 3 A flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

[0057] like Figure 3 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0058] Step S310: providing a first semiconductor layer and an initial second semiconductor layer respectively;

[0059] Step S320: sequentially forming a first dielectric layer and a first sub-dielectric layer covering the first semiconductor layer, and sequentially forming a third dielectric layer and a second sub-dielectric layer covering the initial second semiconductor layer;

[0060] Step S330: etching the first sub-dielectric layer to form a first groove, and etching the second sub-dielectric layer to form a second groove;

[0061] Step S340: forming a first sub-conductive structure in the first groove, and forming a second sub-conductive structure in the second groove;

[0062] Step S350: Bonding the first semiconductor layer and the initial second semiconductor layer so that the first sub-conductive structure and the second sub-conductive structure are in corresponding contact to form a conductive structure, and the first sub-dielectric layer and the second sub-dielectric layer are in corresponding contact to form a second dielectric layer; wherein the first semiconductor layer and the initial second semiconductor layer are isolated by the first dielectric layer, the second dielectric layer and the third dielectric layer, the second dielectric layer and the first dielectric layer are made of different materials, and the second dielectric layer and the third dielectric layer are made of different materials.

[0063] Figures 4 to 9 A partial cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure during the manufacturing process. Figure 3 as well as Figures 4 to 9 , describing in detail the manufacturing process of the semiconductor structure provided by the embodiment of the present disclosure.

[0064] like Figure 4 As shown, in step S310 , a first semiconductor layer 202 and an initial second semiconductor layer 246 are provided respectively.

[0065] Here, the first semiconductor layer 202 and the initial second semiconductor layer 246 may be the same two wafers. For example, the first semiconductor layer 202 and the initial second semiconductor layer 246 may include a silicon substrate.

[0066] like Figure 5 and Figure 6 As shown, in step S320, the first dielectric layer 206 and the first sub-dielectric layer 208 covering the first semiconductor layer 202 are formed in sequence, and the third dielectric layer 210 and the second sub-dielectric layer 212 covering the initial second semiconductor layer 246 are formed in sequence. Here, the process of forming the first dielectric layer 206 and the third dielectric layer 210 can be performed on two wafers at the same time, and the materials and thicknesses of the first dielectric layer 206 and the third dielectric layer 210 can be the same, so that the manufacturing process can be saved. The process of forming the first sub-dielectric layer 208 and the second sub-dielectric layer 212 can be performed on two wafers at the same time, and the materials and thicknesses of the first sub-dielectric layer 208 and the second sub-dielectric layer 212 can be the same, so that the manufacturing process can be saved.

[0067] Here, the process of forming the first dielectric layer 206, the first sub-dielectric layer 208, the third dielectric layer 210 and the second sub-dielectric layer 212 may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0068] like Figure 6 As shown, in step S330 , the first sub-dielectric layer 208 is etched to form a first groove 248 , and the second sub-dielectric layer 212 is etched to form a second groove 250 . Figure 6 The dashed box illustrates the first groove 248 and the second groove 250 .

[0069] By way of example, a photoresist layer may be formed on the first sub-dielectric layer 208, and the photoresist layer may be patterned using a mask to form a patterned photoresist layer; the first sub-dielectric layer 208 may be etched using the patterned photoresist layer as a mask to form a first groove 248 exposing the first dielectric layer 206; and the patterned photoresist layer may be removed. Here, the first dielectric layer 206 and the first sub-dielectric layer 208 are made of different materials, and during the etching of the first sub-dielectric layer 208, the first dielectric layer 206 may be used as an etching stop layer. Similarly, the second sub-dielectric layer 212 may also be etched to form a second groove 250, which will not be described in detail herein.

[0070] In some embodiments, the sizes of the first groove 248 and the second groove 250 may be the same or different. Correspondingly, the sizes of the first sub-conductive structure 220 and the second sub-conductive structure 226 formed by filling the first groove 248 and the second groove 250 with conductive material may be the same or different.

[0071] Still Figure 6 As shown, in step S340 , a conductive material, such as a metal material, is filled in the first groove 248 to form a first sub-conductive structure 220 , and a conductive material, such as a metal material, is filled in the second groove 250 to form a second sub-conductive structure 226 .

[0072] Here, the surface of the first sub-dielectric layer 208 is substantially flush with the surface of the first sub-conductive structure 220. More specifically, the height difference between the surface of the first sub-dielectric layer 208 and the surface of the first sub-conductive structure 220 along the Z direction is 0, or the height difference between the surface of the first sub-dielectric layer 208 and the surface of the first sub-conductive structure 220 along the Z direction is within an acceptable process error range. Similarly, the surface of the second sub-dielectric layer 212 is substantially flush with the surface of the second sub-conductive structure 226.

[0073] For example, the first groove 248 may be filled with a conductive material to form a conductive material layer that fills the first groove 248 and covers the first sub-dielectric layer 208; the conductive material layer is planarized to expose the surface of the first sub-dielectric layer 208, and the conductive material layer disposed in the first groove 248 forms the first sub-conductive structure 220. Similarly, a second sub-conductive structure 226 may also be formed, which will not be described in detail herein.

[0074] Here, the planarization process may include but is not limited to a chemical mechanical polishing (CMP) process.

[0075] like Figure 7 As shown, in step S350, Figure 6 After the schematic initial second semiconductor layer 246 is flipped, the first semiconductor layer 202 and the initial second semiconductor layer 246 are bonded, so that the first dielectric layer 206, the second dielectric layer 214, the third dielectric layer 210 and the conductive structure 218 are arranged between the first semiconductor layer 202 and the initial second semiconductor layer 246, the first sub-conductive structure 220 and the second sub-conductive structure 226 are in contact with each other to form the conductive structure 218, and the first sub-dielectric layer 208 and the second sub-dielectric layer 212 are in contact with each other to form the second dielectric layer 214; wherein the first semiconductor layer 202 and the initial second semiconductor layer 246 are separated by the first dielectric layer 206, the second dielectric layer 214 and the third dielectric layer 210, the second dielectric layer 214 and the first dielectric layer 206 are made of different materials, and the second dielectric layer 214 and the third dielectric layer 210 are made of different materials. Here, the first sub-dielectric layer 208 and the second sub-dielectric layer 212 are in contact with each other, and the first sub-conductive structure 220 and the second sub-conductive structure 226 are in contact with each other. Figure 7 The dashed line in the middle indicates the bonding interface.

[0076] Combination Figure 7 and Figure 8 As shown, in some embodiments, after step S350 , the method further includes: thinning the initial second semiconductor layer 246 , that is, removing a portion of the initial second semiconductor layer 246 to form the second semiconductor layer 204 . Figure 8 The direction of the middle arrow indicates the direction in which the initial second semiconductor layer 246 is thinned.

[0077] Here, the thickness of the first semiconductor layer 202 and the initial second semiconductor layer 246 may be the same, and the thickness of the second semiconductor layer 204 formed after the thinning process is less than the thickness of the first semiconductor layer 202 .

[0078] In some embodiments, the step of removing part of the initial second semiconductor layer may further include: before the bonding process, ion implanting the initial second semiconductor layer to form a defect layer in the initial second semiconductor layer, the defect layer dividing the initial second semiconductor layer into a first part and a second part, the first part and the second part are separated by the defect layer, and the first part is in contact with the third dielectric layer. After the bonding process, the second part is peeled off along the defect layer, and the remaining first part forms the second semiconductor layer. Therefore, the depth of the ion implantation determines the depth of the defect layer in the initial second semiconductor layer, and also determines the thickness of the final second semiconductor layer.

[0079] In some embodiments, the second semiconductor layer may be further etched to form an isolation groove; and an isolation material may be filled in the isolation groove to form a shallow trench isolation structure; wherein the second semiconductor layer between adjacent shallow trench isolation structures forms an active region.

[0080] like Fig. 9 As shown, in some embodiments, the method further includes: forming a gate structure 236 on a side of the second semiconductor layer 204 away from the third dielectric layer 210, the gate structure 236 including a gate electrode layer 240 and a gate dielectric layer 238 disposed between the second semiconductor layer 204 and the gate electrode layer 240; and forming a source region 242 and a drain region 244 in the second semiconductor layer 204 on opposite sides of the gate structure 236 along the X direction.

[0081] Exemplarily, forming the semiconductor device 216 may include the following steps: sequentially forming a gate dielectric material layer and a gate electrode material layer covering the second semiconductor layer 204; etching the gate electrode material layer and the gate dielectric material layer to form a gate electrode layer 240 and a gate dielectric layer 238, wherein the gate electrode layer 240 and the gate dielectric layer 238 together form a gate structure 236; forming an isolation layer covering the surface of the second semiconductor layer 204 exposed by the gate structure 236 and covering the sidewalls and top surface of the gate structure 236; removing part of the isolation layer covering the surface of the second semiconductor layer 204; ion implanting the second semiconductor layer 204 on opposite sides of the gate structure 236 along the X direction to form a source region 242 and a drain region 244 respectively; wherein the isolation layer covering the sidewalls of the gate structure 236 can play a protective role during the ion implantation process. Here, only taking the MOS transistor as an example, the process of forming the semiconductor device 216 in the second semiconductor layer 204 is exemplarily described. Of course, other types of semiconductor devices 216 can also be formed in the second semiconductor layer 204 provided in the embodiment of the present disclosure, which will not be described in detail here.

[0082] The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first semiconductor layer, a first dielectric layer, a second dielectric layer, a third dielectric layer and a second semiconductor layer which are stacked, the first semiconductor layer and the second semiconductor layer are separated by the first dielectric layer, the second dielectric layer and the third dielectric layer, and the second semiconductor layer is used to form a semiconductor device; a plurality of conductive structures are arranged in the second dielectric layer, the conductive structure includes a first end and a second end which are opposite to each other along the stacking direction, the first end is in contact with the first dielectric layer, and the second end is in contact with the third dielectric layer; wherein the second dielectric layer and the first dielectric layer are made of different materials, and the second dielectric layer and the third dielectric layer are made of different materials; the semiconductor device dissipates heat through the third dielectric layer, the conductive structure and the first dielectric layer. In the embodiment of the present disclosure, the first semiconductor layer and the second semiconductor layer are separated by the first dielectric layer, the second dielectric layer and the third dielectric layer, the second semiconductor layer is used to form a semiconductor device, and a plurality of conductive structures are also arranged in the second dielectric layer, the semiconductor device can sequentially conduct the heat generated during operation through the third dielectric layer, the conductive structure and the first dielectric layer to avoid the internal temperature of the semiconductor device from rising, so as to improve the performance attenuation and reliability reduction of the semiconductor device caused by the self-heating effect, and also improve the uniformity of the thermal process.

[0083] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0084] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: A first semiconductor layer, a first dielectric layer, a second dielectric layer, a third dielectric layer and a second semiconductor layer are stacked, the first semiconductor layer and the second semiconductor layer are isolated from each other by the first dielectric layer, the second dielectric layer and the third dielectric layer, and the second semiconductor layer is used to form a semiconductor device; A plurality of conductive structures are provided in the second dielectric layer, the conductive structures comprising a first end and a second end opposite to each other along a stacking direction, the first end contacts the first dielectric layer, and the second end contacts the third dielectric layer; wherein the second dielectric layer and the first dielectric layer are made of different materials, and the second dielectric layer and the third dielectric layer are made of different materials; and the semiconductor device dissipates heat through the third dielectric layer, the conductive structures and the first dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that: The thermal conductivity of the second medium layer is smaller than the thermal conductivity of the first medium layer, and the thermal conductivity of the second medium layer is smaller than the thermal conductivity of the third medium layer; The thermal conductivity of the first dielectric layer is smaller than the thermal conductivity of the conductive structure, and the thermal conductivity of the third dielectric layer is smaller than the thermal conductivity of the conductive structure.

3. The semiconductor structure according to claim 1, characterized in that: The size of the second semiconductor layer along the stacking direction is smaller than the size of the first semiconductor layer along the stacking direction; The sum of the sizes of the first dielectric layer, the second dielectric layer and the third dielectric layer along the stacking direction is smaller than the size of the first semiconductor layer along the stacking direction.

4. The semiconductor structure according to claim 1, characterized in that: The second dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer which are stacked, and the first sub-dielectric layer is arranged between the first dielectric layer and the second sub-dielectric layer; The conductive structure includes a first sub-conductive structure arranged in the first sub-dielectric layer and a second sub-conductive structure arranged in the second sub-dielectric layer, the first sub-conductive structure includes the first end and the third end opposite to each other along the stacking direction, the second sub-conductive structure includes the second end and the fourth end opposite to each other along the stacking direction, and the third end is in contact with the fourth end.

5. The semiconductor structure according to claim 4, characterized in that: A first contact interface is provided between the first sub-dielectric layer and the second sub-dielectric layer, a second contact interface is provided between the first sub-conductive structure and the second sub-conductive structure, and the first contact interface and the second contact interface are in the same plane; The first dielectric layer and the third dielectric layer are planar symmetrical about the first contact interface or the second contact interface.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor device comprises: a gate structure disposed on a side of the second semiconductor layer away from the third dielectric layer, the gate structure comprising a gate electrode layer and a gate dielectric layer disposed between the second semiconductor layer and the gate electrode layer; A source region and a drain region are disposed in the second semiconductor layer and respectively disposed on two opposite sides of the gate structure.

7. The semiconductor structure according to claim 1, characterized in that: The material of the second dielectric layer includes silicon oxide material; and / or the material of the conductive structure includes metal material.

8. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: providing a first semiconductor layer and an initial second semiconductor layer respectively; sequentially forming a first dielectric layer and a first sub-dielectric layer covering the first semiconductor layer, and sequentially forming a third dielectric layer and a second sub-dielectric layer covering the initial second semiconductor layer; Etching the first sub-dielectric layer to form a first groove, and etching the second sub-dielectric layer to form a second groove; forming a first sub-conductive structure in the first groove, and forming a second sub-conductive structure in the second groove; The first semiconductor layer and the initial second semiconductor layer are bonded to each other so that the first sub-conductive structure and the second sub-conductive structure are in contact with each other to form a conductive structure, and the first sub-dielectric layer and the second sub-dielectric layer are in contact with each other to form a second dielectric layer; wherein the first semiconductor layer and the initial second semiconductor layer are separated by the first dielectric layer, the second dielectric layer and the third dielectric layer, the second dielectric layer and the first dielectric layer are made of different materials, and the second dielectric layer and the third dielectric layer are made of different materials.

9. The manufacturing method according to claim 8, characterized in that: After bonding the first semiconductor layer and the initial second semiconductor layer, the method further comprises: The initial second semiconductor layer is thinned to form a second semiconductor layer, and the second semiconductor layer is used to form a semiconductor device; wherein the semiconductor device dissipates heat through the third dielectric layer, the conductive structure and the first dielectric layer.

10. The manufacturing method according to claim 9, characterized in that: After thinning the initial second semiconductor layer to form the second semiconductor layer, the method further comprises: forming a gate structure on a side of the second semiconductor layer away from the third dielectric layer, the gate structure comprising a gate electrode layer and a gate dielectric layer disposed between the second semiconductor layer and the gate electrode layer; A source region and a drain region are respectively formed in the second semiconductor layer at opposite sides of the gate structure.

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