Silicon through hole array layout structure for UCIe interconnection repair
By adopting a spiral alternately distributed via-silicon array layout structure in three-dimensional integrated circuits, the problem of insufficient fault tolerance of TSV clustering faults is solved, and the yield rate of the chip is significantly improved.
Patent Information
- Application Number
- CN202411837029.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-18
AI Technical Summary
The prior art lacks fault tolerance for TSV clustering faults based on redundant TSV architecture in three-dimensional integrated circuits, resulting in a low yield of three-dimensional integrated circuits.
A through-silicon array layout structure is adopted, including a through-hole first link and a through-hole second link, and the two are spiral alternately distributed to improve the fault tolerance of TSV clustering faults.
By alternately setting through silicon holes in a spiral wound form, ensuring that each TSV neighbor is arranged in different TSV links as much as possible, greatly improving the fault tolerance of TSV clustering faults and improving the yield rate of chip production.
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Figure CN119855242A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a through silicon via array layout structure for UCIe interconnect repair. Background Art
[0002] Through-Silicon Via (TSV) technology is a popular interconnection technology for three-dimensional integrated circuits (3DIC) and chiplets. In chiplets, small chips (die) are interconnected through micro-bumps, and TSV is one of the ways. Three-dimensional integrated circuits use TSV to stack two or more active device layers in the vertical direction, which not only reduces the length of the interconnection line, reduces the size of the chip, and increases the data bandwidth, but also has the characteristics of heterogeneous integration. Therefore, it has attracted more and more attention from the semiconductor industry. Due to the immature manufacturing process, TSV may fail during the assembly and stacking process, misalignment during the TSV pad alignment process may cause interconnection failure, or open circuit failure may occur due to insufficient filling of conductive materials in TSV, which greatly reduces the yield of three-dimensional integrated circuits. Therefore, in order to improve the yield of three-dimensional integrated circuits, a certain number of redundant TSVs are generally set for these TSV arrays. When a TSV fails, its signal can be routed to the redundant TSV for transmission through some designs. Therefore, the design method of the redundant TSV architecture is very important for TSV fault tolerance. Summary of the invention
[0003] The main technical problem solved by the present application is how to improve the fault tolerance capability of TSV clustering based on redundant TSV architecture.
[0004] In one embodiment, a through silicon via array layout structure for UCIe interconnect repair is provided, including a first through silicon via link and a second through silicon via link for TSV cluster fault tolerance, wherein the first through silicon via link includes a plurality of first through silicon vias separated from each other, and the second through silicon via link includes a plurality of second through silicon vias separated from each other; the first through silicon via link is spirally distributed around the endpoint through silicon vias of the first through silicon via link and the endpoint through silicon vias of the second through silicon via link, the second through silicon via link is spirally distributed around the endpoint through silicon vias of the first through silicon via link and the endpoint through silicon vias of the second through silicon via link, and the first through silicon via link and the second through silicon via link are spirally distributed alternately.
[0005] In one embodiment, the endpoint TSV is a starting TSV or a last TSV in the first TSV link and the second TSV link.
[0006] In one embodiment, the number of through silicon vias included in the first through via link is the same as the number of through silicon vias included in the second through via link.
[0007] In one embodiment, the first through-via link includes an even number of through-silicon vias, and the number of the through-silicon vias included is not less than four.
[0008] In one embodiment, the through silicon via array layout structure includes at least one first type through silicon via interconnection area, and the through silicon vias included in the first type through silicon via interconnection area are arranged in an array in the same area; wherein each of the through silicon via interconnection areas includes the first through silicon via link and the second through silicon via link.
[0009] In one embodiment, the through silicon via array layout structure further includes: a through via third link, the through via third link including a plurality of third through silicon vias separated from each other, the through via first link being spirally distributed around the endpoint through silicon vias of the through via first link, the endpoint through silicon vias of the through via second link, and the endpoint through silicon vias of the through via third link, the through via second link being spirally distributed around the endpoint through silicon vias of the through via first link, the endpoint through silicon vias of the through via second link, and the endpoint through silicon vias of the through via third link, the through via third link being spirally distributed around the endpoint through silicon vias of the through via first link, the endpoint through silicon vias of the through via second link, and the endpoint through silicon vias of the through via third link, and the through via first link, the through via second link, and the through silicon vias of the through via third link are alternately distributed in a spiral manner in a predetermined order.
[0010] In one embodiment, the through silicon via array layout structure includes at least one second type through silicon via interconnection area, and the second type through silicon via interconnection area includes through silicon vias arranged in an array in the same area; wherein each of the through silicon via interconnection areas includes the first through silicon via link, the second through silicon via link and the third through silicon via link.
[0011] In one embodiment, the through silicon via array layout structure further includes: a through hole fourth link, the through hole fourth link includes a plurality of fourth through silicon vias separated from each other, the through hole first link is spirally distributed around the endpoint through silicon vias of the through hole first link, the endpoint through silicon vias of the through hole second link, the endpoint through silicon vias of the through hole third link, and the endpoint through silicon vias of the through hole fourth link, the through hole second link is spirally distributed around the endpoint through silicon vias of the through hole first link, the endpoint through silicon vias of the through hole second link, the endpoint through silicon vias of the through hole third link, and the endpoint through silicon vias of the through hole fourth link, The third through-via link is spirally distributed around the endpoint silicon vias of the first through-via link, the endpoint silicon vias of the second through-via link, the endpoint silicon vias of the third through-via link, and the endpoint silicon vias of the fourth through-via link; the fourth through-via link is spirally distributed around the endpoint silicon vias of the first through-via link, the endpoint silicon vias of the second through-via link, the endpoint silicon vias of the third through-via link, and the endpoint silicon vias of the fourth through-via link; the first through-via link, the second through-via link, the third through-via link, and the fourth through-via link are alternately distributed in a spiral in a predetermined order.
[0012] In one embodiment, the through silicon via array layout structure includes at least one third type through silicon via interconnection area, and the through silicon vias included in the third type through silicon via interconnection area are arranged in an array in the same area; wherein each of the through silicon via interconnection areas includes the first through silicon via link, the second through silicon via link, the third through silicon via link and the fourth through silicon via link.
[0013] In one embodiment, the through silicon vias included in the third type through hole interconnection area are arranged in a central symmetrical manner.
[0014] According to the through silicon via array layout structure in the above embodiment, since the through silicon vias in multiple groups of TSV links are arranged alternately in a mutually winding spiral manner, each TSV neighbor is arranged in a different TSV link as much as possible, which greatly improves the fault tolerance capability of TSV clustering and improves the yield rate of chip production. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 is a schematic diagram of remapping for UCIe repair; Figure 2 Schematic diagram of interconnect module micro-bump layout and repair chain signal mapping in UCIe; Figure 3 A schematic diagram of a dual-link through silicon via array layout structure in an embodiment; Figure 4 A schematic diagram of a through silicon via array layout structure of three links in an embodiment; Figure 5A schematic diagram of a through silicon via array layout structure of four links in an embodiment; Figure 6 A histogram of the fault recovery capability of rectangular array arrangement versus clustered window; Figure 7 The bar graph shows the fault recovery capability of the spiral cross-arrangement versus the aggregation window. DETAILED DESCRIPTION
[0016] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.
[0017] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.
[0018] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).
[0019] Due to the differences in the processes of each manufacturer, the functions of small chips may not be compatible. In order to define the standards for chiplets in the industry, Tel took the lead in initiating a new interconnection standard, namely Universal Chiplet Interconnect Express (UCIe). The standards for the interconnection level of small chips are defined in the UCIe White Paper 2.0. Under the advanced packaging standards, the interconnection at the electrical level can be carried out in modules. The x64 interconnection consists of two x32 modules. Each x32 module includes 32 signal channels (lanes) and two redundant channels. TSV is used as the data transmission channel at the physical level. Each module consists of 32 signal through silicon vias (Signal TSV, STSV) and 2 redundant through silicon vias (Redundant TSV, RTSV). When an interconnection fault occurs in the data channel STSV, the self-repair mechanism can call the RTSV resources within the module to remap the faulty STSV (Fault TSV, FTSV) signal, and perform a signal shift operation through the repair chain composed of multiplexers (Multiplexer, MUX) to shift the signal left or right.
[0020] Please refer to Figure 1 , is a remapping diagram for UCIe repair. Under this repair scheme, 32 physical data channels are equipped with 2 redundant channels, and at most two interconnect failures can be repaired in one module. When two faults occur in the TSV interconnect, the signal of the first interconnect failure is remapped to the left (left shift) through the MUX repair chain, that is, Figure 1 The green darkened arrow part of the path; remap the second interconnection fault signal to the right (right shift), i.e. Figure 1 The yellow darkened arrow part of the path; and the TSV normal interconnection between the two faults. Figure 1 The blue darkened arrow part of the path can complete the self-repair work of the shift operation.
[0021] Please refer to Figure 2 , which is a schematic diagram of the micro-bump layout and repair chain signal mapping of the interconnection module in UCIe. The layout of the interconnection module of UCIe centrally arranges the data channels and redundant channels of a single module in one area. Figure 2The schematic diagram of the x64 layout and repair chain in UCIe is shown. The TSV and repair chain of module1 are marked in blue, and the repair chain of module2 is marked in gray. This layout arranges all signals in a single module in a centralized manner to achieve TSV between neighbors in the same group, which makes it easier to find the signal mapping path. There are no more than two faults in a single module, and they can all be repaired through the repair chain.
[0022] In the actual chiplet generation process, due to the influence of silicon surface roughness and cleanliness as well as bonding technology, TSV failures tend to be clustered. If one TSV fails, its adjacent TSVs may also fail. Therefore, TSV failures are mostly clustered rather than evenly distributed on the chip. A failed TSV that has already appeared on the chip will affect the probability of failure of nearby TSVs, and this probability has a certain corresponding relationship with the distance of the failed TSV. Assume that N d A faulty TSV already exists, then TSV i The probability of failure P i It can be expressed as: ; Among them, d ij represents the distance between the ith TSV and the jth faulty TSV, α represents the clustering factor, and P i Larger values indicate a higher degree of aggregation.
[0023] The clustering of faults will cause a large number of faults to cluster in a small area. In the original solution, the two modules are separated from each other in space. If multiple faults are clustered in a small area, then these faults are likely to be located in the same module, which will cause the number of faults in a module to easily exceed the maximum number that can be repaired (preset to be two).
[0024] In view of the situation where TSV failures are distributed in clusters, a method is designed in an embodiment of the present application to effectively improve the repair rate without affecting the wiring length, power consumption, Lane overhead and delay overhead of the UCIe solution.
[0025] Embodiment 1: Please refer to Figure 3, is a schematic diagram of a through silicon via array layout structure of a dual link in an embodiment, wherein the through silicon via array layout structure includes a through via first link and a through via second link for TSV cluster fault tolerance. Among them, the through via first link includes a plurality of first through silicon vias separated from each other, the through via second link includes a plurality of second through silicon vias separated from each other, the through via first link is spirally distributed around the endpoint through silicon vias of the through via first link and the endpoint through silicon vias of the through via second link, the through via second link is spirally distributed around the endpoint through silicon vias of the through via first link and the endpoint through silicon vias of the through via second link, and the through via first link and the through via second link are spirally distributed alternately. In one embodiment, the endpoint through silicon via is the starting through silicon via or the ending through silicon via in the through via first link and the through via second link. In one embodiment, the number of through silicon vias included in the through via first link is the same as the number of through silicon vias included in the through via second link. In one embodiment, the through via first link includes an even number of through silicon vias, and the number of through silicon vias included is not less than four.
[0026] In one embodiment, the through-via array layout structure includes at least one first-type through-via interconnection area, wherein the first-type through-via interconnection area includes through-silicon vias arranged in an array in the same area, wherein each through-via interconnection area includes a first through-via link and a second through-via link.
[0027] like Figure 3 As shown, the first through silicon vias included in the first through silicon via link include through silicon vias numbered from 1 to 32 and two through silicon vias marked as R, wherein one of the two through silicon vias marked as R is the starting through silicon via of the first through silicon via link, and the other is the ending through silicon via of the first through silicon via link. The second through silicon vias included in the second through silicon via link include through silicon vias numbered from 1 to 32 and two through silicon vias marked as R, wherein one of the two through silicon vias marked as R is the starting through silicon via of the second through silicon via link, and the other is the ending through silicon via of the second through silicon via link.
[0028] In this embodiment, in order to improve the repair rate of cluster failures without increasing any area delay overhead, the layout of two interconnected through-hole interconnection areas of the advanced package X64 is optimized, and the specific layout optimization follows the following rules: Rule 1: When the positions of all through silicon via (TSV) points in the original array remain unchanged, rearrange the TSV arrangement of at least two module areas (through hole links) to avoid increasing the chip area overhead. Assuming the coordinates of a certain TSV are (x, y), there must be at least one TSV in the same link in the neighbors {(x, y+1), (x, y-1), (x+1, y), (x-1, y)} of any TSV in the first through hole link and the second through hole link, so that the wiring length remains unchanged from the original solution and the delay overhead is not increased.
[0029] Rule 2: Each TSV has more TSVs with different through-hole links in its immediate neighborhood, so that the faults can be distributed within two through-hole links as much as possible.
[0030] Under the constraint of Rule 1, the total number of TSVs of different through-hole links near each neighbor TSV in Rule 2 is calculated, and the one with a larger total number can be considered as a local optimal solution.
[0031] By solving the above algorithm, the embodiments of the present application disclose the following Figure 3 The spiral cross arrangement structure shown in FIG. The first through-hole link and the second through-hole link are arranged in a spiral cross arrangement, and the spacing between the "adjacent" Data Lanes in each through-hole link is the minimum value, that is, it satisfies Rule 1. Therefore, compared with Figure 2 The original solution shown does not introduce additional delay overhead. In addition, in this arrangement structure, each TSV neighbor arranges TSVs of different through-hole links as much as possible, that is, it satisfies Rule 2 and achieves a local optimal solution.
[0032] Compared with Figure 2 The original scheme shown, Figure 3 The improved through silicon via array layout structure shown has significantly improved the repair capability for clustered faults. The two through-hole links are closely intertwined in space. If multiple faults clustered in one place occur, there is a high probability that these faults will not be concentrated in one through-hole link, but will be dispersed in two through-hole links, that is, there is a high probability that the repair pressure of the clustered faults will be shared by the two through-hole links. Therefore, the improved through silicon via array layout structure can effectively improve the repair capability for clustered faults without increasing any overhead.
[0033] The through silicon via array layout structure disclosed in the embodiment of the present application includes a first through-hole link and a second through-hole link for TSV cluster fault tolerance, wherein the first through-hole link includes a plurality of first through-silicon vias separated from each other, and the second through-hole link includes a plurality of second through-silicon vias separated from each other. Among them, the first through-hole link is spirally distributed around the endpoint through-silicon vias of the first through-hole link and the endpoint through-silicon vias of the second through-hole link, the second through-hole link is spirally distributed around the endpoint through-silicon vias of the first through-hole link and the endpoint through-silicon vias of the second through-hole link, and the first through-hole link and the second through-hole link are spirally distributed alternately. Since the through-silicon vias in multiple groups of TSV links are arranged alternately in a mutually winding spiral, each TSV neighbor is arranged in a different TSV link as much as possible, which greatly improves the fault tolerance capability of TSV cluster and improves the yield rate of chip production.
[0034] Embodiment 2: Please refer to Figure 4, is a schematic diagram of a through silicon via array layout structure of three links in an embodiment. On the basis of the first embodiment, the through silicon via array layout structure also includes a through-hole third link, and the through-hole third link includes a plurality of third through silicon vias separated from each other. The through-hole first link is spirally distributed around the end point through silicon vias of the first through-hole link, the end point through silicon vias of the second through-hole link, and the end point through silicon vias of the third through-hole link. The through-hole second link is spirally distributed around the end point through silicon vias of the first through-hole link, the end point through silicon vias of the second through-hole link, and the end point through silicon vias of the third through-hole link. The through-hole third link is spirally distributed around the end point through silicon vias of the first through-hole link, the end point through silicon vias of the second through-hole link, and the end point through silicon vias of the third through-hole link. The through-hole first link, the through-hole second link, and the through-hole third link are alternately distributed in a spiral according to a predetermined order. In one embodiment, the through silicon via array layout structure includes at least one second type through-hole interconnection area, and the through silicon vias included in the second type through-hole interconnection area are arranged in an array in the same area, wherein each through-hole interconnection area includes a first through-hole link, a second through-hole link, and a third through-hole link.
[0035] Embodiment three: Please refer to Figure 5 , is a schematic diagram of a through silicon via array layout structure of four links in an embodiment. On the basis of the second embodiment, the through silicon via array layout structure further includes a through hole fourth link, the through hole fourth link includes a plurality of fourth through silicon vias separated from each other, the through hole first link is spirally distributed around the endpoint through silicon vias of the through hole first link, the endpoint through silicon vias of the through hole second link, the endpoint through silicon vias of the through hole third link, and the endpoint through silicon vias of the through hole fourth link, the through hole second link is spirally distributed around the endpoint through silicon vias of the through hole first link, the endpoint through silicon vias of the through hole second link, the endpoint through silicon vias of the through hole third link, and the through silicon vias of the through hole fourth link. The endpoint silicon vias of the fourth link of the through hole are spirally distributed, the third link of the through hole is spirally distributed around the endpoint silicon vias of the first link of the through hole, the endpoint silicon vias of the second link of the through hole, the endpoint silicon vias of the third link of the through hole, and the endpoint silicon vias of the fourth link of the through hole, the fourth link of the through hole is spirally distributed around the endpoint silicon vias of the first link of the through hole, the endpoint silicon vias of the second link of the through hole, the endpoint silicon vias of the third link of the through hole, and the endpoint silicon vias of the fourth link of the through hole, and the first link of the through hole, the second link of the through hole, the third link of the through hole, and the fourth link of the through hole are spirally distributed alternately in a predetermined order. In one embodiment, the through silicon via array layout structure includes at least one third type of through hole interconnection area, and the silicon vias included in the third type of through hole interconnection area are arranged in an array in the same area, wherein each through hole interconnection area includes the first link of the through hole, the second link of the through hole, the third link of the through hole, and the fourth link of the through hole. In one embodiment, the silicon vias included in the third type of through hole interconnection area are arranged in a central symmetrical manner.
[0036] In order to facilitate understanding of the significant improvement in the cluster fault repair capability of the through silicon via array layout structure disclosed in the embodiments of the present application, the following comparison of the repair rate data is performed by using a cluster window method, specifically including: The clustering window is the area where the faulty TSVs (FTSVs) are clustered together, and is used for clustered fault injection. In the TSV fault distribution model (compound Poisson distribution), the probability of more than four faults occurring in a chip is very low. The clustering window can be used here to simulate the extreme case of fault distribution. The Monte Carlo method is used to randomly inject 1 to 4 faults in the 2×2, 3×3, and 4×4 clustering windows, and 100,000 simulated fault injections are performed to calculate the repair rate.
[0037] Please refer to Table 1, which shows the ability of a rectangular array normally arranged in a UCIe-x64 advanced package to repair the aggregation window. Number of TSV failures 2×2 Window 3×3 Window 4×4 Window 1 100.00% 100.00% 100.00% 2 100.00% 100.00% 100.00% 3 22.85% 36.97% 49.90% 4 20.52% 28.42% 39.85%
[0038] Please refer to Table 2, which shows the repair capability of the UCIe-x64 advanced package spirally cross-arranged rectangular array for the aggregation window. Number of TSV failures 2×2 Window 3×3 Window 4×4 Window 1 100.00% 100.00% 100.00% 2 100.00% 100.00% 100.00% 3 94.90% 86.69% 88.79% 4 79.79% 62.30% 68.61%
[0039] Tables 1 and 2 are respectively the rectangular arrays normally arranged in the UCIe x64 advanced package (e.g. Figure 2 ) and a cross-shaped rectangular array (as shown Figure 3 The ability to repair the clustered window is shown in Figure 2. Based on the two tables, we can conclude that: Each array can achieve 100% repair when facing less than two faults, because each through-hole link (module) contains two RTSVs for fault tolerance. As long as the number of faults does not exceed 2, they can be repaired through the shift operation of the MUX repair chain. When there are three or four faults, due to the clustering of defects, the faults distributed on the array with ordinary arrangement will most likely be concentrated on one through-hole link, and one through-hole link can only repair a maximum of two FTSVs, so the repair rate will be greatly reduced. In the rectangular array with spiral cross arrangement, the TSVs between the two through-hole links are staggered in space, and there are TSVs of different through-hole links near each TSV. The aggregated faults can be effectively dispersed in the two through-hole links, achieving the effect of improving the repair rate.
[0040] Please refer to Figure 6 and Figure 7, which are the repair rate bar graphs corresponding to Table 1 and Table 2, which are the bar graphs of the repair capability of the normal rectangular array to the clustering window and the bar graphs of the spiral cross arrangement scheme to the clustering window fault repair capability. The number axis represents the repair rate, and 1, 2, 3 and 4 represent the number of faults in the clustering window. Figure 6 It can be clearly seen that the normal arrangement has a poor ability to repair more than two faults, and the worst case is only 20%. Figure 5 It is obvious that the repair rate of clustered faults is much higher than that of the normal arrangement scheme. In the 2×2 clustering window, the fault repair capability is 4-5 times that of the normal arrangement scheme.
[0041] The above specific examples are used to illustrate the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art, according to the concept of the present invention, some simple deductions, modifications or substitutions can be made.
Claims
1. A through silicon via array layout structure for UCIe interconnect repair, characterized in that: The invention comprises a first through-via link and a second through-via link for TSV cluster fault tolerance, wherein the first through-via link comprises a plurality of first through-silicon vias separated from each other, and the second through-via link comprises a plurality of second through-silicon vias separated from each other; the first through-via link is spirally distributed around the endpoint through-silicon vias of the first through-via link and the endpoint through-silicon vias of the second through-via link, the second through-via link is spirally distributed around the endpoint through-silicon vias of the first through-via link and the endpoint through-silicon vias of the second through-via link, and the first through-via link and the second through-via link are spirally distributed alternately.
2. The through silicon via array layout structure according to claim 1, characterized in that: The endpoint TSV is a starting TSV or a last TSV in the first TSV link and the second TSV link.
3. The through silicon via array layout structure according to claim 2, characterized in that: The number of through silicon vias included in the first through via link is the same as the number of through silicon vias included in the second through via link.
4. The through silicon via array layout structure according to claim 3, characterized in that: The first through-hole link includes an even number of through-silicon vias, and the number of the through-silicon vias included is not less than four.
5. The through silicon via array layout structure according to claim 1, wherein: It comprises at least one first type through-via interconnection area, wherein the through-silicon vias included in the first type through-via interconnection area are arranged in an array in the same area; wherein each of the through-via interconnection areas comprises the first through-via link and the second through-via link.
6. The through silicon via array layout structure according to claim 1, wherein: Also includes: A third through-via link, wherein the third through-via link comprises a plurality of third through-silicon vias separated from each other, the first through-via link is spirally distributed around the endpoint through-silicon vias of the first through-via link, the endpoint through-silicon vias of the second through-via link, and the endpoint through-silicon vias of the third through-via link, the second through-via link is spirally distributed around the endpoint through-silicon vias of the first through-via link, the endpoint through-silicon vias of the second through-via link, and the endpoint through-silicon vias of the third through-via link, the third through-via link is spirally distributed around the endpoint through-silicon vias of the first through-via link, the endpoint through-silicon vias of the second through-via link, and the endpoint through-silicon vias of the third through-via link, and the first through-via link, the second through-via link, and the third through-via link are alternately distributed in a spiral in a predetermined order.
7. The through silicon via array layout structure according to claim 6, characterized in that: It includes at least one second type of through-hole interconnection area, wherein the silicon through-holes included in the second type of through-hole interconnection area are arranged in an array in the same area; wherein each of the through-hole interconnection areas includes the first through-hole link, the second through-hole link and the third through-hole link.
8. The through silicon via array layout structure according to claim 6, characterized in that: Also includes: The through-hole fourth link comprises a plurality of fourth silicon through vias separated from each other, the through-hole first link is spirally distributed around the end silicon through vias of the through-hole first link, the end silicon through vias of the through-hole second link, the end silicon through vias of the through-hole third link, and the end silicon through vias of the through-hole fourth link, the through-hole second link is spirally distributed around the end silicon through vias of the through-hole first link, the end silicon through vias of the through-hole second link, the end silicon through vias of the through-hole third link, and the end silicon through vias of the through-hole fourth link, the through-hole third link is spirally distributed around the end silicon through vias of the through-hole first link, the end silicon through vias of the through-hole second link, the end silicon through vias of the through-hole third link, and the end silicon through vias of the through-hole fourth link, the through-hole third link is spirally distributed around the end silicon through vias of the through-hole The through silicon vias at the endpoints of the first through-via link, the second through-via link, the third through-via link, and the fourth through-via link are spirally distributed; the fourth through-via link is spirally distributed around the endpoint through silicon vias of the first through-via link, the second through-via link, the third through-via link, and the fourth through-via link; the first through-via link, the second through-via link, the third through-via link, and the fourth through-via link are alternately distributed in a spiral in a predetermined order.
9. The through silicon via array layout structure according to claim 8, characterized in that: It includes at least one third type of through-hole interconnection area, wherein the silicon through-holes included in the third type of through-hole interconnection area are arranged in an array in the same area; wherein each of the through-hole interconnection areas includes the first through-hole link, the second through-hole link, the third through-hole link and the fourth through-hole link.
10. The through silicon via array layout structure according to claim 9, characterized in that: The through silicon vias included in the third type through hole interconnection area are arranged in a central symmetrical manner.