Light emitting diode and preparation method thereof

Abstract

The invention provides a light emitting diode and a preparation method thereof. The light-emitting diode comprises a three-dimensional nucleating layer, a two-dimensional filling layer, a hollow structure layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer, the three-dimensional nucleating layer, the two-dimensional filling layer, the hollow structure layer, the first semiconductor layer, the light-emitting layer and the second semiconductor layer are stacked in sequence; the hollow structure layer comprises a three-dimensional growth sub-layer and a two-dimensional covering sub-layer which are sequentially stacked on the two-dimensional filling and leveling layer, and the three-dimensional growth sub-layer comprises a hollow structure. The hollow structure layer can effectively improve the thickness consistency of the epitaxial wafer, thereby improving the light-emitting wavelength consistency and brightness consistency.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for preparing the same. Background Art

[0002] Micro Light Emitting Diode (Micro LED) is a semiconductor electronic component that can emit light and is commonly used in the field of display screens.

[0003] The related art provides a micro light emitting diode, which includes a three-dimensional nucleation layer, a two-dimensional filling layer, a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in sequence.

[0004] The above-mentioned micro light-emitting diode will generate stress during the process of making the three-dimensional nucleation layer, two-dimensional filling layer, first semiconductor layer, light-emitting layer and second semiconductor layer, causing the epitaxial wafer composed of the above-mentioned film layers to bend, resulting in uneven thickness of the epitaxial wafer, thereby affecting the light-emitting quality of the light-emitting diode. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode and a method for manufacturing the same, which can effectively improve the thickness uniformity of the epitaxial wafer, thereby improving the light emitting quality of the light emitting diode. The technical solution is as follows:

[0006] In one aspect, a light emitting diode is provided, the light emitting diode comprising:

[0007] A three-dimensional nucleation layer, a two-dimensional filling layer, a hollow structure layer, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer;

[0008] The three-dimensional nucleation layer, the two-dimensional filling layer, the hollow structure layer, the first semiconductor layer, the light-emitting layer and the second semiconductor layer are stacked in sequence;

[0009] The hollow structure layer includes: a three-dimensional growth sublayer and a two-dimensional covering sublayer sequentially stacked on the two-dimensional filling layer, and the three-dimensional growth sublayer includes a hollow structure.

[0010] Optionally, the three-dimensional growth sublayer is a GaN sublayer, and the two-dimensional cover sublayer is a GaN or AlGaN sublayer.

[0011] Optionally, the thickness of the three-dimensional growth sublayer is 10 to 1000 nm, and the thickness of the two-dimensional covering sublayer is 100 to 2000 nm.

[0012] Optionally, the hollow structure layer includes a superlattice structure consisting of 2 to 20 periods of the three-dimensional growth sublayer and the two-dimensional covering sublayer.

[0013] In another aspect, a method for preparing a light emitting diode comprises:

[0014] Making a three-dimensional nucleation layer;

[0015] Making a two-dimensional filling layer on the three-dimensional nucleation layer;

[0016] A hollow structure layer is fabricated on the two-dimensional filling layer, wherein the hollow structure layer comprises: a three-dimensional growth sublayer and a two-dimensional covering sublayer sequentially stacked on the two-dimensional filling layer, wherein the three-dimensional growth sublayer comprises a hollow structure;

[0017] Fabricating a first semiconductor layer on the hollow structure layer;

[0018] forming a light-emitting layer on the first semiconductor layer;

[0019] A second semiconductor layer is formed on the light emitting layer.

[0020] Optionally, a hollow structure layer is fabricated on the two-dimensional filling layer, comprising:

[0021] growing the three-dimensional growth sublayer in a pure nitrogen atmosphere;

[0022] Treating the three-dimensional growth sublayer under a pure hydrogen atmosphere so that the three-dimensional growth sublayer forms a hollow structure;

[0023] The two-dimensional cover sublayer is grown under a pure hydrogen atmosphere.

[0024] Optionally, ammonia is used as the N source when growing the three-dimensional growth sublayer, and the concentration ratio of nitrogen to ammonia is 3:1 to 10:1;

[0025] When growing the two-dimensional cover sublayer, ammonia is used as the N source, and the concentration ratio of hydrogen to ammonia is 5:1 to 30:1.

[0026] Optionally, growing the three-dimensional growth sublayer in a pure hydrogen atmosphere comprises:

[0027] The three-dimensional growth sublayer with a thickness of 10 to 1000 nm is grown in a pure hydrogen atmosphere at a growth temperature of 900 to 1080° C., a growth pressure of 200 to 500 mtorr, and a growth rate of 5 to 15 μm / h.

[0028] Optionally, the processing of the three-dimensional growth sublayer under a pure hydrogen atmosphere so that the three-dimensional growth sublayer forms a hollow structure includes:

[0029] The three-dimensional growth sublayer is treated in a pure hydrogen atmosphere at a growth temperature greater than 830-1100° C. and a growth pressure of 100-500 torr for 10-300 seconds, so that the three-dimensional growth sublayer forms a hollow structure.

[0030] Optionally, growing the two-dimensional cover sublayer in a pure hydrogen atmosphere comprises:

[0031] The two-dimensional covering sublayer with a thickness of 100 to 2000 nm is grown in a pure hydrogen atmosphere at a growth temperature of 1100 to 1150° C., a growth pressure of 100 to 500 mtorr, and a growth rate of 5 to 10 μm / h.

[0032] The technical solution provided by the embodiments of the present disclosure brings the following beneficial effects:

[0033] In the disclosed embodiment, a hollow structure layer is arranged between the two-dimensional filling layer and the first semiconductor layer of the light-emitting diode, and the hollow structure layer includes a three-dimensional growth sublayer and a two-dimensional covering sublayer in sequence. Among them, the three-dimensional growth sublayer is arranged on the two-dimensional filling layer. Since it is grown in a three-dimensional manner, it can provide conditions for the subsequent production of a hollow structure. The three-dimensional growth sublayer includes a hollow structure, that is, the three-dimensional growth sublayer has a hollow (that is, a "hole") inside, which can leave space for stress release for epitaxial materials such as GaN during the subsequent semiconductor layer production process, so that the stress is effectively released and the epitaxial bending is avoided. The two-dimensional covering sublayer can quickly cover the "hole", so that the surface of the three-dimensional growth sublayer is restored to flatness, and the uniformity of the epitaxial thickness is improved. In summary, by setting a hollow structure layer, stress release can be achieved, the epitaxial curvature can be reduced, the consistency of the epitaxial thickness can be improved, and the light-emitting quality of the light-emitting diode can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0036] Figure 2 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0037] Figure 3 This is a flow chart of another method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0038] The reference numerals are as follows:

[0039] 101: substrate; 102: buffer layer; 103: three-dimensional nucleation layer; 104: two-dimensional filling layer; 105: hollow structure layer; 106: first semiconductor layer; 107: light-emitting layer; 108: electron blocking layer; 109: second semiconductor layer; 201: three-dimensional growth sublayer; 202: two-dimensional covering sublayer. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0041] Figure 1 A schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 The light emitting diode comprises: a three-dimensional nucleation layer 103, a two-dimensional filling layer 104, a hollow structure layer 105, a first semiconductor layer 106, a light emitting layer 107 and a second semiconductor layer 109;

[0042] The three-dimensional nucleation layer 103, the two-dimensional filling layer 104, the hollow structure layer 105, the first semiconductor layer 106, the light-emitting layer 107 and the second semiconductor layer 109 are stacked in sequence;

[0043] The hollow structure layer 105 includes: a three-dimensional growth sublayer 201 and a two-dimensional covering sublayer 202 sequentially stacked on the two-dimensional filling layer 104, and the three-dimensional growth sublayer 201 includes a hollow structure.

[0044] The light emitting diode provided in the embodiment of the present disclosure may be a micro light emitting diode.

[0045] In the disclosed embodiment, a hollow structure layer is arranged between the two-dimensional filling layer and the first semiconductor layer of the light-emitting diode, and the hollow structure layer includes a three-dimensional growth sublayer and a two-dimensional covering sublayer in sequence. Among them, the three-dimensional growth sublayer is arranged on the two-dimensional filling layer. Since it is grown in a three-dimensional manner, it can provide conditions for the subsequent production of a hollow structure. The three-dimensional growth sublayer includes a hollow structure, that is, the three-dimensional growth sublayer has a hollow (that is, a "hole") inside, which can leave space for stress release for epitaxial materials such as GaN during the subsequent semiconductor layer production process, so that the stress is effectively released and the epitaxial bending is avoided. The two-dimensional covering sublayer can quickly cover the "hole", so that the surface of the three-dimensional growth sublayer is restored to flatness, and the uniformity of the epitaxial thickness is improved. In summary, by setting a hollow structure layer, stress release can be achieved, the epitaxial curvature can be reduced, the consistency of the epitaxial thickness can be improved, and the light-emitting quality of the light-emitting diode can be improved.

[0046] In the embodiment of the present disclosure, the three-dimensional growth sublayer 201 is a GaN sublayer, and the two-dimensional cover sublayer 202 is a GaN or AlGaN sublayer.

[0047] In this implementation, the three-dimensional growth sublayer is a GaN sublayer, and GaN can be distributed in an island shape, with convex and concave shapes formed on the surface as the basis for the subsequent production of a hollow structure; the three-dimensional growth sublayer includes a hollow structure, and the GaN in the three-dimensional growth sublayer has unstable polycrystals or impurities. By retaining the thermodynamically stable hexagonal structure as the stable-phase GaN crystal nucleus, the obtained 3D nucleation island has a GaN lattice with the same crystal orientation, which reduces the probability of GaN lattice distortion, so that the surface of the hollow structure forms a similar "void" phenomenon at a microscopic level, leaving space for the epitaxial structure to release stress; the two-dimensional covering sublayer is a GaN or AlGaN sublayer, which can quickly cover the "void", restore the surface morphology flatness of the hollow structure, and improve the thickness uniformity of the epitaxial wafer. In addition, by combining GaN material or GaN material and AlGaN material, the composite structure has a stress release effect.

[0048] In the embodiment of the present disclosure, the thickness of the three-dimensional growth sublayer 201 may be 10-1000 nm.

[0049] Exemplarily, the thickness of the three-dimensional growth sublayer 201 is 300 nm.

[0050] The three-dimensional growth sublayer manufactured with the above thickness will not be too thin to affect the manufacturing of the hollow structure, nor will it be too thick to cause the light emitting diode to be too thick as a whole.

[0051] In the embodiment of the present disclosure, the thickness of the two-dimensional cover sublayer 202 is 100-2000 nm.

[0052] Exemplarily, the thickness of the two-dimensional cover sublayer 202 is 500 nm.

[0053] The two-dimensional covering sublayer manufactured with the above thickness will not be too thin to cause uneven coverage of the surface of the hollow structure, nor will it be too thick to cause the light-emitting diode to be too thick as a whole.

[0054] In an implementation of the embodiment of the present disclosure, the hollow structure layer 105 only includes a three-dimensional growth sublayer 201 and a two-dimensional covering sublayer 202 .

[0055] In another implementation of the embodiment of the present disclosure, the hollow structure layer 105 may include a superlattice structure composed of 2 to 20 periods of three-dimensional growth sublayers 201 and two-dimensional cover sublayers 202. Using a superlattice structure of multiple periods to form the hollow structure layer 105 can provide more stress release space, which is conducive to avoiding epitaxial bending.

[0056] Exemplarily, the hollow structure layer includes a superlattice structure consisting of 10 periods of three-dimensional growth sublayers 201 and two-dimensional cover sublayers 202 .

[0057] In the embodiment of the present disclosure, the light-emitting diode also includes: a substrate 101 and a buffer layer 102, wherein the buffer layer 102, a three-dimensional nucleation layer 103, a two-dimensional filling layer 104, a hollow structure layer 105, a first semiconductor layer 106, a light-emitting layer 107 and a second semiconductor layer 109 are sequentially stacked on the substrate 101.

[0058] In the embodiment of the present disclosure, the substrate 101 may be a gallium nitride, sapphire, patterned sapphire, SiC or Si substrate.

[0059] Exemplarily, the substrate is a sapphire patterned substrate.

[0060] In the embodiment of the present disclosure, the substrate 101 may be a 4-inch, 6-inch or 8-inch substrate, and may be applied to large-size epitaxial light-emitting diodes.

[0061] By way of example, the substrate 101 may be a 4-inch substrate.

[0062] Exemplarily, the light-emitting diode provided in the embodiment of the present disclosure may be a large-sized Micro LED.

[0063] In the embodiment of the present disclosure, the buffer layer 102 may be an AlN thin film layer.

[0064] In the embodiment of the present disclosure, the buffer layer 102 may be manufactured by physical vapor deposition (PVD), for example, by magnetron sputtering.

[0065] Exemplarily, the thickness of the buffer layer 102 may be 10-50 nm, for example, 30 nm.

[0066] In the embodiment of the present disclosure, the three-dimensional nucleation layer 103 may be a GaN layer manufactured by using a metal-organic chemical vapor deposition (MOCVD) method.

[0067] Exemplarily, the thickness of the three-dimensional nucleation layer 103 may be 0.3-2 nm, for example, 1 nm.

[0068] In the embodiment of the present disclosure, the two-dimensional filling layer 104 may be an undoped GaN layer.

[0069] In the embodiment of the present disclosure, the first semiconductor layer 106 may be an N-type GaN layer.

[0070] In an embodiment of the present disclosure, the light-emitting layer 107 may be a multi-quantum well barrier layer.

[0071] In one example, the multi-quantum well barrier layer includes 8 to 15 periods of In x Ga 1-x N(0.2 < x < 0.5) / GaN (or AlGaN) multi-quantum well barrier layer, where the thickness of the InGaN quantum well layer in each period is 1.5 - 6 nm, and the thickness of the GaN or AlGaN quantum barrier layer in each period is 8 - 20 nm.

[0072] Exemplarily, the thickness of the InGaN quantum well layer is 3.6 nm, and the thickness of the GaN or AlGaN quantum barrier layer in each period is 9.5 nm.

[0073] In another example, the multi-quantum well barrier layer includes 12 periods of In x Ga 1-x N(0.2 < x < 0.5) / GaN (or AlGaN) multi-quantum well barrier layer.

[0074] Among them, the InGaN quantum well layer in each period includes a first sub-layer, a second sub-layer, a third sub-layer, and a fourth sub-layer stacked in sequence.

[0075] Among them, the first sub-layer is an In x Ga 1-x N(0 ≤ x ≤ 0.2) layer, where X can be 0.05 and the thickness can be 0.3 nm.

[0076] The second sub-layer is an In y Ga 1-y N(0.3 ≤ y ≤ 0.8) layer, where Y can be 0.5, the growth atmosphere is a mixed gas of nitrogen and ammonia, and the thickness can be 0.5 nm;

[0077] The third sub-layer is an In z Ga 1-z N(0.2 ≤ z ≤ 0.5) layer, where Z can be 0.35, the growth atmosphere is a mixed gas of nitrogen and ammonia, and the thickness can be 2.8 nm;

[0078] The fourth sub-layer is an In w Ga 1-w N(0 ≤ w ≤ 0.2) layer, where W can be 0.05, the growth atmosphere is a mixed gas of nitrogen, hydrogen, and ammonia, the hydrogen concentration ratio can be 5%, and the thickness can be 0.3 nm.

[0079] Among them, the thickness of the GaN or AlGaN quantum barrier layer in each period can be 9 nm.

[0080] In an embodiment of the present disclosure, the light-emitting diode further includes: an electron blocking layer 108, and the electron blocking layer 108 is located between the light-emitting layer 107 and the second semiconductor layer 109.

[0081] In an embodiment of the present disclosure, the electron blocking layer 108 can be an electron blocking Al y Ga 1-y N(0.1 < y < 0.5) layer.

[0082] Exemplarily, the thickness of the electron blocking layer 108 can be 10 to 100 nm, such as 50 nm.

[0083] In an embodiment of the present disclosure, the light-emitting diode may further include a P-type doped AlGaN layer between the electron blocking layer 108 and the light-emitting layer 107.

[0084] Wherein, the P-type doped AlGaN layer can be a P-type doped Al w Ga 1-w N(0.1 < w < 0.3) layer.

[0085] Exemplarily, the thickness of the P-type doped AlGaN layer can be 10 to 100 nm, such as 50 nm.

[0086] In an embodiment of the present disclosure, the second semiconductor layer 109 may include a high-temperature P-type GaN layer and a P-type doped GaN contact layer stacked in sequence.

[0087] Exemplarily, the thickness of the high-temperature P-type GaN layer can be 10 to 100 nm, such as 50 nm. The thickness of the P-type doped GaN contact layer can be 1 to 30 nm, such as 20 nm.

[0088] It should be noted that, in an embodiment of the present disclosure, the structure can be selectively increased or decreased based on the above structure of the light-emitting diode, and the present disclosure does not limit this.

[0089] Figure 2 A flowchart of a method for manufacturing a light-emitting diode provided by an embodiment of the present disclosure. Refer to Figure 2 , and the method steps include:

[0090] S11, fabricating a three-dimensional nucleation layer.

[0091] S12, fabricating a two-dimensional planarization layer on the three-dimensional nucleation layer.

[0092] S13, fabricating a hollow structure layer on the two-dimensional planarization layer, and the hollow structure layer includes: a three-dimensional growth sub-layer and a two-dimensional covering sub-layer stacked in sequence on the two-dimensional planarization layer, and the three-dimensional growth sub-layer includes a hollow structure.

[0093] S14, fabricating a first semiconductor layer on the hollow structure layer.

[0094] S15, forming a light-emitting layer on the first semiconductor layer.

[0095] S16. Fabricate a second semiconductor layer on the light-emitting layer.

[0096] In the disclosed embodiment, a hollow structure layer is arranged between the two-dimensional filling layer and the first semiconductor layer of the light-emitting diode, and the hollow structure layer includes a three-dimensional growth sublayer and a two-dimensional covering sublayer in sequence. Among them, the three-dimensional growth sublayer is arranged on the two-dimensional filling layer. Since it is grown in a three-dimensional manner, it can provide conditions for the subsequent production of a hollow structure. The three-dimensional growth sublayer includes a hollow structure, that is, the three-dimensional growth sublayer has a hollow (that is, a "hole") inside, which can leave space for stress release for epitaxial materials such as GaN during the subsequent semiconductor layer production process, so that the stress is effectively released and the epitaxial bending is avoided. The two-dimensional covering sublayer can quickly cover the "hole", so that the surface of the three-dimensional growth sublayer is restored to flatness, and the uniformity of the epitaxial thickness is improved. In summary, by setting a hollow structure layer, stress release can be achieved, the epitaxial curvature can be reduced, the consistency of the epitaxial thickness can be improved, and the light-emitting quality of the light-emitting diode can be improved.

[0097] Figure 3 Another light emitting diode manufacturing method provided by the present disclosure is a flow chart. Figure 3 The method steps include:

[0098] S21. Growing a buffer layer on the substrate.

[0099] In the embodiments of the present disclosure, the substrate may be a gallium nitride, sapphire, patterned sapphire, SiC or Si substrate.

[0100] Exemplarily, the substrate is a sapphire patterned substrate.

[0101] In the embodiment of the present disclosure, the buffer layer may be an AlN thin film layer.

[0102] In the embodiment of the present disclosure, the buffer layer can be manufactured by PVD method, for example, by magnetron sputtering method.

[0103] Exemplarily, the thickness of the buffer layer may be 10-50 nm, for example, 30 nm.

[0104] In the embodiment of the present disclosure, the growth conditions of the buffer layer may be: a growth temperature of 400-800° C., a growth pressure of 2-10 mtorr, and a sputtering power of 3000-5000W.

[0105] For example, the growth conditions of the buffer layer may be: a growth temperature of 500° C., a growth pressure of 10 mtorr, and a sputtering power of 4000W.

[0106] S22. Growing a three-dimensional nucleation layer on the buffer layer.

[0107] In the embodiment of the present disclosure, the three-dimensional nucleation layer may be a GaN layer manufactured by MOCVD.

[0108] Exemplarily, the thickness of the three-dimensional nucleation layer may be 0.3-2 nm, for example, 1 nm.

[0109] Exemplarily, the growth conditions of the three-dimensional nucleation layer may be: a growth temperature of 1030-1100° C. and a growth pressure of 150-500 mtorr in a mixed atmosphere of nitrogen, hydrogen and ammonia.

[0110] For example, the growth temperature is 1050°C and the growth pressure is 300 mtorr under the mixed atmosphere of nitrogen, hydrogen and ammonia.

[0111] S23. Growing a two-dimensional filling layer on the three-dimensional nucleation layer.

[0112] Exemplarily, a two-dimensional filling layer is grown on the three-dimensional nucleation layer by MOCVD.

[0113] In the embodiment of the present disclosure, the two-dimensional filling layer may be an undoped GaN layer.

[0114] Exemplarily, the growth conditions of the undoped semiconductor layer may include: a growth temperature of 1000-1150° C., a growth pressure of 100-500 Torr, and a growth thickness of 0.5-3 μm.

[0115] For example, the growth temperature is 1130° C., the growth pressure is 250 Torr, and the growth thickness is 2 μm.

[0116] S24, sequentially growing a three-dimensional growth sublayer and a two-dimensional covering sublayer on the two-dimensional filling layer, wherein the three-dimensional growth sublayer includes a hollow structure.

[0117] In the embodiment of the present disclosure, a hollow structure layer having a composite structure is arranged between the two-dimensional filling layer and the first semiconductor, wherein the hollow structure layer sequentially comprises a three-dimensional growth sublayer and a two-dimensional covering sublayer.

[0118] In one example, step S24 includes:

[0119] The first step is to grow a three-dimensional growth sublayer on the two-dimensional filling layer.

[0120] In the embodiment of the present disclosure, the three-dimensional growth sublayer is grown in a pure nitrogen atmosphere.

[0121] By using pure N2 to increase the average molecular density of GaN growth and reduce the diffusion length of reactive atoms, GaN can be distributed in an island shape, so that the three-dimensional growth sublayer forms convex and concave shapes.

[0122] In the embodiment of the present disclosure, ammonia is used as the N source when growing the three-dimensional growth sublayer, and the concentration ratio of nitrogen to ammonia is 3: 1 to 10: 1. With this ratio, nitrogen can be used as a nitrogen source, which helps to improve the growth rate and crystal quality of GaN materials.

[0123] Exemplarily, ammonia is used as the N source when growing the three-dimensional growth sublayer, and the concentration ratio of nitrogen to ammonia is 5:1.

[0124] In the disclosed embodiment, the three-dimensional growth sublayer with a thickness of 10 to 1000 nm is grown in a pure hydrogen atmosphere at a growth temperature of 900 to 1080° C., a growth pressure of 200 to 500 mtorr, and a growth rate of 5 to 15 μm / h.

[0125] For example, under the conditions of a growth temperature of 1050° C., a growth pressure of 350 mtorr, and a growth rate of 9 μm / h, the three-dimensional growth sublayer with a thickness of 300 nm is grown in a pure hydrogen atmosphere.

[0126] In the embodiment of the present disclosure, growth under the above environment can ensure the growth quality of the three-dimensional growth sublayer and provide conditions for processing the hollow structure.

[0127] The second step is to process the three-dimensional growth sublayer to form a hollow structure on the three-dimensional growth sublayer.

[0128] In the disclosed embodiment, the three-dimensional growth sublayer is processed in a pure hydrogen atmosphere so that the three-dimensional growth sublayer forms a hollow structure. In a pure hydrogen atmosphere, oxidation of oxygen can be prevented, and unstable impurity crystals in the three-dimensional growth sublayer GaN can be more easily removed at high temperature, which is conducive to growing a higher quality and more uniform hollow structure.

[0129] In the disclosed embodiment, the three-dimensional growth sublayer is treated in a pure hydrogen atmosphere at a growth temperature greater than 830-1100° C. and a growth pressure of 100-500 torr for 10-300 seconds, so that the three-dimensional growth sublayer forms a hollow structure.

[0130] For example, the three-dimensional growth sublayer is treated in a pure hydrogen atmosphere at a growth temperature greater than 1200° C., a growth pressure of 200 torr, and a treatment time of 120 seconds, so that the three-dimensional growth sublayer forms a hollow structure in a pure hydrogen atmosphere.

[0131] The hollow structure grown under the above conditions can remove unstable crystals within the three-dimensional growth sublayer GaN, providing favorable conditions for the formation of "voids".

[0132] The third step is to grow a two-dimensional covering sublayer on the hollow structure.

[0133] In the embodiment of the present disclosure, the two-dimensional covering sublayer is grown in a pure hydrogen atmosphere, so that the diffusion speed of atoms in the two-dimensional covering sublayer can be increased, and the two-dimensional covering sublayer can quickly cover the hollow structure to form a flat surface.

[0134] In the disclosed embodiment, ammonia is used as the N source when growing the two-dimensional cover sublayer, and the concentration ratio of hydrogen to ammonia is 5:1 to 30:1.

[0135] Exemplarily, ammonia is used as the N source when growing the two-dimensional cover sublayer, and the concentration ratio of hydrogen to ammonia is 20:1.

[0136] In the disclosed embodiment, the two-dimensional covering sublayer with a thickness of 100 to 2000 nm is grown in a pure hydrogen atmosphere at a growth temperature of 1100 to 1150° C., a growth pressure of 100 to 500 mtorr, and a growth rate of 5 to 10 μm / h.

[0137] For example, under the conditions of a growth temperature of 1120° C., a growth pressure of 200 mtorr, and a growth rate of 8 μm / h, the two-dimensional cover sublayer with a thickness of 500 nm is grown in a pure hydrogen atmosphere.

[0138] In this implementation, the two-dimensional covering sublayer produced under the above conditions can quickly cover the "voids" to form a hollow structure, thereby improving the crystal quality and the electrical performance of the device. At the same time, the surface morphology flatness of the hollow structure can be restored and the thickness uniformity of the epitaxial wafer can be improved.

[0139] In an implementation of the embodiment of the present disclosure, the hollow structure layer only includes a three-dimensional growth sublayer and a two-dimensional covering sublayer.

[0140] In another implementation of the disclosed embodiment, the hollow structure layer may include a superlattice structure composed of 2 to 20 periods of three-dimensional growth sublayers and two-dimensional covering sublayers. Using a superlattice structure of multiple periods to form a hollow structure layer can provide more stress release space, which is conducive to avoiding epitaxial bending.

[0141] Exemplarily, the hollow structure layer includes a superlattice structure consisting of 10 periods of three-dimensional growth sublayers and two-dimensional covering sublayers. Accordingly, the method includes repeating the first to third steps ten times.

[0142] S25. Growing a first semiconductor layer on the hollow structure layer.

[0143] In the embodiment of the present disclosure, the first semiconductor layer may be an N-type GaN layer.

[0144] Exemplarily, the growth conditions of the first semiconductor layer may include: a growth temperature of 1000 - 1150 °C, a growth pressure of 100 - 300 Torr, a growth thickness of 0.5 - 3 μm, and a doping concentration of Si of 5×10^18 - 5×10^19 cm^-3.

[0145] For example, the growth temperature is 1100 °C, the growth pressure is 150 Torr, the growth thickness is 2 μm, and the doping concentration of Si is 5×10^19 cm^-3.

[0146] S26. Grow a light-emitting layer on the first semiconductor layer.

[0147] In the embodiments of the present disclosure, the light-emitting layer may be a multi-quantum well barrier layer.

[0148] In one example, the multi-quantum well barrier layer includes 8 - 15 periods of In x Ga 1-x N(0.2 < x < 0.5) / GaN (or AlGaN) multi-quantum well barrier layer.

[0149] In one example, the growth conditions of the light-emitting layer may include: growing InGaN quantum wells in a pure nitrogen atmosphere, with a growth temperature of 700 - 850 °C, a growth pressure of 200 - 500 Torr, and a thickness of each period of InGaN quantum wells of 1.5 - 6 nm; growing GaN quantum barriers in a mixed atmosphere of nitrogen and hydrogen, with a growth temperature of 800 - 960 °C, a growth pressure of 100 - 300 Torr, and a thickness of each period of GaN quantum barriers of 8 - 20 nm.

[0150] For example, the growth temperature of InGaN quantum wells is 750 °C, the growth pressure is 350 Torr, and the thickness of each period of InGaN quantum wells is 3.6 nm; for GaN quantum barriers, the growth temperature is 900 °C, the growth pressure is 200 Torr, and the thickness of each period of GaN quantum barriers is 9.6 nm.

[0151] In another example, the multi-quantum well barrier layer includes 12 periods of In x Ga 1-x N(0.2 < x < 0.5) / GaN (or AlGaN) multi-quantum well barrier layer.

[0152] Wherein, each period of InGaN quantum well layer includes a first sub-layer, a second sub-layer, a third sub-layer, and a fourth sub-layer stacked in sequence.

[0153] Exemplarily, for each period of InGaN quantum well layer, the growth method is as follows:

[0154] Under the conditions of a growth temperature of 795 °C and a growth pressure of 200 Torr, the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer are grown in sequence.

[0155] Among them, the first sub-layer is In x Ga 1-x N (0 ≤ x ≤ 0.2), where X can be 0.05, grown using TMGa as the Ga source, and the growth atmosphere is a mixed gas of nitrogen, hydrogen, and ammonia. The hydrogen concentration ratio can be 5%, and the thickness can be 0.3 nm.

[0156] The second sub-layer is In y Ga 1-y N (0.3 ≤ y ≤ 0.8) layer, where Y can be 0.5, grown using TMGa as the Ga source, and the growth atmosphere is a mixed gas of nitrogen and ammonia. The thickness can be 0.5 nm;

[0157] The third sub-layer is In z Ga 1-z N (0.2 ≤ z ≤ 0.5) layer, where Z can be 0.35, grown using TEGa as the Ga source, and the growth atmosphere is a mixed gas of nitrogen and ammonia. The thickness can be 2.8 nm;

[0158] The fourth sub-layer is In w Ga 1-w N (0 ≤ w ≤ 0.2) layer, where W can be 0.05, grown using TMGa as the Ga source, and the growth atmosphere is a mixed gas of nitrogen, hydrogen, and ammonia. The hydrogen concentration ratio can be 5%, and the thickness can be 0.3 nm;

[0159] Among them, each period of the GaN quantum barrier layer is grown in a mixed atmosphere of nitrogen and hydrogen, with a growth temperature of 860 °C and a growth pressure of 200 Torr. The total thickness of each period of the GaN or AlGaN quantum barrier layer can be 9 nm.

[0160] S27. An electron blocking layer is grown on the light-emitting layer.

[0161] In the embodiment of the present disclosure, the electron blocking layer can be a P-type Al y Ga 1-y N (0.1 < y < 0.5) layer.

[0162] Exemplarily, the growth conditions of the electron blocking layer can include: a growth temperature of 800 - 1000 °C, a growth pressure of 50 - 300 Torr, and a growth thickness of 10 - 100 nm.

[0163] For example, the growth temperature is 900 °C, the growth pressure is 200 Torr, and the growth thickness is 50 nm.

[0164] Optionally, the method may further include growing a P-type doped AlGaN layer before the electron blocking layer.

[0165] Wherein, the growth conditions of the P-type doped AlGaN layer may be a P-type doped Al w Ga 1-w N(0.1 < w < 0.3) layer.

[0166] Exemplarily, the growth conditions of the P-type doped AlGaN layer may include: a growth temperature of 700 - 800 °C, a growth pressure of 200 - 500 Torr, a growth thickness of 10 - 100 nm, and a doping concentration of Mg of 5×10 2 0 - 1×10 2 1 cm-3.

[0167] For example, the growth temperature is 750 °C, the growth pressure is 350 Torr, the growth thickness is 50 nm. The doping concentration of Mg is 1×10 2 1 cm-3.

[0168] S28. Grow a second semiconductor layer on the electron blocking layer.

[0169] In the embodiments of the present disclosure, the second semiconductor layer may include a high-temperature P-type GaN layer and a P-type doped GaN contact layer.

[0170] Exemplarily, the growth conditions of the high-temperature P-type GaN layer may include: a growth temperature of 800 - 1000 °C, a growth pressure of 200 - 600 Torr, a growth thickness of 10 - 100 nm for growth, and a doping concentration of Mg of 1×1018 - 1×10 2 0 cm-3.

[0171] For example, the growth temperature is 900 °C, the growth pressure is 400 Torr, the growth thickness is 50 nm, and the doping concentration of Mg is 1×1019 cm-3.

[0172] Exemplarily, the growth conditions of the high-temperature P-type doped GaN contact layer may include: a growth temperature of 850 - 1000 °C, a growth pressure of 100 - 300 Torr, a growth thickness of 1 - 30 nm for growth, and a doping concentration of Mg of 1×10 2 0 - 1×10 2 1 cm-3.

[0173] For example, the growth temperature is 900 °C, the growth pressure is 200 Torr, the growth thickness is 20 nm, and the doping concentration of Mg is 1×10 2 1 cm-3.

[0174] In the embodiments of the present disclosure, high-purity NH3 can be used as the N source, trimethylgallium or triethylgallium as the Ga source, trimethylaluminum as the aluminum source, bismuthocene magnesium as the magnesium source, and high-purity SiH4 to provide electrons; the temperature and pressure controlled during the growth process actually refer to the temperature and pressure in the reaction chamber of the MOCVD equipment.

[0175] Optionally, after the epitaxial growth is completed, the temperature in the reaction chamber of the MOCVD equipment is lowered, and annealing treatment is performed in a pure nitrogen atmosphere at a temperature range of 650 to 850 degrees Celsius for 5 to 15 minutes, and then the temperature is reduced to room temperature to complete the epitaxial growth.

[0176] Table 1 below compares the thickness standard deviation data of the epitaxial wafers of the related art process and the epitaxial wafers of the process provided by the embodiment of the present disclosure: Thickness Std Dev is the thickness standard deviation, and the larger the numerical mean value, the larger the thickness standard deviation. Based on Table 1, it can be seen that the average value of the thickness standard deviation of the solution provided by the present disclosure is reduced by 15%, which improves the consistency of the epitaxial thickness, thereby improving the light quality of the light-emitting diode.

[0177] Table 1

[0178]

[0179]

[0180] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light-emitting diode comprises: a three-dimensional nucleation layer (103), a two-dimensional filling layer (104), a hollow structure layer (105), a first semiconductor layer (106), a light-emitting layer (107) and a second semiconductor layer (109); The three-dimensional nucleation layer (103), the two-dimensional filling layer (104), the hollow structure layer (105), the first semiconductor layer (106), the light-emitting layer (107) and the second semiconductor layer (109) are stacked in sequence; The hollow structure layer (105) comprises: a three-dimensional growth sublayer (201) and a two-dimensional covering sublayer (202) sequentially stacked on the two-dimensional filling layer (104), and the three-dimensional growth sublayer (201) comprises a hollow structure.

2. The light emitting diode according to claim 1, characterized in that: The three-dimensional growth sublayer (201) is a GaN sublayer, and the two-dimensional cover sublayer (202) is a GaN or AlGaN sublayer.

3. The light emitting diode according to claim 1 or 2, characterized in that: The thickness of the three-dimensional growth sublayer (201) is 10 to 1000 nm, and the thickness of the two-dimensional covering sublayer (202) is 100 to 2000 nm.

4. The light emitting diode according to claim 1 or 2, characterized in that: The hollow structure layer (105) comprises a superlattice structure composed of 2 to 20 periods of the three-dimensional growth sublayer (201) and the two-dimensional covering sublayer (202).

5. A method for preparing a light emitting diode, characterized in that: The method comprises: Making a three-dimensional nucleation layer; Making a two-dimensional filling layer on the three-dimensional nucleation layer; A hollow structure layer is fabricated on the two-dimensional filling layer, wherein the hollow structure layer comprises: a three-dimensional growth sublayer and a two-dimensional covering sublayer sequentially stacked on the two-dimensional filling layer, wherein the three-dimensional growth sublayer comprises a hollow structure; Fabricating a first semiconductor layer on the hollow structure layer; forming a light-emitting layer on the first semiconductor layer; A second semiconductor layer is formed on the light emitting layer.

6. The method for preparing a light emitting diode according to claim 5, characterized in that: Producing a hollow structure layer on the two-dimensional filling layer, comprising: growing the three-dimensional growth sublayer in a pure nitrogen atmosphere; Treating the three-dimensional growth sublayer under a pure hydrogen atmosphere so that the three-dimensional growth sublayer forms a hollow structure; The two-dimensional cover sublayer is grown under a pure hydrogen atmosphere.

7. The method for preparing a light emitting diode according to claim 6, characterized in that: When growing the three-dimensional growth sublayer, ammonia is used as the N source, and the concentration ratio of nitrogen to ammonia is 3:1 to 10:1; When growing the two-dimensional cover sublayer, ammonia is used as the N source, and the concentration ratio of hydrogen to ammonia is 5:1 to 30:

1.

8. The method for preparing a light emitting diode according to claim 6 or 7, characterized in that: The growing of the three-dimensional growth sublayer in a pure hydrogen atmosphere comprises: The three-dimensional growth sublayer with a thickness of 10 to 1000 nm is grown in a pure hydrogen atmosphere at a growth temperature of 900 to 1080° C., a growth pressure of 200 to 500 mtorr, and a growth rate of 5 to 15 μm / h.

9. The method for preparing a light emitting diode according to claim 6 or 7, characterized in that: The step of treating the three-dimensional growth sublayer under a pure hydrogen atmosphere so that the three-dimensional growth sublayer forms a hollow structure includes: The three-dimensional growth sublayer is treated in a pure hydrogen atmosphere at a growth temperature greater than 830-1100° C. and a growth pressure of 100-500 torr for 10-300 seconds, so that the three-dimensional growth sublayer forms a hollow structure.

10. The method for preparing a light emitting diode according to claim 6 or 7, characterized in that: The step of growing the two-dimensional cover sublayer in a pure hydrogen atmosphere comprises: The two-dimensional covering sublayer with a thickness of 100 to 2000 nm is grown in a pure hydrogen atmosphere at a growth temperature of 1100 to 1150° C., a growth pressure of 100 to 500 mtorr, and a growth rate of 5 to 10 μm / h.

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