Light-emitting diode capable of improving loss of reflective area and preparation method of light-emitting diode

Abstract

The invention provides a light-emitting diode capable of improving reflection area loss and a preparation method of the light-emitting diode, and belongs to the technical field of photoelectron manufacturing. The preparation method of the light-emitting diode comprises the following steps: preparing an epitaxial layer; preparing an etching buffer layer on the epitaxial layer; preparing an insulating reflecting layer on the etching buffer layer; performing first-section etching on the insulating reflecting layer; performing second-section etching on the etching buffer layer to form a via hole penetrating through the insulating reflecting layer and the etching buffer layer; wherein the etching power of the first section of etching is greater than the etching power of the second section of etching. According to the invention, the excessive insulating reflecting layer can be prevented from being etched, the light-emitting area of the insulating reflecting layer is ensured, and the light-emitting brightness is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved reflective area loss and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a new product with great influence in the optoelectronics industry. Light Emitting Diode usually includes an epitaxial layer, a transparent conductive layer, an insulating reflective layer and a metal reflective layer stacked in sequence. The surface of the insulating reflective layer has vias so that the metal reflective layer can be electrically connected to the transparent conductive layer through the vias. The reflective structure formed by the combination of the insulating reflective layer and the metal reflective layer can completely cover the surface of the epitaxial layer, thereby improving the reflective effect of the light emitting diode.

[0003] In the related art, when etching via holes on the insulating reflective layer, an etching buffer layer is first formed between the insulating reflective layer and the transparent conductive layer to avoid over-etching the transparent conductive layer below the insulating reflective layer.

[0004] However, after adding the etching buffer layer, two hole opening processes are required to expose the transparent conductive layer. The first hole opening process etches the insulating reflective layer first, and the second hole opening process etches the buffer layer, and the ITO damage is avoided through the etching process. Usually, in order to ensure that the hole diameter obtained by the second hole opening process meets the requirements, the first hole opening process will form a larger hole. This makes the size of the via hole opened on the insulating reflective layer too large, that is, more of the insulating reflective layer is etched away, thereby reducing the reflective area of ​​the insulating reflective layer, affecting the brightness of the light-emitting diode. Summary of the invention

[0005] The embodiments of the present disclosure provide a light-emitting diode and a method for manufacturing the same with improved reflective area loss, which can avoid etching away too much insulating reflective layer, ensure the light-emitting area of ​​the insulating reflective layer, and improve the light-emitting brightness. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode, the method comprising: preparing an epitaxial layer; preparing an etching buffer layer on the epitaxial layer; preparing an insulating reflective layer on the etching buffer layer; performing a first stage of etching on the insulating reflective layer; performing a second stage of etching on the etching buffer layer to form a via hole passing through the insulating reflective layer and the etching buffer layer; wherein the etching power of the first stage of etching is greater than the etching power of the second stage of etching.

[0007] In another implementation of the present disclosure, the insulating reflective layer is sequentially subjected to first-stage etching and second-end etching, comprising: when performing the first-stage etching, the upper power of the etching device is controlled to be 400W to 600W, and the lower power of the etching device is controlled to be 150W to 250W; when performing the second-stage etching, the upper power of the etching device is controlled to be 80W to 120W, and the lower power of the etching device is controlled to be 30W to 70W.

[0008] In another implementation of the present disclosure, the duration of the first etching stage is 400s to 450s, and the duration of the second etching stage is 60s to 100s.

[0009] In another implementation of the present disclosure, a rate of etching the etching buffer layer is lower than a rate of etching the insulating reflective layer.

[0010] In another implementation of the present disclosure, the thickness of the etching buffer layer is 4000 angstroms to 6000 angstroms.

[0011] In another implementation of the present disclosure, the radius of the via hole of the insulating reflective layer is less than or equal to 5 μm.

[0012] On the other hand, an embodiment of the present disclosure provides a light-emitting diode, which includes: an epitaxial layer, an insulating reflective layer and an etching buffer layer; the etching buffer layer is located on the epitaxial layer, and the insulating reflective layer is located on the etching buffer layer; the surface of the insulating reflective layer has at least one via hole penetrating the insulating reflective layer and the etching buffer layer; the projection of the side wall of the etching buffer layer on the side of the via hole on the surface of the epitaxial layer and the projection of the side wall of the insulating reflective layer on the side of the via hole on the surface of the epitaxial layer intersect.

[0013] In another implementation of the present disclosure, the via hole is a tapered hole, and an average radius of the via hole is less than or equal to 5 μm.

[0014] In another implementation of the present disclosure, the depth of the via hole is equal to the sum of the thicknesses of the etching buffer layer and the insulating reflective layer.

[0015] In another implementation of the present disclosure, the light emitting diode further includes a transparent conductive layer, the transparent conductive layer is located on the surface of the epitaxial layer, the insulating reflective layer is located on the transparent conductive layer, and the via hole exposes the transparent conductive layer.

[0016] In the preparation method provided by the embodiment of the present disclosure, when preparing a light-emitting diode, the insulating reflective layer is etched in the first stage, and the etching buffer layer is etched in the second stage to form a via that penetrates the insulating reflective layer and the etching buffer layer. Among them, the etching power of the first stage etching is greater than the etching power of the second stage etching. In this way, when performing the first stage etching, a relatively high etching speed can be maintained to etch the insulating reflective layer; and when the via formed by etching is about to approach the epitaxial layer, the etching buffer layer is etched in the second stage. Since the etching speed of the second stage etching is lower, it can be avoided that the etching speed is too fast and the film layer is quickly etched through to cause damage to the epitaxial layer. In addition, the etching power of the second stage etching is lower, and the speed of etching the epitaxial layer is also slower. Therefore, it is also difficult to etch the epitaxial layer in the second stage etching. In this way, excessive etching can be prevented from causing damage to the film layer below the insulating reflective layer of the epitaxial layer.

[0017] Compared with the related art, the embodiment of the present disclosure etches the insulating reflective layer directly through a single etching process, without the need for multiple hole-opening processes. Therefore, the aperture of the via formed on the insulating reflective layer can be effectively reduced, avoiding etching away too much of the insulating reflective layer, increasing the reflective area of ​​the insulating reflective layer, and improving the light emitting brightness of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 It is a structural schematic diagram of a light emitting diode provided by the related technology;

[0020] Figure 2 It is a schematic diagram of etching an insulating reflective layer provided by the related technology;

[0021] Figure 3 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram of etching an insulating reflective layer provided by an embodiment of the present disclosure;

[0023] Figure 5 It is a structural schematic diagram of a light emitting diode provided in an embodiment of the present disclosure.

[0024] The descriptions of the marks in the figure are as follows:

[0025] 10. Substrate;

[0026] 20. Epitaxial layer;

[0027] 30. Transparent conductive layer;

[0028] 41. insulating reflective layer; 410. via hole;

[0029] 42. Etching buffer layer;

[0030] 43. Metal reflective layer; 44. Enveloping layer;

[0031] 51. a first passivation layer; 52. a second passivation layer;

[0032] 61. Electrode; 62. Pad. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0034] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] Figure 1 It is a schematic diagram of the structure of a light emitting diode provided by the related technology. Figure 1 As shown, in the related art, a light emitting diode generally includes an epitaxial layer 20, a transparent conductive layer 30, an insulating reflective layer 41 and a metal reflective layer 43 stacked in sequence. The surface of the insulating reflective layer 41 generally needs to be etched to form a via 410 so that the metal reflective layer 43 can be electrically connected to the transparent conductive layer 30 through the via 410.

[0036] In the related art, in order to avoid over-etching the transparent conductive layer 30 below the insulating reflective layer 41 , an etching buffer layer 42 is first formed between the insulating reflective layer 41 and the transparent conductive layer 30 .

[0037] Figure 2 FIG. 4 is a schematic diagram of etching the insulating reflective layer 41 provided by the related art. Figure 2 As shown, when etching the via hole 410 on the insulating reflective layer 41 , two hole opening processes are required to expose the transparent conductive layer 30 .

[0038] The insulating reflective layer 41 is etched in the first hole-opening process, and the buffer layer 42 is etched in the second hole-opening process, so that ITO is not damaged by the etching process.

[0039] In order to ensure that the hole diameter obtained by the second hole-making process meets the requirements, the first hole-making process will form a larger hole. This makes the size of the via hole 410 opened on the insulating reflective layer 41 too large, that is, more of the insulating reflective layer 41 is etched away, thereby reducing the reflective area of ​​the insulating reflective layer 41 and affecting the light emitting brightness of the light-emitting diode.

[0040] To this end, an embodiment of the present disclosure provides a method for preparing a light emitting diode. Figure 3 FIG. 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 3 As shown, the preparation method comprises:

[0041] Step S11: preparing an epitaxial layer.

[0042] The epitaxial layer 20 may include a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence.

[0043] Step S12 : preparing an etching buffer layer 42 on the epitaxial layer 20 .

[0044] Step S13 : preparing an insulating reflective layer 41 on the etching buffer layer 42 .

[0045] Step S14: performing a first etching process on the insulating reflective layer 41 .

[0046] Step S15 : performing second end etching on the etching buffer layer 42 to form a via hole 410 penetrating the insulating reflective layer 41 and the etching buffer layer 42 .

[0047] The etching power of the first etching stage is greater than the etching power of the second etching stage.

[0048] In the preparation method provided by the embodiment of the present disclosure, when preparing a light-emitting diode, the insulating reflective layer 41 is etched in the first stage, and the etching buffer layer is etched in the second stage to form a via hole that penetrates the insulating reflective layer and the etching buffer layer. Among them, the etching power of the first stage etching is greater than the etching power of the second stage etching. In this way, when the first stage etching is performed, the insulating reflective layer 41 can be etched at a relatively high etching speed; and when the via hole 410 formed by etching is about to approach the epitaxial layer 20, the etching buffer layer is etched in the second stage. Since the etching speed of the second stage etching is lower, it can be avoided that the etching speed is too fast and the film layer is quickly etched through to cause damage to the epitaxial layer 20. In addition, the etching power of the second stage etching is lower, and the speed of etching the epitaxial layer 20 is also slower. Therefore, it is also difficult to etch the epitaxial layer 20 in the second stage etching. In this way, excessive etching can be prevented from causing damage to the film layer below the insulating reflective layer 41 of the epitaxial layer 20.

[0049] Compared with the related art, the embodiment of the present disclosure etches the insulating reflective layer 41 directly through a single etching process, without the need for multiple hole-opening processes. Therefore, the aperture of the via hole 410 formed on the insulating reflective layer 41 can be effectively reduced, avoiding etching away too much of the insulating reflective layer 41, increasing the reflective area of ​​the insulating reflective layer 41, and improving the light emitting brightness of the light-emitting diode.

[0050] The process of preparing the epitaxial layer 20 in step S11 may include the following steps:

[0051] First, a substrate is provided.

[0052] The substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0053] As an example, in the embodiment of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0054] The sapphire substrate may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0055] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0056] Growing the epitaxial layer 20 on the substrate may include: sequentially forming a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer on the sapphire substrate by using MOCVD technology.

[0057] The first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0058] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0059] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0060] Optionally, the multi-quantum well layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Wherein, the multi-quantum well layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0061] When growing multi-quantum well layers, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing InGaN quantum well layers, the temperature of the reaction chamber is 760°C to 780°C. When growing GaN quantum barrier layers, the temperature of the reaction chamber is 860°C to 890°C.

[0062] As an example, in the embodiment of the present disclosure, the multi-quantum well layer includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0063] Optionally, the thickness of the multi-quantum well layer may be 150 nm to 200 nm.

[0064] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0065] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0066] Then, the second semiconductor layer is etched to form a groove exposing the first semiconductor layer.

[0067] Next, the transparent conductive layer 30 is sputtered on the surface of the second semiconductor layer.

[0068] For example, the transparent conductive layer 30 may be an indium tin oxide (ITO) layer, which has good transmittance and low resistivity.

[0069] For example, the transparent conductive layer 30 may be an indium zinc oxide (IZO) layer, which has good transmittance and low resistivity.

[0070] Since the ITO layer or the IZO layer has good adhesion to the metal, using the ITO layer or the IZO layer as the transparent conductive layer 30 can improve the adhesion of the metal layer and effectively avoid the problem of the metal layer peeling off.

[0071] At the same time, using an ITO layer or an IZO layer as the transparent conductive layer 30 can allow more light to be transmitted from the transparent conductive layer 30, thereby ensuring the light extraction effect; at the same time, due to the low resistivity, the carriers can be more efficiently conducted to the epitaxial layer 20, thereby improving the injection efficiency.

[0072] Exemplarily, the thickness of the transparent conductive layer 30 may be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 30 is 1500 angstroms.

[0073] Step S12 and step S13 may include the following steps:

[0074] First, an etching buffer layer 42 is formed on the surface of the epitaxial layer 20 .

[0075] Optionally, the etching buffer layer 42 includes a silicon oxide layer. The silicon oxide layer has a good insulation effect and can prevent the transparent conductive layer 30 from being short-circuited with other film layers. The silicon oxide layer has good stability and can protect the transparent conductive layer 30.

[0076] Optionally, the thickness of the etching buffer layer 42 is 4000 angstroms to 6000 angstroms.

[0077] The thickness of the through hole etching buffer layer 42 is within the above range, which can prevent the etching buffer layer 42 from being too thick and absorbing a large amount of light, and can also prevent the etching buffer layer 42 from being too thin and failing to protect the transparent conductive layer 30 .

[0078] By way of example, the thickness of the etch buffer layer 42 may be 5000 angstroms.

[0079] Optionally, the etching rate of the etch buffer layer 42 is lower than the etching rate of the insulating reflective layer 41 , that is, the insulating reflective layer 41 is less easily etched than the etching buffer layer 42 .

[0080] In this way, after the insulating reflective layer 41 is etched, the etching buffer layer 42 is difficult to etch, so that the etching rate is reduced, thereby effectively avoiding rapid etching to the transparent conductive layer 30 and damaging the transparent conductive layer 30 .

[0081] Then, the insulating reflective layer 41 is formed on the surface of the etching buffer layer 42 .

[0082] Exemplarily, the insulating reflective layer 41 may be a DBR (Distributed Bragg Reflector) layer.

[0083] The DBR layer includes a plurality of silicon oxide layers and a plurality of titanium oxide layers stacked alternately, and the thickness of the DBR layer is 3 μm to 4 μm.

[0084] By providing the insulating reflective layer 41 , the light emitted from the epitaxial layer 20 can be reflected, so that more light can be emitted from the light emitting surface of the epitaxial layer 20 , thereby improving the light emitting intensity of the light emitting diode.

[0085] Figure 4 FIG. 4 is a schematic diagram of etching an insulating reflective layer 41 provided in an embodiment of the present disclosure. Figure 4 As shown, steps S14 and S15 may include:

[0086] First, a first etching step is performed on the surface of the insulating reflective layer 41 away from the epitaxial layer 20 .

[0087] When performing the first stage of etching, the upper power of the etching equipment is controlled to be 400W to 600W, and the lower power of the etching equipment is controlled to be 150W to 250W.

[0088] During the first etching stage, controlling the upper power and the lower power within the above range can increase the etching speed of the insulating reflective layer 41 and ensure that the insulating reflective layer 41 is quickly etched.

[0089] Exemplarily, when performing the first stage of etching, the upper power of the etching equipment is controlled to be 500W, and the lower power of the etching equipment is controlled to be 200W.

[0090] Exemplarily, the duration of the first etching is 400s to 450s. Controlling the duration of the first etching to be within the above range can ensure that at least the insulating reflective layer 41 is etched through after the first etching.

[0091] As an example, after the first etching, the insulating reflective layer 41 is etched through, and the thickness of the etching buffer layer 42 remains 100 angstroms to 300 angstroms. That is, a portion of the etching buffer layer 42 is also etched after the first etching. Therefore, providing the etching buffer layer 42 can effectively prevent the transparent conductive layer 30 from being etched and lost.

[0092] Then, the etching buffer layer 42 is etched in the second stage to form a via hole 410 exposing the transparent conductive layer 30 .

[0093] When performing the second etching, the upper power of the etching equipment is controlled to be 80W to 120W, and the lower power of the etching equipment is controlled to be 30W to 70W.

[0094] In the second etching stage, controlling the upper power and the lower power within the above range can slow down the etching speed of the etching buffer layer 42, avoid quickly etching through the etching buffer layer 42, and prevent the transparent conductive layer 30 from being easily etched and damaged.

[0095] Moreover, the etching power of the second etching is significantly lower than that of the first etching, and the lower the etching power, the slower the etching speed of the transparent conductive layer 30. Therefore, even if the second etching penetrates the etching buffer layer 42, it is difficult to damage the transparent conductive layer 30.

[0096] Exemplarily, when performing the second etching, the upper power of the etching device is controlled to be 100W, and the lower power of the etching device is controlled to be 50W.

[0097] Exemplarily, the duration of the second etching is 60s to 100s. Controlling the duration of the second etching within the above range can ensure that only the remaining etching barrier layer is etched through after the second etching, and the transparent conductive layer 30 is not etched.

[0098] Alternatively, if Figure 4 As shown in FIG. 1 , after the insulating reflective layer 41 is etched, a via hole 410 penetrating the insulating reflective layer 41 and the etching buffer layer 42 is formed on the insulating reflective layer 41. The via hole 410 is a tapered hole, rather than a Figure 2 The stepped hole shown is formed by multiple etching steps.

[0099] Figure 2 The maximum radius of the step hole shown in the figure is 10 μm, that is, a hole of about 10 μm needs to be formed on the surface of the insulating reflective layer 41 to form a step hole exposing the transparent conductive layer 30 during the secondary etching.

[0100] In the present disclosure, Figure 4 As shown, the insulating reflective layer 41 is etched once to form a conical hole, and the radius of the via hole 410 of the insulating reflective layer 41 is less than or equal to 5μm. That is, only a hole of no more than 5μm needs to be formed on the surface of the insulating reflective layer 41 to obtain the via hole 410 that exposes the transparent conductive layer 30. Therefore, the etching method provided in the embodiment of the present disclosure does not require multiple hole opening processes. Therefore, the aperture of the via hole 410 formed on the insulating reflective layer 41 can be effectively reduced, avoiding etching of too much insulating reflective layer 41, increasing the reflective area of ​​the insulating reflective layer 41, and improving the luminous brightness of the light-emitting diode.

[0101] After step S15, the method further includes:

[0102] First, the metal reflective layer 43 is formed on the surface of the insulating reflective layer 41 .

[0103] Illustratively, the metal reflective layer 43 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0104] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0105] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0106] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0107] Then, the surrounding layer 44 is formed on the surface of the insulating reflection layer 41 and the surface of the metal reflection layer 43 so that the surrounding layer 44 covers the metal reflection layer 43 .

[0108] Optionally, the surrounding layer 44 includes an aluminum oxide layer. Exemplarily, the thickness of the surrounding layer 44 is 500 angstroms.

[0109] Then, a first passivation layer 51 is formed on the surface of the surrounding layer 44 and in the groove.

[0110] Next, through-holes exposing the metal reflective layer 43 and through-holes exposing the bottom of the grooves are formed on the surface of the first passivation layer 51 by photolithography.

[0111] Exemplarily, the first passivation layer 51 may be a silicon oxide layer.

[0112] Exemplarily, the thickness of the first passivation layer 51 is 4000 angstroms to 6000 angstroms.

[0113] Then, an electrode 61 is formed on the surface of the first passivation layer 51 , and the electrode 61 is connected to the metal reflective layer 43 through a through hole.

[0114] Next, the second passivation layer 52 is formed on the surface of the first passivation layer 51 so that the second passivation layer 52 covers the electrode 61 .

[0115] Exemplarily, the second passivation layer 52 is a DBR layer, which includes a plurality of silicon oxide layers and a plurality of titanium oxide layers, and has a thickness of 3 μm to 4 μm.

[0116] Then, the second passivation layer 52 is etched to form a through hole exposing the electrode 61 on the surface of the second passivation layer 52 .

[0117] Next, a pad 62 is formed on a surface of the second passivation layer 52 away from the epitaxial layer 20 , so that the pad 62 is electrically connected to the electrode 61 through a through hole.

[0118] Optionally, the pad 62 layer includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.

[0119] Exemplarily, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0120] Exemplarily, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0121] Exemplarily, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0122] Exemplarily, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0123] Exemplarily, the thickness of the Ni layer is 6000 angstroms to 8000 angstroms. For example, the thickness of the Ni layer is 7000 angstroms.

[0124] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0125] Figure 5 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 5 As shown, the light emitting diode is formed by the preparation method described above. The light emitting diode comprises: an epitaxial layer 20, an insulating reflective layer 41 and an etching buffer layer 42; the etching buffer layer 42 is located on the epitaxial layer 20, and the insulating reflective layer 41 is located on the etching buffer layer 42.

[0126] like Figure 5 As shown, the surface of the insulating reflective layer 41 has at least one via hole 410 penetrating the insulating reflective layer 41 and the etching buffer layer 42 .

[0127] like Figure 5 As shown in FIG. 1 , the projection of the side wall of the etching buffer layer 42 on the side of the via hole 410 on the surface of the epitaxial layer 20 and the projection of the side wall of the insulating reflective layer 41 on the side of the via hole 410 on the surface of the epitaxial layer intersect. That is, the via holes on the etching buffer layer and the insulating reflective layer are continuous and smooth holes, rather than Figure 2 Stepped hole shown.

[0128] The via hole in the light-emitting diode prepared by the preparation method provided by the embodiment of the present disclosure is not a stepped hole, which can effectively avoid etching away too much insulating reflective layer, thereby increasing the reflective area of ​​the insulating reflective layer and improving the light-emitting brightness of the light-emitting diode.

[0129] Alternatively, if Figure 5As shown, the light emitting diode further includes a metal reflective layer 43 . The metal reflective layer 43 is located on a surface of the insulating reflective layer 41 away from the epitaxial layer 20 , and the metal reflective layer 43 is connected to the epitaxial layer 20 through a via 410 .

[0130] Alternatively, if Figure 5 As shown, the light emitting diode further includes a substrate 10 , and an epitaxial layer 20 is located on the surface of the substrate 10 .

[0131] Exemplarily, the substrate is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0132] In the disclosed embodiment, the epitaxial layer 20 includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on a substrate, and a surface of the second semiconductor layer has a groove exposing the first semiconductor layer.

[0133] In the embodiment of the present disclosure, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0134] Exemplarily, the first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0135] In the implementation of the present disclosure, the first semiconductor layer is Al x Ga (1-x) N material layer, wherein X is greater than or equal to 0 and less than or equal to 1.

[0136] Exemplarily, when X is 0, the first semiconductor layer is a GaN layer. For example, the first semiconductor layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0137] Optionally, the multi-quantum well layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Wherein, the multi-quantum well layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0138] As an example, in the embodiment of the present disclosure, the multi-quantum well layer includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0139] Optionally, the thickness of the multi-quantum well layer may be 150 nm to 200 nm.

[0140] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0141] Optionally, the second semiconductor layer has a groove exposing the first semiconductor layer.

[0142] Illustratively, the insulating reflective layer 41 may be a DBR layer.

[0143] The DBR layer includes a plurality of silicon oxide layers and a plurality of titanium oxide layers stacked alternately, and the thickness of the DBR layer is 3 μm to 4 μm.

[0144] By providing the insulating reflective layer 41 , the light emitted from the epitaxial layer 20 can be reflected, so that more light can be emitted from the light emitting surface of the epitaxial layer 20 , thereby improving the light emitting intensity of the light emitting diode.

[0145] Optionally, the metal reflective layer 43 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0146] Since Ag has a good reflective effect, providing an Ag layer in the reflective layer can enhance the reflection of light by the reflective layer and improve the light emitting brightness of the light emitting surface of the light emitting diode.

[0147] The Ni layer has good corrosion resistance and wear resistance, and the TiW layer can be successfully deposited on other films as an adhesion layer without peeling or cracking. The alternating stacked Ni and TiW layers can act as a barrier layer to protect the silver mirror.

[0148] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0149] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0150] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0151] Alternatively, if Figure 5 As shown, the via hole 410 of the insulating reflective layer 41 is a tapered hole, and the average radius of the via hole 410 is less than or equal to 5 μm.

[0152] In the embodiment of the present disclosure, the holes formed on the surface of the insulating reflective layer 41 do not exceed 5 μm, so that the aperture of the via 410 formed on the insulating reflective layer 41 is effectively reduced, thereby avoiding etching too much of the insulating reflective layer 41, increasing the reflective area of ​​the insulating reflective layer 41, and improving the brightness of the light-emitting diode.

[0153] Alternatively, if Figure 5 As shown, the light emitting diode further includes an etching buffer layer 42 , and the etching buffer layer 42 is located between the epitaxial layer 20 and the insulating reflective layer 41 . The via hole 410 also penetrates the etching buffer layer 42 .

[0154] Exemplarily, the etching buffer layer 42 includes a silicon oxide layer. The silicon oxide layer has a good insulation effect and can prevent the epitaxial layer 20 from being short-circuited with other film layers. The silicon oxide layer has good stability and can protect the epitaxial layer 20.

[0155] Exemplarily, the thickness of the etch buffer layer 42 is 4000 angstroms to 6000 angstroms. For example, the thickness of the etch buffer layer 42 may be 5000 angstroms.

[0156] Optionally, the depth of the via hole 410 is equal to the sum of the thicknesses of the etching buffer layer 42 and the insulating reflective layer 41 .

[0157] Alternatively, if Figure 5 As shown, the light emitting diode further includes a transparent conductive layer 30 , which is located on the surface of the epitaxial layer 20 , an insulating reflective layer 41 is located on the transparent conductive layer 30 , and a via hole 410 exposes the transparent conductive layer 30 .

[0158] Exemplarily, the transparent conductive layer 30 may be an ITO layer or an IZO layer.

[0159] Since the ITO layer or the IZO layer has good adhesion to the metal, using the ITO layer or the IZO layer as the transparent conductive layer 30 can improve the adhesion of the metal layer and effectively avoid the problem of the metal layer peeling off.

[0160] Exemplarily, the thickness of the transparent conductive layer 30 may be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 30 is 1500 angstroms.

[0161] Alternatively, if Figure 5 As shown, the light emitting diode further includes a surrounding layer 44 , which is located on a surface of the insulating reflective layer 41 away from the epitaxial layer 20 and covers the metal reflective layer 43 .

[0162] By covering the metal reflective layer 43 with a surrounding layer 44, the metal in the metal reflective layer 43 can be prevented from migrating upward.

[0163] Optionally, the surrounding layer 44 includes an aluminum oxide layer. Exemplarily, the thickness of the aluminum oxide layer is 500 angstroms to 1000 angstroms.

[0164] Alternatively, if Figure 5 As shown, the light emitting diode further includes: a first passivation layer 51 and an electrode 61 . The first passivation layer 51 is located on the surface of the surrounding layer 44 and in the groove.

[0165] Among them, the surface of the first passivation layer 51 has a through hole exposing the metal reflective layer 43 and the bottom of the groove, and the through hole also penetrates the through hole of the surrounding layer 44. The electrode 61 is located on the surface of the first passivation layer 51 and is connected to the metal reflective layer 43 and the first semiconductor layer respectively through the through hole.

[0166] Exemplarily, the first passivation layer 51 may be a silicon oxide layer.

[0167] Exemplarily, the thickness of the first passivation layer 51 is 4000 angstroms to 6000 angstroms.

[0168] Exemplarily, the electrode 61 may include at least one of an Al layer, an Ag layer, a Ni layer, a Pt layer, an Au layer, and an AlCu layer.

[0169] For example, the electrode 61 may include an Al layer, a Ti layer, a Ni layer, a Pt layer, and an Au layer stacked in sequence.

[0170] Illustratively, the thickness of the Al layer is 1500 angstroms to 2500 angstroms.

[0171] Illustratively, the thickness of the Ti layer is 300 angstroms to 700 angstroms.

[0172] Illustratively, the Ni layer has a thickness of 800 angstroms to 1200 angstroms.

[0173] Illustratively, the thickness of the Pt layer is 1500 angstroms to 2500 angstroms.

[0174] Illustratively, the Au layer has a thickness of 6000 angstroms to 10000 angstroms.

[0175] Alternatively, if Figure 5 As shown, the light emitting diode may further include a second passivation layer 52 and a pad 62, wherein the second passivation layer 52 is located on the surface of the first passivation layer 51 and covers the electrode 61. The second passivation layer 52 has a through hole exposing the electrode 61, the pad 62 is located on the surface of the second passivation layer 52 away from the epitaxial layer 20, and the pad 62 is electrically connected to the electrode 61 through the through hole.

[0176] Optionally, the pad 62 includes at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0177] The above metal material has good heat dissipation performance. Therefore, the pad 6260 made of the above material also has good heat dissipation performance and can improve the heat dissipation effect of the light emitting diode.

[0178] Alternatively, the pad 62 includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.

[0179] Exemplarily, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0180] Exemplarily, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0181] Exemplarily, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0182] Exemplarily, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0183] Exemplarily, the thickness of the Ni layer is 60,000 angstroms to 80,000 angstroms. For example, the thickness of the Ni layer is 70,000 angstroms.

[0184] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0185] The experimental data of the light emitting diode provided by the embodiment of the present disclosure are as follows in Table 1:

[0186] Table 1

[0187]

[0188] According to the test results in Table 1, the average brightness of the light-emitting diode provided in the embodiment of the present disclosure is 1015.2, while the average brightness of the light-emitting diode in the related art is 995.3. It can be seen that under the same working environment, the light-emitting diode provided in the present disclosure has a higher brightness, which is 2% higher than the brightness of the light-emitting diode in the related art, indicating that the light-emitting brightness of the light-emitting diode provided in the embodiment of the present disclosure is higher.

[0189] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: preparing an epitaxial layer (20); Preparing an etching buffer layer (42) on the epitaxial layer (20); Preparing an insulating reflective layer (41) on the etching buffer layer (42); Performing a first stage of etching on the insulating reflective layer (41); The etching buffer layer (42) is subjected to a second stage of etching to form a via hole (410) penetrating the insulating reflective layer (41) and the etching buffer layer (42); wherein the etching power of the first stage of etching is greater than the etching power of the second stage of etching.

2. The preparation method according to claim 1, characterized in that: When performing the first etching, the upper power of the etching device is controlled to be 400W to 600W, and the lower power of the etching device is controlled to be 150W to 250W; When performing the second etching, the upper power of the etching equipment is controlled to be 80W to 120W, and the lower power of the etching equipment is controlled to be 30W to 70W.

3. The preparation method according to claim 2, characterized in that: The duration of the first etching period is 400s to 450s, and the duration of the second etching period is 60s to 100s.

4. The preparation method according to any one of claims 1 to 3, characterized in that: The etching rate of the etching buffer layer (42) is lower than the etching rate of the insulating reflective layer (41).

5. The preparation method according to claim 4, characterized in that: The thickness of the etching buffer layer (42) is 4000 angstroms to 6000 angstroms.

6. The preparation method according to any one of claims 1 to 3, characterized in that: The radius of the via hole (410) of the insulating reflective layer (41) is less than or equal to 5 μm.

7. A light emitting diode, characterized in that: The light emitting diode comprises: an epitaxial layer (20), an insulating reflective layer (41) and an etching buffer layer (42); the etching buffer layer (42) is located on the epitaxial layer (20), and the insulating reflective layer (41) is located on the etching buffer layer (42); The surface of the insulating reflective layer (41) has at least one via hole (410) penetrating the insulating reflective layer (41) and the etching buffer layer (42); The projection of the side wall of the etching buffer layer (42) on the side of the via hole (410) on the surface of the epitaxial layer (20) and the projection of the side wall of the insulating reflective layer (41) on the side of the via hole (410) on the surface of the epitaxial layer intersect.

8. The light emitting diode according to claim 7, characterized in that: The via hole (410) is a tapered hole, and the average radius of the via hole (410) is less than or equal to 5 μm.

9. The light emitting diode according to claim 7, characterized in that: The depth of the via hole (410) is equal to the sum of the thicknesses of the etching buffer layer (42) and the insulating reflective layer (41).

10. The light emitting diode according to any one of claims 7 to 9, characterized in that: The light emitting diode further comprises a transparent conductive layer (30), wherein the transparent conductive layer (30) is located on the surface of the epitaxial layer (20), the insulating reflective layer (41) is located on the transparent conductive layer (30), and the via hole (410) exposes the transparent conductive layer (30).

Images