Quantum chip packaging device capable of eliminating quasi-particle influence

Abstract

The invention discloses a quantum chip packaging device capable of eliminating quasi-particle influence, which comprises a shielding barrel bottom plate, a substrate, a packaging upper plate, a PCB (Printed Circuit Board), a connecting plate component, a cover plate component and a shielding barrel body, and is characterized in that the shielding barrel bottom plate is located at the bottom end of the shielding barrel body, and the substrate is provided with a first square hole, a second square hole, a third square hole, a fourth square hole and a chip square hole; a fifth square hole, a sixth square hole, a seventh square hole, an eighth square hole and a central square hole are formed in the packaging upper plate, the connecting plate component comprises a first connecting plate and a second connecting plate, and the first connecting plate is arranged on the PCB; the second connecting plate is arranged in the fifth square hole, the sixth square hole, the seventh square hole and the eighth square hole, the cover plate component comprises a first cover plate, a second cover plate, a third cover plate and a center cover plate, and the shielding barrel body is assembled with the shielding barrel bottom plate and the packaging upper plate. According to the invention, high integration, magnetic shielding and stable performance in an extremely low temperature environment are realized, quasi-particle interference can be effectively reduced, and high stability of quantum calculation is ensured.

Description

Technical Field

[0001] The present invention relates to the field of quantum chip packaging technology, and in particular to a quantum chip packaging device for eliminating the influence of quasiparticles. Background Art

[0002] Quantum technology research has become a hot topic in the world's current scientific and technological research. Among them, the research on quantum computers is an important direction in the field of quantum technology. Quantum computers have computing power far exceeding that of classical computers. The number and quality of their core components, quantum bits (qubits), directly determine the computing power of the computer. In order to further improve the computing power of quantum computers, it is necessary to continuously expand the number of quantum bits and integrate them into high-density quantum chips. However, as the size of quantum chips continues to expand, the impact of their packaging structure on quantum bits becomes increasingly obvious.

[0003] In quantum chip packaging technology, the influence of quasiparticles has become an important factor limiting the performance of quantum bits. Quasiparticles refer to excited particles generated by the destruction of Cooper pairs in superconducting materials at low temperatures. The transport and accumulation of these quasiparticles in quantum chips will cause energy relaxation of superconducting quantum bits, thereby shortening the coherence time of quantum bits and affecting the stability of quantum computing. Existing quantum chip packaging technology usually uses superconducting shielding layers or low-temperature treatment to suppress the influence of quasiparticles, but it is still difficult to effectively control the transport and accumulation of quasiparticles in the chip, resulting in difficulty in further improving the coherence time of quantum bits. Summary of the invention

[0004] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: a quantum chip packaging device for eliminating the influence of quasiparticles, mainly comprising: A shielding barrel bottom plate, the shielding barrel bottom plate is located at the bottom end of the shielding barrel body, and is provided with a first groove, a second groove and a third groove; A substrate, wherein the substrate is provided with a first square hole, a second square hole, a third square hole and a fourth square hole for placing a connector and a chip square hole for placing a quantum chip; A packaging upper plate, the packaging upper plate is a cylindrical structure, and is provided with a fifth square hole, a sixth square hole, a seventh square hole, an eighth square hole and a central square hole inside, and the central square hole is placed at the center of the packaging upper plate; A PCB board, wherein the PCB board is placed on the substrate; A connecting plate component, the connecting plate component comprising a first connecting plate and a second connecting plate, the first connecting plate being placed on the PCB board; the second connecting plate being placed in the fifth square hole, the sixth square hole, the seventh square hole and the eighth square hole; A cover plate component, wherein the cover plate component includes a first cover plate, a second cover plate, a third cover plate and a central cover plate, which are respectively packaged at different positions to protect internal components; The shielding barrel body is assembled with the shielding barrel bottom plate and the packaging upper plate to form an outer shielding structure of the packaging device.

[0006] As a preferred solution of the quantum chip packaging device for eliminating the influence of quasiparticles as described in the present invention, the bottom plate of the shielding barrel includes an outer wall of the bottom plate and an inner wall of the bottom plate, wherein the outer diameter of the outer wall of the bottom plate is larger than the outer diameter of the inner wall of the bottom plate, and the protruding thickness of the outer wall of the bottom plate relative to the inner wall of the bottom plate matches the wall thickness of the shielding barrel body.

[0007] As a preferred solution of the quantum chip packaging device for eliminating the influence of quasiparticles as described in the present invention, wherein: the packaging upper plate includes an upper plate outer wall and an upper plate inner wall, the outer diameter of the upper plate outer wall is larger than the outer diameter of the upper plate inner wall, and the protruding thickness of the upper plate outer wall relative to the upper plate inner wall matches the wall thickness of the shielding barrel body; the positions of the fifth square hole, the sixth square hole, the seventh square hole and the eighth square hole are coaxially arranged with the first square hole, the second square hole, the third square hole and the fourth square hole on the substrate respectively.

[0008] As a preferred solution of the quantum chip packaging device for eliminating the influence of quasiparticles described in the present invention, wherein: the size of the first connecting plate is set according to the size and number of the connector, and the position of the first connecting plate corresponds to the first square hole, the second square hole, the third hole and the fourth square hole on the substrate, the first connecting plate is provided with a connecting hole for fixing the connector, the protruding parts on both sides of the first connecting plate are provided with threaded holes, and the first connecting plate, the PCB board and the substrate are fixedly connected by screws; the second connecting plate is provided with a connecting hole for fixing the connector, the protruding parts on both sides of the second connecting plate are provided with threaded holes, the upper plate of the package is provided with a threaded hole coaxially corresponding to the second connecting plate, and the second connecting plate and the substrate are fixedly connected by screws.

[0009] As a preferred solution of the quantum chip packaging device for eliminating the influence of quasi-particles described in the present invention, wherein: the first cover plate is packaged under the first square hole, the second square hole, the third square hole and the fourth square hole, and the first cover plate is placed in the second groove, both sides of the first cover plate are provided with arc protrusions, and the arc protrusions are placed in the third groove, and a threaded hole is provided in the middle of the protruding arc, and the first cover plate is fixed to the substrate by screws; the second cover plate is packaged under the chip square hole, and the top of the second cover plate is provided with a groove, the groove is used for gold wire bonding of the chip, the second cover plate is placed in the first groove, and is fixedly connected to the substrate by screws; the third cover plate is packaged above the chip and is fixedly connected to the PCB board by screws; the third cover plate is embedded in the middle part surrounded by the first connecting plate, and the thickness of the third cover plate is consistent with the thickness of the first connecting plate; the central cover plate is placed in the central square hole for packaging the central square hole, the central cover plate adopts a trapezoidal structure design, the upper layer size is larger than the lower layer size, and the central cover plate is fixedly connected to the packaging upper plate by screws; The inside of the shielding barrel body is coated with infrared glue coating, and the shielding barrel bottom plate, base plate, first connecting plate, second connecting plate, first cover plate, center cover plate, packaging upper plate and shielding barrel body are all made of oxygen-free copper, and the second cover plate and the third cover plate are made of ink-splashing alloy.

[0010] A packaging method for a quantum chip packaging device for eliminating the influence of quasiparticles, the method comprising: Step 1: Deposit a superconducting material layer with a high critical temperature on the bottom plate of the shielding barrel, the barrel body of the shielding barrel and the inner wall of the packaging upper plate to form a superconducting interlayer shielding structure, and apply an infrared glue coating on the inside of the barrel body of the shielding barrel; Step 2: Coat a graphene-doped superconductor low-energy state trap material layer on the surface of the substrate and PCB board, especially increase the coating thickness around the square holes of the chip, and use low-temperature heat treatment to optimize the trap energy state distribution to capture quasi-particles and confine them in a local minimum potential well; Step 3: Depositing a quantum dot adsorption layer on the inner wall of the chip square hole and the surface of the central square hole inside the package upper plate; Step 4: Assemble the shield barrel body, shield barrel bottom plate, package upper plate, substrate, PCB board, cover plate component and connecting plate component to form a complete packaging structure, and introduce a microstructure guide layer into the first groove, the second groove and the third groove to diffuse the captured quasiparticles to the low temperature zone; Step 5: Perform multi-dimensional performance tests on the packaging structure in a low-temperature environment, and determine the quasiparticle suppression capability based on the multi-dimensional performance test results.

[0011] As a preferred solution of the quantum chip packaging method for eliminating the influence of quasiparticles described in the present invention, wherein: the multi-dimensional performance test of the packaging structure in step 5 includes the following steps: Use cryogenic probe scanning technology or microwave resonance measurement to measure the density of quasiparticles at different locations, record the number and distribution of quasiparticles, and calculate the change in quasiparticle density. , the calculation formula is: , in: is the number of quasiparticles per unit volume, is the volume of the measurement area; The energy dissipation effect of quasiparticles is tested through the quantum dot adsorption layer. The kinetic energy conversion of quasiparticles in the adsorption layer is measured using a nanoscale thermal probe. The energy dissipation efficiency of quasiparticles is calculated based on the energy consumption efficiency of quasiparticles in the quantum dot layer. , and compared it with the theoretical expected value to evaluate the quasi-particle dissipation capacity of the adsorption layer, where the energy dissipation efficiency The calculation formula is: , in: represents the dissipated energy, represents the total energy of the quasiparticle; The standard quantum bit coherence time measurement method is used to test the quantum bits and record the coherence time of the quantum bits under different packaging schemes. and compared with the benchmark value without any quasiparticle suppression scheme; By comparing the quasiparticle transmittance of different layers using quantum current transport measurement techniques or microwave reflectometry , the effective shielding capability of each level in the packaging structure is obtained; the quasiparticle transmittance The calculation formula is: , in, is the intensity of the quasi-particle flux through the material, is the flux intensity of the incident quasiparticle.

[0012] As a preferred solution of the quantum chip packaging method for eliminating the influence of quasiparticles described in the present invention, the quasiparticle suppression ability of the packaging structure is related to the change in the quasiparticle density. , Energy dissipation efficiency , bit coherence time and the quasiparticle transmittance Related; the mathematical expression of the quasiparticle suppression ability is: , in: It is a comprehensive indicator used to quantify the suppression effect of different packaging schemes on quasi-particles; The change in quasiparticle density, indicating the location of the packaging material and time On the top, the concentration of quasiparticles changes; is an exponential decay factor, which indicates the attenuation effect of quasiparticles when propagating in space. As the quasiparticle density increases, it decays exponentially, where is the attenuation coefficient of the material, which reflects the shielding ability of the material against quasi-particles; is the energy dissipation efficiency function, which is the efficiency with which the kinetic energy of the quasiparticles is converted into heat or other forms of energy in the quantum dots or other material layers; is the Gaussian decay factor, describing the quasiparticle kinetic energy The effect on energy dissipation, as the quasiparticle kinetic energy As the energy dissipation efficiency increases, it shows a decreasing trend. is the attenuation coefficient related to the quasiparticle kinetic energy and material properties; represents the spatial integration region, which is used to calculate the quasiparticle density variation in the entire encapsulated area; represents the total effect of energy dissipation on all quasiparticles; The combined effect of coherence time and transmittance is described. As transmittance increases, coherence time decreases, showing the effect of encapsulation on quasiparticle suppression. is the adjustment factor, which indicates the effect of package design on transmittance; is the quantum bit coherence time, which indicates the time that a quantum bit can maintain its quantum state without external interference; The quasiparticle transmittance indicates the shielding effect of the encapsulation layer on the quasiparticles and measures the degree of penetration of different shielding layers on the quasiparticles. Indicates the volume of the package; Represents the surface area of ​​the package; Value range meaning: when >0.8, indicating that the packaging solution has good quasiparticle suppression effect and is suitable for long-term stable operation; When 0.5< ≤0.8, indicating that the packaging solution needs to be optimized; when ≤0.5, indicating that the packaging solution has poor quasiparticle suppression effect and the material and structure need to be redesigned.

[0013] As a preferred solution of the quantum chip packaging method for eliminating the influence of quasiparticles described in the present invention, a dynamic quasiparticle transport control mechanism is introduced into the packaging structure, and the quasiparticles are guided to move to the energy dissipation area through adjustable microstructure channels to improve the quasiparticle suppression ability of the package.

[0014] As a preferred solution of the quantum chip packaging method for eliminating the influence of quasiparticles described in the present invention, the dynamic quasiparticle transport control mechanism includes the following steps: An adjustable microstructure channel is integrated inside the encapsulation layer, and the channel forms a periodic potential field through a superconducting microbridge or a quantum dot array to guide the quasiparticles to diffuse into the low temperature region; By adjusting the transport characteristics of microstructure channels through low-temperature electric or magnetic fields, the movement direction and distribution of quasiparticles can be dynamically optimized; Add a real-time monitoring system outside the package, combine microwave resonance measurement and nanoscale thermal probe to analyze the density distribution of quasiparticles, and adjust the opening and closing state of the microstructure channel according to the monitoring data to enhance the shielding ability of the package structure; Combined with the mathematical expression of quasiparticle suppression ability, the exponential decay factor is dynamically adjusted The coefficients in and Gaussian attenuation factor The coefficients in , maximizing the dissipation efficiency of quasiparticles and improving the overall shielding performance of the package.

[0015] Beneficial effects of the present invention: 1. The packaging device proposed in the present invention can achieve high integration, magnetic shielding, and can still maintain good performance in an extremely low temperature environment. In addition, the entire device has simple parts, is easy to assemble, and is also easy to mass produce; 2. The present invention reduces the interference of quasiparticles on quantum bits from multiple dimensions by introducing a superconducting material layer with a high critical temperature, a low-energy state trap material layer doped with graphene, and a quantum dot adsorption layer inside the packaging structure. Among them, the trap material layer can capture and confine quasiparticles in a local potential well, and the quantum dot adsorption layer can efficiently dissipate the energy of quasiparticles, thereby reducing its impact on the coherence time of the quantum bit. At the same time, a microstructure guide layer and a dynamic transport control mechanism are used to guide the quasiparticles to diffuse into the low-temperature energy dissipation zone, further enhancing the shielding ability of the packaging structure, thereby significantly reducing the density of quasiparticles, increasing the coherence time of the quantum bit, and ensuring the high stability and long life of quantum computing; 3. The present invention integrates a dynamic quasiparticle transport control mechanism in the packaging structure, uses an adjustable microstructure channel to guide the quasiparticles to move to a specific dissipation area, and adjusts the transport characteristics of the microstructure channel through a low-temperature electric field or magnetic field to improve the quasiparticle shielding effect. At the same time, the real-time monitoring system combines microwave resonance measurement and nanoscale thermal probe technology to dynamically adjust the material coefficient so that the packaging structure maintains the best quasiparticle shielding ability under different environments. In addition, through the dynamic adjustment of the exponential attenuation factor and the Gaussian attenuation factor, the dissipation efficiency of the quasiparticle is maximized, ensuring that the quantum chip package has long-term and stable anti-interference ability and adapts to quantum computing needs under different temperature and environmental conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them: Figure 1 This is a schematic diagram of the overall structure of a quantum chip packaging device for eliminating the influence of quasiparticles after assembly according to the present invention; Figure 2 This is a schematic diagram of the disassembly of a quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention; Figure 3 This is a schematic structural diagram of a substrate of a quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention; Figure 4 This is a schematic structural diagram of a shielding barrel bottom plate of a quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention; Figure 5 This is a schematic structural diagram of a packaging upper plate of a quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention.

[0017] In the figure: 1. shielding barrel bottom plate; 101. first groove; 102. second groove; 103. third groove; 104. bottom plate inner wall; 105. bottom plate outer wall; 2. substrate; 201. first square hole; 202. second square hole; 203. third square hole; 204. fourth square hole; 205. chip square hole; 3. shielding barrel body; 4. package upper plate; 401. fifth square hole; 402. sixth square hole; 403. seventh square hole; 404. eighth square hole; 405. center square hole; 406. upper plate inner wall; 407. upper plate outer wall; 5. PCB board; 6. first connecting plate; 7. first cover plate; 8. second cover plate; 9. third cover plate; 10. second connecting plate; 11. center cover plate. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0019] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0020] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0021] Secondly, the present invention is described in detail with reference to the schematic diagram. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0022] Example 1

[0023] Reference Figure 1-5 , as one embodiment of the present invention, provides a quantum chip packaging device for eliminating the influence of quasiparticles, comprising: Shielding barrel bottom plate 1, such as Figure 4 The shield barrel bottom plate 1 is a cylinder that supports the entire assembly structure. The shield barrel bottom plate 1 is located at the bottom end of the shield barrel body 3, and is provided with a first groove 101, a second groove 102 and a third groove 103; in addition, the shield barrel bottom plate 1 includes a bottom plate outer wall 105 and a bottom plate inner wall 104, wherein the outer diameter of the bottom plate outer wall 105 is greater than the outer diameter of the bottom plate inner wall 104, and the protruding thickness of the bottom plate outer wall 105 relative to the bottom plate inner wall 104 matches the wall thickness of the shield barrel body 3.

[0024] Substrate 2, such as Figure 3 The substrate 2 is provided with a first square hole 201, a second square hole 202, a third square hole 203 and a fourth square hole 204 for placing a connector and a chip square hole 205 for placing a quantum chip.

[0025] The packaging upper plate 4 is a cylindrical structure, and is provided with a fifth square hole 401 , a sixth square hole 402 , a seventh square hole 403 , an eighth square hole 404 and a central square hole 405 . The central square hole 405 is located at the center of the packaging upper plate 4 .

[0026] The PCB board 5 is placed on the substrate 2 .

[0027] The connecting plate component includes a first connecting plate 6 and a second connecting plate 10 . The first connecting plate 6 is placed on the PCB board 5 ; the second connecting plate 10 is placed in the fifth square hole 401 , the sixth square hole 402 , the seventh square hole 403 and the eighth square hole 404 .

[0028] The cover plate component includes a first cover plate 7, a second cover plate 8, a third cover plate 9 and a central cover plate 11, which are respectively packaged in different positions to protect internal components.

[0029] The shielding barrel body 3 is assembled with the shielding barrel bottom plate 1 and the packaging upper plate 4 to form an outer shielding structure of the packaging device.

[0030] Specifically, Figure 5 The packaging upper plate 4 includes an upper plate outer wall 407 and an upper plate inner wall 406. The outer diameter of the upper plate outer wall 407 is greater than the outer diameter of the upper plate inner wall 406, and the protruding thickness of the upper plate outer wall 407 relative to the upper plate inner wall 406 matches the wall thickness of the shield barrel body 3. The fifth square hole 401, the sixth square hole 402, the seventh square hole 403 and the eighth square hole 404 are coaxially arranged with the first square hole 201, the second square hole 202, the third square hole 203 and the fourth square hole 204 on the base plate 2, respectively.

[0031] like Figure 2 The size of the first connecting plate 6 is set according to the size and quantity of the connector, and the position of the first connecting plate 6 corresponds to the first square hole 201, the second square hole 202, the third square hole 203 and the fourth square hole 204 on the substrate 2. The first connecting plate 6 is provided with connecting holes for fixing the connector, and the protruding parts on both sides of the first connecting plate 6 are provided with threaded holes. The first connecting plate 6, the PCB board 5 and the substrate 2 are fixedly connected by screws.

[0032] The second connecting plate 10 is provided with connecting holes for fixing the connector, the protruding parts on both sides of the second connecting plate 10 are provided with threaded holes, the packaging upper plate 4 is provided with threaded holes coaxially corresponding to the second connecting plate 10, and the second connecting plate 10 is fixedly connected to the base plate 2 by screws.

[0033] like Figure 2 The first cover plate 7 is encapsulated under the first square hole 201, the second square hole 202, the third hole 203 and the fourth square hole 204, and the first cover plate 7 is placed in the second groove 102. Arc protrusions are provided on both sides of the first cover plate 7, and the arc protrusions are placed in the third groove 103, and a threaded hole is provided in the middle of the protruding arc. The first cover plate 7 is fixed to the substrate 2 by screws.

[0034] The second cover plate 8 is packaged under the chip square hole 205. A groove is provided on the top of the second cover plate 8 for gold wire bonding of the chip. The second cover plate 8 is placed in the first groove 101 and fixedly connected to the substrate 2 by screws.

[0035] The third cover plate 9 is embedded in the middle part surrounded by the first connecting plate 6, and the thickness of the third cover plate 9 is consistent with the thickness of the first connecting plate 6. The third cover plate 9 is packaged above the chip and fixedly connected to the PCB board 5 by screws.

[0036] The center cover plate 11 is placed in the center square hole 405 and is used to encapsulate the center square hole 405. The center cover plate 11 adopts a trapezoidal structure design. The upper layer size is larger than the lower layer size. The center cover plate 11 is provided with a threaded hole, and the corresponding position of the encapsulation upper plate 4 is provided with a threaded hole coaxial with the center cover plate 11. The center cover plate 11 is fixedly connected to the encapsulation upper plate 4 by screws.

[0037] The inside of the shielding barrel body 3 is coated with an infrared glue coating, and the shielding barrel bottom plate 1, the base plate 2, the first connecting plate 6, the second connecting plate 10, the first cover plate 7, the center cover plate 11, the packaging upper plate 4, and the shielding barrel body 3 are all made of oxygen-free copper, and the second cover plate 8 and the third cover plate 9 are made of ink-splashing alloy.

[0038] The oxygen-free copper material used in the present invention enables the quantum packaging design to maintain good performance in ultra-low temperature environments, achieving the effects of high integration, high thermal conductivity and magnetic shielding, and can quickly dissipate the heat generated by the quantum chip when it is working. The overall structure of the device is very strong and reliable, and the components that make up the device are simple, easy to assemble and mass-produce.

[0039] A packaging method for a quantum chip packaging device for eliminating the influence of quasiparticles is used, the method comprising: Step 1: Deposit a layer of superconducting material with a high critical temperature on the bottom plate of the shielding barrel, the shielding barrel body and the inner wall of the packaging upper plate to form a superconducting interlayer shielding structure, and apply infrared glue coating on the inside of the shielding barrel body to enhance the thermal radiation absorption and shielding effect, and improve the low-temperature performance of the packaging system; among them, the superconducting interlayer shielding structure adopts a multi-layer superconductor-insulator-superconductor (SIS) structure design, and optimizes the coverage uniformity through low-temperature plasma enhanced deposition (PECVD) technology, thereby forming an effective quasiparticle shielding barrier and reducing the diffusion of quasiparticles to the quantum chip area.

[0040] Step 2: Coat the surface of the substrate and PCB with a graphene-doped superconductor (such as NbSe2+ graphene) or alumina) low-energy trap material layer, especially increase the coating thickness around the square holes of the chip, and use low-temperature heat treatment to optimize the trap energy state distribution to capture quasiparticles and confine them to a local minimum potential well, thereby improving the quasiparticle dissipation ability. Among them, the minimum potential well refers to the quasiparticles (such as quasiparticle excited state electrons in superconducting systems or single electrons after Cooper pairs are broken) in the graphene-doped superconductor low-energy trap material layer. By adjusting the energy state distribution and optimizing the treatment of the material, the quasiparticles (such as quasiparticle excited state electrons in superconducting systems or single electrons after Cooper pairs are broken) are confined to a local low-energy region (i.e., a minimum potential well), thereby reducing their interference with the quantum chip.

[0041] Specifically, the minimal potential well has the following characteristics:

[0042] Local low-energy regions: Due to the doping and low-temperature heat treatment of the material, the potential energy of some local regions is lower than that of the surrounding areas, forming a "trap" effect, causing quasiparticles to tend to stay in this area.

[0043] Quasiparticle capture capability: By adjusting the band structure of doped graphene superconducting materials, the depth and density of these extremely small potential wells can be adjusted, enabling them to effectively capture and confine quasiparticles and reduce their diffusion into the interior of the chip.

[0044] Step 3: Deposit a semiconductor quantum dot adsorption layer such as PbSe or InAs on the inner wall of the square hole of the chip and the surface of the central square hole inside the package upper plate to actively dissipate the kinetic energy of the quasiparticles by using the local electron-phonon coupling effect, and ensure that the quantum dots are evenly distributed through chemical vapor deposition (CVD) or spraying nanomaterials, thereby enhancing the active consumption capacity of the packaging system for quasiparticles.

[0045] Step 4: Assemble the shielding barrel body, shielding barrel bottom plate, packaging upper plate, substrate, PCB board, cover plate component and connecting plate component to form a complete packaging structure, and introduce microstructure guide layers in the first groove, the second groove and the third groove to allow the captured quasiparticles to diffuse to the low-temperature zone. At the same time, optimize the thickness and number of packaging materials through low-temperature probe scanning (LT-SPM) or microwave resonance measurement to enhance the quasiparticle suppression effect.

[0046] Step 5: Perform multi-dimensional performance tests on the packaging structure in a low-temperature environment, and determine the quasiparticle suppression capability based on the multi-dimensional performance test results.

[0047] Specifically, a multi-dimensional performance test is performed on the packaging structure, including the following steps: Use cryogenic probe scanning technology or microwave resonance measurement to measure the density of quasiparticles at different locations, record the number and distribution of quasiparticles, and calculate the change in quasiparticle density. , the calculation formula is: , in: is the number of quasiparticles per unit volume, is the volume of the measurement area; The energy dissipation effect of quasiparticles is tested through the quantum dot adsorption layer. The kinetic energy conversion of quasiparticles in the adsorption layer is measured using a nanoscale thermal probe. The energy dissipation efficiency of quasiparticles is calculated based on the energy consumption efficiency of quasiparticles in the quantum dot layer. , and compared it with the theoretical expected value to evaluate the quasi-particle dissipation capacity of the adsorption layer, where the energy dissipation efficiency The calculation formula is: , in: represents the dissipated energy, represents the total energy of the quasiparticle; The standard quantum bit coherence time measurement method is used to test the quantum bits and record the coherence time of the quantum bits under different packaging schemes. and compared with the benchmark value without any quasiparticle suppression scheme; By comparing the quasiparticle transmittance of different layers using quantum current transport measurement techniques or microwave reflectometry , the effective shielding capability of each level in the packaging structure is obtained; the quasiparticle transmittance The calculation formula is: , in, is the intensity of the quasi-particle flux through the material, is the flux intensity of the incident quasiparticle.

[0048] Furthermore, the quasiparticle suppression capability of the packaging structure is related to the change in quasiparticle density. , Energy dissipation efficiency , bit coherence time and the quasiparticle transmittance The mathematical expression of quasiparticle suppression capability is: , in: It is a comprehensive indicator used to quantify the suppression effect of different packaging schemes on quasi-particles; The change in quasiparticle density, indicating the location of the packaging material and time On the top, the concentration of quasiparticles changes; is an exponential decay factor, which indicates the attenuation effect of quasiparticles when propagating in space. As the quasiparticle density increases, it decays exponentially, where is the attenuation coefficient of the material, which reflects the shielding ability of the material against quasi-particles. The specific value is obtained by fitting experimental data; is the energy dissipation efficiency function, which is the efficiency with which the kinetic energy of the quasiparticles is converted into heat or other forms of energy in the quantum dots or other material layers; is the Gaussian decay factor, describing the quasiparticle kinetic energy The effect on energy dissipation, as the quasiparticle kinetic energy As the energy dissipation efficiency increases, it shows a decreasing trend. is the attenuation coefficient related to the quasiparticle kinetic energy and material properties; represents the spatial integration region, which is used to calculate the quasiparticle density variation in the entire encapsulated area; represents the total effect of energy dissipation on all quasiparticles; The combined effect of coherence time and transmittance is described. As transmittance increases, coherence time decreases, showing the effect of encapsulation on quasiparticle suppression. is the adjustment factor, which indicates the effect of package design on transmittance; is the quantum bit coherence time, which indicates the time that a quantum bit can maintain its quantum state without external interference. It is a regulatory factor under the influence of environmental factors (such as temperature, magnetic field, etc.); The quasiparticle transmittance indicates the shielding effect of the encapsulation layer on quasiparticles and measures the degree of penetration of different shielding layers (such as superconducting layer and trap coating) on ​​quasiparticles. Indicates the volume of the package; Represents the surface area of ​​the package; Value range meaning: when >0.8, indicating that the packaging solution has good quasiparticle suppression effect and is suitable for long-term stable operation; When 0.5< ≤0.8, indicating that the packaging solution needs to be optimized, especially in terms of energy dissipation or coherence time; when ≤0.5, indicating that the packaging solution has poor quasiparticle suppression effect and the material and structure need to be redesigned.

[0049] This formula adopts a comprehensive integral form, combining the physical mechanisms of quasiparticle density, energy dissipation, quantum bit coherence time and transmittance, reflecting the multi-dimensional impact of different packaging schemes on quasiparticle suppression.

[0050] Furthermore, a dynamic quasiparticle transport control mechanism is introduced into the packaging structure, which guides the quasiparticles to move to the energy dissipation area through an adjustable microstructure channel to improve the quasiparticle suppression ability of the package. The dynamic quasiparticle transport control mechanism includes the following steps: An adjustable microstructure channel is integrated inside the encapsulation layer. The channel forms a periodic potential field through a superconducting microbridge or quantum dot array to guide the quasiparticles to diffuse into the low-temperature area. By adjusting the transport characteristics of the microstructure channel through low-temperature electric or magnetic fields, the movement direction and distribution of quasiparticles are dynamically optimized to improve the overall energy dissipation efficiency; Add a real-time monitoring system outside the package, combine microwave resonance measurement and nanoscale thermal probe to analyze the density distribution of quasiparticles, and adjust the opening and closing state of the microstructure channel according to the monitoring data to enhance the shielding ability of the package structure; Combined with the mathematical expression of quasiparticle suppression ability, the exponential decay factor is dynamically adjusted The coefficients in and Gaussian attenuation factor The coefficients in , maximizing the dissipation efficiency of quasiparticles and improving the overall shielding performance of the package.

[0051] In summary, the present invention reduces the interference of quasiparticles on quantum bits from multiple dimensions by introducing a superconducting material layer with a high critical temperature, a low-energy state trap material layer doped with graphene, and a quantum dot adsorption layer inside the packaging structure. Among them, the trap material layer can capture and confine quasiparticles in a local potential well, and the quantum dot adsorption layer can efficiently dissipate the energy of quasiparticles, thereby reducing its impact on the coherence time of the quantum bit. At the same time, a microstructure guide layer and a dynamic transport control mechanism are used to guide the quasiparticles to diffuse to the low-temperature energy dissipation zone, further enhancing the shielding ability of the packaging structure, thereby significantly reducing the quasiparticle density, improving the coherence time of the quantum bit, and ensuring the high stability and long life of quantum computing. The present invention integrates a dynamic quasiparticle transport control mechanism in the packaging structure, uses an adjustable microstructure channel to guide the quasiparticles to move to a specific dissipation area, and adjusts the transport characteristics of the microstructure channel through a low-temperature electric field or magnetic field to improve the quasiparticle shielding effect. At the same time, the real-time monitoring system combines microwave resonance measurement and nanoscale thermal probe technology to dynamically adjust the material coefficient so that the packaging structure maintains the best quasiparticle shielding ability under different environments. In addition, the dissipation efficiency of quasiparticles is maximized through dynamic adjustment of the exponential attenuation factor and the Gaussian attenuation factor, ensuring that the quantum chip packaging has long-term stable anti-interference capabilities and can adapt to quantum computing needs under different temperature and environmental conditions.

[0052] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A quantum chip packaging device for eliminating the influence of quasiparticles, characterized in that: include: A shielding barrel bottom plate (1), the shielding barrel bottom plate (1) being located at the bottom end of the shielding barrel body (3), and being provided with a first groove (101), a second groove (102) and a third groove (103); A substrate (2), wherein the substrate (2) is provided with a first square hole (201), a second square hole (202), a third square hole (203), and a fourth square hole (204) for placing a connector, and a chip square hole (205) for placing a quantum chip; A packaging upper plate (4), wherein a fifth square hole (401), a sixth square hole (402), a seventh square hole (403), an eighth square hole (404) and a central square hole (405) are provided inside the packaging upper plate (4), and the central square hole (405) is located at a central position of the packaging upper plate (4); A PCB board (5), wherein the PCB board (5) is placed on the substrate (2); A connecting plate component, the connecting plate component comprising a first connecting plate (6) and a second connecting plate (10), the first connecting plate (6) being placed on the PCB board (5); the second connecting plate (10) being placed in the fifth square hole (401), the sixth square hole (402), the seventh square hole (403) and the eighth square hole (404); A cover plate component, the cover plate component comprising a first cover plate (7), a second cover plate (8), a third cover plate (9) and a central cover plate (11), which are respectively packaged at different positions to protect internal components; A shielding barrel body (3) is assembled with a shielding barrel bottom plate (1) and a packaging upper plate (4) to form an outer shielding structure of the packaging device.

2. The quantum chip packaging device for eliminating the influence of quasiparticles as claimed in claim 1, characterized in that: The shield barrel bottom plate (1) comprises a bottom plate outer wall (105) and a bottom plate inner wall (104), wherein the outer diameter of the bottom plate outer wall (105) is greater than the outer diameter of the bottom plate inner wall (104), and the protruding thickness of the bottom plate outer wall (105) relative to the bottom plate inner wall (104) matches the wall thickness of the shield barrel body (3).

3. The quantum chip packaging device for eliminating the influence of quasiparticles as claimed in claim 1, characterized in that: The packaging upper plate (4) is a cylindrical structure, and the packaging upper plate (4) includes an upper plate outer wall (407) and an upper plate inner wall (406), the outer diameter of the upper plate outer wall (407) is greater than the outer diameter of the upper plate inner wall (406), and the protruding thickness of the upper plate outer wall (407) relative to the upper plate inner wall (406) matches the wall thickness of the shielding barrel body (3); the positions of the fifth square hole (401), the sixth square hole (402), the seventh square hole (403) and the eighth square hole (404) are respectively coaxially arranged with the positions of the first square hole (201), the second square hole (202), the third square hole (203) and the fourth square hole (204) on the substrate (2).

4. The quantum chip packaging device for eliminating the influence of quasiparticles as claimed in claim 1, characterized in that: The size of the first connecting plate (6) is set according to the size and number of the connectors, and the position of the first connecting plate (6) corresponds to the first square hole (201), the second square hole (202), the third square hole (203) and the fourth square hole (204) on the base plate (2); the first connecting plate (6) is provided with connecting holes for fixing the connectors, and the protruding parts on both sides of the first connecting plate (6) are provided with threaded holes, and the first connecting plate (6), the PCB board (5) and the base plate (2) are fixedly connected by screws; the second connecting plate (10) is provided with connecting holes for fixing the connectors, and the protruding parts on both sides of the second connecting plate (10) are provided with threaded holes, and the package upper plate (4) is provided with a threaded hole coaxially corresponding to the second connecting plate (10), and the second connecting plate (10) and the base plate (2) are fixedly connected by screws.

5. The quantum chip packaging device for eliminating the influence of quasiparticles as claimed in claim 1, characterized in that: The first cover plate (7) is packaged below the first square hole (201), the second square hole (202), the third square hole (203) and the fourth square hole (204), and the first cover plate (7) is placed in the second groove (102). The first cover plate (7) is provided with arc protrusions on both sides, and the arc protrusions are placed in the third groove (103), and a threaded hole is provided in the middle of the protruding arcs. The first cover plate (7) is fixed to the substrate (2) by screws. The second cover plate (8) is packaged below the chip square hole (205), and a groove is provided on the top of the second cover plate (8), and the groove is used for gold wire bonding of the chip. The second cover plate (8) 8) is placed in the first groove (101) and fixedly connected to the base plate (2) by screws; the third cover plate (9) is placed above the packaged chip and fixedly connected to the PCB board (5) by screws; the third cover plate (9) is embedded in the middle part surrounded by the first connecting plate (6), and the thickness of the third cover plate (9) is consistent with the thickness of the first connecting plate (6); the central cover plate (11) is placed in the central square hole (405) and is used to package the central square hole (405); the central cover plate (11) adopts a trapezoidal structure design, the upper layer size is larger than the lower layer size, and the central cover plate (11) is fixedly connected to the package upper plate (4) by screws; The shielding barrel body (3) is coated with an infrared adhesive coating on the inside; the shielding barrel bottom plate (1), the base plate (2), the first connecting plate (6), the second connecting plate (10), the first cover plate (7), the center cover plate (11), the packaging upper plate (4), and the shielding barrel body (3) are all made of oxygen-free copper; and the second cover plate (8) and the third cover plate (9) are made of ink-splashing alloy.

6. A quantum chip packaging method for eliminating the influence of quasiparticles, applied to a quantum chip packaging device for eliminating the influence of quasiparticles as claimed in claim 1, characterized in that: The method comprises the following steps: Step 1: Deposit a superconducting material layer with a high critical temperature on the bottom plate of the shielding barrel, the barrel body of the shielding barrel and the inner wall of the packaging upper plate to form a superconducting interlayer shielding structure, and apply an infrared glue coating on the inside of the barrel body of the shielding barrel; Step 2: Coat a graphene-doped superconductor low-energy state trap material layer on the surface of the substrate and PCB board, especially increase the coating thickness around the square holes of the chip, and use low-temperature heat treatment to optimize the trap energy state distribution to capture quasi-particles and confine them in a local minimum potential well; Step 3: Depositing a quantum dot adsorption layer on the inner wall of the chip square hole and the surface of the central square hole inside the package upper plate; Step 4: Assemble the shield barrel body, shield barrel bottom plate, package upper plate, substrate, PCB board, cover plate component and connecting plate component to form a complete packaging structure, and introduce a microstructure guide layer into the first groove, the second groove and the third groove to diffuse the captured quasiparticles to the low temperature zone; Step 5: Perform multi-dimensional performance tests on the packaging structure in a low-temperature environment, and determine the quasiparticle suppression capability based on the multi-dimensional performance test results.

7. A quantum chip packaging method for eliminating the influence of quasiparticles as claimed in claim 6, characterized in that: In step 5, a multi-dimensional performance test is performed on the packaging structure, including the following steps: Use cryogenic probe scanning technology or microwave resonance measurement to measure the density of quasiparticles at different locations, record the number and distribution of quasiparticles, and calculate the change in quasiparticle density. , the calculation formula is: ， in: is the number of quasiparticles per unit volume, is the volume of the measurement area; The energy dissipation effect of quasiparticles is tested through the quantum dot adsorption layer. The kinetic energy conversion of quasiparticles in the adsorption layer is measured using a nanoscale thermal probe. The energy dissipation efficiency of quasiparticles is calculated based on the energy consumption efficiency of quasiparticles in the quantum dot layer. , and compared it with the theoretical expected value to evaluate the quasi-particle dissipation capacity of the adsorption layer, where the energy dissipation efficiency The calculation formula is: ， in: represents the dissipated energy, represents the total energy of the quasiparticle; The standard quantum bit coherence time measurement method is used to test the quantum bits and record the coherence time of the quantum bits under different packaging schemes. and compared with the benchmark value without any quasiparticle suppression scheme; By comparing the quasiparticle transmittance of different layers using quantum current transport measurement techniques or microwave reflectometry , the effective shielding capability of each level in the packaging structure is obtained; the quasiparticle transmittance The calculation formula is: ， in, is the intensity of the quasi-particle flux through the material, is the flux intensity of the incident quasiparticle.

8. The quantum chip packaging method for eliminating the influence of quasiparticles as claimed in claim 7, characterized in that: The quasiparticle suppression capability of the packaging structure and the change in quasiparticle density , Energy dissipation efficiency , bit coherence time and the quasiparticle transmittance The mathematical expression of quasiparticle suppression capability is: ， in: It is a comprehensive indicator used to quantify the suppression effect of different packaging schemes on quasi-particles; The change in quasiparticle density, indicating the location of the packaging material and time On the top, the concentration of quasiparticles changes; is an exponential decay factor, which indicates the attenuation effect of quasiparticles when propagating in space. As the quasiparticle density increases, it decays exponentially, where is the attenuation coefficient of the material, which reflects the shielding ability of the material against quasi-particles; is the energy dissipation efficiency function, which is the efficiency with which the kinetic energy of the quasiparticles is converted into heat or other forms of energy in the quantum dots or other material layers; is the Gaussian decay factor, describing the quasiparticle kinetic energy The effect on energy dissipation, as the quasiparticle kinetic energy As the energy dissipation efficiency increases, it shows a decreasing trend. is the attenuation coefficient related to the quasiparticle kinetic energy and material properties; represents the spatial integration region, which is used to calculate the quasiparticle density variation in the entire encapsulated area; represents the total effect of energy dissipation on all quasiparticles; The combined effect of coherence time and transmittance is described. As transmittance increases, coherence time decreases, showing the effect of encapsulation on quasiparticle suppression. is the adjustment factor, which indicates the effect of package design on transmittance; is the quantum bit coherence time, which indicates the time that a quantum bit can maintain its quantum state without external interference; The quasiparticle transmittance indicates the shielding effect of the encapsulation layer on the quasiparticles and measures the degree of penetration of different shielding layers on the quasiparticles. Indicates the volume of the package; Represents the surface area of ​​the package; Value range meaning: when >0.8, indicating that the packaging solution has good quasiparticle suppression effect and is suitable for long-term stable operation; When 0.5< ≤0.8, indicating that the packaging solution needs to be optimized; when ≤0.5, indicating that the packaging solution has poor quasiparticle suppression effect and the material and structure need to be redesigned.

9. The quantum chip packaging method for eliminating the influence of quasiparticles as claimed in claim 8, characterized in that: A dynamic quasiparticle transport control mechanism is introduced into the packaging structure, and the quasiparticles are guided to move to the energy dissipation area through an adjustable microstructure channel to improve the quasiparticle suppression capability of the package.

10. The quantum chip packaging method for eliminating the influence of quasiparticles as claimed in claim 9, characterized in that: The dynamic quasiparticle transport control mechanism comprises the following steps: An adjustable microstructure channel is integrated inside the encapsulation layer, and the channel forms a periodic potential field through a superconducting microbridge or a quantum dot array to guide the quasiparticles to diffuse into the low temperature region; By adjusting the transport characteristics of microstructure channels through low-temperature electric or magnetic fields, the movement direction and distribution of quasiparticles can be dynamically optimized; Add a real-time monitoring system outside the package, combine microwave resonance measurement and nanoscale thermal probe to analyze the density distribution of quasiparticles, and adjust the opening and closing state of the microstructure channel according to the monitoring data to enhance the shielding ability of the package structure; Combined with the mathematical expression of quasiparticle suppression ability, the exponential decay factor is dynamically adjusted The coefficients in and Gaussian attenuation factor The coefficients in , maximizing the dissipation efficiency of the quasiparticles.

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