Cache scanning

Abstract

Methods, systems, and apparatus for a system-on-chip. A system includes a functional component having one or more embedded random access memories (RAMs), the functional component including a scan memory state machine configured to generate a signal for dumping content of the one or more embedded RAMs during a scan dump process.

Description

Background Art

[0001] Random access memory (RAM) and caches often carry functional debugging information that can be useful in the event of a software crash or computer lockup. Code and conditions present in RAM can help find the root cause of a software crash. However, some RAM and caches may not have direct software visibility for debugging, and may not have an interface to inspect the contents of the RAM. Summary of the invention

[0002] This specification describes a system that can dump the contents of one or more embedded RAMs during a scan dump process. This allows a debugging system or user to inspect the contents of RAMs that may not have direct software visibility. For example, the contents of multiple static RAMs (SRAMs) can be dumped to a logical scan dump chain. The contents of the logical scan dump chain can then be dumped during a scan dump, for example using an existing logical scan dump framework.

[0003] Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages.

[0004] The described systems and methods allow visibility to code and conditions stored in RAM or SRAM that typically do not have visibility for debugging. Additionally, the systems and methods described in this specification can be integrated with existing test paths, such as built-in self-test paths. Integrating the described system with existing test paths can prevent or reduce timing impacts on the functional paths of the system. In addition, the systems and methods can advantageously create a continuous data stream to dump SRAM or cache data with improved efficiency, such as without any dummy or empty signal cycles. Additionally, the systems and methods can utilize an existing logic scan dump framework to read cache data. For example, dumping SRAM data to off-chip DRAM using an existing scan dump framework avoids additional timing and performance impacts on the system during the debugging process. Additionally, the systems and methods can be integrated with existing reset processes, such as on mobile phones, which enables SRAM data to be dumped without connecting to external devices.

[0005] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram of an example system-on-chip.

[0007] Figure 2 is a diagram of an example static RAM integrated on a chip.

[0008] Figure 3 is a diagram of an example dynamic RAM on a chip.

[0009] Figure 4 is a diagram of an example system-on-chip that dumps the contents of embedded RAM.

[0010] Figure 5 is a flow chart of a method for dumping the contents of an embedded RAM.

[0011] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0012] Figure 1 is a diagram of an example system-on-chip 100. System 100 allows the contents of embedded caches or RAM that do not normally have software visibility to be dumped so that the contents can be examined. Example functional components with embedded RAM that do not support software visibility include caches that store cache lines in embedded RAM and translation lookaside buffers that store translation entries in embedded RAM. These functional components are typically occupied by the logic circuitry of a hardware device, and therefore, the contents of these components are typically not accessible by software.

[0013] System 100 includes multiple static RAMs (SRAMs) 102, 104, 106 and a logic scan dump chain 108. For example, a logic scan dump chain can be a logic framework that dumps the logic content of a chip to an external storage device such as an external DRAM. In the example system 100, the logic scan dump chain is also utilized to dump the logic from SRAMs 102, 104, 106. In many cases, dumping the code and conditions present in the SRAM to an external location can help find the root cause of a software crash or computer lockup. The scan dump process can include dumping the code and conditions present in the SRAM. In system 100, a scan memory state machine can generate a signal for dumping the contents of SRAMs 102, 104, 106 to the logic scan dump chain 108. Then, when the contents of the logic scan dump chain 108 are executed, the logic scan dump chain 108 will include the contents of the SRAM. The contents of SRAMs 102, 104, 106 can be dumped to the logic scan dump chain 108 in a daisy chain, for example, in a sequential order. For example, when the contents of SRAM 102 are completely dumped to the logic scan dump chain 108, a signal can be generated to dump the contents of SRAM 104 to the logic scan dump chain 108. Similarly, when the contents of SRAM 104 are completely dumped to the logic scan dump chain 108, a signal can be generated to dump the contents of SRAM 106 to the logic scan dump chain 108. This process can be repeated for any number of SRAMs. Automatically triggering the daisy chain to dump the next SRAM can create a continuous data stream to dump the SRAMs, for example, without any dummy or empty signal cycles. The contents of each SRAM are dumped to the logic scan dump chain 108, which continues to dump the contents to an external storage device, such as an external DRAM.

[0014] Figure 2A diagram of an example functional component 200 for dumping an SRAM is shown. For example, the component 200 may be part of a cache. The functional component 200 includes a RAM wrapper 202. The RAM wrapper 202 includes a memory built-in self-test (MBIST) interface 204 and an SRAM or cache 206. The functional component 200 may include a test controller configured to generate a test signal for a test path 210 such as an MBIST path, and the functional component may have a functional path 208 separated from the test path 210. The MBIST interface 204 includes a scan memory state machine 212 that may be activated to dump the SRAM 206. For example, the scan memory state machine 212 is a component that may perform an operation sequence according to a state machine. The scan memory state machine 212 may be activated in response to a signal 218 that, for example, software writes a value to a configuration register. The MBIST interface 204 may also include a multiplexer 214 that may select between the test path 210 and the signal from the scan memory state machine 212. Another multiplexer 216 can select between the functional path 208 and the output from the first multiplexer 214. Since the scan memory state machine is integrated with the test path 210, there is no additional timing impact on the functional path 208. In this way, the multiplexer 216 can select between the functional path 208 and either the signal from the test controller or the signal from the scan memory state machine 212.

[0015] When signal 218 is generated, scan memory state machine 212 may be activated. Scan memory state machine 212 may generate a signal to dump SRAM 206. Multiplexer 214 may select the signal from scan memory state machine 212, and multiplexer 216 may select the signal from scan memory state machine 212. SRAM 206 may receive the signal to dump its contents to scan memory state machine 212. Scan memory state machine 212 may include an N-bit register 220, where N is the width of the SRAM data bus. Scan memory state machine 212 may read the first address of SRAM 206, which is captured into N-bit register 220. Scan memory state machine 212 may perform a serial shift of N-bit register 220 to unload data, which will take N cycles since it is an N-bit register 220. After the N serial shifts of the N-bit register 220, the scan memory state machine 212 increments the address of the SRAM 206 by one, performs a read on the corresponding address, and updates the contents of the N-bit register 220 with the new data read from the SRAM 206. The N-bit register 220 can continue to unload data onto the output signal 226 at each clock cycle 222, and the output signal 226 can continue to unload data through the logical scan dump chain. When all addresses of the SRAM 206 have been read, the scan memory state machine 212 can output a completion signal 224. If there are additional SRAMs, the completion signal 224 can trigger, for example, the next scan memory state machine in the daisy chain.

[0016] Figure 3 A diagram of a logic scan dump chain 300 is shown. The logic scan dump chain 300 may receive the contents of an SRAM, for example, via an input signal 302. The logic scan dump chain 300 may also output the contents of the logic scan dump chain 300, for example, via an output signal 304 to an external storage device, such as an external DRAM. When the logic scan dump chain 300 receives a scan dump signal 306, the contents 308 of the logic scan dump chain 300 may be output, for example, using a JTAG interface accessible to an external debugger, or the contents of the logic scan dump chain 300 may be output, for example, via an on-chip DDR PHY (DFI) interface. Then, a debugging system or user may examine the contents of the logic scan dump chain 300. If the logic scan dump chain 300 includes the contents of an SRAM due to the process described above, the contents of the SRAM will also be available for examination by a debugging system or user. This allows visibility of the code and conditions stored in the SRAM. As described above, the SRAM and cache do not typically have visibility for debugging, and the code and conditions stored in the SRAM may help find the root cause of a software crash.

[0017] Figure 4A system on chip 400 is shown that allows the contents of embedded cache or RAM that normally does not have software visibility to be dumped so that these contents can be examined. The system 400 includes a plurality of functional components 200a, 200b, 200c, which may be configured, for example, according to Figure 2 The example functional component 200 of 200a is implemented. For example, each functional component includes a RAM wrapper, an MBIST interface, an SRAM, a scan memory state machine, etc. as described above. System 400 also includes a logic scan dump chain 300 as described above. When, for example, a value is written to a configuration register by software to generate a signal 218 to start a scan dump, the signal 218 can be forwarded to the first functional component 200a. The scan memory state machine of the first functional component 200a can be activated and a signal can be generated to dump the SRAM 206a of the first functional component 200a. The scan memory state machine can include an N-bit register as described above, and the serial shift of the N-bit register can be performed as described above to use an output signal 226a to unload data from the SRAM. When all the contents of the SRAM are read out, the scan memory state machine can output a completion signal 224a to, for example, trigger the next functional component 200b in a daisy chain.

[0018] Functional component 200b can receive completion signal 224a at the scan memory state machine of functional component 200b. The scan memory state machine of second functional component 200b can be activated and can generate signal to dump the SRAM 206b of second functional component 200b. The scan memory state machine can include N-bit register as described above, and can perform serial shift of N-bit register as described above to use output signal 226b to unload data from SRAM. When all contents of SRAM are read out, the scan memory state machine can output completion signal 224b to trigger next functional component 200c.

[0019] Functional component 200c can receive completion signal 224b at the scan memory state machine of functional component 200c. The scan memory state machine of the third functional component 200c can be activated and can generate a signal to dump the SRAM 206c of the third functional component 200c. The scan memory state machine can include an N-bit register as described above, and can perform a serial shift of the N-bit register as described above to use output signal 226c to unload data from the SRAM. When all contents of the SRAM are read out, the scan memory state machine can output completion signal 224c to, for example, trigger the next functional component. This process can be repeated for any number of functional components and SRAMs in the system.

[0020] For example, because each SRAM dump is triggered one by one, therefore logic scan dump chain 300 can receive the content of each SRAM 206a, 206b, 206c in serial order.When system 400 receives scan dump signal 306 and random access memory dump (ramdump) signal 218, the content of each SRAM 206a, 206b, 206c is loaded into logic scan dump chain 300, and logic scan dump chain 300 for example uses the JTAG interface that can utilize external debugger to visit or for example uses the external DRAM that adopts scan to DRAM (scan-to-DRAM) to visit to continue to unload its data.Then, debugging system or user can check the content of system 400.Because system 400 for example comprises the content of each SRAM due to the process described above, therefore the content of each SRAM will also be available for checking by debugging system or user.This allows the content of embedded RAM that does not usually have software visibility to be dumped, so that these contents can be checked.

[0021] Figure 5 is a flow chart of an example process 500 for dumping the contents of one or more embedded caches or RAMs during a scan dump. The example process may be performed by one or more components of a system on a chip. The example process will be described as being performed by, for example, Figure 2 The scan memory state machine 212 is executed, and the scan memory state machine is configured accordingly according to the present specification.

[0022] The scan memory state machine receives a signal to be activated (502). For example, the scan memory state machine may receive a signal similar to Figure 2 The signal 218 may be generated by software writing a value into a configuration register.

[0023] The scan memory state machine generates a signal to dump the SRAM (504). For example, the scan memory state machine may send the same signal as described above and be sent to Figure 2 The signals of the SRAM 206 are similar to the signals.

[0024] The scan memory state machine reads the first address of the SRAM (506). For example, this can be done by something like Figure 2 The N-bit register 220 is used to read the contents of the first address.

[0025] The scan memory state machine receives the SRAM contents (508) and outputs the contents in a serial manner to the logic scan dump chain (510). For example, as described above, the contents can be captured by an N-bit register and unloaded to the logic scan dump chain in a serial manner by serial shifting of the N-bit register.

[0026] The scan memory state machine reads the next address of the SRAM (512). Figure 2 As described, the content of the corresponding address of the SRAM can be read by an N-bit register and sent to the logic scan dump chain. For example, for every N shifts of the N-bit register, the address is incremented once, and for every N shifts of the N-bit register, a read is performed. The N-bit register sends the read data to the logic scan dump chain in each clock cycle so that the data is not lost. The serial shift of the N-bit register is a continuous process until the entire content of the SRAM is read.

[0027] If there are additional addresses in the SRAM, the scan state memory machine continues to output the contents of the SRAM (510) (branch to 508). This loop can be repeated until the scan state memory machine has read all addresses of the SRAM, such as reaching a pre-configured maximum address, and sent the contents to the logical scan dump chain via the N-bit register.

[0028] When all addresses of the SRAM are read, the scan memory state machine outputs a completion signal (514). For example, if there are additional SRAMs, the completion signal can trigger the next scan memory state machine in a daisy chain, for example.

[0029] Embodiments of the subject matter and functional operations described in this specification may be implemented in digital electronic circuitry, in tangibly embodied computer software or firmware, in computer hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of them.

[0030] Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or to control the operation of a data processing device. A computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or in addition, program instructions may be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode information for transmission to a suitable receiver device for execution by a data processing device.

[0031] The term "data processing equipment" refers to data processing hardware, and includes all kinds of equipment, devices and machines for processing data, including, for example, a programmable processor, a computer or a plurality of processors or computers. The equipment may also be or further include a dedicated logic circuit system, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, the equipment may also optionally include code for creating an execution environment for a computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0032] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0033] In addition to the above embodiments, the following embodiments are also innovative:

[0034] Embodiment 1 is a cache of a system on a chip having one or more embedded random access memories (RAMs), the cache comprising:

[0035] A scan memory state machine is configured to generate a signal for dumping contents of the one or more embedded RAMs during a scan dump process.

[0036] Embodiment 2 is the cache as described in embodiment 1, wherein the cache comprises a test controller configured to generate test signals separate from the functional path.

[0037] Embodiment 3 is the cache of embodiment 2, wherein the cache is configured to select between a signal from the test controller and a signal from the scan memory state machine.

[0038] Embodiment 4 is the cache of embodiment 3, wherein the cache further comprises a multiplexer configured to select between a functional path and a signal from the test controller or from the scan memory state machine.

[0039] Embodiment 5 is the cache of any one of embodiments 1 to 4, wherein the cache is configured to activate the scan memory state machine in response to software writing a value to a configuration register.

[0040] Embodiment 6 is the cache as described in any one of embodiments 1 to 5, wherein the cache has cache lines stored in the one or more embedded RAMs.

[0041] Embodiment 7 is the cache as described in any one of embodiments 1 to 6, wherein the cache is a translation lookaside buffer having translation entries stored in the one or more embedded RAMs.

[0042] Embodiment 8 is the cache as described in any one of embodiments 1 to 7, wherein the one or more embedded RAMs do not have scan inputs.

[0043] Embodiment 9 is the cache as described in any one of embodiments 1 to 8, wherein the one or more embedded RAMs are static RAMs.

[0044] Embodiment 10 is a method performed by a cache of a system on chip, the method comprising:

[0045] generating, by a scan memory state machine of the cache, a signal for dumping the contents of one or more embedded random access memories of the cache; and

[0046] Signals generated by the scan memory state machine are provided to the one or more embedded RAMs during a scan dump process.

[0047] Embodiment 11 is the method of embodiment 10, wherein the cache includes a test controller configured to generate test signals separate from the functional path.

[0048] Embodiment 12 is the method of embodiment 11, wherein the cache is configured to select between a signal from the test controller and a signal from the scan memory state machine.

[0049] Embodiment 13 is the method of embodiment 12, wherein the cache further comprises a multiplexer configured to select between a functional path and a signal from the test controller or from the scan memory state machine.

[0050] Embodiment 14 is the method of any one of embodiments 10 to 13, wherein the cache is configured to activate the scan memory state machine in response to software writing a value to a configuration register.

[0051] Embodiment 15 is the method of any one of embodiments 10 to 14, wherein the cache has cache lines stored in the one or more embedded RAMs.

[0052] Embodiment 16 is the method of any one of embodiments 10 to 15, wherein the cache is a translation lookaside buffer having translation entries stored in the one or more embedded RAMs.

[0053] Embodiment 17 is the method of any one of embodiments 10 to 16, wherein the one or more embedded RAMs do not have scan inputs.

[0054] Embodiment 18 is the method of any one of embodiments 10 to 17, wherein the one or more embedded RAMs are static RAMs.

[0055] Embodiment 19 is a functional component of a system on a chip having one or more embedded random access memories (RAMs), the functional component comprising:

[0056] A scan memory state machine is configured to generate signals for dumping contents of the one or more embedded RAMs during a scan dump process.

[0057] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but should be interpreted as descriptions of features that may be peculiar to a particular embodiment of a particular invention. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may involve a sub-combination or a variation of the sub-combination.

[0058] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0059] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions set forth in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing can be advantageous.

Claims

1. A cache memory of a system on chip having one or more embedded random access memories RAM, the cache memory comprising: A scan memory state machine is configured to generate a signal for dumping contents of the one or more embedded RAMs during a scan dump process. 2 . The cache of claim 1 , wherein the cache comprises a test controller configured to generate test signals separate from a functional path.

3. The cache of claim 2, wherein the cache is configured to select between a signal from the test controller and a signal from the scan memory state machine.

4. The cache of claim 3, wherein the cache further comprises a multiplexer configured to select between a functional path and a signal from the test controller or from the scan memory state machine.

5. The cache of any one of claims 1 to 4, wherein the cache is configured to activate the scan memory state machine in response to software writing a value to a configuration register.

6. The cache of any one of claims 1 to 5, wherein the cache has cache lines stored in the one or more embedded RAMs.

7. The cache of any one of claims 1 to 6, wherein the cache is a translation lookaside buffer having translation entries stored in the one or more embedded RAMs.

8. A cache as claimed in any one of claims 1 to 7, wherein the one or more embedded RAMs do not have a scan input.

9. The cache of any one of claims 1 to 8, wherein the one or more embedded RAMs are static RAMs.

10. A method performed by a cache of a system on chip, the method comprising: generating, by a scan memory state machine of the cache, a signal for dumping the contents of one or more embedded random access memories of the cache; as well as The generated signals are provided by the scan memory state machine to the one or more embedded RAMs during a scan dump process.

11. The method of claim 10, wherein the cache comprises a test controller configured to generate test signals separate from a functional path.

12. The method of claim 11, wherein the cache is configured to select between a signal from the test controller and a signal from the scan memory state machine.

13. The method of claim 12, wherein the cache further comprises a multiplexer configured to select between a functional path and a signal from the test controller or from the scan memory state machine.

14. The method of any one of claims 10 to 13, wherein the cache is configured to activate the scan memory state machine in response to software writing a value to a configuration register.

15. The method of any one of claims 10 to 14, wherein the cache has cache lines stored in the one or more embedded RAMs.

16. The method of any one of claims 10 to 15, wherein the cache is a translation lookaside buffer having translation entries stored in the one or more embedded RAMs.

17. The method of any one of claims 10 to 16, wherein the one or more embedded RAMs do not have a scan input.

18. The method of any one of claims 10 to 17, wherein the one or more embedded RAMs are static RAMs.

19. A functional component of a system on a chip having one or more embedded random access memories RAM, the functional component comprising: A scan memory state machine is configured to generate a signal for dumping contents of the one or more embedded RAMs during a scan dump process.

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