On-chip hybrid electromagnetic interference (EMI) shielding with thermal mitigation

Abstract

Techniques for on-chip electromagnetic interference (EMI) shielding are disclosed. In one aspect, an integrated circuit includes a noise-sensitive device, a first metallization layer disposed on a first side of the noise-sensitive device, where the first metallization layer includes a plurality of conductive wiring layers, and where the first metallization layer is disposed on a second side of the noise-sensitive device. The conductive wirings within the plurality of conductive wiring layers are configured as a first side of on-chip electromagnetic interference (EMI) shielding around a first side of the noise sensitive device; and a second metallization layer disposed on a second side of the noise-sensitive device opposite the first side of the noise-sensitive device, where the second metallization layer comprises one or more conductive wiring layers, and where the second metallization layer comprises one or more conductive wiring layers. The conductive wiring within the one or more conductive wiring layers is configured as a second side of on-chip EMI shielding around the second side of the noise sensitive device.

Description

Technical Field

[0001] Various aspects of the present disclosure relate generally to semiconductor manufacturing and, more particularly, to on-chip electromagnetic interference (EMI) shielding. Background Art

[0002] An integrated circuit (also called an "IC", "chip", "microchip", etc.) is a group of electronic circuits on a small piece of semiconductor material (usually silicon). Integrated circuits are now used in almost all electronic devices. Computers (e.g., desktop computers, laptop computers, tablet computers, etc.), mobile phones, and other household appliances all contain integrated circuits.

[0003] Integrated circuits that send and receive radio waves are called radio frequency integrated circuits (RFICs). RFICs can be found in portable phones, cell phones, Wi-Fi devices, Bluetooth devices, Global Positioning System (GPS) receivers, wireless routers, wireless base stations, satellite transceivers, and microwave equipment. For example, a modern smartphone includes one or more RFICs that handle cellular voice and data communications, GPS, Wi-Fi, and Bluetooth functions.

[0004] Integrated circuits utilize small voltages and currents that can be easily disturbed by electromagnetic fields. This electromagnetic interference (EMI) or radio frequency interference (RFI) is a problem for most integrated circuits, especially RFICs, because it can degrade the performance of the integrated circuits, or even cause them to fail. EMI shielding is a technique that creates a barrier that prevents the leakage of strong electromagnetic fields that could interfere with sensitive integrated circuits. They can be installed to isolate the source of electromagnetic fields, or as an enclosure on or around electronic equipment that needs protection. Summary of the invention

[0005] A simplified summary of one or more aspects disclosed herein is given below. Therefore, the following summary should not be considered as an extensive review of all covered aspects, nor should it be considered as identifying key or important elements related to all covered aspects or describing the scope associated with any particular aspect. Therefore, the sole purpose of the following summary is to present certain concepts related to one or more aspects of the mechanisms disclosed herein in a brief form before the detailed embodiments presented below.

[0006] In one aspect, an integrated circuit includes a noise sensitive device; a first metallization layer disposed on a first side of the noise sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield surrounding the first side of the noise sensitive device; and a second metallization layer disposed on a second side of the noise sensitive device opposite to the first side of the noise sensitive device, wherein the second metallization layer includes one or more conductive routing layers, wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip EMI shield surrounding the second side of the noise sensitive device, and wherein conductive routing within the one or more conductive routing layers is coupled to conductive routing within the plurality of conductive routing layers.

[0007] In one aspect, a method of manufacturing an integrated circuit includes: coupling a first metallization layer to a first side of a noise sensitive device, wherein the first metallization layer includes multiple conductive routing layers, and wherein conductive routing within the multiple conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield surrounding the first side of the noise sensitive device; and coupling a second metallization layer to a second side of the noise sensitive device opposite to the first side of the noise sensitive device, wherein the second metallization layer includes one or more conductive routing layers, wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip EMI shield surrounding the second side of the noise sensitive device, and wherein conductive routing within the one or more conductive routing layers is coupled to conductive routing within the multiple conductive routing layers.

[0008] Other objects and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art based on the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are presented to aid in describing various aspects of the present disclosure and are provided solely for purposes of illustration and not limitation of the various aspects.

[0010] Figure 1 A comparison of package-level and board-level electromagnetic interference (EMI) shielding is shown.

[0011] Figure 2 is a schematic diagram illustrating a side view of an example radio frequency integrated circuit (RFIC) with chip-level EMI shielding in accordance with various aspects of the present disclosure.

[0012] Figure 3 is a schematic diagram illustrating a top view and cross-section of an example on-chip EMI shield according to various aspects of the present disclosure.

[0013] Figure 4is a schematic diagram illustrating the difference between an RFIC utilizing conventional EMI shielding and an RFIC utilizing on-chip EMI shielding according to various aspects of the present disclosure.

[0014] Figure 5 is a schematic diagram illustrating a top view and cross-section of an example on-chip EMI shield according to various aspects of the present disclosure.

[0015] Figure 6 is a schematic diagram illustrating the difference between an RFIC utilizing traditional EMI shielding and an RFIC utilizing on-chip EMI shielding with double-sided metallization in accordance with various aspects of the present disclosure.

[0016] Figure 7 is another schematic diagram illustrating the difference between an RFIC utilizing traditional EMI shielding and an RFIC utilizing on-chip EMI shielding with double-sided metallization in accordance with various aspects of the present disclosure.

[0017] Figure 8 A cross section of an example integrated circuit according to various aspects of the present disclosure is shown.

[0018] Fig. 9 An example method of fabricating an integrated circuit according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0019] Various aspects of the present disclosure are provided in the following description and related drawings for various examples provided for illustrative purposes. Alternative aspects may be designed without departing from the scope of the present disclosure. In addition, well-known elements of the present disclosure will not be described in detail or will be omitted to avoid making the relevant details of the present disclosure difficult to understand.

[0020] The words "exemplary" and / or "example" are used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" and / or "example" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the disclosure" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation.

[0021] Those skilled in the art will appreciate that any of a variety of different techniques and methods may be used to represent the information and signals described below. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, which depends in part on the specific application, in part on the desired design, in part on the corresponding technology, and so on.

[0022] In addition, many aspects are described in terms of a sequence of actions to be performed by, for example, elements of a computing device. It will be appreciated that the various actions described herein may be performed by a specific circuit (e.g., an application specific integrated circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of the two. In addition, the sequence of actions described herein may be viewed as being fully embodied in any form of non-transitory computer-readable storage medium, in which a corresponding computer instruction set is stored, which, when executed, will cause or instruct the associated processor of the device to perform the functions described herein. Therefore, various aspects of the present disclosure may be embodied in a variety of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the various aspects described herein, the corresponding form of any such aspect may be described herein as, for example, "logic configured to perform the described actions."

[0023] Integrated circuits utilize small voltages and currents that can be easily disturbed by electromagnetic fields. This electromagnetic interference (EMI) or radio frequency interference (RFI) is a problem for most integrated circuits because it can degrade the performance of the integrated circuits, or even cause them to fail. EMI shielding is a technique that creates a barrier that prevents the leakage of strong electromagnetic fields, which can interfere with sensitive integrated circuits. They can be installed to isolate the source of electromagnetic fields, or as an enclosure on or around electronic equipment that needs protection.

[0024] Currently, EMI shielding is provided at the package level or the circuit board level. Figure 1 A comparison of package-level and board-level EMI shielding is shown. Specifically, schematic diagram 100 shows an example of package-level EMI shielding, and schematic diagram 150 shows an example of board-level EMI shielding.

[0025] There are problems with package-level and board-level EMI shielding. For example, noise-sensitive devices such as low-noise amplifiers (LNAs), power amplifiers (PAs), etc. integrated on radio frequency integrated circuits (RFICs) require EMI shielding from the external environment. Due to the radiation side lobes directly above the antenna, these devices cannot be adequately shielded from external EMI by package-level or board-level EMI shielding. Another example is that circulating currents on the module housing may cause spurious emissions that are not blocked by package-level or board-level EMI shielding. Another example is that, for example, if the LNA and PA share a common ground at the chip level, there may be noise coupling between the LNA and PA. Package-level or board-level EMI shielding cannot block this noise coupling.

[0026] Therefore, there is a need for EMI shielding at the chip level. This is not a process of record (POR) because EMI is not considered at the chip design stage.

[0027] Figure 2 2 is a schematic diagram 200 showing a side view of an example RFIC with chip-level EMI shielding according to various aspects of the present disclosure. Figure 2 As shown, patch antenna 210 is mounted to substrate 220. A patch antenna (such as patch antenna 210) is a low profile antenna that can be mounted on a surface. It consists of a thin, planar geometric (e.g., rectangular, circular, triangular, etc.) sheet of metal or "patch" mounted on a larger sheet of metal called a ground plane. The two sheets of metal together form a resonant patch of a microstrip transmission line, which is about half the wavelength of the radio waves that patch antenna 210 is designed to transmit / receive.

[0028] The patch antenna 210 is connected (coupled) to a first back-end-of-line (BEOL) layer 230 through one or more through-silicon vias (TSVs) 222. The BEOL is the second part of IC fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected through metal wiring (e.g., wires) on the substrate 220. The BEOL typically begins with the deposition of a first layer of metal (first wiring layer) on the substrate 220 and includes contacts, insulating layers (dielectrics), metal layers, and bonding locations for chip-to-package connections. In modern integrated circuits, BEOL layers (such as BEOL layers 230) may include more than 10 metal wiring layers separated by insulating layers (dielectric layers).

[0029] The first BEOL layer 230 is connected (coupled) to a second BEOL layer 235 via a hybrid bond (HB) layer 240. Connected (coupled) to the second BEOL layer 235 are two noise sensitive devices, shown as an LNA 250 and a PA 260. As will be understood, there may be more or less than the two noise sensitive devices shown, and the noise sensitive devices may be other types of devices other than the LNA 250 and PA 260 shown. Surrounding the LNA 250 is an on-chip EMI shield 252, and surrounding the PA 260 is an on-chip EMI shield 262, each represented as concentric dashed boxes. The on-chip EMI shields will be discussed in more detail below. The LNA 250 and the PA 260 are embedded in an interposer 270, and the entire RFIC is mounted on a heat sink 280. Note that the interposer 2709 may alternatively be another BEOL layer, as described below with reference to Figure 5 described.

[0030] like Figure 2As shown, the patch antenna 210 is mounted on a substrate 220 (layer silicon) directly above the noise sensitive circuits (e.g., LNA 250 and PA 260). The patch antenna 210 radiates an antenna beam having a main lobe 212 and multiple (e.g., two) side lobes (one of the side lobes is indicated by reference numeral 214). As shown by the arrows, the radiation from the main lobe 212 may be reflected away from one or more objects in the environment and reflected back to the LNA 250 and PA 260. The radiation from the side lobe 214 may be directed toward the LNA 250 and PA 260, as shown by the dashed arrows. The radiation from the main lobe 212 and the side lobe 214 may have severe EMI effects on the LNA 250, the PA 260, and / or other noise sensitive circuits. For example, the distance between the LNA 250 and the patch antenna 210 may be only about 500 microns (μm). For f=30 GHz, 500 μm is approximately 0.05·λ. However, as described further below, due to on-chip EMI shields 252 and 262 , the effects of such radiation are blocked or at least significantly reduced, as indicated by the “X” at the end of each arrow terminating in on-chip EMI shields 252 and 262 .

[0031] At a high level, the on-chip EMI shield 252 is a Faraday cage (a continuous mesh of conductive material) implemented by the BEOL routing layers in the second BEOL layer 235. The resulting metal mesh shield structure largely cancels out EMI reflected from the antenna side lobes 214 and main lobe 212. Shielding on multiple layers further suppresses EMI. In addition, an electrically grounded heat sink 280 suppresses eddy currents on the housing.

[0032] Figure 3 is a schematic diagram 300 illustrating a top view and cross-section of an example on-chip EMI shield according to various aspects of the present disclosure. Figure 3 The on-chip EMI shield shown utilizes front-side BEOL, back-side hybrid bonding and a thermal spreader. Figure 3 The circuit shown may be, for example, a complementary metal oxide semiconductor (CMOS).

[0033] like Figure 3 As shown, the antenna substrate 310 (eg, Figure 2 The patch antenna 210 and substrate 220 in FIG. 2 are mounted on the front side BEOL layer 320. The antenna substrate 310 can be separated from the front side BEOL layer 320 by a substrate (not shown), such as Figure 2 As shown in the RFIC. Figure 3In the example of FIG. 1 , the LNA is surrounded by a front side on-chip EMI shield 330 within the front side BEOL layer 320 and a back side on-chip EMI shield 340 within the interposer. The interposer is the electrical interface routing between one connection and another connection. The purpose of the interposer is to spread the connection to a wider pitch or to reroute the connection to a different connection.

[0034] The front side on-chip EMI shield 330 and the back side on-chip EMI shield 340 are composed of multiple metal (shielding) layers interspersed within the front side BEOL layer 320 and the interposer, respectively. The metal layers of the front side on-chip EMI shield 330 and the back side on-chip EMI shield 340 form stacked metal rings (shielding screens) that are staggered and offset at different levels (as shown in the top view) around the LNA to optimize shielding. Only a few metal layers (e.g., two or three layers) may be required for the front side on-chip EMI shield 330, and the remaining layers can be used for interconnections to or from the LNA (or other shielded components). Figure 3 In the example of FIG. 3 , only two metal layers (in addition to the ground plane) are used for the front side on-chip EMI shield 330. For simplicity, the underlying interconnect layers are not shown in cross section. The stacked metal layers improve EMI shielding by forming a Faraday cage around the LNA. Specifically, Figure 3 The on-chip EMI shielding shown can provide greater than 20 decibel (dB) EMI improvement over current technology.

[0035] like Figure 3 As shown, the first or top metal layer of the front side on-chip EMI shield 330 can be the ground plane of the front side on-chip EMI shield 330. Note that the term "ground plane" has two different meanings in different fields of electrical engineering. In terms of antennas, the ground plane is a conductive surface larger than the wavelength that is connected to the transmitter ground and acts as a reflective surface for radio waves (as described above with respect to Figure 2 In an integrated circuit, a ground plane is a large area of ​​conductive metal on a circuit that is connected (coupled) to the power ground and serves as a return path for current from different components on the circuit. A hybrid bond (HB) between the front side on-chip EMI shield 330 and the back side on-chip EMI shield 340 implements a second ground plane on the back side.

[0036] exist Figure 3In the example of FIG. 1 , an electrically grounded copper (Cu) heat spreader on the back side provides thermal relief and increased EMI shielding. The heat spreader has a large, flat surface that allows heat to be dissipated over a large surface. This surface is typically compressed against another large plane (e.g., a chassis or backplane), and the heat is transferred from the small heat spreader to the larger surface. Heat spreaders are often used in systems that require a low-profile solution or are expected to operate under extreme shock and vibration. The heat spreader also forms an electrical ground (ground plane) to minimize circulating currents in the enclosure. Note that although not shown, a heat sink could also be used even in the presence of a heat spreader, as a heat spreader is a more local, intermediate thermal reliever, while a heat sink is a more global thermal reliever.

[0037] There are considerations with aperture control (i.e., the size of the openings between wiring segments of the metal wiring of the BEOL wiring layer) relative to wavelength. For example, an optimal design may be less than about 0.01λ. However, the design may be tuned based on the application (e.g., frequency band). Additionally, the amount of shielding may depend on the sensitivity of the circuit being protected. For example, a PA may not require as much shielding as an LNA.

[0038] Figure 4 is a schematic diagram illustrating the difference between an RFIC 400 utilizing conventional EMI shielding and an RFIC 450 utilizing on-chip EMI shielding according to various aspects of the present disclosure. Figure 4 As shown, RFIC 400 consists of an antenna (e.g., a patch antenna) mounted on a back side redistribution layer (BSRDL). The redistribution layer (RDL) is a conductive metal interconnect that electrically connects one part of a semiconductor package to another part. TSV 410 connects the antenna to the LNA and PA through the substrate between the antenna and the LNA and PA. The LNA and PA are connected (coupled) to the BEOL layer, which in turn is connected (coupled) to a second BSRDL. The connection path between the LNA and the PA and the BSRDL is represented by the thick black lines / arrows. Surrounding the sides of the RFIC 400 is a conformal package level shield. As shown Figure 4 As shown, conformal package-level shielding does not block radiation from the antenna sidelobes.

[0039] Instead, the RFIC 450 consists of an antenna (e.g., a patch antenna) mounted to an RDL, which in turn is connected (coupled) to the BEOL layers. The LNA and PA are connected (coupled) to the BEOL layers, and the chip-level EMI shielding within the BEOL layers forms part of the RFIC 450 on-chip EMI shielding, as described above with reference to Figure 3 The TSV 460 passes through the substrate between the BSRDL and the LNA, and the PA connects the LNA and the PA to the BSRDL. The BSRDL is connected (coupled) to the interposer via a hybrid bond. Figure 3 As discussed, the metallization in the interposer forms the remainder of the on-chip EMI shield. The interposer is then connected (coupled) to a (e.g., copper) heat spreader. The connection path between the LNA and the PA through the BSRDL and the heat spreader is indicated by the thick black line / arrow. Figure 4 As shown, the on-chip EMI shield blocks (as indicated by the "X") radiation from the antenna side lobes.

[0040] The following table summarizes the differences between an RFIC utilizing conventional EMI shielding (eg, RFIC 400) and an RFIC utilizing on-chip EMI shielding (eg, RFIC 450).

[0041]

[0042]

[0043] Table 1

[0044] Figure 5 5 is a schematic diagram 500 showing a top view and cross-section of an example on-chip EMI shield according to various aspects of the present disclosure. Figure 3 In contrast to the on-chip EMI shielding shown, Figure 5 The on-chip EMI shield shown utilizes double-sided metallization (back-side contacts). For example, Figure 5 The circuit shown may be CMOS.

[0045] exist Figure 5 In the example of , the LNA is surrounded by a front-side on-chip EMI shield 510 within the front-side BEOL layers and a back-side on-chip EMI shield 520 within the back-side BEOL layers. The front-side on-chip EMI shield 510 and the back-side on-chip EMI shield 520 are composed of multiple metal (shielding) layers, which are dispersed in the front-side BEOL layers and the back-side BEOL layers, respectively. The metal layers of the front-side on-chip EMI shield 510 and the back-side on-chip EMI shield 520 form stacked metal rings (shielding screens) around the LNA that are staggered and offset at different levels (as shown in the top view) to optimize shielding. Only a few metal layers (for example, two or three layers) may be required for the front-side on-chip EMI shield 510, and the remaining layers can be used for interconnections to or from the LNA (or other shielded components). In Figure 5 In the example of FIG. 5 , only two metal layers (in addition to the ground plane) are used for the front side on-chip EMI shield 510. For simplicity, the underlying interconnect layers are not shown in cross section. The stacked metal layers improve EMI shielding by forming a Faraday cage around the LNA. Specifically, Figure 5 The on-chip EMI shielding shown can provide greater than 20 decibel (dB) EMI improvement over current technology.

[0046] like Figure 5 As shown, the first layer or top metal layer of the front side on-chip EMI shield 510 and the back side on-chip EMI shield 520 can be the ground plane of the front side on-chip EMI shield 510 and the back side on-chip EMI shield 520, respectively. The buried oxide (BOX) between the front side on-chip EMI shield 510 and the back side on-chip EMI shield 520 (which separates the top thin device silicon from the silicon substrate of the silicon on insulator (SOI) wafer) enables the presence of a second ground plane on the back side.

[0047] There are considerations regarding aperture control vs. wavelength. For example, an optimal design may be less than about 0.01λ. However, the design may be tuned based on the application (e.g., frequency band). Additionally, the amount of shielding may depend on the sensitivity of the circuit being protected. For example, a PA may not require as much shielding as an LNA.

[0048] Figure 6 is a schematic diagram illustrating the difference between an RFIC 600 utilizing conventional EMI shielding and an RFIC 650 utilizing on-chip EMI shielding with double-sided metallization according to aspects of the present disclosure. Figure 6 As shown, RFIC 600 consists of an antenna substrate (e.g., a patch antenna, abbreviated as "Ant.Sub." in the figure) mounted on top of the LNA and PA. Surrounding the sides of RFIC 600 is a conformal package-level shield. Figure 6 As shown, the conformal package-level shielding layer blocks radiation reflected from the main lobe antenna beam (indicated by an "X"), but does not block radiation from the antenna side lobes.

[0049] In contrast, the LNA of RFIC 650 is shielded by chip-level EMI shielding (represented as dashed rounded boxes) within the front-side and back-side BEOL layers, as described above with reference to Figure 5 As stated. Figure 6 As shown, the on-chip EMI shield blocks radiation from both the main lobe of the antenna and the side lobes of the antenna (indicated by an "X"). The on-chip EMI shield eliminates the need for conformal package-level shielding.

[0050] Figure 7 is another schematic diagram illustrating the difference between an RFIC 700 utilizing conventional EMI shielding and an RFIC 750 utilizing on-chip EMI shielding with double-sided metallization according to various aspects of the present disclosure. Figure 7 As shown, RFIC 700 includes an antenna (e.g., a patch antenna) and an antenna substrate mounted on the LNA and PA. Surrounding the sides of RFIC 700 is a conformal package-level shield. Figure 7 As shown, conformal package-level shielding does not block radiation from the antenna sidelobes.

[0051] In contrast, the LNA of RFIC 750 is shielded by chip-level EMI shielding (indicated by dashed boxes) within the front-side and back-side BEOL layers, as described above with reference to Figure 5 As stated. Figure 7 As shown, on-chip EMI shielding blocks radiation from the antenna side lobes. On-chip EMI shielding eliminates the need for conformal package-level shielding.

[0052] The following table summarizes the differences between RFICs that utilize traditional EMI shielding (eg, RFIC 600, RFIC 700) and RFICs that utilize on-chip EMI shielding with double-sided metallization (eg, RFIC 650, RFIC 750).

[0053]

[0054] Table 2

[0055] As will be appreciated, while the above on-chip EMI shielding example illustrates only a shielded LNA, as will be appreciated, a PA may also or alternatively be shielded by an on-chip EMI shield. Furthermore, while the above examples illustrate an LNA and a PA, the techniques described herein are equally applicable to other noise sensitive devices. Similarly, while the above examples illustrate an LNA and a PA, the two devices may be a single device, more than two devices, two LNAs, two PAs, etc.

[0056] As will be appreciated, on-chip EMI shielding can be used in scenarios other than protecting noise-sensitive devices from collocated antenna interference. Rather, on-chip EMI shielding can be used in any situation where noise-sensitive devices need to be shielded from EMI, regardless of the source of the EMI.

[0057] Furthermore, it is obvious to one of ordinary skill in the art that the above-described on-chip EMI shielding example may not include every component of the RFIC. Rather, certain components may be omitted for clarity.

[0058] According to various aspects of the present disclosure, Figure 8 A cross section of an example integrated circuit 800 is shown. The integrated circuit 800 also includes a noise sensitive device 810, such as an LNA or a PA. The integrated circuit 800 also includes a first metallization layer 820 (e.g., a front-side BEOL layer) disposed on a first side (e.g., a top side) of the noise sensitive device 810, wherein the first metallization layer 820 includes a plurality of conductive routing layers 822, and wherein conductive routing 824 in the plurality of conductive routing layers 822 is configured as a first side of an on-chip EMI shield surrounding the first side of the noise sensitive device 810.

[0059] The integrated circuit 800 also includes a second metallization layer 830 (e.g., a backside BEOL layer or an interposer) disposed on a second side (e.g., a bottom side) of the noise sensitive device 810 opposite the first side of the noise sensitive device 810, wherein the second metallization layer 830 includes one or more conductive wiring layers 832, wherein conductive wiring 834 within the one or more conductive wiring layers 832 is configured as a second side of an on-chip EMI shield surrounding the second side of the noise sensitive device 810, and wherein the conductive wiring 834 within the one or more conductive wiring layers 832 is coupled to the conductive wiring 824 within the plurality of conductive wiring layers 822 (e.g., via backside contacts).

[0060] In one aspect, one of the plurality of conductive routing layers 822 farthest from the noise-sensitive device 810 is configured as a first ground plane for a first side of an on-chip EMI shield, and one of the one or more conductive routing layers 832 farthest from the noise-sensitive device 810 is configured as a second ground plane for a second side of the on-chip EMI shield.

[0061] In one aspect, the conductive routing 824 within each of the plurality of conductive routing layers 822 is configured as a conductive mesh, and the conductive routing 834 within each of the plurality of conductive routing layers 832 is configured as a conductive mesh.

[0062] In one aspect, the conductive wiring 824 within each of the plurality of conductive wiring layers 822 is offset from a consecutive layer of the plurality of conductive wiring layers 822 , and the conductive wiring 834 within each of the one or more conductive wiring layers 832 is offset from a consecutive layer of the plurality of conductive wiring layers 832 .

[0063] In one aspect, the integrated circuit 800 optionally includes a radio frequency (RF) antenna 840 disposed on a side of the first metallization layer 820 opposite the second metallization layer 830 .

[0064] In one aspect, the integrated circuit 800 optionally includes a heat spreader 850 coupled to the second metallization layer 830 or a heat sink 860 coupled to the second metallization layer 830 .

[0065] exist Figure 8 In the example of FIG. 8 , the spaces between various blocks such as the first metallization layer 820 and the second metallization layer 830 indicate that other layers or components may be present between the layers shown. For example, a hybrid bond, a substrate, a BSRDL, etc. may be present between the first metallization layer 820 and the second metallization layer 830. Similarly, as another example, a substrate may be present between the optional RF antenna 840 and the first metallization layer 820.

[0066] Fig. 9An example method 900 for manufacturing an integrated circuit is shown according to various aspects of the present disclosure. The method 900 can be performed by various manufacturing machines known in the art. The method 900 can also be stored as instructions on a (non-transitory) computer-readable medium, where various manufacturing machines execute the stored instructions to perform the method 900.

[0067] Operation 910 of method 900 includes connecting a first metallization layer (e.g., first metallization layer 820) to a first side of a noise sensitive device (e.g., noise sensitive device 810), wherein the first metallization layer includes a plurality of conductive routing layers (e.g., conductive routing layer 822), and wherein conductive routing (e.g., conductive routing 824) within the plurality of conductive routing layers is configured as a first side of an on-chip EMI shield surrounding the first side of the noise sensitive device.

[0068] Operation 920 of method 900 includes connecting a second metallization layer (e.g., second metallization layer 830) to a second side of the noise sensitive device opposite the first side of the noise sensitive device, wherein the second metallization layer includes one or more conductive routing layers (e.g., conductive routing layer 832), wherein conductive routing within the one or more conductive routing layers (e.g., conductive routing 834) is configured as a second side of an on-chip EMI shield surrounding the second side of the noise sensitive device, and wherein the conductive routing within the one or more conductive routing layers is coupled to conductive routing within the plurality of conductive routing layers.

[0069] In the detailed description above, it can be seen that different features are grouped together in each example. This disclosure should not be understood as an intention that the example clauses have more features than the features explicitly mentioned in each clause. Specifically, various aspects of the present disclosure may include less than all the features of the disclosed single example clauses. Therefore, the following clauses should be deemed to be included in the specification accordingly, wherein each clause can be individually used as a separate example. Although each dependent clause can refer to a specific combination with one of the other clauses in the clause, the aspects of the dependent clause are not limited to a specific combination. It will be understood that other example clauses may also include a combination of the subject matter of the dependent clause aspect with any other dependent clause or independent clause, or any feature with other dependent and independent clauses. Various aspects disclosed herein explicitly include these combinations, unless it is explicitly expressed or it can be easily inferred that a specific combination is not expected (for example, contradictory aspects, such as defining an element as an electrical insulator and an electrical conductor). In addition, it is also expected that various aspects of the clause may be included in any other independent clause, even if the clause is not directly dependent on the independent clause.

[0070] Examples of implementations are described in the following numbered clauses:

[0071] Item 1. An integrated circuit comprising: a noise sensitive device; a first metallization layer disposed on a first side of the noise sensitive device, wherein the first metallization layer includes a plurality of conductive wiring layers, and wherein conductive wiring within the plurality of conductive wiring layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield surrounding the first side of the noise sensitive device; and a second metallization layer disposed on a second side of the noise sensitive device opposite to the first side of the noise sensitive device, wherein the second metallization layer includes one or more conductive wiring layers, wherein conductive wiring within the one or more conductive wiring layers is configured as a second side of an on-chip EMI shield surrounding the second side of the noise sensitive device, and wherein the conductive wiring within the one or more conductive wiring layers is coupled to the conductive wiring within the plurality of conductive wiring layers.

[0072] Item 2. An integrated circuit according to Item 1, wherein: one of the multiple conductive wiring layers that is farthest from the noise-sensitive device is configured as a first ground plane for the first side of the on-chip EMI shielding, and one of the one or more conductive wiring layers that is farthest from the noise-sensitive device is configured as a second ground plane for the second side of the on-chip EMI shielding.

[0073] Clause 3. An integrated circuit according to any one of clauses 1 to 2, wherein the conductive wiring within the multiple conductive wiring layers includes: a first layer of the multiple conductive wiring layers is configured as a ground plane for the first side of the on-chip EMI shielding, and conductive wiring within an intermediate layer of the multiple conductive wiring layers between the first layer and the first side of the noise-sensitive device are interconnected to each other and to the ground plane.

[0074] Clause 4. An integrated circuit according to any one of clauses 1 to 3, wherein: the conductive wiring within each of the multiple conductive wiring layers is configured as a conductive grid, and the conductive wiring within each of the one or more conductive wiring layers is configured as a conductive grid.

[0075] Item 5. An integrated circuit according to any one of items 1 to 4, wherein: the conductive wiring within each of the multiple conductive wiring layers is offset from a continuous layer in the multiple conductive wiring layers, and the conductive wiring within each of the one or more conductive wiring layers is offset from a continuous layer in the one or more conductive wiring layers.

[0076] Clause 6. The integrated circuit of any one of clauses 1 to 5, wherein the first metallization layer comprises a front-side back-end-of-line (BEOL) layer.

[0077] Clause 7. The integrated circuit of any one of clauses 1 to 6, wherein: the second metallization layer comprises a backside BEOL layer, and the one or more conductive wiring layers comprises a second plurality of conductive wiring layers.

[0078] Item 8. An integrated circuit according to Item 7, wherein the conductive wiring within the second plurality of conductive wiring layers includes: a first layer of the second plurality of conductive wiring layers is configured as a ground plane for the second side of the on-chip EMI shielding, and the conductive wiring within the middle layer of the second plurality of conductive wiring layers between the first layer and the second side of the noise-sensitive device are interconnected to each other and to the ground plane.

[0079] Clause 9. The integrated circuit of any one of clauses 1 to 6, wherein the second metallization layer comprises an interposer.

[0080] Clause 10. The integrated circuit of clause 9, further comprising: a hybrid bond between the first metallization layer and the interposer.

[0081] Clause 11. The integrated circuit of any one of clauses 9 to 10, further comprising: a heat spreader coupled to the interposer, or a heat sink coupled to the interposer.

[0082] Clause 12. The integrated circuit of any one of clauses 1 to 11, further comprising: a radio frequency (RF) antenna disposed on a side of the first metallization layer opposite to the second metallization layer.

[0083] Item 13. An integrated circuit according to Item 12, wherein: the conductive wiring within the multiple conductive wiring layers includes a first plurality of conductive segments, the conductive wiring within the one or more conductive wiring layers includes a second plurality of conductive segments, and the spacing size between the first plurality of conductive segments and the second plurality of conductive segments is based on the wavelength of the frequency band in which the RF antenna operates.

[0084] Clause 14. The integrated circuit of any one of clauses 12 to 13, further comprising: a substrate between the RF antenna and the first metallization layer; and one or more through-silicon vias (TSVs) connecting the RF antenna to the first metallization layer.

[0085] Clause 15. The integrated circuit of any one of clauses 1 to 14, wherein the noise sensitive device comprises a low noise amplifier or a power amplifier.

[0086] Clause 16. An integrated circuit according to any one of clauses 1 to 15, further comprising: a second noise-sensitive device, wherein the conductive routing within the multiple conductive routing layers is also configured as a first side of a second on-chip EMI shield surrounding a first side of the second noise-sensitive device, and wherein the conductive routing within the one or more conductive routing layers is also configured as a second side of the second on-chip EMI shield surrounding a second side of the second noise-sensitive device.

[0087] Item 17. A method of manufacturing an integrated circuit, comprising: coupling a first metallization layer to a first side of a noise sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield surrounding the first side of the noise sensitive device; and coupling a second metallization layer to a second side of the noise sensitive device opposite to the first side of the noise sensitive device, wherein the second metallization layer includes one or more conductive routing layers, wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip EMI shield surrounding the second side of the noise sensitive device, and wherein the conductive routing within the one or more conductive routing layers is coupled to the conductive routing within the plurality of conductive routing layers.

[0088] Item 18. A method according to Item 17, wherein: one of the multiple conductive wiring layers that is farthest from the noise-sensitive device is configured as a first ground plane for the first side of the on-chip EMI shield, and one of the one or more conductive wiring layers that is farthest from the noise-sensitive device is configured as a second ground plane for the second side of the on-chip EMI shield.

[0089] Clause 19. A method according to any one of clauses 17 to 18, wherein the conductive wiring within the multiple conductive wiring layers includes: a first layer of the multiple conductive wiring layers is configured as a ground plane for the first side of the on-chip EMI shielding, and conductive wiring within an intermediate layer of the multiple conductive wiring layers between the first layer and the first side of the noise-sensitive device are interconnected to each other and to the ground plane.

[0090] Clause 20. A method according to any one of clauses 17 to 19, wherein: the conductive wiring within each of the multiple conductive wiring layers is configured as a conductive grid, and the conductive wiring within each of the one or more conductive wiring layers is configured as a conductive grid.

[0091] Clause 21. A method according to any one of clauses 17 to 20, wherein: the conductive wiring within each of the multiple conductive wiring layers is offset from a continuous layer in the multiple conductive wiring layers, and the conductive wiring within each of the one or more conductive wiring layers is offset from a continuous layer in the one or more conductive wiring layers.

[0092] Clause 22. The method of any one of clauses 17 to 21, wherein the first metallization layer comprises a front side back end of line (BEOL) layer.

[0093] Clause 23. The method of any one of clauses 17 to 22, wherein: the second metallization layer comprises a backside BEOL layer, and the one or more conductive wiring layers comprises a second plurality of conductive wiring layers.

[0094] Item 24. A method according to Item 23, wherein the conductive wiring within the second plurality of conductive wiring layers includes: a first layer of the second plurality of conductive wiring layers is configured as a ground plane for the second side of the on-chip EMI shielding, and the conductive wiring within an intermediate layer of the second plurality of conductive wiring layers between the first layer and the second side of the noise-sensitive device are interconnected to each other and to the ground plane.

[0095] Clause 25. The method of any one of clauses 17 to 22, wherein the second metallization layer comprises an interposer.

[0096] Clause 26. The method of clause 25, further comprising: applying a hybrid bond between the first metallization layer and the interposer.

[0097] Clause 27. The method of any of clauses 25 to 26, further comprising: coupling a heat spreader to the interposer; or coupling a heat sink to the interposer.

[0098] Clause 28. The method of any of clauses 17 to 27, further comprising coupling a radio frequency (RF) antenna to a side of the first metallization layer opposite the second metallization layer.

[0099] Item 29. A method according to Item 28, wherein: the conductive wiring within the multiple conductive wiring layers includes a first plurality of conductive segments, the conductive wiring within the one or more conductive wiring layers includes a second plurality of conductive segments, and the spacing between the first plurality of conductive segments and the second plurality of conductive segments is based on the wavelength of the frequency band in which the RF antenna operates.

[0100] Clause 30. The method of any one of clauses 28 to 29, further comprising: providing a substrate between the RF antenna and the first metallization layer; and providing one or more through-silicon vias (TSVs) connecting the RF antenna to the first metallization layer.

[0101] Clause 31. A method as described in any one of clauses 17 to 30, wherein the noise-sensitive device comprises: a low noise amplifier, or a power amplifier.

[0102] Clause 32. The method of any one of clauses 17 to 31, further comprising: coupling a second noise-sensitive device to the first metallization layer and the second metallization layer, wherein the conductive routing within the plurality of conductive routing layers is further configured as a first side of a second on-chip EMI shield surrounding a first side of the second noise-sensitive device, and wherein the conductive routing within the one or more conductive routing layers is further configured as a second side of the second on-chip EMI shield surrounding a second side of the second noise-sensitive device.

[0103] It will be appreciated by those skilled in the art that information and signals may be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0104] In addition, it will be appreciated by those skilled in the art that the various illustrative logical blocks, modules, circuits and algorithmic steps described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits and steps have been roughly described in terms of their functionality. Whether this functionality is implemented as hardware or software depends on specific application and the design constraints proposed to the entire system. Those skilled in the art can implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of the present disclosure.

[0105] The various illustrative logic blocks, modules and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed using a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in an alternative manner, the processor may be any conventional processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors and a DSP core, or any other such configuration.

[0106] The methods, sequences and / or algorithms described in conjunction with the various aspects disclosed herein may be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a random access memory (RAM), a flash memory, a read-only memory (ROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An example storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated with the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., UE). Alternatively, the processor and the storage medium may reside in a user terminal as discrete components.

[0107] In one or more example aspects, the function can be implemented with hardware, software, firmware or any combination thereof. If implemented with software, the function can be stored on a computer-readable medium or transmitted by a computer-readable medium as one or more instructions or codes. Computer-readable media includes both computer storage media and communication media, and communication media includes any medium that promotes the transmission of a computer program from one place to another. Storage media can be any available medium that can be accessed by a computer. Exemplarily and not restrictively, this computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage device, or can be used to carry or store the desired program code in the form of an instruction or data structure and any other medium that can be accessed by a computer. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if the software is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then coaxial cable, optical fiber cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of the medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, wherein disks usually reproduce data magnetically, while discs reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0108] Although the foregoing disclosure shows the illustrative aspects of the present disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims. In addition, the functions, steps and / or actions of the method claims according to the various aspects of the disclosure described herein do not need to be performed in any particular order. In addition, although the elements of the present disclosure may be described or claimed in the singular, the plural form is conceivable unless it is explicitly stated to be limited to the singular.

Claims

1. An integrated circuit, comprising: Noise sensitive equipment; a first metallization layer disposed on a first side of the noise-sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield surrounding the first side of the noise-sensitive device; and a second metallization layer disposed on a second side of the noise-sensitive device opposite to the first side of the noise-sensitive device, wherein the second metallization layer includes one or more conductive routing layers, wherein conductive routing within the one or more conductive routing layers is configured as a second side of an on-chip EMI shield surrounding the second side of the noise-sensitive device, and wherein the conductive routing within the one or more conductive routing layers is coupled to the conductive routing within the plurality of conductive routing layers.

2. The integrated circuit of claim 1 , wherein: A layer of the plurality of conductive routing layers that is farthest from the noise sensitive device is configured as a first ground plane for the first side of the on-chip EMI shield, and One of the one or more conductive routing layers that is farthest from the noise sensitive device is configured as a second ground plane for the second side of the on-chip EMI shield.

3. The integrated circuit according to claim 1, wherein: The conductive wirings within the plurality of conductive wiring layers include: a first layer of the plurality of conductive routing layers is configured as a ground plane for the first side of the on-chip EMI shield, and Conductive wirings in an intermediate layer of the plurality of conductive wiring layers between the first layer and the first side of the noise sensitive device are interconnected with each other and with the ground plane.

4. The integrated circuit of claim 1, wherein: The conductive wiring within each of the plurality of conductive wiring layers is configured as a conductive grid, and The conductive wiring within each of the one or more conductive wiring layers is configured as a conductive grid.

5. The integrated circuit of claim 1 , wherein: The conductive routing within each of the plurality of conductive routing layers is offset from a consecutive layer of the plurality of conductive routing layers, and The conductive routing within each of the one or more conductive routing layers is offset from consecutive layers of the one or more conductive routing layers.

6. The integrated circuit of claim 1, wherein: The first metallization layer includes a front side back end of line (BEOL) layer.

7. The integrated circuit of claim 1, wherein: The second metallization layer includes a backside BEOL layer, and The one or more conductive wiring layers include a second plurality of conductive wiring layers.

8. The integrated circuit according to claim 7, wherein: The conductive wirings in the second plurality of conductive wiring layers include: A first layer of the second plurality of conductive routing layers is configured as a ground plane for the second side of the on-chip EMI shield, and The conductive routing of the second plurality of conductive routing layers in an intermediate layer between the first layer and the second side of the noise sensitive device are interconnected with each other and with the ground plane.

9. The integrated circuit of claim 1, wherein: The second metallization layer includes an interposer.

10. The integrated circuit of claim 9, further comprising: A hybrid bond between the first metallization layer and the interposer.

11. The integrated circuit of claim 9, further comprising: a heat spreader coupled to the interposer, or A heat sink is coupled to the interposer.

12. The integrated circuit of claim 1 , further comprising: A radio frequency (RF) antenna is disposed on a side of the first metallization layer opposite the second metallization layer.

13. The integrated circuit of claim 12, wherein: The conductive routing within the plurality of conductive routing layers comprises a first plurality of conductive segments, The conductive routing within the one or more conductive routing layers comprises a second plurality of conductive segments, and The spacing size between the first plurality of conductive segments and the second plurality of conductive segments is based on the wavelength of a frequency band in which the RF antenna operates.

14. The integrated circuit of claim 12, further comprising: a substrate between the RF antenna and the first metallization layer; as well as The RF antenna is connected to one or more through silicon vias (TSVs) of the first metallization layer.

15. The integrated circuit of claim 1, wherein: The noise sensitive device comprises: Low noise amplifier, or Power amplifier.

16. The integrated circuit of claim 1, further comprising: The second noise sensitive device, wherein the conductive routing within the plurality of conductive routing layers is further configured as a first side of a second on-chip EMI shield surrounding a first side of the second noise sensitive device, and Wherein the conductive routing within the one or more conductive routing layers is further configured as a second side of the second on-chip EMI shield surrounding a second side of the second noise sensitive device.

17. A method of manufacturing an integrated circuit, comprising: coupling a first metallization layer to a first side of a noise sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield surrounding the first side of the noise sensitive device; and A second metallization layer is coupled to a second side of the noise sensitive device opposite the first side of the noise sensitive device, wherein the second metallization layer includes one or more conductive routing layers, wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip EMI shield surrounding the second side of the noise sensitive device, and wherein the conductive routing within the one or more conductive routing layers is coupled to the conductive routing within the plurality of conductive routing layers.

18. The method of claim 17, wherein: A layer of the plurality of conductive routing layers that is farthest from the noise sensitive device is configured as a first ground plane for the first side of the on-chip EMI shield, and One of the one or more conductive routing layers that is farthest from the noise sensitive device is configured as a second ground plane for the second side of the on-chip EMI shield.

19. The method according to claim 17, wherein: The conductive wirings within the plurality of conductive wiring layers include: a first layer of the plurality of conductive routing layers is configured as a ground plane for the first side of the on-chip EMI shield, and Conductive wirings in an intermediate layer of the plurality of conductive wiring layers between the first layer and the first side of the noise sensitive device are interconnected with each other and with the ground plane.

20. The method of claim 17, wherein: The conductive wiring within each of the plurality of conductive wiring layers is configured as a conductive grid, and The conductive wiring within each of the one or more conductive wiring layers is configured as a conductive grid.

21. The method of claim 17, wherein: The conductive routing within each of the plurality of conductive routing layers is offset from a consecutive layer of the plurality of conductive routing layers, and The conductive routing within each of the one or more conductive routing layers is offset from consecutive layers of the one or more conductive routing layers.

22. The method according to claim 17, wherein: The first metallization layer includes a front side back end of line (BEOL) layer.

23. The method of claim 17, wherein: The second metallization layer includes a backside BEOL layer, and The one or more conductive wiring layers include a second plurality of conductive wiring layers.

24. The method according to claim 23, wherein: The conductive wirings in the second plurality of conductive wiring layers include: A first layer of the second plurality of conductive routing layers is configured as a ground plane for the second side of the on-chip EMI shield, and The conductive routing of the second plurality of conductive routing layers in an intermediate layer between the first layer and the second side of the noise sensitive device are interconnected with each other and with the ground plane.

25. The method of claim 17, wherein: The second metallization layer includes an interposer.

26. The method according to claim 25, further comprising: A hybrid bond is applied between the first metallization layer and the interposer.

27. The method of claim 25, further comprising: A heat spreader is coupled to the interposer; or a heat sink is coupled to the interposer.

28. The method of claim 17, further comprising: A radio frequency (RF) antenna is coupled to a side of the first metallization layer opposite the second metallization layer.

29. The method of claim 28, wherein: The conductive routing within the plurality of conductive routing layers comprises a first plurality of conductive segments, The conductive routing within the one or more conductive routing layers comprises a second plurality of conductive segments, and The spacing size between the first plurality of conductive segments and the second plurality of conductive segments is based on the wavelength of a frequency band in which the RF antenna operates.

30. The method of claim 28, further comprising: providing a substrate between the RF antenna and the first metallization layer; and One or more through silicon vias (TSVs) are provided connecting the RF antenna to the first metallization layer.

31. The method of claim 17, wherein: The noise sensitive device comprises: Low noise amplifier, or Power amplifier.

32. The method of claim 17, further comprising: coupling a second noise sensitive device to the first metallization layer and the second metallization layer, wherein the conductive routing within the plurality of conductive routing layers is further configured as a first side of a second on-chip EMI shield surrounding a first side of the second noise sensitive device, and Wherein the conductive routing within the one or more conductive routing layers is further configured as a second side of the second on-chip EMI shield surrounding a second side of the second noise sensitive device.

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