Processing device and related low-power-consumption standby control method

Abstract

The invention discloses a processing device and a related low-power-consumption standby control method, and the processing device is characterized in that the processing device comprises a power management unit, a chip system and an internal memory, and the power management unit supplies power to the chip system through a first power domain and supplies power to the internal memory through a second power domain; the power management unit is used for receiving a first instruction sent by the chip system, and the first instruction is used for instructing the processing device to enter a standby state; controlling to disconnect the first power domain, and keeping part or all of the power supply of the second power domain in a power supply state; after the processing device enters the standby state, the chip system is in a power-off state, and part or all devices of the internal memory are in a power-on state; and a first control signal is sent to the internal memory, the first control signal is used for maintaining the internal memory in a first mode, and the internal memory stores the currently stored data in the first mode. By adopting the embodiment of the invention, the standby power consumption can be reduced, the standby time is prolonged, and the user experience is improved.

Description

A processing device and related low-power standby control method Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a processing device and a related low-power standby control method. Background Art

[0002] Under the condition of limited battery capacity, when terminal devices such as smartphones or smart watches are in standby mode, that is, the terminal devices are turned on but not performing any substantial work (i.e., not operating files and programs), in order to obtain longer standby time, the required standby power consumption is also getting lower and lower.

[0003] When existing terminal devices are in standby mode, considering that the time it takes for the terminal device to recover from standby mode to normal working mode should not be too long, it is necessary to reserve at least one low-voltage always-on (AO) power domain and a high-voltage interface power domain for the terminal device's system on chip (SoC) to ensure that some data or configurations are retained in standby mode, thereby reducing power-on recovery time. In this scenario, the standby power consumption of the terminal device mainly includes the SoC standby power consumption, and also includes other power consumption such as memory, power management unit, and board level. However, in actual application, it is found that when the terminal device enters the standby mode, the SoC standby power consumption is high and the maximum proportion of the SoC standby power consumption can reach more than half of the total power consumption, which greatly shortens the standby time of the terminal device.

[0004] Therefore, how to provide a processing device and a related low-power standby control method to reduce standby power consumption, increase standby time, and improve user experience is an urgent problem to be solved.

[0005] Summary of the Invention

[0006] The embodiments of the present invention provide a processing device and a related low-power standby control method to reduce standby power consumption, increase standby time, and improve user experience.

[0007] In a first aspect, an embodiment of the present invention provides a processing device, characterized in that the processing device includes a power management unit, a system on chip (SoC) and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit, and the power management unit supplies power to the SoC through a first power domain and supplies power to the internal memory through a second power domain; the power management unit is used to: receive a first indication sent by the SoC, wherein the first indication is used to instruct the processing device to enter a standby state; control the disconnection of the first power domain, and keep part or all of the power of the second power domain in a powered state; wherein, after the processing device enters the standby state, the SoC is in a completely powered-off state and part or all of the devices of the internal memory are in a powered-on state; and send a first control signal to the internal memory, wherein the first control signal is used to maintain the internal memory in a first mode, wherein in the first mode the internal memory saves currently stored data.

[0008] In an embodiment of the present invention, when the processing device enters the standby state, the SoC can first control the internal memory to enter the self-refresh mode, and then the power management unit takes over the control signal of part of the internal memory to maintain the internal memory in the self-refresh state, and then the power management unit can turn off the entire power supply of the SoC, thereby reducing the entire standby power consumption of the processing device. Furthermore, when the processing device is awakened (that is, the processing device is restored to a normal working state), since the data in the internal memory is not lost, there is no need to re-read the relevant data from the external memory to the internal memory (that is, the processing device does not need to re-enter the power-on initialization process), thereby reducing the power-on recovery time of the processing device. In the prior art, after the processing device enters the standby state, since the SoC needs to continue to control and manage the internal memory, that is, the SoC needs to maintain the internal memory in the self-refresh mode to ensure that the data currently stored in the internal memory is not lost, it is impossible to completely power off the SoC in the prior art. In summary, in this application, by improving the power management unit in the processing device, when the processing device enters the standby state, the power management unit can take over the internal memory after the SoC is completely powered off, and maintain the internal memory in the self-refresh mode, thereby ensuring that the processing device can resume normal working state in a shorter time, and reducing the standby power consumption of the processing device, increasing the standby time, and improving the user experience.

[0009] In one possible implementation, the power management unit includes a status register and a first control module; the power management unit is specifically used to: after receiving the first indication sent by the SoC, set the status register to a first state; in the first state, shield the signal output by the SoC to the internal memory through the first control module, and send the first control signal to the internal memory to maintain the internal memory in the first mode.

[0010] In an embodiment of the present invention, the power management unit includes a status register and a first control module. When the power management unit receives the first indication sent by the SoC, it can first set the status register to 1 (i.e., the first state), which can indicate that the processing device has entered the standby state, and then the power management unit can take over the internal memory. In this process, in order to avoid the signal sent by the SoC to the internal memory through the power management unit to become unstable after the SoC is powered off, causing the control signal sent by the power management unit to the internal memory to become disordered, thereby destroying the self-refresh state of the internal memory, the first control module in the power management unit will shield the signal sent by the SoC to the internal memory (such as shielding the signal sent by the SoC to the internal memory before the SoC is completely powered off). The power management unit fully controls and manages the internal memory, and then the first control module of the power management unit can send a first control signal to the internal memory to maintain the internal memory in the self-refresh mode, so that the internal memory can still save the currently stored data when the processing device is in the standby state. In summary, since in this application, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, this not only ensures that the processing device can resume normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0011] In a possible implementation, the internal memory is configured to receive the first control signal sent by the power management unit and maintain the first mode to save currently stored data.

[0012] In an embodiment of the present invention, after the power management unit takes over the internal memory, the power management unit can control and manage the state of the internal memory. Therefore, when the internal memory receives the first control signal sent by the power management unit, it can maintain the self-refresh mode (i.e., the first mode), that is, the internal memory continuously refreshes the currently stored data, so that after the processing device enters the standby state, the internal memory can still retain the currently stored data. In summary, since in this application, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, this not only ensures that the processing device can resume normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0013] In one possible implementation, the processing device also includes an external memory, and the power management unit is also coupled to the external memory, and the power management unit supplies power to the external memory through a third power domain; the power management unit is further used to: after receiving the first indication sent by the SoC, keep part or all of the power supplies of the third power domain in a power-on state, wherein after the processing device enters the standby state, part or all of the devices of the external memory are in a powered-on state; and send a second control signal to the external memory, wherein the second control signal is used to maintain the external memory in a second mode, wherein in the second mode the external memory retains the current configuration parameters.

[0014] In an embodiment of the present invention, after the power management unit receives the first indication sent by the SoC, in order to avoid the problem of loss of the current configuration parameters of the external memory after the processing device enters the standby state, the power management unit will keep the third power domain in a powered state. In order to reduce the amount of power loss in standby mode, some of the power domains in the third power domain can also be powered off, that is, some or all of the devices that do not affect the storage of the current configuration parameters of the external memory can be powered off. Furthermore, when the processing device enters the standby state, the SoC can be powered off, and the power management unit can take over the internal memory and the external memory. After the power management unit takes over the external memory, it can send a second control signal to the external memory to maintain the external memory in the second mode, that is, the second mode can be understood as the low power mode of the external memory. In low power mode, the external memory can still retain the current configuration parameters and configuration status. In summary, since in this application, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, this not only ensures that the processing device can resume normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0015] In one possible implementation, the power management unit also includes a second control module; when the status register is set to the first state, the power management unit is specifically used to: shield the signal output by the SoC to the external memory through the second control module, and send the second control signal to the external memory to maintain the external memory in the second mode.

[0016] In an embodiment of the present invention, in addition to including multiple power domains, a first control module and a status register, the power management unit may also include a second control module. When the power management unit receives the first indication sent by the SoC, it may first set the status register to 1 (i.e., the first state), which may indicate that the processing device has entered the standby state, and then the power management unit may take over the external memory. In this process, in order to avoid the signal sent by the SoC to the external memory through the power management unit to be in an unstable state after the SoC is powered off, causing the signal sent by the power management unit to the external memory to be disordered, the second control module in the power management unit will shield the signal sent by the SoC to the external memory, and the power management unit will fully control and manage the external memory, and then the second control module of the power management unit can send a second control signal to the external memory, so that the external memory can be maintained in a low power consumption mode, so that the external memory can still save the current configuration parameters and configuration status when the processing device is in the standby state. In summary, since in this application, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, this not only ensures that the processing device can resume normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0017] In a possible implementation, the external memory is configured to receive the second control signal sent by the power management unit and maintain the second mode to retain current configuration parameters.

[0018] In an embodiment of the present invention, after the power management unit takes over the external memory, the power management unit can control and manage the state of the external memory. Therefore, when the external memory receives the second control signal sent by the power management unit, it can be maintained in a low power mode (second mode), that is, the external memory can still retain the current configuration information and configuration state after the processing device enters the standby state. In summary, since in this application, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, this not only ensures that the processing device can resume normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0019] In one possible implementation, the power management unit is further used to: upon receiving an indication that the processing device needs to resume working status, restore the first power domain and supply power to the SOC; receive a second indication sent by the SOC and set the status register to a second state; in the second state, unmask the signal output by the SoC to the internal memory, and forward the signal output by the SoC to the internal memory to the internal memory; or, unmask the signal output by the SoC to the external memory, and forward the signal output by the SoC to the external memory to the external memory.

[0020] In an embodiment of the present invention, when the power management unit receives an indication that the processing device needs to be awakened, it can restore the first power domain and continue to power the SoC, and when the SoC is powered on, it can continue to control and manage the internal memory and external memory. Furthermore, after the SoC is powered on, it can send a second indication to the power management unit. After receiving the second indication, the power management unit can set the status register to the second state (i.e., SR=0), indicating that the processing device is in a normal working state, or it can indicate that the power management unit does not need to continue to control and manage the internal memory and external memory. Next, the SoC can unblock the control signal from the SoC to the power management unit by controlling the relevant logic of the power management unit, and at the same time, transparently transmit the relevant control signal to the internal memory and external memory through the power management unit. Finally, the processing device returns to a normal working state. In summary, since in this application, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, this not only ensures that the processing device can return to a normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0021] In one possible implementation, the SoC is used to: when the first power domain is turned on, determine whether the status register in the power management unit is in the first state; if the status register is in the first state, send the second indication to the power management unit.

[0022] In an embodiment of the present invention, when the SoC is powered on again, it can first determine whether the status register in the power management unit is in the first state. If the status register is in the first state, a second instruction can be sent to the power management unit to control the relevant logic of the power management unit to unblock the control signal sent by the SoC to the power management unit. At the same time, the SoC can transparently transmit the relevant control signal to the internal memory and the external memory through the power management unit. If the status register is not in the first state, the processing device will execute the power-on and restart process, that is, it is necessary to reconfigure the external memory and re-read the required data from the external memory to the internal memory. In summary, since in this application, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, this not only ensures that the processing device can resume normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0023] In a second aspect, an embodiment of the present invention provides a low-power standby control method, characterized in that it is applied to a processing device, the processing device including a power management unit, a system on chip (SoC) and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit, and the power management unit supplies power to the SoC through a first power domain and supplies power to the internal memory through a second power domain; the method includes: receiving, through the power management unit, a first indication sent by the SoC, wherein the first indication is used to instruct the processing device to enter a standby state; controlling, through the power management unit, to disconnect the first power domain and keep part or all of the power of the second power domain in a powered state; wherein, after the processing device enters the standby state, the SoC is in a completely powered-off state and part or all of the devices of the internal memory are in a powered-on state; sending, through the power management unit, a first control signal to the internal memory, wherein the first control signal is used to maintain the internal memory in a first mode, wherein in the first mode the internal memory saves currently stored data.

[0024] In one possible implementation, the power management unit includes a status register and a first control module; sending a first control signal to the internal memory through the power management unit includes: after receiving the first indication sent by the SoC, setting the status register to a first state; in the first state, shielding the signal output by the SoC to the internal memory through the first control module, and sending the first control signal to the internal memory to maintain the internal memory in the first mode.

[0025] In a possible implementation, the method further includes: receiving, through the internal memory, the first control signal sent by the power management unit, and maintaining the internal memory in the first mode to save currently stored data.

[0026] In one possible implementation, the processing device also includes an external memory, and the power management unit is also coupled to the external memory, and the power management unit supplies power to the external memory through a third power domain; the method also includes: after receiving the first indication sent by the SoC through the power management unit, keeping part or all of the power supplies of the third power domain in a power supply state, wherein after the processing device enters the standby state, part or all of the devices of the external memory are in a powered state; and sending a second control signal to the external memory through the power management unit, wherein the second control signal is used to maintain the external memory in a second mode, wherein the external memory retains current configuration parameters in the second mode.

[0027] In one possible implementation, the power management unit also includes a second control module; when the status register is set to the first state, sending a second control signal to the external memory through the power management unit includes: shielding the signal output by the SoC to the external memory through the second control module, and sending the second control signal to the external memory to maintain the external memory in the second mode.

[0028] In a possible implementation, the method further includes: receiving, through the external memory, the second control signal sent by the power management unit, and maintaining the external memory in the second mode to retain current configuration parameters.

[0029] In one possible implementation, the method further includes: upon receiving an indication that the processing device needs to resume working status, restoring the first power domain and supplying power to the SoC through the power management unit; receiving a second indication sent by the SoC through the power management unit, and setting the status register to a second state; in the second state, unmasking the signal output by the SoC to the internal memory through the power management unit, and forwarding the signal output by the SoC to the internal memory to the internal memory; or, unmasking the signal output by the SoC to the external memory, and forwarding the signal output by the SoC to the external memory to the external memory.

[0030] In one possible implementation, the method further includes: after the first power domain is turned on, determining through the SoC whether the status register in the power management unit is in the first state; if the status register is in the first state, sending the second indication to the power management unit through the SoC.

[0031] In a third aspect, the present application provides a terminal device having the function of implementing any of the above-mentioned low-power standby control methods. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions.

[0032] In a fourth aspect, an embodiment of the present invention provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can execute the process in the low-power standby control method of any one of the above-mentioned second aspects.

[0033] In a fifth aspect, the present application provides a semiconductor chip, characterized in that the semiconductor chip includes the processing device described in any one of the above-mentioned first aspects.

[0034] In a sixth aspect, the present application provides an electronic device, characterized in that the electronic device includes the semiconductor chip described in the fifth aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention.

[0036] FIG2 is a schematic structural diagram of a processing device provided by an embodiment of the present invention.

[0037] FIG3 is a schematic diagram of power domains in a power management unit provided by an embodiment of the present invention.

[0038] FIG4 is a schematic diagram of a user interface of an electronic device entering a standby state provided by an embodiment of the present invention.

[0039] FIG5 is a schematic diagram of a power domain of a processing device in a standby state according to an embodiment of the present invention.

[0040] FIG6 is a schematic diagram of a power management unit of a processing device after entering a standby state according to an embodiment of the present invention.

[0041] FIG7 is a schematic diagram of a power management unit of another processing device in a standby state provided by an embodiment of the present invention.

[0042] FIG8 is a schematic structural diagram of a power management unit of another processing device in a standby state provided by an embodiment of the present invention.

[0043] FIG9 is a schematic structural diagram of another processing device provided by an embodiment of the present invention.

[0044] FIG10 is a schematic diagram of another power management unit of another processing device provided by an embodiment of the present invention in a standby state.

[0045] FIG11 is a schematic diagram of a power management unit of a processing device in a working state provided by an embodiment of the present invention.

[0046] FIG12 is a schematic diagram of a power management unit of another processing device in a working state provided by an embodiment of the present invention.

[0047] FIG13 is a schematic diagram of a user interface for waking up an electronic device provided by an embodiment of the present invention.

[0048] FIG14 is a schematic diagram of a flow chart of a processing device entering a standby state according to an embodiment of the present invention.

[0049] FIG15 is a flowchart of a low-power standby control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0051] The terms "first," "second," "third," and "fourth," etc., in the specification and claims of this application and the accompanying drawings are used to distinguish different objects, not to describe a specific order. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0052] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0053] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0054] Based on the above, an embodiment of the present invention provides an electronic device. Please refer to Figure 1, which is a structural diagram of an electronic device provided by an embodiment of the present invention. The electronic device 100 may include but is not limited to smart phones, smart wearable devices (such as smart watches), tablet computers, personal digital assistants and other types of devices that need to rely on batteries for power supply. The electronic device 100 may have a built-in chip or chipset or a circuit board equipped with a chip or chipset, and the chip or chipset or the circuit board equipped with a chip or chipset can work under the necessary software drive. The chip or chipset or the circuit board equipped with a chip or chipset may include a power management unit 101, a system on chip 102, an internal memory 103, an external memory 104, and a battery 105. Further, it may also include interfaces, peripherals and other components not shown in Figure 1. Specifically,

[0055] The power management unit 101 manages the power supply of the electronic device 100. The power management unit 101 can be connected to devices such as the battery 105, the system-on-chip 102, the internal memory 103, and the external memory 104. The power management unit 101 receives input from the battery 105 and / or the charge management unit to provide power to the system-on-chip 102, the internal memory 103, and the external memory 104. The power management unit 101 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). The battery 105 can include a rechargeable battery and / or a lithium battery. In some embodiments, when electronic device 100 enters standby mode, power management unit 101 may completely power off system-on-chip 102 and take over internal memory 103 and external memory 104 to maintain internal memory 103 in a self-refresh state and external memory 104 in a low-power state. This not only reduces standby power consumption, increases standby time, and improves user experience, but also allows system-on-chip 102 to be quickly powered back on. How power management unit 101 takes over internal memory 103 and external memory 104 in standby mode will be described in detail in subsequent embodiments and will not be detailed here.

[0056] The system on chip 102 (SoC) may include a processor 1021 and a controller 1022. When the electronic device 100 is in normal working state, the power management unit 101 supplies power to the system on chip 102. The processor 1021 in the system on chip 102 may run an operating system, a file system (such as a flash file system), or an application program, etc., to control multiple hardware or software components connected to the processor 1021, and may process various data and perform operations. The processor 1021 may load instructions or data stored in the external memory 104 into the internal memory 103, and transfer instructions or data that require calculation to the processor 1021 for calculation. After the calculation is completed, the processor 1021 temporarily stores the result in the internal memory 103, and stores instructions or data that require long-term storage in the external memory 104 through the controller 1022. Processor 1021 may include one or more processing units (also referred to as processing cores). For example, processor 1021 may include one or more of a central processing unit (CPU), an application processing unit (AP), a modem processing unit (MPU), a graphics processing unit (GPU), an image signal processing unit (ISP), a video codec unit, a digital signal processing unit (DSP), a baseband processing unit, and a neural network processing unit (NPU). The different processing units may be independent devices or integrated into one or more devices. Optionally, processor 1021 may also include memory for storing instructions and data. In some embodiments, the memory in processor 1021 is a high-speed cache. The cache can store instructions or data that have just been used or are being recycled by processor 1021. If processor 1021 needs to use the same instruction or data again, it can directly call it from the cache. This avoids duplicate accesses, reduces the waiting time of processor 1021, and thus improves system efficiency. The controller 1022 in the system-on-chip 102 can be used to manage and control the reading and writing of data between the processor 1021 and the internal memory 103 and the external memory 104, and provide a standardized interface (such as the Universal Flash Storage (UFS) standard) for communication between the processor 1021 and the internal memory 103, and between the processor 1021 and the external memory 104. In some embodiments, the controller 1022 can encapsulate instructions or data sent from the processor 1021 into data packets supporting a specific protocol, and perform the reverse operation for data received by the processor 1021.In some embodiments, when the electronic device 100 is in a standby state, all components in the system on chip 102 may be in a power-off state, that is, the power management unit 101 may stop supplying power to the system on chip 102 .

[0057] The internal memory 103 is typically a volatile memory that loses its contents when the power is turned off. It can also be called memory or main memory. The internal memory 103 in this application includes a readable and writable operating memory, which is used to temporarily store the calculation data of the processor 1021 and to exchange data with the external memory 104 or other external memories. It can be used as a storage medium for temporary data of the operating system or other running programs. For example, the operating system running on the processor 1021 transfers the data to be calculated from the internal memory 103 to the processor 1021 for calculation. When the calculation is completed, the processor 1021 transmits the result. In some embodiments, when the electronic device 100 enters the standby state, the power management unit 101 will continue to supply power to the internal memory 103 and put the internal memory 103 into the self-refresh mode to ensure that the data currently stored in the internal memory 103 is not lost, thereby avoiding the need to load the required data or instructions in the external memory 104 into the internal memory 103 again after the on-chip system 102 is powered on again, reducing the power-on recovery time of the on-chip system 102, so that the electronic device 100 can recover to normal working state more quickly.

[0058] The internal memory 103 may include one or more of dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), etc. DRAM includes double data rate synchronous dynamic random access memory (DDR SDRAM), second-generation double data rate synchronous dynamic random access memory (DDR2), third-generation double data rate synchronous dynamic random access memory (DDR3), fourth-generation low power double data rate synchronous dynamic random access memory (LPDDR4), and fifth-generation low power double data rate synchronous dynamic random access memory (LPDDR5).

[0059] External memory 104 is a non-volatile memory whose stored contents are not lost after a power outage. External memory 104 can be used for long-term storage of instructions and data involved in the operation of processor 1021, such as boot programs, operating systems, applications, and data. Since processor 1021 cannot directly read instructions and data from external memory 104 or directly write instructions or data to external memory 104, when processor 1021 executes a read (or load) instruction, it actually temporarily loads the contents to be read (including instructions and / or data) stored in external memory 104 into internal memory 103 through controller 1022, and then processor 1021 reads the contents from internal memory 103. When executing a write (i.e., store) instruction, processor 1021 actually temporarily writes the data to be stored (including instructions and / or data) into internal memory 103, and then controller 1022 stores the contents from internal memory 103 into external memory 104. In some embodiments, when the electronic device 100 enters the standby state, the power management unit 101 will continue to supply power to the external memory 104 and put the external memory 104 into a low power consumption mode to ensure that the external memory 104 retains the current configuration parameters, thereby avoiding the need for the external memory 104 to re-perform the power-on initialization process after the on-chip system 102 is powered on again, reducing the power-on recovery time of the on-chip system 102, so that the electronic device 100 can return to normal working state more quickly.

[0060] The external memory 104 may include one or more of Flash memory (for example, NAND flash memory, NOR flash memory, etc.), universal flash storage (UFS), embedded multimedia card eMMC, universal flash storage multi-chip package uMCP memory, embedded multimedia card multi-chip package eMCP memory, solid-state drive (SSD), etc.

[0061] It can be understood that the structure of the electronic device 100 in FIG. 1 is only some exemplary implementations provided by the embodiments of the present invention. The structure of the electronic device in the embodiments of the present invention includes but is not limited to the above implementations.

[0062] The embodiments of the present invention are described below with reference to the accompanying drawings.

[0063] Please refer to Figure 2, which is a structural diagram of a processing device provided in an embodiment of the present invention. The processing device in the embodiment of the present application will be described in detail below in conjunction with Figure 2. As shown in Figure 2, the processing device 200 may include but is not limited to a power management unit 201, a system on chip 202 and an internal memory 203, wherein the system on chip SoC202 and the internal memory 203 are coupled to the power management unit 201, and the power management unit 201 supplies power to the SoC202 through a first power domain, and supplies power to the internal memory 203 through a second power domain. It should be noted that the processing device 200 can be built into various types of devices that need to rely on battery power, such as the electronic device 100 in Figure 1 above. The functions of the power management unit 201 may include part or all of the functions of the power management unit 101 in Figure 1 above, the functions of the SoC202 may include part or all of the functions of the system on chip 102 in Figure 1 above, and the internal memory 203 may include part or all of the functions of the internal memory 103 in Figure 1 above. Among them,

[0064] The power management unit 201 is configured to receive a first instruction sent by the SoC 202 , where the first instruction is configured to instruct the processing device 200 to enter a standby state.

[0065] Specifically, the power management unit 201 can manage the power supply of each module in the processing device 200. For example, as shown in Figure 3, which is a schematic diagram of power domains in a power management unit provided by an embodiment of the present invention, the power management unit 201 supplies power to the SoC 202 through a first power domain, where the first power domain may include multiple sub-power domains, such as the system interface power supply (also known as IO power), the low-voltage always-on (AO) power supply of the SoC 202, the memory control signal power supply, and other power supplies. The power management unit 201 supplies power to the internal memory 203 (such as LPDDR4) through a second power domain, where the second power domain may also include multiple sub-power domains, such as the IO power supply and control signal power supply within the DDR. The system on chip (SoC) 202 can refer to a complete system integrated on a single chip. The so-called complete system generally includes a central processing unit (CPU) and peripheral circuits. The internal memory 203 is typically a volatile memory that loses its stored content when the power is off. It can also be called memory or main memory. The internal memory 203 in this application includes a readable and writable running memory, which is used to temporarily store the calculation data in the SoC202, and can interact with the external memory or other external memory. It can be used as a storage medium for temporary data of the operating system or other running programs.

[0066] Optionally, when SoC202 receives a target operation of the user on the processing device 200, or when the user does not perform any operation on the processing device 200 within a preset time period, SoC202 may be triggered to send a first instruction to the power management unit 201 to enable the processing device 200 to enter a standby state. For example, as shown in FIG4 , FIG4 is a schematic diagram of a user interface of an electronic device entering a standby state provided by an embodiment of the present invention. In the figure, the electronic device (such as a smart phone, a smart wearable device, a tablet computer, and other types of battery-powered devices) has a built-in processing device 200. FIG4 (a) shows that the electronic device can display an operation interface during normal operation. When a user presses the electronic device (such as a user presses the power button on both sides of the electronic device), SoC202 may be triggered to send a first instruction to the power management unit 201 to enable the processing device 200 to enter a standby state. Then, as shown in FIG4 (b), the electronic device will be in a black screen standby state.

[0067] The power management unit 201 is further used to: control the disconnection of the first power domain and keep part or all of the power supply of the second power domain in a powered state; wherein, after the processing device 200 enters the standby state, the SoC202 is in a completely powered-off state and part or all of the devices of the internal memory 203 are in a powered-on state.

[0068] Specifically, after the power management unit 201 receives the first instruction sent by the SoC 202, the power management unit 201 may disconnect the first power domain. For example, as shown in FIG5 , FIG5 is a schematic diagram of a power domain after a processing device is in a standby state provided by an embodiment of the present invention. In the figure, the first power domain may include multiple sub-power domains. After the power management unit 201 receives the first instruction sent by the SoC 202, it will disconnect all sub-power supplies in the first power domain so that the SoC 202 is in a completely powered-off state when the processing device 200 is in the standby state. In addition, since the internal memory 202 is a volatile memory that is powered off, in order to avoid data loss in the internal memory 203 when the processing device 200 is in the standby state, the power management unit 201 will keep the second power domain in a powered state. Furthermore, in order to reduce the amount of power lost in standby mode, some power domains in the second power domain can be powered off, that is, some or all devices that do not affect the internal memory 203 in storing currently stored data can be powered off, such as powering off the IO power supply of the internal memory 203 (when the processing device 200 is in standby mode, the internal memory 203 does not need to interact with other modules, so the IO power supply can be powered off).

[0069] The power management unit 201 is further configured to send a first control signal to the internal memory 203, wherein the first control signal is configured to maintain the internal memory 203 in a first mode, wherein the internal memory 203 stores currently stored data in the first mode.

[0070] Specifically, after the power management unit 201 disconnects the first power domain, the SoC 202 is in a power-off state and cannot continue to control and manage the internal memory 203. The power management unit 201 can take over the internal memory 203, and the power management unit 201 can send a first control signal to the internal memory 203 to maintain the internal memory 203 in the first mode (that is, the first mode can be understood as the self-refresh mode of the internal memory 203). The first control signal is a signal that maintains the internal memory 203 in the self-refresh mode (which can be a signal with a fixed level), and can be a signal composed of multiple signals, such as a signal composed of a clock enable signal and a reset signal. When the clock enable signal sent by the power management unit 201 to the internal memory 203 is 0 and the reset signal is 1, the internal memory 203 can always be maintained in the self-refresh mode.

[0071] Optionally, before the SoC 202 sends the first control signal to the power management unit 201 , it may first send a control signal and related control commands to the internal memory 203 , so that the internal memory 203 can enter the self-refresh state.

[0072] For example, as shown in Figure 6, Figure 6 is a schematic diagram of a power management unit after a processing device provided by an embodiment of the present invention enters a standby state. In the figure, a control logic module (such as a first control module) can be added to the power management unit 201. When the SoC 202 is in a power-off state, a first control signal can be sent to the internal memory 203 through the control logic module, that is, the reset signal is 1 and the clock enable signal is 0, so as to maintain the internal memory 203 in a self-refresh mode, so that the internal memory 203 can still save the currently stored data when the processing device 200 is in the standby state.

[0073] It should be noted that when the processing device 200 enters the standby state, the internal memory 203 can save the currently stored data, avoiding the need to re-read relevant data from the external memory after the processing device 200 wakes up, thereby reducing the power-on recovery time of the processing device 200.

[0074] Alternatively, the first control signal may be a single signal, such as a reset signal. Before powering off, the SoC 202 may first send a clock enable signal of 0 to the internal memory 203. After the SoC 202 is powered off, the clock enable signal may be maintained at 0 via a pull-down resistor. Then, when the power management unit 201 sends a reset signal of 1 to the internal memory 203, the internal memory 203 may be maintained in the self-refresh mode. For example, as shown in FIG5 , the SoC 202 and the internal memory 203 may be connected via a transmission line and a pull-down resistor. Furthermore, before powering off, the SoC 202 may first send a clock enable signal of 0 to the internal memory 203. After the SoC 202 is powered off, the clock enable signal may be maintained at 0 via a pull-down resistor. Furthermore, after the power management unit 201 takes over the internal memory 203, it may send a reset signal of 1 to the internal memory 203 to maintain the internal memory 203 in the self-refresh mode, thereby enabling the currently stored data to be saved when the processing device 200 is in the standby state.

[0075] In one possible implementation, the power management unit 201 includes a status register and a first control module; the power management unit 201 is specifically used to: after receiving the first indication sent by the SoC202, set the status register to a first state; in the first state, shield the signal output by the SoC202 to the internal memory through the first control module, and send the first control signal to the internal memory to maintain the internal memory in the first mode.

[0076] Specifically, the status register (SR) in the power management unit 201 can have two states: when SR = 0, it can indicate that the processing device 200 is in normal working state; when SR = 1 (which can be understood as setting the status register to the first state, and it should be emphasized that in the first state, SR = 1), it can indicate that the processing device 200 has entered the standby state. The first control module in the power management unit 201 can have control logic and can send signals to the internal memory 203.

[0077] Next, the explanation will be given in conjunction with Figure 7. Figure 7 is a schematic diagram of a power management unit of another processing device provided in an embodiment of the present invention after being in standby state. In the figure, a status register and a first control module can be added to the power management unit 201. When the power management unit 201 receives the first indication sent by SoC202, it can first set the status register to 1 (i.e., the first state), which can indicate that the processing device 200 enters the standby state, and then the power management unit 201 can take over the internal memory 203. During this process, since the SoC 202 may still send signals to the internal memory 203 through the power management unit 201 after the power management unit 201 takes over the internal memory 203 and before the SoC 202 is completely powered off, the first control module of the power management unit 201 can shield the signal sent by the SoC 202 to the power management unit 201, and the power management unit 201 can fully control and manage the internal memory 203. Then, the first control module of the power management unit 201 can send a first control signal to the internal memory 203 to maintain the internal memory 203 in the self-refresh mode, so that the internal memory 203 can still save the currently stored data when the processing device 200 is in the standby state. In addition, after the SoC 202 is completely powered off, since the signal sent by the SoC 202 to the internal memory 203 through the power management unit 201 is shielded by the power management unit 201, the power management unit 201 fully controls and manages the internal memory 203 after the SoC 202 is completely powered off.

[0078] It should be noted that before SoC202 is powered off, SoC202 can also send configuration information of the first control module to the power management unit 201, so that the power management unit 201 configures the first control module based on the configuration information to send a first control signal to the internal memory 203 when SR=1.

[0079] In a possible implementation, the internal memory 203 is configured to receive the first control signal sent by the power management unit 201 and maintain the first mode to save currently stored data.

[0080] Specifically, after the power management unit 201 takes over the internal memory 203, the power management unit 201 can manage the state of the internal memory 203. Therefore, after the internal memory 203 receives the first control signal sent by the power management unit 201, it can be maintained in the self-refresh mode (i.e., the first mode), that is, the internal memory 203 continuously refreshes the currently stored data, so that after the processing device 200 enters the standby state, the internal memory 203 can still retain the currently stored data. In summary, since in this application, after the processing device 200 enters the standby state, the SoC 202 is in a completely powered-off state and the internal memory 203 can still retain the currently stored data, this not only ensures that the processing device 200 can resume normal operation in a relatively short period of time, but also reduces the standby power consumption of the processing device 200.

[0081] Optionally, as shown in FIG7 , the SoC 202 and the internal memory 203 can be connected via a transmission line and a pull-down resistor. Furthermore, before powering off, the SoC 202 can first send a clock enable signal of 0 to the internal memory 203, and after powering off, the SoC 202 can maintain the clock enable signal at 0 via the pull-down resistor. Furthermore, after the power management unit 201 takes over the internal memory 203, it can actively send a reset signal of 1 (i.e., a first control signal) to the internal memory 203. Then, when the clock enable signal is 0 and the reset signal is 1, the internal memory 203 can be maintained in a self-refresh mode. That is, the internal memory 203 continuously refreshes the currently stored data, so that after the processing device 200 enters the standby state, the internal memory 203 can still retain the currently stored data.

[0082] Optionally, as shown in FIG8 , FIG8 is a schematic structural diagram of another processing device provided by an embodiment of the present invention in a standby state power management unit. In the figure, the first control module in the power management unit 201 can send a reset signal to the internal memory 203 and can also send a clock enable signal. After the power management unit 201 takes over the internal memory 203, the power management unit 201 can actively send a reset signal of 1 and a clock enable signal of 0 to the internal memory 203 (that is, the first control signal consists of a reset signal of 1 and a clock enable signal of 0). Then, when the clock enable signal is 0 and the reset signal is 1, the internal memory 203 can be maintained in the self-refresh mode, that is, the internal memory 203 continuously refreshes the currently stored data, so that after the processing device 200 enters the standby state, the internal memory 203 can still retain the currently stored data.

[0083] In one possible implementation, the processing device 200 also includes an external memory 204, and the power management unit 201 is also coupled to the external memory 204, and the power management unit 201 supplies power to the external memory 204 through a third power domain; the power management unit 201 is further used to: after receiving the first indication sent by the SoC202, keep part or all of the power supplies of the third power domain in a power-on state, wherein after the processing device 200 enters the standby state, part or all of the devices of the external memory 204 are in a powered-on state; and send a second control signal to the external memory 204, wherein the second control signal is used to maintain the external memory 204 in a second mode, wherein in the second mode, the external memory 204 retains the current configuration parameters.

[0084] Specifically, the external memory 204 is generally a non-volatile memory, and its stored content will not be lost after power failure. Common external memory 204 may include Flash memory (for example, NAND flash memory, NOR flash memory, etc.), universal flash storage (UFS), etc. Next, it will be explained in conjunction with Figure 9. As shown in Figure 9, Figure 9 is a structural schematic diagram of another processing device provided by an embodiment of the present invention. In the figure, the power management unit 201 can also power the external memory 204 (such as EMMC or UFS) through the third power domain, wherein the third power domain may include multiple sub-power domains, such as the IO power supply inside the external memory 204, the control signal power supply, etc. When the power management unit 201 receives the first indication sent by the SoC202, in order to avoid the problem of the current configuration parameters of the external memory 204 being lost after the processing device 200 enters the standby state, the power management unit 201 will keep the third power domain in a power supply state. To reduce standby power consumption, some power domains within the third power domain can be powered down. Specifically, some or all components that do not affect the storage of current configuration parameters in the external memory 204 can be powered down, such as the IO power supply of the external memory 204. (When the processing device 200 is in standby mode, the external memory 204 does not need to interact with other modules, so this IO power supply can be powered down.) Furthermore, when the processing device 200 enters standby mode, the SoC 202 can be powered down, and the power management unit 201 can take over control of the internal memory 203 and the external memory 204. After the power management unit 201 takes over control of the external memory 204, it can send a second control signal to the external memory 204. This second control signal can be a reset signal. Because the external memory 204 can continuously receive a reset signal of 1, the external memory 204 can remain in the second mode, which can be understood as a low-power mode for the external memory 204. In low-power mode, the external memory 204 can still retain its current configuration parameters and configuration state.

[0085] Optionally, before the SoC 202 sends the first control signal to the power management unit 201 , it may first send a control signal and related control commands to the external memory 204 , so that the external memory 204 can enter the low power consumption mode.

[0086] It should be noted that when the processing device 200 enters the standby state, the current configuration parameters and configuration status of the external memory 204 can be retained, avoiding the need to reconfigure the external memory 204 after the processing device 200 wakes up, thereby reducing the power-on recovery time of the processing device 200.

[0087] In one possible implementation, the power management unit 201 also includes a second control module; when the status register is set to the first state, the power management unit 201 is specifically used to: shield the signal output by the SoC202 to the external memory 204 through the second control module, and send the second control signal to the external memory 204 to maintain the external memory 204 in the second mode.

[0088] Specifically, the power management unit 201 may also include a second control module. Next, the following will be explained in conjunction with Figure 10. As shown in Figure 10, Figure 10 is a schematic diagram of another power management unit provided by an embodiment of the present invention after another processing device is in standby state. In addition to including multiple power domains, a first control module and a status register, the power management unit 201 in the figure may also include a second control module. When the power management unit 201 receives the first indication sent by the SoC 202, it may first set the status register to 1 (i.e., the first state), which may indicate that the processing device 200 has entered the standby state, and then the power management unit 201 may take over the external memory 204. During this process, after the power management unit 201 takes over the external memory 204 and before the SoC 202 is completely powered off, the SoC 202 may still send signals to the external memory 204 through the power management unit 201. Therefore, the second control module in the power management unit 201 will shield the signals sent by the SoC 202 to the external memory 204, and the power management unit 201 will fully control and manage the external memory 204. Then, the second control module of the power management unit 201 can send a second control signal to the external memory 204 to maintain the external memory 204 in a low power mode, so that the current configuration parameters and configuration status can still be saved when the processing device 200 is in a standby state. In addition, after the SoC 202 is completely powered off, the second control module will also shield the indeterminate signals output by the SoC 202 to the external memory 204 through the power management unit 201, so that after the SoC 202 is completely powered off, the power management unit 201 will fully control and manage the external memory 204.

[0089] It should be noted that before SoC202 is powered off, SoC202 can also send configuration information of the second control module to the power management unit 201, so that the power management unit 201 configures the second control module based on the configuration information to send a second control signal to the external memory 204 when SR=1.

[0090] In a possible implementation, the external memory is configured to receive the second control signal sent by the power management unit and maintain the second mode to retain current configuration parameters.

[0091] Specifically, after the power management unit 201 takes over the external memory 204, the power management unit 201 can control and manage the state of the external memory 204. Therefore, when the external memory 204 receives the second control signal sent by the power management unit 201, it can be maintained in a low power mode (second mode), that is, the external memory 204 can still retain the current configuration information and configuration state after the processing device 200 enters the standby state. In summary, since in this application, after the processing device 200 enters the standby state, the SoC 202 is in a completely powered-off state and the external memory 204 can still retain the current configuration parameters and configuration state, this not only ensures that the processing device 200 can resume normal working state in a relatively short time, but also reduces the standby power consumption of the processing device 200, increases the standby time, and improves the user experience.

[0092] In one possible implementation, the power management unit 201 is further used to: upon receiving an indication that the processing device 200 needs to resume working status, restore the first power domain and supply power to the SoC 202; receive a second indication sent by the SoC 202, and set the status register to a second state; in the second state, unmask the signal output by the SoC 202 to the internal memory 203, and forward the signal output by the SoC 202 to the internal memory 203 to the internal memory 203; or, unmask the signal output by the SoC 202 to the external memory 204, and forward the signal output by the SoC 202 to the external memory 204 to the external memory 204.

[0093] Specifically, after the power management unit 201 receives an instruction to wake up the processing device 200, it can restore the first power domain and continue to power the SoC 202. When the SoC 202 is powered on, it can continue to control and manage the internal memory 203 and the external memory 204. Furthermore, after the SoC 202 is powered on, it can send a second instruction to the power management unit 201. After receiving the second instruction, the power management unit 201 can set the status register to the second state (i.e., SR = 0), indicating that the processing device 200 is in normal working state, or indicating that the power management unit 201 no longer needs to control and manage the internal memory 203 and the external memory 204. Next, the SoC 202 can unblock the control signals from the SoC 202 to the power management unit 201 by controlling the relevant logic of the power management unit 201, and at the same time, transparently transmit the relevant control signals to the internal memory 203 and the external memory 204 through the power management unit 201. Finally, the processing device 200 resumes normal working state.

[0094] For example, as shown in FIG11 , FIG11 is a schematic diagram of a power management unit of a processing device in a working state according to an embodiment of the present invention. In the figure, after the power management unit 201 receives the second control signal sent by the SoC 202, it can set the status register to 0, indicating that the power management unit 201 can no longer control and manage the internal memory 203 and the external memory 204. That is, the first control module of the power management unit 201 no longer controls and manages the internal memory 203, and the second control module of the power management unit 201 no longer controls and manages the external memory 204. Furthermore, the first control module can unblock the signal output by the SoC 202 to the internal memory 203 and forward the signal output by the SoC 202 to the internal memory 203 to the internal memory 203, for example, the first control module can directly forward the reset signal sent by the SoC 202 to the internal memory 203; the second control module can unblock the signal output by the SoC 202 to the external memory 204 and forward the signal output by the SoC 202 to the external memory 204 to the external memory 204, for example, the second control module can directly forward the reset signal sent by the SoC 202 to the external memory 204.

[0095] For another example, as shown in Figure 12, Figure 12 is a schematic diagram of a power management unit in the working state of another processing device provided by an embodiment of the present invention. In the figure, when the power management unit 201 receives the second control signal sent by SoC202, the status register can be set to 0, indicating that the power management unit 201 does not need to continue to control and manage the internal memory 203 and the external memory 204, that is, the first control module of the power management unit 201 does not need to continue to control and manage the internal memory 203, and the second control module of the power management unit 201 does not need to continue to control and manage the external memory 204. Furthermore, the first control module can unshield the signal output by SoC202 to the internal memory 203, and forward the signal output by SoC202 to the internal memory 203 to the internal memory 203, such as the first control module can directly forward the reset signal and clock enable signal sent by SoC202 to the internal memory 203; the second control module can unshield the signal output by SoC202 to the external memory 204, and forward the signal output by SoC202 to the external memory 204 to the external memory 204, such as the second control module can directly forward the reset signal sent by SoC202 to the external memory 204.

[0096] Optionally, as shown in Figure 13, Figure 13 is a schematic diagram of a user interface for waking up an electronic device provided by an embodiment of the present invention. The electronic device in the figure has a built-in processing device 200. When the processing device 200 is in standby state, the electronic device is in a black screen standby state as shown in Figure 13 (a). When a user pressing operation on the electronic device is detected (such as the user pressing the power buttons on both sides of the electronic device), the power management unit 201 will receive an indication that the processing device 200 needs to resume working status to wake up the processing device 200, and then the electronic device can be lit up as shown in Figure 13 (b), and the operation interface is displayed on the electronic device.

[0097] In one possible implementation, the SoC202 is used to: when the first power domain is turned on, determine whether the status register in the power management unit 201 is in the first state; if the status register is in the first state, send the second indication to the power management unit 201.

[0098] Specifically, when SoC 202 is powered on again, it can first determine whether the status register in the power management unit 201 is in the first state. If the status register is in the first state, it can send a second instruction to the power management unit 201 to control the relevant logic of the power management unit 201 to unmask the control signal sent by SoC 202 to the power management unit 201. At the same time, SoC 202 can transparently transmit the relevant control signal to the internal memory 203 and the external memory 204 through the power management unit 201. If the status register is not in the first state, the processing device 200 will execute the power-on and restart process, that is, it is necessary to reconfigure the external memory 204 and re-read the required data from the external memory 204 to the internal memory 203.

[0099] Next, a mobile phone is used as an example and FIG14 is combined with the SoC 202 side to explain. As shown in FIG14, FIG14 is a schematic diagram of a process flow of a processing device entering a standby state according to an embodiment of the present invention. In the figure, the mobile phone has a built-in processing device 200. The mobile phone entering the standby state may include the following steps S401 to S419. The detailed description is as follows:

[0100] S401: The mobile phone enters normal standby mode. Specifically, upon receiving a user's target operation on the mobile phone, the SoC 202 may first enter normal standby mode. It should be emphasized that in this normal standby mode, the power management unit 201 does not completely power off the SoC 202, and the SoC 202 still controls and manages the internal memory 203 and the external memory 204.

[0101] S402: The SOC returns to normal operation and the PMU exits power saving mode. Specifically, when the mobile phone enters normal standby mode for a time period exceeding a preset value, the SoC 202 may receive a timeout interrupt to wake it up, thereby returning the SoC 202 to normal operation and the power management unit 201 (i.e., the PMU) exiting power saving mode.

[0102] S403: SOC saves the DDR training sequence to FLASH. Specifically, SoC 202 saves the training sequence of the internal memory 203 (ie, DDR) to the external memory 204 (ie, FLASH).

[0103] S404: SOC saves the field parameters to DDR and configures DDR to enter self-refresh mode. Specifically, SoC202 saves the data to internal memory 203 and configures internal memory 203 to enter self-refresh mode so that the data saved in internal memory 203 is not lost after the mobile phone enters super standby mode.

[0104] S405: The SOC configures PMU Logic control1 to shield the input signal PMU_FLASH_RST_N and fix the output FLASH_RST_N to 1. Specifically, before the SoC 202 is completely powered off, the SoC 202 can configure the logic control module in the power management unit 201 so that after the SoC 202 is completely powered off, the logic control module can shield the signal output by the SoC 202 to the external memory 204 and output a control signal to the external memory 204 to cause the external memory 204 to enter a low power mode and retain the current configuration parameters and configuration status.

[0105] S406: The SOC configures PMU Logic control 2 to shield the input signal PMU_DDR_RST_N and fix the output DDR_RST_N to 1. Specifically, before the SoC 202 is completely powered off, the SoC 202 can configure the logic control module in the power management unit 201 so that after the SoC 202 is completely powered off, the logic control module can shield the signal output by the SoC 202 to the internal memory 203 and output a control signal to the internal memory 203 to cause the internal memory 203 to enter the self-refresh mode, thereby preventing data loss in the internal memory 203.

[0106] S407: The SOC configures the PMU Super SR to 1. Specifically, before the SoC 202 is completely powered off, the SoC 202 may first configure the status register in the power management unit 201 so that SR=1, which may indicate that the mobile phone is about to enter the deep standby state and that the power management unit 201 may take over the internal memory 203 and the external memory 204.

[0107] S408: The SOC controls the PMU to power off, and the PMU enters the Super SR power-off process. Specifically, the SoC 202 may send a first instruction to the power management unit 201, so that the power management unit 201 completely powers off the SoC 202.

[0108] S409: The entire SoC is powered off, while the DDR and FLASH components maintain power, and the PMU enters economical (ECO) mode. Specifically, upon receiving the first instruction from the SoC 202, the power management unit 201 may completely power off the SoC 202, or partially power off the internal memory 203 and the external memory 204.

[0109] S410: SOC enters super standby mode.

[0110] S411: The mobile phone enters super standby mode. Specifically, when the SoC 202 is completely powered off, the mobile phone enters super standby mode, and the power management unit 201 can take over the internal memory 203 and the external memory 204.

[0111] S412: The PMU performs a Super SR power-on process including starting the clock. Specifically, when the power management unit 201 receives a wakeup interrupt such as a user pressing the power button of the mobile phone, the power management unit 201 may perform a Super SR power-on process including starting the clock.

[0112] S413: The SOC is powered on and runs the startup code, and accesses the PMU Super SR to see if it is 1. Specifically, the power management unit 201 can re-power the SoC 202, and after the SoC 202 resumes normal operation, it can first access the status register in the power management unit 201 to see if it is 1 to determine whether the mobile phone is in deep standby mode.

[0113] S414: If yes, the SOC executes the Super Standby recovery process. Specifically, if the status register in the power management unit 201 is 1 after the SoC 202 resumes normal operation, it indicates that the mobile phone needs to be awakened from the Deep Standby state. If not, the SOC executes the normal power-on reset process, indicating that the mobile phone needs to be awakened from the Off state.

[0114] S415: SOC configures PMU Super SR to 0. Specifically, the status register in the power management unit 201 can be configured to 0 to indicate that the mobile phone has entered a normal working state, and also to indicate that the power management unit 201 does not need to continue to control and manage the internal memory 203 and the external memory 204.

[0115] S416: SOC configures PMU Logic control1 to pass-through mode, that is, signal FLAHS_RST_N is equal to SOC output signal PMU_FLASH_RST_N. Specifically, the power management unit 201 no longer needs to control and manage the external memory 204, so the logic control module can be configured to pass-through mode.

[0116] S417: SOC configures PMU Logic control2 to pass-through mode, that is, signal DDR_RST_N is equal to SOC output signal PMU_DDR_RST_N. Specifically, the power management unit 201 no longer needs to control and manage the internal memory 203, so the logic control module can be configured to pass-through mode.

[0117] S418: DDR exits self-refresh, FLASH completes fast initialization, and SOC recovers the scene.

[0118] S419: The SOC returns to Normal mode.

[0119] In an embodiment of the present invention, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, while the external memory also retains the current configuration parameters. This not only ensures that the processing device can resume normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0120] The processing device according to the embodiment of the present invention is described in detail above. The following provides a related method according to the embodiment of the present invention.

[0121] Please refer to Figure 15, which is a flowchart of a low-power standby control method provided by an embodiment of the present invention. The method is applicable to a processing device in Figure 2 above and a device including the processing device. The method may include the following steps S501-S503. The processing device includes a power management unit, a system on chip SoC and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit, and the power management unit supplies power to the SoC through a first power domain and supplies power to the internal memory through a second power domain. The detailed description is as follows:

[0122] Step S501: Receive a first instruction sent by the SoC through the power management unit.

[0123] Specifically, the first indication is used to instruct the processing device to enter a standby state;

[0124] Step S502: controlling, through the power management unit, to disconnect the first power domain, and keeping part or all of the power supply of the second power domain in a power supply state.

[0125] wherein, after the processing device enters the standby state, the SoC is in a completely powered-off state and some or all of the components of the internal memory are in a powered-on state;

[0126] Step S503: Sending a first control signal to the internal memory via the power management unit.

[0127] Specifically, the first control signal is used to maintain the internal memory in a first mode, wherein the internal memory saves currently stored data in the first mode.

[0128] In one possible implementation, the power management unit includes a status register and a first control module; sending a first control signal to the internal memory through the power management unit includes: after receiving the first indication sent by the SoC, setting the status register to a first state; in the first state, shielding the signal output by the SoC to the internal memory through the first control module, and sending the first control signal to the internal memory to maintain the internal memory in the first mode.

[0129] In a possible implementation, the method further includes: receiving, through the internal memory, the first control signal sent by the power management unit, and maintaining the internal memory in the first mode to save currently stored data.

[0130] In one possible implementation, the processing device also includes an external memory, and the power management unit is also coupled to the external memory, and the power management unit supplies power to the external memory through a third power domain; the method also includes: after receiving the first indication sent by the SoC through the power management unit, keeping part or all of the power supplies of the third power domain in a power supply state, wherein after the processing device enters the standby state, part or all of the devices of the external memory are in a powered state; and sending a second control signal to the external memory through the power management unit, wherein the second control signal is used to maintain the external memory in a second mode, wherein the external memory retains current configuration parameters in the second mode.

[0131] In one possible implementation, the power management unit also includes a second control module; when the status register is set to the first state, sending a second control signal to the external memory through the power management unit includes: shielding the signal output by the SoC to the external memory through the second control module, and sending the second control signal to the external memory to maintain the external memory in the second mode.

[0132] In a possible implementation, the method further includes: receiving, through the external memory, the second control signal sent by the power management unit, and maintaining the external memory in the second mode to retain current configuration parameters.

[0133] In one possible implementation, the method further includes: upon receiving an indication that the processing device needs to resume working status, restoring the first power domain and supplying power to the SOC through the power management unit; receiving a second indication sent by the SOC through the power management unit, and setting the status register to a second state; in the second state, unmasking the signal output by the SoC to the internal memory through the power management, and forwarding the signal output by the SoC to the internal memory to the internal memory; or, unmasking the signal output by the SoC to the external memory, and forwarding the signal output by the SoC to the external memory to the external memory.

[0134] In one possible implementation, the method further includes: after the first power domain is turned on, determining through the SoC whether the status register in the power management unit is in the first state; if the status register is in the first state, sending the second indication to the power management unit through the SoC.

[0135] In an embodiment of the present invention, after the processing device enters the standby state, the SoC is in a completely powered-off state and the internal memory can still retain the currently stored data, while the external memory also retains the current configuration parameters. This not only ensures that the processing device can resume normal working state in a shorter time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

[0136] The present application provides a terminal device that has the function of implementing any of the above-mentioned low-power standby control methods. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions.

[0137] The present application provides a terminal device, comprising a processor configured to support the terminal device in executing the corresponding functions of the low-power standby control method provided above. The terminal device may also include a memory coupled to the processor and storing program instructions and data necessary for the terminal device. The terminal device may also include a communication interface for communicating with other devices or a communication network.

[0138] An embodiment of the present invention provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can execute the process in any one of the low-power standby control methods mentioned above.

[0139] The present application provides a semiconductor chip, characterized in that the semiconductor chip includes any one of the processing devices mentioned above.

[0140] The present application provides an electronic device, characterized in that the electronic device includes the semiconductor chip mentioned above.

[0141] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0142] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0143] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0144] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0145] In addition, the functional units in the embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0146] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0147] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A processing device, characterized in that The processing device includes a power management unit, a system on chip (SoC), and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit, and the power management unit supplies power to the SoC through a first power domain and supplies power to the internal memory through a second power domain; the power management unit is configured to: receiving a first instruction sent by the SoC, where the first instruction is used to instruct the processing device to enter a standby state; Controlling to disconnect the first power domain and keeping part or all of the power supplies of the second power domain in a powered state; wherein, after the processing device enters the standby state, the SoC is in a completely powered-off state and part or all of the components of the internal memory are in a powered-on state; A first control signal is sent to the internal memory, where the first control signal is used to maintain the internal memory in a first mode, wherein the internal memory saves currently stored data in the first mode.

2. The device according to claim 1, wherein The power management unit includes a status register and a first control module; the power management unit is specifically configured to: After receiving the first instruction sent by the SoC, setting the status register to a first state; In the first state, the first control module shields the signal output by the SoC to the internal memory, and sends the first control signal to the internal memory to maintain the internal memory in the first mode.

3. The device according to claim 1 or 2, characterized in that The internal memory is used for: The first control signal sent by the power management unit is received, and the first mode is maintained to save the currently stored data.

4. The device according to claim 2 or 3, characterized in that The processing device further includes an external memory, and the power management unit is further coupled to the external memory, and the power management unit supplies power to the external memory via a third power domain; the power management unit is further configured to: After receiving the first instruction sent by the SoC, keep part or all of the power supplies of the third power domain in a power supply state, wherein after the processing device enters the standby state, part or all of the devices of the external memory are in a powered-on state; A second control signal is sent to the external memory, where the second control signal is used to maintain the external memory in a second mode, wherein the external memory retains current configuration parameters in the second mode.

5. The device according to claim 4, characterized in that The power management unit further includes a second control module; when the status register is set to the first state, the power management unit is specifically configured to: The second control module shields the signal output by the SoC to the external memory, and sends the second control signal to the external memory to maintain the external memory in the second mode.

6. The device according to claim 4 or 5, characterized in that The external memory is used for: Receive the second control signal sent by the power management unit, and maintain the second mode to retain current configuration parameters.

7. The device according to any one of claims 4 to 6, characterized in that The power management unit is further configured to: Upon receiving an indication from the processing device that the processing device needs to resume working, restoring the first power domain and supplying power to the SOC; receiving a second instruction sent by the SOC, and setting the status register to a second state; In the second state, the signal output by the SoC to the internal memory is unshielded, and the signal output by the SoC to the internal memory is forwarded to the internal memory; or The signal outputted from the SoC to the external memory is unshielded, and the signal outputted from the SoC to the external memory is forwarded to the external memory.

8. The device according to claim 7, characterized in that The SoC is used to: After the first power domain is turned on, determining whether the status register in the power management unit is in the first state; If the status register is in the first state, the second indication is sent to the power management unit.

9. A low power standby control method, characterized in that: The method is applied to a processing device, the processing device including a power management unit, a system on chip (SoC), and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit, the power management unit supplies power to the SoC via a first power domain, and supplies power to the internal memory via a second power domain; the method comprising: receiving, by the power management unit, a first instruction sent by the SoC, where the first instruction is used to instruct the processing device to enter a standby state; Controlling, by the power management unit, to disconnect the first power domain and keep part or all of the power supplies of the second power domain in a powered state; wherein, after the processing device enters the standby state, the SoC is in a completely powered-off state and part or all of the components of the internal memory are in a powered-on state; A first control signal is sent to the internal memory through the power management unit, where the first control signal is used to maintain the internal memory in a first mode, wherein the internal memory saves currently stored data in the first mode.

10. The method according to claim 9, wherein The power management unit includes a status register and a first control module; the sending of a first control signal to the internal memory through the power management unit includes: After receiving the first instruction sent by the SoC, setting the status register to a first state; In the first state, the first control module shields the signal output by the SoC to the internal memory, and sends the first control signal to the internal memory to maintain the internal memory in the first mode.

11. The method according to claim 9 or 10, wherein: The method further comprises: The first control signal sent by the power management unit is received through the internal memory, and the internal memory is maintained in the first mode, so that the internal memory saves the currently stored data in the first mode.

12. The method according to claim 10 or 11, wherein: The processing device further includes an external memory, and the power management unit is further coupled to the external memory, and the power management unit supplies power to the external memory via a third power domain; the method further includes: After receiving the first instruction sent by the SoC, the power management unit maintains part or all of the power supplies of the third power domain in a power supply state, wherein after the processing device enters the standby state, part or all of the devices of the external memory are in a powered state; A second control signal is sent to the external memory through the power management unit, where the second control signal is used to maintain the external memory in a second mode, wherein the external memory retains current configuration parameters in the second mode.

13. The method according to claim 12, wherein: The power management unit further includes a second control module; when the status register is set to the first state, sending a second control signal to the external memory through the power management unit includes: The second control module shields the signal output by the SoC to the external memory, and sends the second control signal to the external memory to maintain the external memory in the second mode.

14. The method according to claim 12 or 13, wherein: The method further comprises: The second control signal sent by the power management unit is received through the external memory, and the external memory is maintained in the second mode, so that the external memory retains the current configuration parameters in the second mode.

15. The method according to any one of claims 12 to 14, wherein: The method further comprises: Upon receiving an indication from the processing device that the working state needs to be restored, restoring the first power domain and supplying power to the SOC through the power management unit; receiving, by the power management unit, a second instruction sent by the SOC, and setting the status register to a second state; In the second state, the power management unit unshields the signal output by the SoC to the internal memory and forwards the signal output by the SoC to the internal memory to the internal memory; or, the power management unit unshields the signal output by the SoC to the external memory and forwards the signal output by the SoC to the external memory to the external memory.

16. The method according to claim 15, wherein The method further comprises: After the first power domain is turned on, determining, by the SoC, whether the status register in the power management unit is in the first state; If the status register is in the first state, the second indication is sent to the power management unit through the SoC.

17. A computer storage medium, characterized in that The method comprises computer instructions, which, when executed on an electronic device, cause the electronic device to execute the method according to any one of claims 9 to 16.

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