Programmable gate driver array for switched capacitor DC-DC converter

Abstract

The invention relates to a programmable gate driver array for a switched capacitor DC-DC converter, comprising at least one input terminal, a plurality of power switch terminals connectable to a plurality of power switches, in one embodiment, the system includes at least one input terminal, a plurality of power switches configured to convert a DC input voltage from the at least one input terminal to a DC output voltage by switched capacitor DC-DC conversion, a plurality of gate drivers configured to drive the plurality of power switch terminals, and a clock controller unit, the clock controller unit is configured to perform individual clock control of the plurality of gate drivers. A switched capacitor DC-DC converter including a programmable gate driver array for a switched capacitor DC-DC converter, and a method for performing individual clocking of a programmable gate driver array for a switched capacitor DC-DC converter.

Description

Technical Field

[0001] The present disclosure relates to a programmable gate driver array for a switched capacitor DC-DC converter with individual clock control. Background Art

[0002] In a typical switched capacitor DC-DC converter, a dead time is required during switching in order to avoid high currents in the switches, also called shoot-through. In practice, in the case of a simple charge pump, it may happen that when the upper switch is closed, the lower switch is not fully opened. This will then create a short circuit between the power supply and ground of the charge pump. In order to avoid this, a control circuit is provided to prevent the switches on both sides (i.e. high side and low side) from being turned on at the same time, i.e. both sides are turned off before the appropriate switch is turned on. The control circuit introduces what is usually called a dead time.

[0003] Some characteristics of this dead time are very critical for charge pumps, or more generally for switched capacitor DC-DC converters. The dead time cannot be too short, because the risk of creating a short circuit between the power supply and ground of the switched capacitor DC-DC converter will be relatively high. Conversely, the dead time cannot be too long, because this leads to higher power dissipation due to the higher flying capacitor ripple voltage, and therefore higher conduction losses in the switch due to the accompanying higher RMS current.

[0004] The current architecture of switched capacitor DC-DC converters is based on a global dead time, which means that the dead time can be adjusted in the clock controller unit, but it remains the same for all switches used in the switched capacitor DC-DC converter. Therefore, some disadvantages may occur, such as an increase in parasitic charge losses and higher electromagnetic interference (EMI). In fact, in the same switching phase, the switches are not turned on or off at the same time due to the variations in propagation and transition delays in the digital circuits, level shifters and gate drivers. It is during this critical time period that the parasitic capacitance can be charged and / or discharged by the switch or switches that are turned off first.

[0005] It would be beneficial to be able to provide a high efficiency switched capacitor DC-DC converter in which parasitic charge losses can be reduced. Summary of the invention

[0006] The present disclosure relates to a programmable gate driver array for a switched capacitor DC-DC converter, comprising at least one input terminal, a plurality of power switch terminals connectable to a plurality of power switches, the plurality of power switches configured to convert a DC input voltage from the at least one input terminal to a DC output voltage through switched capacitor power conversion, a plurality of gate drivers configured to drive the plurality of power switch terminals, and a clock controller unit, wherein the clock controller unit is configured to perform individual clock control of the plurality of gate drivers, wherein the clock controller unit generates individual clock signals to the gate drivers, and wherein the clock controller is further configured to generate individual edge delays on the individual clock signals.

[0007] By providing a clock controller unit configured to perform individual clock control of the plurality of gate drivers, the plurality of power switch terminals can then control the plurality of power switches with independent clock signals, thereby enabling the reduction of parasitic charge losses of the switched capacitor DC-DC converter.

[0008] The present disclosure also relates to a switched capacitor DC-DC converter, which includes a programmable gate driver array for a switched capacitor DC-DC converter such as a previously disclosed switched capacitor DC-DC converter, a plurality of flying capacitors connected to the plurality of flying capacitor terminals, and a plurality of power switches connected to the plurality of power switch terminals, wherein the programmable gate driver array is arranged with the plurality of flying capacitors and the plurality of power switches to perform switched capacitor DC-DC conversion with separate clock control of the plurality of power switches.

[0009] A switched capacitor DC-DC converter has several parasitic elements inherent to its design and implementation, such as parasitic resistance, capacitance, or inductance. These parasitic elements reduce the efficiency of the switched capacitor DC-DC converter, especially at high switching frequencies. However, the performance and efficiency of the switched capacitor DC-DC converter can be enhanced by independently controlling the multiple power switches using separate clock controls for each of the multiple power switches connected to the multiple power switch terminals.

[0010] Also disclosed is a method for performing individual clock control of a programmable gate driver array for a switched capacitor DC-DC converter, the method comprising the steps of providing a programmable gate driver array for a switched capacitor DC-DC converter, comprising at least one input terminal, a plurality of power switch terminals connectable to a plurality of power switches, the plurality of power switches being configured to convert a DC input voltage from the at least one input terminal into a DC output voltage by switched capacitor DC-DC conversion, a plurality of gate drivers configured to drive the plurality of power switch terminals, a clock controller unit, wherein the clock controller unit is configured to generate individual clock signals to the gate drivers, and wherein the clock controller is also configured to generate individual edge delays on the individual clock signals, and performing individual clock control of the programmable gate driver array for the switched capacitor DC-DC converter by using the clock controller unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the following, embodiments and examples will be described in more detail with reference to the accompanying drawings. The drawings are examples of embodiments and are not limiting of the currently disclosed programmable gate driver array for a switched capacitor DC-DC converter.

[0012] Figure 1A A schematic diagram of an embodiment of a programmable gate driver array for a switched capacitor DC-DC converter is shown.

[0013] Figure 1B A schematic diagram of an embodiment of a programmable gate driver array for a switched capacitor DC-DC converter including a plurality of power switches, wherein the power switches are segmented switches, is shown. Figure 2 A schematic diagram showing an embodiment of a clock controller unit is shown.

[0014] Figure 3A -B shows an embodiment of a clock generation scheme for a single inductor hybrid switched capacitor DC-DC converter topology.

[0015] Figure 4A -D shows a schematic diagram of an embodiment of a single inductor hybrid switched capacitor DC-DC converter topology and some associated clock generation schemes for different switching phases.

[0016] Figure 5A -C shows a schematic diagram of an embodiment of a two-phase Dickson switched capacitor DC-DC converter topology with segmented power switches and some associated clock generation schemes.

[0017] Fig. 6A-D shows a schematic diagram of embodiments of a single inductor hybrid switched capacitor DC-DC converter topology with external switches and some associated clock generation schemes for different switching phases.

[0018] Fig. 7A -B shows a schematic diagram of an embodiment of a two-phase Dickson switched capacitor DC-DC converter topology and an associated clock generation scheme for parasitic charge recycling.

[0019] Figure 8 A flow chart of the presently disclosed method of performing individual clock control of a programmable gate driver array for a switched capacitor DC-DC converter is shown. DETAILED DESCRIPTION

[0020] The present disclosure relates to a programmable gate driver array for a switched capacitor DC-DC converter, comprising a plurality of gate drivers configured to drive a plurality of power switch terminals. The programmable gate driver array also includes a clock controller unit, which can be configured to perform separate clock control of the plurality of gate drivers. The programmable gate driver array for a switched capacitor DC-DC converter includes a plurality of gate drivers and should be interpreted as including a minimum of two gate drivers. In other embodiments, the programmable gate driver array may include at least 3, at least 4, or at least 8 gate drivers. As will be appreciated by those skilled in the art, the programmable gate driver array includes, for example, two gate drivers (wherein the clock controller is configured to perform separate clock control of the two gate drivers) and should be interpreted as falling within the above language, even if additional gate drivers without separate clock control are added.

[0021] A programmable gate driver array for a switched capacitor DC-DC converter, and / or a switched capacitor DC-DC converter, and / or a system comprising a programmable gate driver array or a switched capacitor DC-DC converter may include a processing unit for programming and / or controlling the programmable gate driver array and / or its operation. The processing unit may be, for example, a microcontroller or any other microcomputer or processing unit suitable for the purpose.

[0022] Figure 1AA schematic diagram of an embodiment of a programmable gate driver array for a switched capacitor DC-DC converter is shown. The programmable gate driver array includes at least one input terminal, a plurality of gate drivers configured to drive a plurality of power switch terminals, a plurality of power switch terminals connected to a plurality of power switches, the plurality of power switches being configured to convert a DC input voltage from at least one input terminal into a DC output voltage through switched capacitor power conversion, and a clock controller unit. The programmable gate driver array includes a clock controller CLK_CNTRL. At least one input terminal is called VIN, which corresponds to a DC input voltage of a programmable gate driver array for a switched capacitor DC-DC converter. The programmable gate driver array includes a plurality of gate drivers GDRV0-GDRV7, which are configured to independently drive power switch terminals, namely G0-G7 and S0-S7. Power is supplied to the plurality of gate drivers from the VTOP terminal, and power is supplied to GDRV7 from the VBST terminal. A plurality of power switches SW0-SW7 are arranged outside the programmable gate array and connected to the plurality of power switch terminals. A plurality of flying capacitors (i.e., C1, C2, and C3) are connected together with a plurality of power switches to perform switched capacitor DC-DC conversion. The clock controller unit transmits signals s[0]-s[7] to a plurality of gate drivers. A bootstrap circuit is implemented to provide a boost voltage to a topmost gate driver GDRV7. The bootstrap circuit includes a bootstrap capacitor CBST and a bootstrap diode DBST. The topmost gate driver GDRV7 may require a positive supply voltage, which cannot be provided by connecting the GDRV7 positive supply terminal to VTOP and connecting the GDRV7 negative supply terminal to the source terminal of SW7, because the voltage from VTOP to the source of SW7 is approximately zero when SW7 is turned on. The bootstrap diode can provide a charging path from VTOP to the CBST boost capacitor when SW7 is turned on (off), and the diode blocks when SW7 is turned off (on). The result of the bootstrap circuit operation is a stable supply voltage of GDRV7 relative to the negative supply terminal of GDRV7 connected to the source terminal of SW7. A decoupling capacitor GOUT filters the DC output voltage of the switched capacitor DC-DC converter, and a decoupling capacitor CIN is connected to at least one input terminal to filter the DC input voltage of the switched capacitor DC-DC converter.

[0023] Figure 1BA schematic diagram of an embodiment of one of a plurality of power switches is shown. Each of a plurality of power switches (SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7) has three switch segments connected in parallel. The three switch segments have three terminals, namely "g", "s" and "d". "g" may represent "gate", "d" may represent "drain", and "s" may potentially represent "source". The three switch segments may preferably be connected in parallel. This means that the "d" terminals of all switch segments of the switch may be connected together, and the "s" terminals of all switch segments of the switch may be connected together. The "g" terminals may be individually controlled by different gate drivers. It can be seen that a plurality of power switches may be connected in various suitable ways. For example, in Figure 1B In the example, SW6 and SW7 are connected in series.

[0024] The clock controller unit can be configured to perform individual clock control of multiple gate drivers. Any clock signal from the clock controller unit can be configured with different frequencies, phases and / or edge delays in order to cancel the effects of any parasitic elements (such as parasitic capacitance, resistance and / or inductance of the switched capacitor DC-DC converter). These parasitic elements are inherent to the design and implementation of the switched capacitor DC-DC converter, so it may be beneficial to potentially have various clock signals to remove undesirable effects that affect performance and efficiency.

[0025] To perform switched capacitor DC-DC conversion, the programmable gate driver array may need to transmit signals to multiple power switch terminals having specific characteristics, depending on the desired DC-DC conversion. In this case, the multiple power switch terminals may be independently controlled by multiple gate drivers. Each of the multiple gate drivers may output signals having different characteristics and / or properties to their respective power switch terminals.

[0026] The individual clock control may be configured to select an individual clock signal from the plurality of clock signals, the individual clock signal having a clock frequency, a clock duty cycle and / or a clock edge delay.

[0027] The separate clock signal may be a digital clock signal that oscillates between a low state and a high state. The low state and high state of the clock digital signal may generally be defined as voltages, wherein the low state has a lower voltage than the high state. Figure 3AAn example of a clock signal that may be generated by a clock generator is shown. In this particular example, two digital clock signals clka and clkb are generated, where clkb has a 180 degree phase shift compared to clka. Both clka and clkb may be generated by a clock generator, while clka and clkb may be generated by a clock controller. The clock controller may generate at least one secondary clock signal based on a clock signal received from the clock generator.

[0028] The clock frequency of the individual clock signals may be between 1 Hz and 10 MHz, preferably between 50 kHz and 5 MHz. Typically, it may be desirable to have as low a clock frequency as possible, for example in standby mode, where the output voltage can be maintained but power consumption can be minimized. In standby mode, the gate driver may still require a supply current, and therefore a continuous balance of the flying capacitor may be required. However, the supply current of the gate driver may be very low, so that a very low clock frequency may be used. More generally, it may be desirable to have a high operating frequency to minimize the size of the required passive components. A higher switching frequency may produce a lower flying capacitor ripple, which may allow the use of a smaller capacitance value of the flying capacitor. Even more generally, it may be desirable to have a high switching frequency to avoid switching in some ranges of the spectrum to which other EMI victims in the surrounding system may be sensitive. For example, in an automotive system, it may be desirable to use a switching frequency at or above 2.2 MHz to avoid the AM radio band. The clock controller unit may also include at least one clock switch unit and at least one edge delay controller unit. At least one clock switch unit may be configured to select a clock from a plurality of available clock signals. At least one edge delay controller unit may be configured to generate an edge delay on a separate clock signal. The edge delays can be individually configured to deliver multiple different clock signals to multiple gate drivers to optimize parasitic charge losses in a switched capacitor DC-DC converter.

[0029] The edge delay may be a delay of the rising edge or the falling edge or both of the digital clock signal. The edge delay may correct duty cycle distortion by adjusting the edge of the digital clock signal independently of the duty cycle of the digital clock signal. Duty cycle distortion may be due to nonlinearity in the components, impedance mismatch, capacitive or inductive load, signal propagation delay, crosstalk, or power supply noise. By having a separate edge delay control, different clock signals that can be transmitted to multiple gate drivers can optimize the drive signals of multiple power switches of the switched capacitor DC-DC converter. This may be useful for several reasons. For example, in an embodiment of a DC-DC converter topology with multiple segmented power switches, separate edge delay control is useful because the switch segments can be used for charge recycling and reduce electromagnetic interference caused by switching. In addition, in a capacitor DC-DC converter topology with parasitic capacitance, the charging and discharging of the parasitic capacitance may cause undesirable parasitic losses. The parasitic capacitor may be charged and discharged through different loops, depending on which power switches are closed or opened. In such an embodiment, by controlling the edge delay of the power switch, parasitic losses may be reduced. Programmable gate driver arrays for switched capacitor DC-DC converters can also be configured to recycle parasitic losses through individual edge control.

[0030] Figure 2 A schematic diagram of an embodiment of a clock controller unit is shown. The clock controller unit, i.e., CLK_CNTRL, includes a clock switch sw_src_sel and an edge delay controller unit deadtime_gen. The clock controller unit has three input terminals, and clk_a, clk_b, and clk_c may be three different clock signals. These three different clock signals may have different frequencies, different duty cycles, and different phases. They may be generated from an internal clock generator further included in the clock controller unit, or they may be provided from one of at least one input terminal, and potentially generated outside of a programmable gate driver array for a switched capacitor DC-DC converter. The clock controller unit has an output terminal s[7:0], which consists of 8 different clock signals. The clock controller unit also includes digital input terminals sw_src_cfg[7:0][1:0], sw_src_inv[7:0], and sw_dly_cfg[7:0][1:0], wherein these signals may be intended to control the clock controller unit features. The clock switch includes a multiplexer and an XOR gate. The multiplexer and XOR gate are controlled by digital control signals (i.e., sw_src_cfg[7:0][1:0] and sw_src_inv[7:0]). The edge delay controller unit includes a delay unit and an AND gate. The delay unit is controlled by digital control signal sw_dly_cfg[7:0][1:0].

[0031] The clock controller unit may further include at least one clock input terminal and at least one clock output terminal. The at least one clock output terminal may be connectable to each of the plurality of gate drivers. Figure 2 As shown in the example of , at least one clock output terminal s[7:0] that can transmit at least one individual clock signal can be connected to each of the multiple gate drivers. At least one clock input terminal can be connected to a clock generator. The clock generator can be a voltage controlled oscillator or a ring oscillator. It can be integrated on the same chipset as the programmable gate driver array for the switched capacitor DC-DC converter, or it can be integrated on an external device and then potentially provided to the programmable gate driver array clock controller unit through one of the at least one input terminals. A voltage controlled oscillator is an electronic oscillator whose oscillation frequency is controlled by a voltage input. The applied input voltage determines the instantaneous oscillation frequency. A ring oscillator is a device consisting of an odd number of NOT gates in a ring, whose output oscillates between two voltage levels. A ring oscillator is a type of voltage controlled oscillator. NOT gates or inverters are attached in a chain, and the output of the last inverter is fed back into the first. This potentially creates instability, thus causing oscillation to occur. Another type of voltage controlled oscillator is an LC oscillator. LC oscillators are commonly used as voltage controlled oscillators because they can provide much less phase noise than ring oscillators, which is critical for good sensitivity and selectivity in transceivers. LC oscillators are very useful for high frequencies, typically above 1 GHz, where phase noise becomes critical. On the other hand, they are usually much larger than ring oscillators because they require relatively large integrated inductors.

[0032] The clock generator may also include a phase-locked loop (PLL) and / or a clock divider. A PLL is a control system that generates an output signal whose phase is related to the phase of an input signal. They may include multiple elements, such as a phase detector, a low-pass filter, and a feedback path and / or an optional divider. PLLs can be used for a variety of reasons: jitter and noise reduction, frequency synthesis, clock recovery, or clock generation. PLLs may be one of their several variants, such as an analog or linear PLL (APLL), a digital PLL (DPLL), or a charge pump PLL (CP-PLL). Each of these variants may have advantages and / or inconveniences, such as size, complexity, or frequency range. The choice of one of the PLL variants may depend on the desired and / or required application. A clock divider is a circuit that acquires an input signal of a frequency fin and generates an output signal of a frequency fout, where fout=fin / N, and where N is an integer. A clock divider may be a cheap and fast solution for providing multiple clock signals with different frequencies from a single clock signal.

[0033] The clock controller unit may include a plurality of input digital terminals connected from the digital register block. Figure 2 As shown in , digital control signals such as sw_src_cfg or sw_src_inv are connected to the input digital terminals of the clock controller unit and can be provided by the digital register block. The digital control signal can be connected to at least one clock switch unit and / or at least one edge delay controller unit. Figure 2 As shown in FIG. 1 , the digital control signal sw_src_inv is connected to the clock switch unit, and sw_dly_cfg is connected to the edge delay controller unit. The digital register block may have a serial communication interface connected to a system or a user.

[0034] The serial communication interface may be a serial communication bus, such as an inter-integrated circuit (I2C) serial bus protocol, a serial peripheral interface (SPI) serial bus protocol, a system management bus (SMBus), a power management bus (PMBus), an adaptive voltage scaling bus (AVSBus), or a USB protocol. Using a serial communication bus, data bits are transmitted one at a time in a sequential manner on a data bus or communication channel. Parallel communication, such as a small computer system interface (SCSI) or a peripheral component interconnect (PCI), may also be used. Due to the inherent disadvantages of the architecture of parallel communication, such as crosstalk, the number of cables used, or possible clock deviations, serial communication is generally preferred.

[0035] At least one clock switch unit may include a multiplexer and an XOR gate. Figure 2 As shown in , the XOR gate can be configured to provide a 180 degree phase shift to the individual clock signals from the multiplexer by effectively inverting the clock signals. The 180 degree phase shift can also be configured by using other types of logic gate configurations. Due to the unique control signal consisting of one bit, the XOR gate can present the benefit of providing a 180 degree phase shift. If the unique control signal is set to a low digital state, the individual clock signals are output from the XOR gate without a phase shift. If the unique control signal is set to a high digital state, the individual clock signals are output from the XOR gate with a 180 degree phase shift.

[0036] The at least one edge delay controller may further include a delay unit and an AND gate, wherein the delay unit and the AND gate may be configured to implement edge delays of the individual clock signals. Figure 3B An embodiment of a clock generation scheme for a single inductor hybrid switched capacitor DC-DC converter topology is shown. The switching phase generated p 1. p1n, p2 and p2n are all derived from the clock signals clka, clkb, clka and clkb, where clka and clkb are the inverse of clka and clkb respectively, and as Figure 3AAs shown in . Some edge delays are shown, such as tdr1, which is the edge delay from the falling edge of clkb (corresponding to the rising edge of clkb) to the rising edge of the sw1 signal, and the sw1 signal is individually configured to have a shape of p2n switching phase. Tdr2 is the edge delay from the falling edge of clkb (corresponding to the rising edge of clkb) to the rising edge of the sw2 clock signal, and the sw2 clock signal is individually configured to have a shape of p2n switching phase. Tdr4 is the edge delay from the rising edge of clkb to the rising edge of the sw4 clock signal, and the sw4 clock signal is individually configured to have a shape of p2 switching phase. All edge delays, namely tdr0-tdr7, can be generated independently.

[0037] Figure 4A -D shows a schematic diagram of an embodiment of a single inductor hybrid switched capacitor DC-DC converter topology and some associated clock generation schemes for different switching phases. Figure 4A Schematic diagram of an embodiment of a single inductor hybrid topology and an associated clock generation scheme is shown. The power switches sw0-sw7 are controlled by different clock signals. Figure 4A As shown in , the duty cycle of the switching phases p1 and p2 is different from the duty cycle of p1n and p2n. Some clock edge delays are implemented between p1 and p1n and between p2 and p2n, namely tdr0-tdr7. Tdr1, tdr2, tdr4 and tdr6 are implemented to avoid the potential risk of having p2 and p2n in the same state. Tdr0, tdr3, tdr5 and tdr7 are implemented to avoid the potential risk of having p1 and p1n in the same state. Figure 4B -D shows a schematic diagram of an embodiment of a single inductor hybrid switched capacitor DC-DC converter topology in different switching states. The associated diagrams with different clock signals show which power switches are turned off and which power switches are not turned off. Figure 4B The switching state is shown when the switching phases p1 and p2n are closed and the others are open. Figure 4C The switching state is shown when the switching phases p1n and p2n are closed and the others are open. Figure 4D The switching state is shown when the switching phases p1n and p2 are closed and the others are open.

[0038] The edge delay may be a rising edge delay and / or a falling edge delay. The edge delay may be between 0% and 25% of a single clock signal period, preferably between 0% and 5% of a single clock signal period. A single clock signal period is a period of a single clock signal.

[0039] The programmable gate driver array for a switched capacitor DC-DC converter can have a DC input voltage between 12 and 400 V, preferably between 36 and 60 V. It can be configured for step-up and step-down DC-DC conversion, where the DC input voltage can be lower or higher than the DC output voltage, with many possible DC-DC conversion ratios, depending on the programmable gate driver array configuration. The architecture of multiple gate drivers can allow the system or user to use a wide range of DC input voltages.

[0040] In another aspect, a switched capacitor DC-DC converter is disclosed. The switched capacitor DC-DC converter may include a programmable gate driver array for a switched capacitor DC-DC converter as described above, a plurality of flying capacitors connected to a plurality of flying capacitor terminals, and a plurality of power switches connected to a plurality of power switch terminals. The programmable gate driver array may be arranged with a plurality of flying capacitors and a plurality of power switches to perform switched capacitor DC-DC conversion using separate control of the plurality of power switches.

[0041] Multiple power switches and multiple flying capacitors can be configured to perform various power conversions, such as Dickson type power conversion, such as Dickson 1 / 4 or Dickson 1 / 6. Other variations of power conversion, such as Ladder 1 / 3, Divider 1 / 2, or Ladder 1 / 5, can also be performed. Multiple power switches and multiple flying capacitors can also be configured in a single inductor hybrid converter (SIHC) configuration. Figure 4AAs shown in , an inductor is connected to a flying capacitor through switches sw1, sw3 and sw4. This enables a hybrid configuration of a switched capacitor DC-DC converter. The hybrid configuration can add some benefits to a switched capacitor DC-DC converter without an inductor. Depending on where at least one inductor is placed, a hybrid switched capacitor converter can be classified as resonant or soft charging. Adding at least one inductor in series with multiple flying capacitors produces a resonant topology. Adding at least one inductor with an inductor terminal connected to the converter input, output, ground / reference terminal or intermediate DC bus produces a soft charging converter. In a resonant switched capacitor DC-DC converter, an inductor is added in series with at least one flying capacitor to produce a resonant LC tank circuit with low impedance at a given resonant frequency. The inductor will have zero DC current because it is connected in series with one or more capacitors. The resonant configuration allows a smaller capacitor to be used in conjunction with one or more inductors. Depending on the available capacitor and inductor technology for implementing the passive components of the converter, it may be beneficial to use a resonant topology (such as a switched tank converter) in some cases to utilize a combination of inductors and capacitors rather than just capacitors to achieve certain converter performance. In addition, the resonant switched capacitor power converter has approximately sinusoidal current and voltage waveforms, which have lower high-frequency spectral energy than the approximately square-wave waveforms of the switched capacitor power converter without an inductor. This may be beneficial in some applications, however the benefit is a trade-off with a larger radiated magnetic field from the inductor, which is not a problem in the switched capacitor power converter without an inductor.

[0042] In one embodiment, at least one of the plurality of power switches is a segmented switch, comprising a plurality of switch segments. The segmentation of the plurality of power switches can allow safe startup of the switched capacitor DC-DC converter by possibly limiting the inrush current, which is caused by the presence of a plurality of low impedance loops in the switched capacitor DC-DC converter. Secondly, the segmentation of the power switch can allow the system or user to enable only some of the switch segments, thus limiting the power consumption of the switched capacitor DC-DC converter. If the output load requires a small current, only a few switch segments may be required. For example, in the case where the switched capacitor DC-DC converter is supplying power to the CPU, if the CPU is in throttling mode, it does not require as much current as when it can be configured in normal mode, where more current may be required.

[0043] Figure 5A -C shows a schematic diagram of an embodiment of a two-phase Dickson switched capacitor DC-DC converter topology with segmented power switches and some associated clock generation schemes. Figure 5AA schematic diagram of an embodiment of a two-phase Dickson switched capacitor DC-DC converter topology is shown, in which eight power switches are segmented. Each power switch includes three switch segments, where each switch segment is controlled by a separate clock signal. For example, clk7[2:0] is a bus of 3 independent clock signals. The same applies to the rest of the bus, such as clk6, clk5, clk4, clk3, clk2, clk1, or clk0. Figure 5B Shown with Figure 5A 0048 ] The clock generation scheme associated with the first switching segment in each of the eight power switches shown in . Figure 5C An example of edge delay between switching segments of one of the power switches (i.e., the power switch controlled by clk0[2:0]) is shown. Figure 5C As shown in , three switch segments can be enabled at different times, each of which has a different edge delay, such as tds1 or tds2, compared to the reference clock signal (i.e., clk0[0]. In this case, the switch segments can be used for charge recycling and reduce electromagnetic interference caused by switching.

[0044] A plurality of power switches may be provided on an external semiconductor die. The external semiconductor die may be manufactured using a semiconductor process optimized for power transistor implementations. These semiconductor processes optimized for power transistor implementations may use a vertical transistor structure, in which the transistor drain-source terminals are arranged on opposite sides of the transistor die. This may be beneficial for high voltage power transistor implementations, but may not be beneficial for advanced analog and digital circuits (preferably designed for low power consumption). In addition, power transistors may benefit from possible implementations using high electron mobility materials such as GaN or SiC. Semiconductor processes based on such materials may not be suitable for implementing p-type transistors, which may be required for implementing digital logic circuits using complementary metal oxide semiconductor (CMOS) technology. External semiconductor dies may also be optimized to implement advanced analog and digital circuits, such as level shifters, gate drivers, clock generation circuits, clock controllers, linear voltage regulators, or temperature sensors. Semiconductor processes optimized for advanced analog and digital circuits may require more processing steps and photomasks to achieve a wider selection of electronic components. In order to support a possible wider selection of electronic components, a trade-off must be made in semiconductor material features, which may reduce the performance of power transistors implemented using the same semiconductor process.

[0045] Fig. 6A -D shows a schematic diagram of embodiments of a single inductor hybrid switched capacitor DC-DC converter topology with external switches and some associated clock generation schemes for different switching phases. Fig. 6AA schematic diagram of a single-inductor hybrid topology with an external switch and the associated clock generation scheme is shown. Figure 6B A schematic diagram of an embodiment of a single inductor hybrid switched capacitor DC-DC converter topology is shown with four switches closed and the remaining switches open. Figure 6B The associated clock generation scheme is also shown, with the first switching phase highlighted in grey. Two clocks clka and clkb are generated, as well as their inverses clka and clkb. From these four clock signals, all switch drive signals, namely tdr0-tdr7 and tdr0e, are generated with different and independent edge delays. The clock signal controlling the external switch SW0E is generated by the logical combination of clka and clkb, clkaORclkb, because the frequency of interest is twice the frequency of clka or clkb. In this first switching state, switches SW1, SW2, SW5 and SW7 are closed, while the other switches are open. Figure 6C -D shows the Figure 6B Schematic diagram of an embodiment of a single inductor hybrid topology in different switching states. Figure 6C A second switching state is shown, in which the external switches SW0E and SW0 - SW3 are closed, while the other switches are open. Fig.6D A third switching state is shown, in which switches SW0 , SW3 , SW4 and SW6 are closed, while the other switches are open. Figure 6B -D shows different switching phases of a single inductor hybrid switched capacitor DC-DC converter topology including an external switch. As can be seen on different clock generation schemes, each of the switches can be independently controlled by a unique clock signal that is generated from the clock signal and includes independent edge delays. Fig. 6A -D, the rising edge delay tdr0e can be configured to be greater than tdr1 and tdr2 to minimize the dv / dt at the switch node by turning off SW1 and SW2 before the low impedance SW0E turns off.

[0046] Fig. 7A -B shows a schematic diagram of an embodiment of a two-phase Dickson switched capacitor DC-DC converter topology and an associated clock generation scheme for parasitic charge recycling. Fig. 7AA schematic diagram of an embodiment of a two-phase Dickson switched capacitor DC-DC converter topology is shown. It includes eight switches SW0-SW7, three flying capacitors C1A-C1AA-C1B, and two parasitic capacitors CpA and CpB. The two parasitic capacitors can generally be smaller than the flying capacitors. These parasitic capacitors CpA and CpB can be charged and discharged in each switching cycle of the switched capacitor DC-DC converter. The charging and discharging of the parasitic capacitors cause undesirable parasitic losses. The parasitic capacitors can be charged and discharged through different loops, depending on which power switches are closed or opened. By controlling the timing of each of the multiple power switches, parasitic losses can be reduced. A decoupling capacitor is also arranged to filter the DC output voltage Vout. Figure 7B An example of a clock generation scheme for a two-phase Dickson switched capacitor DC-DC converter topology is shown in order to potentially optimize the efficiency of the switched capacitor DC-DC converter. Dead time is implemented by delaying the rising edge of the power switch in a given switching phase in order to give the power switch enough time to fully turn on or off. Due to their physical implementation, the power switches controlled by p1 or p2 may not be turned off or on at the same time. This effect may cause the parasitic capacitance to charge and / or discharge through the power switch that is turned off first, and that power switch may not be the most efficient power switch for recycling parasitic losses in the best possible manner. Therefore, according to the clock signal clk, Fig. 7A Each of the multiple power switches SW0-SW7 shown in generates multiple clock signals. For example, SW7 is controlled by a clock signal having an edge delay tdr7 after the rising edge of the clock signal clk. SW6 is controlled by a clock signal having an edge delay tdr6 after the falling edge of the clock signal. Figure 7B Each edge delay shown in can be independently generated by the clock controller, and they can potentially be different from each other.

[0047] In another aspect, a method for performing individual clock control of a programmable gate driver array for a switched capacitor DC-DC converter is disclosed. The method includes the following steps: providing a programmable gate driver array for a switched capacitor DC-DC converter, comprising at least one input terminal, a plurality of power switch terminals connectable to a plurality of power switches, the plurality of power switches configured to convert a DC input voltage from the at least one input terminal to a DC output voltage through switched capacitor power conversion, a plurality of gate drivers configured to drive the plurality of power switch terminals, a clock controller unit, wherein the clock controller unit is configured to perform individual clock control of the plurality of gate drivers; and performing clock control of the programmable switch array for switched capacitor DC-DC conversion by using the clock controller unit.

[0048] Figure 8 A flow chart of a currently disclosed method (800) for performing individual clock control of a programmable gate driver array for a switched capacitor DC-DC converter is shown. The method includes the steps of providing a programmable gate driver array for a switched capacitor DC-DC converter (801), and performing individual clock control of the programmable gate driver array for the switched capacitor DC-DC converter (802).

[0049] Further details of the invention

[0050] 1. A programmable gate driver array for a switched capacitor DC-DC converter, comprising:

[0051] at least one input terminal;

[0052] a plurality of power switch terminals connectable to a plurality of power switches configured to convert a DC input voltage from the at least one input terminal to a DC output voltage via switched capacitor DC-DC conversion;

[0053] a plurality of gate drivers configured to drive the plurality of power switch terminals; and

[0054] Clock controller unit;

[0055] Wherein, the clock controller unit is configured to perform individual clock control of the plurality of gate drivers.

[0056] 2. A programmable gate driver array for a switched capacitor DC-DC converter according to item 1, wherein the plurality of power switch terminals are independently controlled by the plurality of gate drivers.

[0057] 3. A programmable gate driver array for a switched capacitor DC-DC converter according to any of the preceding items, wherein the separate clock control configuration is used to select a separate clock signal from a plurality of clock signals, the separate clock signal having a clock frequency, a clock duty cycle and / or a clock edge delay.

[0058] 4. A programmable gate driver array for a switched capacitor DC-DC converter according to item 3, wherein the separate clock signal is a digital clock signal that oscillates between a high state and a low state.

[0059] 5. A programmable gate driver array for a switched capacitor DC-DC converter according to item 3, wherein the clock frequency is between 1 Hz and 10 MHz, preferably between 50 kHz and 5 MHz.

[0060] 6. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of the preceding clauses, wherein the clock controller unit comprises at least one clock switch unit and at least one edge delay controller unit.

[0061] 7. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of the preceding items, wherein the clock controller unit further comprises at least one clock input terminal and at least one clock output terminal connectable to the plurality of gate drivers.

[0062] 8. The programmable gate driver array for a switched capacitor DC-DC converter according to item 7, wherein the at least one clock input terminal is connected to a clock generator.

[0063] 9. The programmable gate driver array for a switched capacitor DC-DC converter according to item 8, wherein the clock generator is a voltage controlled oscillator or a ring oscillator.

[0064] 10. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of items 8 or 9, wherein the clock generator further comprises a phase locked loop (PLL) and / or a clock divider.

[0065] 11. A programmable gate driver array for a switched capacitor DC-DC converter according to any of the preceding items, wherein the clock controller unit further comprises a plurality of input digital terminals connected from a digital register block to the at least one clock switch unit and / or the at least one edge delay controller unit.

[0066] 12. A programmable gate driver array for a switched capacitor DC-DC converter according to item 11, wherein the digital register block has a serial communication interface.

[0067] 13. A programmable gate driver array for a switched capacitor DC-DC converter according to item 12, wherein the serial communication interface is an I2C serial communication bus.

[0068] 14. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of the preceding clauses, wherein the at least one clock switch unit comprises a multiplexer and an XOR gate.

[0069] 15. A programmable gate driver array for a switched capacitor DC-DC converter according to item 14, wherein the XOR gate is configured to provide a 180 degree phase shift to the separate clock signal.

[0070] 16. A programmable gate driver array for a switched capacitor DC-DC converter according to any of the preceding items, wherein the at least one edge delay controller unit further comprises a delay unit and an AND gate, wherein the delay unit and the AND gate are configured to implement edge delay of the separate clock signal.

[0071] 17. The programmable gate driver array for a switched capacitor DC-DC converter according to item 16, wherein the edge delay is a rising edge delay and / or a falling edge delay.

[0072] 18. A programmable gate driver array for a switched capacitor DC-DC converter according to any of the preceding items, wherein the edge delay is between 0% and 25% of a single clock signal period, preferably between 0% and 5% of a single clock signal period.

[0073] 19. A programmable gate driver array for a switched capacitor DC-DC converter according to any of the preceding clauses, wherein the individual clock signal period is a period of the individual clock signal.

[0074] 20. A programmable gate driver array for a switched capacitor DC-DC converter according to any of the preceding items, wherein the DC input voltage is between 12 and 400V, preferably between 36 and 60V.

[0075] 21. A switched capacitor DC-DC converter comprising:

[0076] A programmable gate driver array for a switched capacitor DC-DC converter according to item 1-20;

[0077] a plurality of flying capacitors connected to the plurality of flying capacitor terminals; and

[0078] a plurality of power switches connected to the plurality of power switch terminals;

[0079] The programmable gate driver array is arranged with the plurality of flying capacitors and the plurality of power switches to perform switched capacitor DC-DC conversion with individual clock control of the plurality of power switches.

[0080] 22. The switched capacitor DC-DC converter according to item 21, wherein the plurality of power switches and the plurality of flying capacitors are configured to perform DC-DC conversion in a Dickson 1 / 4 or Ladder 1 / 5 or Dickson 1 / 6 configuration.

[0081] 23. A switched capacitor DC-DC converter according to any one of items 21 or 22, wherein at least one of the plurality of power switches is a segmented switch comprising a plurality of switch segments.

[0082] 24. A switched capacitor DC-DC converter according to any one of items 21-23, wherein the plurality of power switches are disposed on an external semiconductor die.

[0083] 25. A method for performing individual clock control of a programmable gate driver array for a switched capacitor DC-DC converter, comprising the steps of:

[0084] A programmable gate driver array for a switched capacitor DC-DC converter is provided, comprising:

[0085] at least one input terminal;

[0086] a plurality of power switch terminals connectable to a plurality of power switches configured to convert a DC input voltage from the at least one input terminal to a DC output voltage via switched capacitor DC-DC conversion;

[0087] a plurality of gate drivers configured to drive the plurality of power switch terminals;

[0088] a clock controller unit, wherein the clock controller unit is configured to perform individual clock control of the plurality of gate drivers; and

[0089] Individual clock control of a programmable gate driver array for a switched capacitor DC-DC converter is performed by using the clock controller unit.

[0090] 26. A method for performing separate clock control of a programmable gate driver array for a switched capacitor DC-DC converter according to item 25, wherein the programmable gate driver array is a programmable gate driver array for a switched capacitor DC-DC converter according to items 1-20.

Claims

1. A programmable gate driver array for a switched capacitor DC-DC converter, comprising: at least one input terminal; a plurality of power switch terminals connectable to a plurality of power switches configured to convert a DC input voltage from the at least one input terminal to a DC output voltage via switched capacitor DC-DC conversion; a plurality of gate drivers configured to drive the plurality of power switch terminals; as well as Clock controller unit; wherein the clock controller unit is configured to perform individual clock control of the plurality of gate drivers, wherein the clock controller unit generates individual clock signals to the gate drivers, and wherein the clock controller is further configured to generate individual edge delays on the individual clock signals.

2. The programmable gate driver array for a switched capacitor DC-DC converter according to claim 1, wherein: The plurality of power switch terminals are independently controlled by the plurality of gate drivers.

3. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of the preceding claims, wherein: The individual clock control configuration is used to select an individual clock signal from a plurality of clock signals, the individual clock signal having a clock frequency, a clock duty cycle and / or a clock edge delay.

4. The programmable gate driver array for a switched capacitor DC-DC converter according to claim 3, wherein: The clock frequency is between 1 Hz and 10 MHz, preferably between 50 kHz and 5 MHz.

5. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of the preceding claims, wherein: The clock controller unit includes at least one clock switch unit and at least one edge delay controller unit.

6. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of the preceding claims, wherein: The at least one clock switch unit includes a multiplexer and an XOR gate.

7. The programmable gate driver array for a switched capacitor DC-DC converter according to claim 6, wherein: The XOR gate is configured to provide a 180 degree phase shift to the separate clock signal.

8. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of the preceding claims, wherein: The at least one edge delay controller unit further comprises a delay unit and an AND gate, wherein the delay unit and the AND gate are configured to implement an edge delay of the separate clock signal.

9. The programmable gate driver array for a switched capacitor DC-DC converter according to claim 8, wherein: The edge delay is a rising edge delay and / or a falling edge delay, and wherein the edge delay is between 0% and 25% of a single clock signal period, preferably between 0% and 5% of a single clock signal period.

10. A programmable gate driver array for a switched capacitor DC-DC converter according to any one of the preceding claims, wherein: The DC input voltage is between 12 and 400V, preferably between 36 and 60V.

11. A switched capacitor DC-DC converter comprising: A programmable gate driver array for a switched capacitor DC-DC converter according to claims 1-10; a plurality of flying capacitors connected to the plurality of flying capacitor terminals; as well as a plurality of power switches connected to the plurality of power switch terminals; The programmable gate driver array is arranged with the plurality of flying capacitors and the plurality of power switches to perform switched capacitor DC-DC conversion with individual clock control of the plurality of power switches.

12. The switched capacitor DC-DC converter according to claim 11, wherein: At least one of the plurality of power switches is a segmented switch including a plurality of switch segments.

13. The switched capacitor DC-DC converter according to any one of claims 11 or 12, wherein: The plurality of power switches are disposed on an external semiconductor die.

14. A method for performing individual clock control of a programmable gate driver array for a switched capacitor DC-DC converter, the method comprising the steps of: A programmable gate driver array for a switched capacitor DC-DC converter is provided, the programmable gate driver array comprising: at least one input terminal; a plurality of power switch terminals connectable to a plurality of power switches configured to convert a DC input voltage from the at least one input terminal to a DC output voltage via switched capacitor DC-DC conversion; a plurality of gate drivers configured to drive the plurality of power switch terminals; a clock controller unit, wherein the clock controller unit is configured to generate a separate clock signal to the gate driver, and wherein the clock controller is further configured to generate a separate edge delay on the separate clock signal; and Individual clock control of the programmable gate driver array for a switched capacitor DC-DC converter is performed by using the clock controller unit.

15. The method for performing individual clock control of a programmable gate driver array for a switched capacitor DC-DC converter according to claim 14, wherein: The programmable gate driver array is a programmable gate driver array for a switched capacitor DC-DC converter according to claims 1-10.

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