Stacked random access memory with complementary adjacent cells

Abstract

A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans the first layer and the second layer. The second layer is vertically stacked on the first layer. The first cell includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers. The second cell includes at least one of a plurality of NFETs on one of the first and second layers different from the number of NFETs in the first cell and a plurality of PFETs on the other of the first and second layers different from the number of PFETs in the first cell.

Description

Background Art

[0001] The present invention relates generally to methods of fabricating semiconductor devices and the resulting structures. More particularly, the present invention relates to stacked random access memories (RAMs) having complementary adjacent cells.

[0002] Semiconductor and integrated circuit (IC) chips have become ubiquitous in many products, especially as they continue to decrease in cost and size. Recently, it has been desirable to reduce the size of structural features and / or provide a greater number of structural features for a given chip size. This is because miniaturization generally allows for improved performance at lower power levels and lower costs. Current technology is at or near the atomic scale of some micro devices, such as logic gates, field effect transistors (FETs), and capacitors.

[0003] For example, a FET array in a given cell structure may have a word line and two bit lines, and may include a first and a second transistor, each of which is operably connected to the word line, one of which is operably connected to one of the bit lines, and the other of which is operably connected to another bit line. The first and second transistors may be provided as n-doped access transistors or NFETs. The array in a given cell may also include first and second pull-up transistors, which are operably inserted between the access transistors and connected to the voltage terminal. The first and second pull-up transistors may be provided as p-doped pull-up transistors or PFETs. The array in a given cell may also include first and second pull-down transistors, which are operably inserted between the access transistors and connected to the ground terminal. The first and second pull-down transistors may be provided as NFETs.

[0004] The above cell structure may be provided as a static RAM cell structure or SRAM.

[0005] For the above cell structure, there are obviously four total NFETs and two total PFETs. In conventional designs, the arrangement of these four total NFETs and two total PFETs is not optimized for space considerations and other issues. This creates a problem of achieving the desired level of miniaturization. Summary of the invention

[0006] Embodiments of the present invention relate to a field effect transistor (FET) cell structure of an integrated circuit (IC). A non-limiting example of a FET cell structure includes a first and a second adjacent cell. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers. The second cell includes at least one of a plurality of NFETs on one of the first and second layers that is different in number from the NFETs in the first cell and a plurality of PFETs on the other of the first and second layers that is different in number from the PFETs in the first cell.

[0007] The first and second units are vertically complementary to each other, which allows the first and second units to mate adjacently in an optimized manner. This optimized adjacency allows for a desired level of miniaturization of the IC.

[0008] According to one or more additional or alternative embodiments of the present invention, the first and second units are vertically complementary.

[0009] According to one or more additional or alternative embodiments of the present invention, the first cell may have four NFETs and the second cell may have two NFETs, or more specifically, the first cell may have four NFETs and two PFETs and the second cell may have two NFETs and four PFETs.

[0010] According to one or more additional or alternative embodiments of the present invention, the first and second units are of the same functional type or are individually operable.

[0011] According to one or more additional or alternative embodiments of the present invention, the IC further includes first and second bit lines having different bit line voltage precharge capabilities, the first bit line being associated with the first cell and the second bit line being associated with the second cell.

[0012] According to one or more additional or alternative embodiments of the invention, the IC further comprises first and second bit lines, the first bit line being associated with the front side or the back side of the first cell and the second bit line being associated with the back side or the front side of the second cell.

[0013] According to one or more additional or alternative embodiments of the invention, the IC further includes first and second different word lines having different word line voltages, the first word line being associated with the first cell and the second word line being associated with the second cell.

[0014] According to one or more additional or alternative embodiments of the present invention, each of the first and second adjacent cells includes one or more additional layers, and each of the first and second cells further includes a complementary number of NFETs and PFETs on the one or more additional layers.

[0015] Embodiments of the present invention relate to a field effect transistor (FET) cell structure of an integrated circuit (IC). A non-limiting example of a FET cell structure includes a first and a second cell, each cell spanning a first layer and a second layer vertically stacked on the first layer. The first cell includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers. The second cell includes at least one of a plurality of NFETs on one of the first and second layers that is different in number from the NFETs in the first cell and a plurality of PFETs on the other of the first and second layers that is different in number from the PFETs in the first cell. The FET cell structure also includes additional electronic devices on the first and second layers and inserted between the first and second cells. The first and second cells and the additional electronic devices are vertically complementary.

[0016] In case the first and second units and the additional electronic devices are vertically complementary to each other, the first and second units and the additional electronic devices can be fitted adjacently in an optimized manner. This optimized adjacency allows for a desired level of miniaturization of the IC.

[0017] According to one or more additional or alternative embodiments of the invention, the additional electronics are shared between the first and second units.

[0018] Embodiments of the present invention relate to a cell structure of an integrated circuit (IC). A non-limiting example of a cell structure includes first and second vertically complementary and adjacent cells, each cell spanning a first layer and a second layer vertically stacked on the first layer. The first cell includes a first electronic device on one of the first and second layers and a second electronic device on the other of the first and second layers. The second cell includes at least one of a plurality of first electronic devices on one of the first and second layers that is different in number from the first electronic device in the first cell and a plurality of second electronic devices on the other of the first and second layers that is different in number from the second electronic device in the first cell.

[0019] In the case where the first and second units are vertically complementary to each other, the first and second units can be mated adjacently in an optimized manner. This optimized adjacency allows for a desired level of miniaturization of the IC.

[0020] According to one or more additional or alternative embodiments of the present invention, the first electronic device includes an n-doped field effect transistor (NFET) and the second electronic device includes a p-doped field effect transistor (PFET).

[0021] According to one or more additional or alternative embodiments of the present invention, the cell structure is a static random access memory (SRAM) cell, the first electronic device includes a transistor, and the second electronic device includes a resistor.

[0022] According to one or more additional or alternative embodiments of the present invention, the cell structure is a ternary content addressable memory (TCAM) cell, the first electronic device includes a transistor, and the second electronic device includes a capacitor.

[0023] According to one or more additional or alternative embodiments of the present invention, the first and second units are of the same functional type or are individually operable.

[0024] According to one or more additional or alternative embodiments of the present invention, the cell structure further includes first and second bit lines having different bit line voltage precharge capabilities, the first bit line being associated with the first cell and the second bit line being associated with the second cell.

[0025] According to one or more additional or alternative embodiments of the present invention, the cell structure further comprises first and second bit lines, the first bit line being associated with the front side or the back side of the first cell and the second bit line being associated with the back side or the front side of the second cell.

[0026] According to one or more additional or alternative embodiments of the present invention, the cell structure further includes first and second different word lines having different word line voltages, the first word line being associated with the first cell and the second word line being associated with the second cell.

[0027] Additional technical features and benefits are achieved through the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, reference is made to the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The details of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a schematic circuit diagram of a memory cell according to one or more embodiments of the present invention;

[0030] Figure 2 is a schematic diagram of a FET cell structure according to one or more embodiments of the present invention;

[0031] Figure 3 According to one or more embodiments of the present invention Figure 2 Detailed schematic diagram of the FET unit structure;

[0032] Figure 4 is a schematic diagram of a FET cell structure with additional electronics according to one or more embodiments of the present invention;

[0033] Figure 5 is a schematic diagram of a first type of static random access memory (SRAM) cell structure according to one or more embodiments of the present invention;

[0034] Figure 6 is a schematic diagram of a second type of static random access memory (SRAM) cell structure according to one or more embodiments of the present invention; and

[0035] Figure 7 is a schematic diagram of a ternary content addressable memory (TCAM) cell structure according to one or more embodiments of the present invention.

[0036] The figures described herein are illustrative. Many variations may be made to the figures or operations described therein without departing from the scope of the present invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. In addition, the term "coupled" and variations thereof describe having a communication path between two elements, and do not imply a direct connection between elements without an intermediate element / connection between them. All of these variations are considered part of the specification.

[0037] In the drawings and the following detailed description of the embodiments, various elements shown in the drawings have two or three-digit reference numerals. With minor exceptions, the leftmost digit of each reference numeral corresponds to the figure in which its element is first shown. DETAILED DESCRIPTION

[0038] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, the various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and thus, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0039] Turning now to an overview of aspects of the present invention, one or more embodiments of the present invention address the above-mentioned shortcomings and problems of the prior art by providing a stacked cell structure of an SRAM, for example, with complementary adjacent cells. This allows the arrangement of the number of NFETs and PFETs in the cell structure to be optimized for space considerations and facilitates achieving a desired level of miniaturization.

[0040] The above aspects of the present invention address the shortcomings of the prior art by providing a FET cell structure for an IC. The FET cell structure includes first and second adjacent cells, each cell spanning a first layer and a second layer vertically stacked on the first layer. The first cell includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers. The second cell includes a PFET on one of the first and second layers and an NFET on the other of the first and second layers.

[0041] As used herein, the terms FET, NFET, and PFET may be used interchangeably with VTFET, FINFET, nanosheet FET, etc., or combinations thereof. However, for the purposes of clarity and brevity, the terms FET, NFET, and PFET will be used.

[0042] Turning now to a more detailed description of aspects of the present invention, Figure 1 A memory cell structure 101 having a transistor array is depicted. The memory cell structure 101 has a word line 102 and two bit lines 103, and includes a first transistor 104 and a second transistor 105 each operably connected to the word line 102. One of the first and second transistors 104 and 105 is operably connected to one of the bit lines 103, and the other is operably connected to the other of the bit lines 103. The first and second transistors 104 and 105 may be provided as n-doped access transistors or NFETs. The transistor array in the memory cell structure 101 may further include a first pull-up transistor 106 and a second pull-up transistor 107, which are operably inserted between the first transistor 104 and the second transistor 105 and connected to voltage terminals 108 and 109. The first and second pull-up transistors 106 and 107 may be provided as p-doped pull-up transistors or PFETs. The transistor array in the memory cell structure 101 may also include first and second pull-down transistors 110 and 111 operably inserted between the first and second transistors 104 and 105 and connected to ground terminals 112 and 113. The first and second pull-down transistors 110 and 111 may be provided as NFETs.

[0043] refer to Figure 2 , Figure 1 The transistor array in the memory cell structure 101 may be arranged together with additional transistor arrays in additional memory cell structures (other types of cell structures) in the IC in the FET cell structure 201 .

[0044] The FET cell structure 201 includes a first cell 210 in which a transistor array is provided and a second cell 220 in which a transistor array is provided. The first cell 210 and the second cell 220 are adjacent, and each of the first cell 210 and the second cell 220 spans a first layer 230 and a second layer 231. The second layer 231 is vertically stacked on the first layer 230 within the IC. The first cell 210 includes an NFET 211 on one of the first layer 230 and the second layer 231 and a PFET 212 on the other of the first layer 230 and the second layer 231. The second cell 220 includes an NFET 211 on one of the first layer 230 and the second layer 231 and a PFET 212 on the other of the first layer 230 and the second layer 231. In the second cell 220, the number of NFETs 211 on one of the first layers 230 is different from the number of NFETs 211 in the first cell 210. Similarly, in the second cell 220 , the number of PFETs 212 on the other of the first layer 230 and the second layer 231 is different from the number of PFETs 212 in the first cell 210 .

[0045] like Figure 2 As shown, due to their respective configurations, the first cell 210 and the second cell 220 of the FET cell structure 201 are vertically complementary at least along their respective inner sides.

[0046] Although Figure 2 2, but it is understood that the FET cell structure 201 may have one or more additional layers and one or more additional cells. The first and second cells 210 and 220 and the one or more additional cells may span the first and second layers 230 and 231 and the one or more additional layers. The one or more additional cells may be vertically complementary in configuration relative to the first and second cells 210 and 220 and relative to other additional cells at least along their respective inner sides.

[0047] refer to Figure 3 , showing in more detail Figure 2 FET unit structure 201. Figure 3 As shown, the first cell of the FET cell structure 201 may be provided as an NFET pass gate cell 301, and the second cell of the FET cell structure 201 may be provided as a PFET pass gate cell 302. The NFET pass gate cell 301 and the PFET pass gate cell 302 may be the same functional type, or they may be independently operable.

[0048] The NFET pass gate cell 301 and the PFET pass gate cell 302 are vertically complementary along at least their respective inner sides 301a and 302a. The FET cell structure 201 includes a first layer 303 and a second layer 304. The NFET pass gate cell 301 spans the first layer 303 and the second layer 304. The PFET pass gate cell 302 also spans the first layer 303 and the second layer 304. The FET cell structure 201 also includes a first bit line 310, a second bit line 320, and a word line 330. The first bit line 310 may be provided in a plurality of portions, including a first bit line portion 311 in the NFET pass gate cell 301, a second bit line portion 312 in the NFET pass gate cell 301, and a bit line bar 313. The second bit line 320 may similarly be provided in a plurality of portions, including a first bit line portion 321 and a bit line bar 322 in the PFET pass gate cell 302. The FET cell structure 201 may be fabricated on a back metal ground plane of the IC to form a ground terminal 340 and a ground terminal 341 in the NFET transmission gate cell 301 and the PFET transmission gate cell 302, respectively, and the FET cell structure 201 may also include a voltage terminal 342 and a voltage terminal 343 in the NFET transmission gate cell 301 and the PFET transmission gate cell 302, respectively.

[0049] According to one or more embodiments of the present invention, the first bit line 310 and the second bit line 320 may have different bit line voltage precharge capabilities. In addition, the first bit line 310 may be associated with the front side or the back side of the NFET transmission gate unit 301, and the second bit line 320 may be associated with the back side or the front side of the PFET transmission gate unit 302, or vice versa. In addition, the word line 330 may be provided as a plurality of or first and second different word lines having different word line voltages.

[0050] According to one or more embodiments of the present invention, the NFET transmission gate cell 301 may include two NFET transmission gates or access transistors 350 and 351 sandwiching two NFET pull-down transistors 352 and 353 on the first layer 303 (a total of four NFETs on the first layer 303), and two PFETs or pull-up transistors 354 and 355 on the second layer 304 (a total of two PFETs on the second layer 304). The two NFET transmission gates or access transistors 350 and 351 communicate with the first bit line portion 311 and the bit line bar 313, respectively, and the two NFET pull-down transistors 352 and 353 each communicate with the ground terminal 340. The two PFETs or pull-up transistors 354 and 355 communicate with the four NFETs on the first layer 303 and the voltage terminal 342. According to one or more further embodiments of the present invention, the PFET transmission gate unit 302 may include two NFET pull-down transistors 360 and 361 on the first layer 303 (a total of two NFETs on the first layer 303) and two PFET transmission gates or access transistors 362 and 363 on the second layer 304 sandwiching two PFET pull-up transistors 364 and 365 (a total of four PFETs on the second layer 304). The two NFET pull-down transistors 360 and 361 communicate with the four PFETs on the second layer 304 and the ground terminal 341. The two PFET transmission gates or access transistors 362 and 363 communicate with the second bit line portion 312 and the word line 330, and the two PFET pull-up transistors 364 and 365 communicate with the voltage terminal 343.

[0051] Therefore, one group of NFETs of the NFET pass gate unit 301 is an NFET pass gate, and another group of NFETs is an NFET pull-down gate, and one group of PFETs of the NFET pass gate unit 301 is a pull-up gate. Similarly, one group of PFETs of the PFET pass gate unit 302 is a PFET pass gate, and another group of PFETs is a pull-up gate, and one group of NFETs of the PFET pass gate unit 302 is a pull-down gate.

[0052] Although in Figure 3In the embodiment of the present invention, the NFET transmission gate cell 301 has a total of four NFETs on the first layer 303 (with two PFETs on the second layer 304), and the PFET transmission gate cell 302 has two NFETs on the first layer 303 (with a total of four PFETs on the second layer 304), but it should be understood that this is not required and other embodiments are possible. For example, as long as the NFET transmission gate cell 301 and the PFET transmission gate cell 302 remain vertically complementary, the number of NFETs and PFETs in the NFET transmission gate cell 301 and the PFET transmission gate cell 302 can be increased or decreased (i.e., the NFET transmission gate cell 301 and the PFET transmission gate cell 302 can have a 4 / 2:2 / 4 configuration, a 5 / 2:2 / 5 configuration, a 6 / 2:2 / 6 configuration, etc.). As another example, as described above, one or more additional layers may be present in the FET cell structure 201, and the NFET pass-gate cell 301 and the PFET pass-gate cell 302 may include additional NFETs and PFETs on the one or more additional layers (i.e., the NFET pass-gate cell 301 and the PFET pass-gate cell 302 may have a 6 / 4 / 2:2 / 4 / 6 configuration, an 8 / 5 / 2:2 / 5 / 8 configuration, a 10 / 6 / 2:2 / 6 / 10 configuration, etc.). In addition, the FET cell structure 201 may include one or more additional cell structures that may be configured similarly to the NFET pass-gate cell 301 and the PFET pass-gate cell 302 having a vertically complementary structure (i.e., the NFET pass-gate cell 301, the PFET pass-gate cell 302, and the additional cell structures may have a 4 / 2:2 / 4:4 / 2 configuration, a 5 / 2:2 / 5:5 / 2 configuration, a 6 / 2:2 / 6:6 / 2 configuration, etc.)

[0053] refer to Figure 4 According to one or more embodiments of the present invention, the FET cell structure 201 may further include additional electronic devices 401 on the first layer 303 and the second layer 304 and inserted between the NFET transmission gate cell 301 and the PFET transmission gate cell 302 (which need not be adjacent). These additional electronic devices 401 may be dummy electronic devices or functional electronic devices shared between the NFET transmission gate cell 301 and the PFET transmission gate cell 302. Figure 4 As shown, a corresponding number or size of additional electronic devices 401 may be provided on the first layer 303 and the second layer 304, so that the vertical complementary characteristics of the NFET pass gate cell 301 and the PFET pass gate cell 302 continue in the presence of the additional electronic devices 401. In other words, the NFET pass gate cell 301, the PFET pass gate cell 302, and the additional electronic devices 401 are vertically complementary.

[0054] Continue to refer Figure 2-4 And also refer to Figure 5-7 It will be appreciated that the above cell structure need not be limited to a FET cell structure, and other options and configurations are possible. That is, a cell structure of an integrated circuit (IC) is provided, and can be configured as a first type SRAM cell 501 (see Figure 5 ), the second type of SRAM cell 601 (see Figure 6 ) and TCAM cell 701 (see Figure 7 )

[0055] like Figure 5 As shown, the first type SRAM cell 501 includes first and second vertically complementary and adjacent cells 502 and 503, each cell spanning a first layer 504 and a second layer 505 vertically stacked on the first layer 504. The first cell 502 includes a first electronic device 510 on one of the first layer 504 and the second layer 505 and a second electronic device 520 on the other of the first layer 504 and the second layer 505. The second cell 503 includes at least one of a plurality of first electronic devices 510 on one of the first layer 504 and the second layer 505 that is different in number from the first cell 502 and a plurality of second electronic devices 520 on the other of the first layer 504 and the second layer 505 that is different in number from the first cell 502. According to an embodiment, the first electronic device 510 may include or be provided as an NFET, and the second electronic device 520 may include or be provided as a PFET.

[0056] like Figure 6 As shown, the second type SRAM cell 601 includes first and second vertically complementary and adjacent cells 602 and 603, each cell spanning a first layer 604 and a second layer 605 vertically stacked on the first layer 604. The first cell 602 includes a first electronic device 610 on one of the first layer 604 and the second layer 605 and a second electronic device 620 on the other of the first layer 604 and the second layer 605. The second cell 603 includes at least one of a plurality of first electronic devices 610 on one of the first layer 604 and the second layer 605, the number of which is different from that of the first electronic device 610 in the first cell 602, and a plurality of second electronic devices 620 on the other of the first layer 604 and the second layer 605, the number of which is different from that of the second electronic device 620 in the first cell 602. According to an embodiment, the first electronic device 610 may include or be provided as a transistor, and the second electronic device 620 may include or be provided as a resistor or a resistance element.

[0057] like Figure 7As shown, the second type TCAM cell 701 includes first and second vertically complementary and adjacent cells 702 and 703, each cell spanning a first layer 704 and a second layer 705 vertically stacked on the first layer 704. The first cell 702 includes a first electronic device 710 on one of the first layer 704 and the second layer 705 and a second electronic device 720 on the other of the first layer 704 and the second layer 705. The second cell 703 includes at least one of a plurality of first electronic devices 710 on one of the first layer 704 and the second layer 705, which is different in number from the first cell 702, and a plurality of second electronic devices 720 on the other of the first layer 704 and the second layer 705, which is different in number from the first cell 702. According to an embodiment, the first electronic device 710 may include or be provided as a transistor, and the second electronic device 720 may include or be provided as a capacitor or a capacitive element.

[0058] The technical benefits of one or more embodiments of the present invention described above enable the arrangement of multiple electronic devices in an IC, such as the number of NFETs and PFETs in a cell structure of an SRAM cell, to be optimized for space considerations, and facilitate achieving a desired level of miniaturization.

[0059] Various embodiments of the present invention are described herein with reference to the relevant drawings. Without departing from the scope of the present invention, alternative embodiments may be designed. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described in the following description and drawings, it will be appreciated by those skilled in the art that many positional relationships described herein are orientation-independent when the described functions are maintained even when the orientation is changed. Unless otherwise indicated, these connections and / or positional relationships may be direct or indirect, and the present invention is not intended to be limited in this regard. Therefore, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, it is mentioned in this specification that forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the relevant characteristics and functions of layer "A" and layer "B" are not substantially changed by the intermediate layer.

[0060] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "including," "having," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0061] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect "connected" and direct "connected."

[0062] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not include the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments.

[0063] For the purposes of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the described structures and methods as oriented in the accompanying drawings. The terms "overlying", "on top", "on top of", "positioned on" or "positioned on top" indicate that a first element, e.g., a first structure, is present on a second element, e.g., a second structure, wherein intermediate elements, e.g., an interface structure, may be present between the first element and the second element. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected without any intermediate conductive, insulating or semiconducting layer at the interface of the two elements.

[0064] For ease of description, spatially relative terms such as "below", "below", "below", "above", "on", etc. may be used here to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figure is turned over, the elements described as being "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the term "below" can include both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein are interpreted accordingly.

[0065] The phrase "selective to," for example, "a first element is selective to a second element," means that the first element may be etched while the second element may serve as an etch stop layer.

[0066] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time this application was filed. For example, "about" may include a range of ±8% or 5% or 2% of a given value.

[0067] The term "conformal" (eg, conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness varies by less than 15% of the nominal thickness of the layer.

[0068] The terms "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), wherein the grown semiconductor material (crystalline capping layer) has substantially the same crystal properties as the semiconductor material (seed material) of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gas can be controlled, and the system parameters can be set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move on the surface so that the deposited atoms orient themselves to the crystal arrangement of atoms of the deposition surface. The epitaxially grown semiconductor material may have substantially the same crystal properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} crystalline surface may exhibit a {100} crystalline orientation. In some embodiments of the present invention, the epitaxial growth and / or deposition process may be selectively formed on a semiconductor surface, and material may not be deposited on an exposed surface, such as a silicon dioxide or silicon nitride surface.

[0069] As previously described herein, for the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, as background, a more general description of a semiconductor device manufacturing process that can be used to implement one or more embodiments of the present invention will now be provided. Although the specific manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the combination of operations described and / or the resulting structure of the present invention are unique. Therefore, the unique combination of operations described in conjunction with the manufacture of semiconductor devices according to the present invention utilizes various individually known physical and chemical processes performed on semiconductor (e.g., silicon) substrates, some of which are described in the immediately following paragraphs.

[0070] Generally, the various processes for forming the microchips to be packaged into ICs are divided into four general categories, i.e., film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process for growing, coating, or otherwise transferring materials onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), etc. Removal / etching is any process for removing materials from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP), etc. Semiconductor doping is to change electrical properties by doping, such as transistor source and drain, usually by diffusion and / or by ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopants. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various areas of a semiconductor substrate allows the conductivity of the substrate to be changed as a voltage is applied. By forming structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate so that the pattern can be subsequently transferred to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated many times in order to build the complex structures that make up the transistors and the many wires that connect the millions of transistors of the circuit. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0071] Flowchart and block diagram in the accompanying drawings show the possible realization of manufacturing and / or operating method according to various embodiments of the present invention.The various functions / operations of the method are represented by blocks in the flow chart.In some alternative embodiments, the functions noted in the frame may not occur in the order noted in the figure.For example, two frames shown in succession can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, which depends on the function involved.

[0072] The description of various embodiments of the present invention has been given for the purpose of illustration, but it is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over existing technologies on the market, or to enable other persons of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A field effect transistor (FET) unit structure of an integrated circuit (IC), the FET unit structure comprising: a first unit and a second unit arranged adjacent to the first unit, each unit spanning a first layer and a second layer vertically stacked on the first layer, The first unit includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers, and The second unit includes at least one of the following: a plurality of NFETs on said one of said first and second layers different from the number of NFETs in said first cell; as well as A plurality of PFETs on the other of the first and second layers is different than the number of PFETs in the first cell.

2. The FET cell structure of claim 1, wherein the first and second cells are vertically complementary.

3. The FET cell structure of claim 1, wherein a group of NFETs of the first cell are NFET transmission gates and a group of PFETs of the second cell are PFET transmission gates.

4. The FET cell structure of claim 1, wherein the first cell has four NFETs and the second cell has two NFETs. 5 . The FET cell structure according to claim 4 , wherein the first cell has the four NFETs and two PFETs, and the second cell has the two NFETs and four PFETs.

6. The FET cell structure of claim 1, wherein the first and second cells are of the same functional type or are independently operable.

7. The FET cell structure of claim 1, further comprising first and second bit lines having different bit line voltage precharge capabilities, the first bit line being associated with the first cell and the second bit line being associated with the second cell.

8. The FET cell structure of claim 1, further comprising first and second bit lines, the first bit line being associated with a front side or a back side of the first cell, and the second bit line being associated with a back side or a front side of the second cell.

9. The FET cell structure of claim 1, further comprising first and second different word lines having different word line voltages, the first word line being associated with the first cell and the second word line being associated with the second cell.

10. The FET cell structure of claim 1, wherein: Each of the first and second adjacent cells includes one or more additional layers, and Each of the first and second cells further includes a complementary number of NFETs and PFETs on the one or more additional layers.

11. A field effect transistor (FET) unit structure of an integrated circuit (IC), the FET unit structure comprising: first and second units, each unit spanning a first layer and a second layer vertically stacked on the first layer, The first unit includes an n-doped FET (NFET) on one of the first and second layers and a p-doped FET (PFET) on the other of the first and second layers, and The second unit includes at least one of the following: a plurality of NFETs on said one of said first and second layers different from the number of NFETs in said first cell; as well as a plurality of PFETs on the other of the first and second layers that is different in number from the number of PFETs in the first cell; as well as additional electronic devices on the first and second layers and interposed between the first and second cells, The first and second units and the additional electronic device are vertically complementary.

12. The FET cell structure of claim 11, wherein the additional electronics are shared between the first and second cells.

13. A unit structure of an integrated circuit (IC), the unit structure comprising: first and second vertically complementary and adjacent cells, each cell spanning a first layer and a second layer vertically stacked on the first layer, The first unit includes a first electronic device on one of the first and second layers and a second electronic device on the other of the first and second layers, and The second unit includes at least one of the following: a plurality of first electronic devices on said one of said first and second layers that is different in number from the first electronic devices in said first unit; as well as A plurality of second electronic devices on the other of the first and second layers is different in number from the number of the second electronic devices in the first unit.

14. The cell structure of claim 13, wherein the cell structure is a static random access memory (SRAM) cell, the first electronic device comprises an n-doped field effect transistor (NFET), and the second electronic device comprises a p-doped field effect transistor (PFET).

15. The cell structure of claim 13, wherein the cell structure is a static random access memory (SRAM) cell, the first electronic device comprises a transistor, and the second electronic device comprises a resistor.

16. The cell structure of claim 13, wherein the cell structure is a ternary content addressable memory (TCAM) cell, the first electronic device comprises a transistor, and the second electronic device comprises a capacitor.

17. The unit structure according to claim 13, wherein the first and second units are of the same functional type or are independently operable.

18. The cell structure of claim 13, further comprising first and second bit lines having different bit line voltage precharge capabilities, the first bit line being associated with the first cell, and the second bit line being associated with the second cell.

19. The cell structure of claim 13, further comprising first and second bit lines, the first bit line being associated with a front side or a back side of the first cell, and the second bit line being associated with a back side or a front side of the second cell.

20. The cell structure of claim 13, further comprising first and second different word lines having different word line voltages, the first word line being associated with the first cell and the second word line being associated with the second cell.

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