Single gate three-dimensional (3D) dynamic random access memory (DRAM) device

Abstract

A memory cell array includes a plurality of memory stages stacked in a first direction, each of the plurality of memory stages including an active region, a cell transistor having a single gate over the active region in the first direction, and a cell capacitor having a bottom electrode layer electrically connected to the active region.

Description

Technical Field

[0001] Embodiments described herein relate generally to semiconductor device fabrication, and more particularly, to single-gate three-dimensional dynamic random access memory devices and methods of forming the same. Background Art

[0002] Three-dimensional (3D) dynamic random-access memory (DRAM) devices have manufacturability challenges due to their three-dimensional (3D) design and small size. As the number of vertical stacks of memory cells in a 3D DRAM device increases (e.g., due to an increase in chip density), the height of each vertical stack needs to be reduced. Typically, a 3D DRAM device includes individual memory cells, each of which includes a field-effect transistor (FET) having a dual-gate structure, in which two gates (and word lines connected to the two gates) are disposed on the sides of an active region along the direction of the vertical stack. However, such a structure has limitations in reducing the vertical height without increasing word line resistance or bit line capacitance.

[0003] Therefore, there is a need for a 3D DRAM device structure and method for fabricating such a 3D DRAM device structure that reduces the height of each vertical stack of memory cells without increasing wordline resistance or bitline capacitance. Summary of the invention

[0004] Embodiments of the present disclosure provide a memory cell array. The memory cell array includes a plurality of memory levels stacked along a first direction, each of the plurality of memory levels including an active region, a cell transistor having a single gate above the active region along the first direction, and a cell capacitor having a bottom electrode layer electrically connected to the active region.

[0005] An embodiment of the present disclosure provides a method for forming a cell transistor in a semiconductor memory device. The method includes depositing a stacking mold including a plurality of cell stacks, each cell stack including a thicker channel layer stacked along a first direction, a thicker sacrificial layer on the thicker channel layer, a thinner channel layer on the thicker sacrificial layer, and a thinner sacrificial layer on the thinner channel layer, forming a transistor slit through the stacking mold in the first direction, forming a first groove in the thicker sacrificial layer and a second groove in the thinner sacrificial layer from a sidewall of the transistor slit, partially filling the first groove with a first insulator layer and completely filling the second groove from a sidewall of the transistor slit, and removing the first insulator layer on the sidewall of the transistor slit and in the first groove.

[0006] An embodiment of the present disclosure provides a method for forming a cell capacitor in a semiconductor memory device. The method includes depositing a stacking mold including a plurality of cell stacks, each cell stack including a thicker channel layer stacked along a first direction, a thicker sacrificial layer on the thicker channel layer, a thinner channel layer on the thicker sacrificial layer, and a thinner sacrificial layer on the thinner channel layer, forming a transistor slit through the stacking mold along the first direction, forming a first opening in the thicker sacrificial layer and a second opening in the thinner sacrificial layer from a sidewall of the capacitor slit, partially filling the first opening with a spacer layer and completely filling the second opening from a sidewall of the capacitor slit, and removing the spacer layer on the sidewall of the capacitor slit and within the first opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description of the present disclosure briefly summarized above may be provided by reference to embodiments (some of which are illustrated in the accompanying drawings). However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and are therefore not to be considered as limiting the scope of the present disclosure, as the present disclosure may allow for other equally effective embodiments.

[0008] Figure 1A is a schematic diagram of a portion of a three-dimensional (3D) memory cell array of a dynamic random access memory (DRAM) cell according to one embodiment. Figure 1B is a schematic diagram of a dynamic random access memory cell.

[0009] Figure 2A is a top view of a portion of a semiconductor structure according to one embodiment. Figure 2B It is along Figure 2A A cross-sectional view of a portion of a semiconductor structure taken along line BB' is shown.

[0010] Figure 3 A process flow diagram of a method for forming a unit transistor in a semiconductor structure according to one embodiment is shown.

[0011] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Fig. 4I is corresponding to Figure 3 A cross-sectional view of a portion of a semiconductor structure at various states of the method.

[0012] Figure 5A and Figure 5B A process flow diagram of a method 500 is shown for Figure 3A unit capacitor is formed in a semiconductor structure formed by the method.

[0013] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H , Fig.6I , Figure 6J , Figure 6K , Figure 6L , Figure 6M , Figure 6N and Fig.6O 5 are cross-sectional views of a portion of a semiconductor structure at various states corresponding to the method of FIG. 5 .

[0014] For ease of understanding, where possible, the same reference numerals are used to represent the same elements as the accompanying drawings. It should be envisioned that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further elaboration. In the accompanying drawings and the following description, an orthogonal coordinate system including an X-axis, a Y-axis, and a Z-axis is used. For convenience, the direction represented by the arrow in the figure is represented as the positive direction. It can be expected that the disclosed elements in some embodiments can be beneficially used in other embodiments without specific elaboration. DETAILED DESCRIPTION

[0015] Embodiments described herein provide a single-gate three-dimensional (3D) dynamic random access memory (DRAM) device and a method for forming a cell transistor and a cell capacitor in a single-gate 3D DRAM device. Since the single-gate structure and the word line connected to the gate can be shorter than in a dual-gate structure, the height of each vertical stack of memory cells can be reduced without increasing the gate resistance or the bit line capacitance. In addition, in a single-gate 3D DRAM device, the active region can be epitaxially grown, so when the height of each vertical stack of memory cells is reduced, it may not collapse. Embodiments described herein also provide a method for forming a single-gate 3D DRAM device in a dual-color stack mold of, for example, silicon (Si) and silicon germanium (SiGe).

[0016] Figure 1A is a schematic diagram of a portion of a three-dimensional (3D) memory cell array 100 of dynamic random access memory (DRAM) cells (also referred to as "memory cells") M according to one or more embodiments of the present disclosure.

[0017] like Figure 1BAs shown, a single memory cell M includes an access transistor Q and a storage capacitor C. The memory cell M stores a data bit by storing a charge packet (i.e., binary one) or no charge (i.e., binary zero) on the storage capacitor C. The data bit is input and output by a bit line BL connected to the source / drain of the access transistor Q, and the input is controlled by a word line WL connected to the gate of the access transistor Q.

[0018] The memory cell array 100 includes memory levels L stacked in the Z direction. n (n=1, 2, ...) (shown is the first memory level L x and the second memory level L 2 Each memory level L n A two-dimensional (2-D) array of memory cells M is included. Although Figure 1A Only two memory levels are shown in FIG. 1 , but the memory cell array 100 may include more memory levels L n (n=3, 4, ...), which are stacked in the Z direction on the second memory level L 2 Above.

[0019] In the memory cell array 100, the bit lines BL extend vertically in the Z direction, and the word lines WL extend horizontally in the X direction. Each bit line BL is connected to the source / drain of an access transistor Q vertically aligned in the Z direction. Each word line WL is connected to the gate of an access transistor horizontally aligned in the Y direction.

[0020] Figure 2A is a top view of a portion of a semiconductor structure 200 (eg, a portion of the memory cell array 100 ) that may form a 3D memory cell array according to one or more embodiments of the present disclosure. Figure 2B It is along Figure 2A The cross-sectional view of a portion of the semiconductor structure 200 along the line BB' is shown. As shown in the figure, the three memory levels L 1 , L 2 and L 3 The semiconductor structure 200 may include a third memory level L stacked in the Z direction on the substrate 202. 3 More memory levels above L n (n=4, 5, ...) (not shown).

[0021] The semiconductor structure 200 includes a left field effect transistor (FET) module TR L , through the groove 204 in the X direction with the left FET module TR L Separate right FET module TR RThe semiconductor structure 200 further includes a left FET module TR L The adjacent left capacitor module C L and in the X direction with the right FET module TR R The adjacent right capacitor module C R . Left FET module TR L and left capacitor module C L In the Y direction, it is divided into a plurality of segments S Lm (m=1, 2, 3, ...) (e.g. Figure 2A An S shown Lm ). Right FET module TR R and right capacitor module C R In the Y direction, it is divided into a plurality of segments S Rm (m=1, 2, 3, ...) (e.g. Figure 2A An S shown Rm ). In each memory level L n In each segment S (n=1, 2, ...) Lm Left FET module TR in (m=1, 2, 3) L and left capacitor module C L The access transistor Q and the storage capacitor C that together form the memory cell M are formed separately. Similarly, in each memory level L n (n=1, 2, ...) in each segment S Rm Right FET module TR in (m=1, 2, 3) R and right capacitor module C R An access transistor (also referred to as a "cell transistor") Q and a storage capacitor (also referred to as a "cell capacitor") C that together form a memory cell M are formed separately. Although only one segment S is shown Lm and a segment S Rm (m=1, 2, 3), but more segments can be set along the Y direction.

[0022] The term "substrate" as used herein refers to a material layer that serves as a basis for subsequent processing operations and includes a surface to be cleaned. Substrate 202 may be a silicon-based material or any suitable insulating or conductive material as desired. Substrate 202 may include, for example, crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire materials.

[0023] Memory Level L nFET module TR in (n=1, 2, 3, ...) L and TR R (referred to as unit transistor Q Ln and Q Rn ) each includes an active region 206 in the Z direction and a gate 208 above the active region 206. In the single-gate 3D DRAM structure described herein, compared with the conventional dual-gate 3D DRAM structure, the unit transistor Q Ln and Q Rn Each of the gates 208 has a single gate 208. The word line connected to the gate in the single-gate 3D structure can be shorter than in the dual-gate structure, so the word line resistance can be reduced. Low word line resistance leads to fast operating speed due to the reduction of resistance-capacitance (RC) delay generated by the word line. Lower bit line capacitance can reduce the required cell capacitance, thereby reducing the capacitor area. The gate 208 is part of the word line layer 210 extending in the Y direction. The cross-section of the active area 206 each serves as the source / drain of the corresponding access transistor Q. An offset 212 is formed between the gate 208 and the source / drain. The active area 206 has a gate oxide layer 214 above the active area 206 in the Z direction. At the memory level L n In (n=1, 2, 3, ...), FET module TR L and TR R (Unit transistor Q Ln and Q Rn ) by directly setting the memory level L n+1 The spacer layer 216 below and in contact with the active region 206 in the adjacent memory level L n+1 FET module TR in L and TR R (Unit transistor Q Ln+1 and Q Rn+1 ) are separated. The spacer layer 216 is also configured to n (n=1, 2, 3, ...) within the adjacent part (e.g., S Lm and S Lm±1 , S Rm and S Rm±1) separate active regions 206. The active regions 206 may each have a width between about 20 nm and about 60 nm, for example, about 40 nm, in the Y direction, and a thickness between about 10 nm and about 30 nm, for example, about 20 nm, in the Z direction. The horizontal spacing between adjacent active regions 206 in the Y direction may be between about 140 nm and about 180 nm, for example, about 160 nm, and the vertical spacing between adjacent active regions 206 in the Z direction may be between about 50 nm and about 70 nm, for example, about 60 nm. The bit line BL may have a width between about 40 nm and about 120 nm, for example, about 80 nm, in the Y direction, and a thickness between about 40 nm and about 120 nm, for example, about 80 nm, in the X direction. In some memory array designs, the bit line (BL) is for the left FET module TR passing through the trench 204. L and right FET module TR R are the same, so the width of the bit line BL in the X direction is the width of the trench 204. In these designs, the left FET module TR L and right FET module TR R The word line WL on the left FET module TR can address two logical word line addresses and be controlled separately. In some other memory array designs, two independent bit lines BL are formed, one in the left FET module TR L On the right FET module TR R These bit lines BL are isolated from each other and can be connected to different global bit lines, respectively.

[0024] The active region 206 may be formed of silicon (Si) or indium gallium zinc oxide (IGZO). The active region 206 may be epitaxially grown, and thus each memory level L n (n=1, 2, ...) may not collapse when the height is reduced. The word line layer 210 may be formed of tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta) or platinum (Pt), or conductive oxides or nitrides thereof, or any combination thereof. The offset 212 may be formed of silicon nitride (Si 3 N 4 ) is formed. The gate oxide layer 214 may be made of silicon oxide (SiO 2 ), silicon oxynitride (SiON), high-k dielectric materials such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), vanadium oxide (VO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), niobium oxide (Nb 2 O 5 ), Tantalum pentoxide (Ta 2 O 5 ) or any combination thereof. The spacer layer 216 may be formed of a dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), silicon oxycarbide (SiOCN), boron-doped silicon oxycarbonitride (SiOCBN), or any combination thereof.

[0025] The semiconductor structure 200 further includes an adjacent section S Lm and S Rm The bit lines BL (m=1, 2, 3, . . . ) extending along the Z direction in the trenches 204 between the bit lines BL (m=1, 2, 3, . . . ) Figure 2A As shown, in S Lm and S Rm Segment S Lm and S Rm The bit lines BL (m=1, 2, 3, ...) between all memory levels L n (n=1, 2, 3, ...), electrically connected to segment S Lm The left FET module TR L The active region 206 in the section S Lm and S Rm The bit lines BL between (m=1, 2, 3, . . . ) are further electrically connected to all memory levels L n (n=1, 2, 3, ...) middle segment S Rm Right FET module TR R The active region 206 in FIG.

[0026] The bit line BL may be formed of a metal such as tungsten (W), molybdenum (Mo), titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), or any combination thereof.

[0027] Memory Level L n The left capacitor module C L and right capacitor module C R (n=1, 2, 3, ...) each including a memory level L electrically connected to nThe bottom electrode layer 218 of the active region 206 in the capacitor C is formed by a top electrode layer 220 connected to the ground (not shown), and a high-k dielectric layer 222 between the bottom electrode layer 218 and the top electrode layer 220. The bottom electrode layer 218 and the top electrode layer 220 can be used as two plates of a capacitor C. The bottom electrode layer 218 and the top electrode layer 220 can be formed of titanium nitride (TiN), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), rhodium (Rh), or a conductive metal nitride, or any combination thereof. The high-k dielectric layer 222 can be formed of a high-k dielectric material, such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), alumina (AbO 3 ), vanadium oxide (VO 2 ), titanium oxide (TiO 2 ), tin oxide (SnO 2 ), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), niobium oxide (Nb 2 O 5 ), Tantalum pentoxide (Ta 2 O 5 ) or any combination thereof.

[0028] The semiconductor structure 200 further includes an insulator layer 224 on the uppermost spacer layer 216. The insulator layer 224 may be made of silicon oxide (SiO 2 ) is formed and acts as an etch stop layer in the patterning process.

[0029] Figure 3 A process flow diagram of a method 300 of forming a cell transistor in a semiconductor structure 200 is depicted. Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Fig. 4I is a cross-sectional view of a portion of semiconductor structure 200 corresponding to various states of method 300. It should be understood that Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Fig. 4I Only a partial schematic diagram of semiconductor structure 200 is shown, and semiconductor structure 200 may include any number of transistor portions and additional materials having aspects as shown. It should also be noted that although Figure 3 The methods shown are described sequentially, but the scope of the disclosed embodiments provided herein includes other process sequences in which one or more operations have been omitted and / or added and / or have been rearranged in another desired order.

[0030] like Figure 4A As shown, the method 300 starts from block 302, where a mold deposition process is performed to deposit a stack mold 402 on the substrate 202, and an insulator layer 224 is deposited on the stack mold 402. The insulator layer 224 may be made of silicon oxide (SiO 2 ) is formed and acts as an etch stop layer during patterning of the stack mold 402. The stack mold 402 includes a plurality of unit stacks of a thicker channel layer 402A, a thicker sacrificial layer 402B on the thicker channel layer 402A, a thinner channel layer 402a on the thicker sacrificial layer 402B, and a thinner sacrificial layer 402b on the thinner channel layer 402a stacked in the Z direction. The thicker channel layer 402A and the thinner channel layer 402a can be formed of a first material. The thicker sacrificial layer 402B and the thinner sacrificial layer 402b can be formed of a second material. The etching selectivity of the second material (i.e., the ratio of the etching rate of the second material to the etching rate of the first material) is between about 10:1 and 500:1. Examples of the first material include pure silicon (Si) and indium gallium zinc oxide (IGZO). Examples of the second material include silicon germanium (SiGe) having a germanium (Ge) concentration between about 1% and about 50%, silicon oxide (SiO 2 ), borophosphosilicate glass (BPSG), boron silica glass (BSG), and phosphosilicate glass (PSG). The thicker channel layer 402A each has a thickness t A than the thickness t of each thinner channel layer 402a a The thicker sacrificial layers 402B each have a thickness t B than the thickness t of each thinner sacrificial layer 402b b The thickness t of the thicker channel layer 402A is about 1.1 to about 2 times (eg, 2 times). A and the thickness t of the thicker sacrificial layer 402B B The thickness t of the thinner channel layer 402b may be between about 10 nm and about 40 nm, for example about 20 nm. a and the thickness t of the thinner sacrificial layer 402b b It may be between about 5 nm and about 20 nm, for example about 10 nm.

[0031] In such Figure 4AIn the example shown, the number of unit stacks of the thicker channel layer 402A, the thicker sacrificial layer 402B, the thinner channel layer 402a, and the thinner sacrificial layer 402b is 2. However, the number of unit stacks may be greater than 100, such as about 200.

[0032] The mold deposition process in block 302 may include any suitable deposition process, such as chemical vapor deposition (CVD), epitaxial deposition process, and the like.

[0033] In block 304, if Figure 4B As shown, a transistor slit patterning process is performed to form a transistor slit 404 passing through the stack mold 402 and the insulator layer 224 along the Z direction. The transistor slit 404 may have a width between about 50 nm and about 200 nm, for example about 100 nm, in the X direction, and a depth between about 50 nm and about 200 nm in the Y direction.

[0034] The transistor slit patterning process in block 304 may include any suitable lithography and etching process, such as photolithography.

[0035] In block 306, if Figure 4C As shown, a groove forming process is performed to form a groove 406 in the thicker sacrificial layer 402B and a groove 408 in the thinner sacrificial layer 402b in the stack mold 402 from the sidewall of the transistor slit 404. The grooves 406 each have a thickness t corresponding to the thicker sacrificial layer 402B. B The grooves 408 each have a thickness t corresponding to the thinner sacrificial layer 402b. b Grooves 406 and 408 may have a width between 50 nanometers and about 300 nanometers, for example, about 150 nanometers.

[0036] The groove forming process in block 306 may include using a hydrofluoric acid (HF)-hydrogen peroxide (H 2 O 2 ) mixture, such as hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ) and acetic acid (CH 3 COOH) in a volume ratio of 1:2:3.

[0037] In block 308, if Figure 4DAs shown, an insulator formation process is performed to partially fill the groove 408 with an insulator layer 410 from the sidewalls of the transistor slit 404 and completely fill the groove 408. The insulator layer 410 is conformally deposited on the exposed surface within the transistor slit 404. The insulator layer 410 may be made of silicon oxide (SiO 2 ) is formed and has t b (the height of each groove 408, for example, about 10 nm) and t B The thickness of each groove 406 is about half of that of the insulator layer 410 (eg, about 20 nm). Thus, the groove 406 is partially filled with the insulator layer 410 , and the groove 408 is completely filled with the insulator layer 410 .

[0038] The insulator formation process in block 308 may include any suitable deposition process, such as atomic layer deposition (ALD).

[0039] In block 310, if Figure 4E As shown, an insulator removal process is performed to remove the insulator layer 410 on the sidewalls of the transistor slit 404 and within the recess 406. The insulator layer 410 in the recess 408 remains.

[0040] The insulator removal process in block 310 may include an etching process using a hydrofluoric acid (HF) solution.

[0041] In block 312, if Figure 4F As shown, a channel trimming process is performed to partially remove a portion of the thicker channel layer 402A adjacent to the groove 406 in the Z direction, and completely remove a portion of the thinner channel layer 402a adjacent to the groove 406 in the Z direction. The thicker channel layer 402A and the portion of the thinner channel layer 402a are cut out from the groove 406 by a thickness t of the thinner channel layer 402a. a The exposed portions 402A′ of the thicker channel layer 402A each have a thickness t of about 10 nm from the thicker channel layer 402A. A Subtract the thickness t of the thinner channel layer 402a a Thickness (t A -t a , for example, about 5 nm to about 20 nm, for example, about 10 nm), and the extended grooves 406' each have a thickness t of the thicker sacrificial layer 402B. B and the thickness t of the thinner channel layer 402b a The height of the sum of two times (t B +2t a , for example, about 20 nm to about 60 nm, for example, about 40 nm).

[0042] The channel trimming process in block 312 may include using silicon oxide (SiO 2 )Tetramethylammonium hydroxide (TMAH, (CH 3 ) 4 The etching process may be a wet etching process such as reactive ion etching (RIE), or a dry etching process such as reactive ion etching (RIE).

[0043] At block 314, a gate oxide formation process is performed to form a gate oxide layer 214 on the exposed portion 402A′ of the thicker channel layer 402A. Figure 4G As shown, gate oxide layer 214 may have a thickness between about 1 nanometer and about 5 nanometers.

[0044] The gate oxide formation process in block 314 may include a suitable thermal oxidation process of the oxide surface of the exposed portion 402A′ of the thicker channel layer 402A, for example, using nitrous oxide (N 2 O) gas enhanced in-situ steam generation (eISSG) process, using H 2 and O 2 In-situ steam generation (ISSG) of gases, or the use of NH 3 and O 2 Rapid thermal oxidation (RTO) process of gas.

[0045] In block 316, if Figure 4H As shown, a word line layer formation process is performed to form a barrier metal layer 412 on the inner surface of the extension groove 406' and to form a word line layer 210 on the exposed surface of the barrier metal layer 412. The barrier metal layer 412 and the word line layer 210 are then recessed from the transistor slit 404. This node separation process ensures isolation of vertically adjacent access transistors Q. The word line layer 210 may be formed of a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The barrier metal layer 412 may be formed of a barrier metal material of titanium nitride (TiN) or tantalum nitride (TaN).

[0046] The word line layer formation process in block 316 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0047] In block 318, if Fig. 4IAs shown, a transistor slit filling process is performed to fill the transistor slit 404 with an insulator layer 414. The insulator layer 414 may be made of silicon oxide (SiO 2 As shown in the figure, the left FET module TR is formed. L and right FET module TR R .

[0048] The transistor slot fill process in block 318 may include any suitable deposition process, such as atomic layer deposition (ALD).

[0049] Figure 5A and Figure 5B A process flow diagram of a method 500 for forming a unit capacitor in the semiconductor structure 200 formed by the method 300 is shown. Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H , Fig.6I , Figure 6J , Figure 6K , Figure 6L , Figure 6M , Figure 6N and Fig.6O is a cross-sectional view of a portion of semiconductor structure 200 corresponding to various states of method 500. It should be understood that Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H , Fig.6I , Figure 6J , Figure 6K , Figure 6L , Figure 6M , Figure 6N and Fig.6O Only a partial schematic diagram of semiconductor structure 200 is shown, and semiconductor structure 200 may include any number of transistor portions and additional materials having aspects as shown. It should also be noted that although Figure 5A and Figure 5B The methods shown in are described sequentially, but the scope of the disclosed embodiments provided herein includes other process sequences in which one or more operations have been omitted and / or added and / or have been rearranged in another desired order.

[0050] Method 500 begins at block 502, such as Fig. 6A As shown, a capacitor slit patterning process is performed to form a capacitor slit patterning process in the left FET module TRL and right FET module TR R Capacitor slits 602 are formed on both sides of the stack mold 402 and the insulator layer 224. The capacitor slits 602 may each have a width between about 80 nm and about 200 nm.

[0051] The capacitor slit patterning process in block 502 may include any suitable lithography and etching process, such as photolithography.

[0052] At block 504, a selective sacrificial layer removal process is performed to form an opening 604 in the thicker sacrificial layer 402b and an opening 606 in the thinner sacrificial layer 402b from the sidewalls of the capacitor slot 602, as shown in FIG. Figure 6B The openings 604 are formed where the thicker sacrificial layer 402B is removed, and each opening 604 has a thickness t corresponding to the thicker sacrificial layer 402B. B The openings 606 are formed where the thinner sacrificial layer 402b is removed, and each opening 606 has a thickness t corresponding to the thinner sacrificial layer 402b. b height.

[0053] The selective sacrificial layer removal process in block 504 may include using a hydrofluoric acid (HF)-hydrogen peroxide (H 2 O 2 ) mixture, such as hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ) and acetic acid (CH 3 COOH) in a volume ratio of 1:2:3.

[0054] In block 506, if Figure 6C As shown, a spacer formation process is performed to partially fill the opening 604 and completely fill the opening 606 with the spacer layer 216 from the sidewalls of the capacitor slit 602. Figure 6C As shown, the spacer layer 216 is conformally deposited on the exposed surface within the capacitor slot 602. The spacer layer 216 may be made of silicon oxide (SiO 2 ) is formed and has a value of about t b (the height of each opening 606, for example, about 10 nm) and about t B The thickness of each opening 604 is between half of the height of the opening 604, for example, about 20 nm. Thus, the opening 604 is partially filled with the spacer layer 216, and the opening 606 is completely filled with the spacer layer 216. The spacer layer 216 in the opening 606 merges with the insulator layer 410 formed in the transistor slit 404.

[0055] The spacer formation process in block 506 may include any suitable deposition process, such as atomic layer deposition (ALD).

[0056] In block 508, if Fig.6D As shown, a spacer removal process is performed to remove the spacer layer 216 on the sidewalls of the capacitor slot 602 and within the opening 604. The spacer layer 216 in the opening 606 remains unchanged.

[0057] The spacer removal process in block 508 may include an etching process using a hydrofluoric acid (HF) solution.

[0058] In block 510, if Fig. 6E As shown, a channel trimming process is performed to partially remove a portion of the thicker channel layer 402A adjacent to the opening 604 in the Z direction from the opening 604, and completely remove a portion of the thinner channel layer 402a adjacent to the opening 604 in the Z direction. The thicker channel layer 402A and the portion of the thinner channel layer 402a are separated by a thickness t of the thinner channel layer 402a. a The same thickness (eg, about 10 nm) is cut from the opening 604. Thus, the thinner channel layer 402a is completely removed, and the thicker channel layer 402A is partially removed. The remaining portions 402A" of the thicker channel layer 402A each have a thickness t A Subtract the thickness t of the thinner channel layer 402a a Thickness (t A -t a , for example, between about 5 nm and about 20 nm, for example, about 10 nm), and the extended openings 604' each have a thickness t of the thicker sacrificial layer 402B. B and the thickness t of the thinner channel layer 402b a The height of the sum of two times (t B +2t a , for example, between about 20 nm and about 60 nm, for example, about 40 nm).

[0059] The channel trimming process in block 510 may include using silicon oxide (SiO 2 )Tetramethylammonium hydroxide (TMAH, (CH 3 ) 4 The etching process may be a wet etching process such as reactive ion etching (NOH), or a dry etching process such as reactive ion etching (RIE).

[0060] In block 512, if Fig. 6F As shown, an insulator filling process is performed to fill the extended opening 604' with an insulator layer 608. The insulator layer 608 may be made of silicon nitride (Si 3 N 4 )form.

[0061] The insulator filling process in block 512 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0062] In block 514, if Figure 6G As shown, an insulator removal process is performed to partially remove the insulator layer 608. The remaining insulator layers 212 on the sidewalls of the word line layer 210 (i.e., the inner surface of the expanded opening 604" opposite to the capacitor slit 602 in the X direction), and each remaining insulator layer 212 may have a thickness between about 5 nm and about 50 nm. The remaining insulator layers 212 on the inner surface of the expanded opening 604" serve as an offset between the word line layer 210 and the source / drain (S / D) to be formed.

[0063] The insulator removal process in block 514 may include a dry etching process, such as reactive ion etching (RIE).

[0064] In block 516, if Figure 6H As shown, a channel trimming process is performed to remove the remaining portion 402A" of the thicker channel layer 402A outside the offset 212 within the enlarged opening 604". The removed portions 402A" of the thicker channel layer 402A each have a thickness t of the thicker channel layer 402A. A Subtract the thickness t of the thinner channel layer 402a a Thickness (t A -t a , for example, about 10 nm). A portion 402A' of the thicker channel layer 402A adjacent to the word line layer 210 in the Z direction remains unchanged. Therefore, the extended opening 604' is further expanded to the opening 604", so that the area of ​​the unit capacitor to be formed can be expanded.

[0065] The channel trimming process in block 516 may include using tetramethylammonium hydroxide (TMAH, (CH 3 ) 4 The etching process may be a wet etching process such as reactive ion etching (NOH), or a dry etching process such as reactive ion etching (RIE).

[0066] In block 518, if Fig.6I As shown, a doping process is performed to dope the portion 402A′ of the thicker channel layer 402A inside the offset 212 with an n-type dopant, such as phosphorus (P) or arsenic (As), from a side 610 adjacent to the enlarged opening 604 ″.

[0067] The doping process in block 518 may include vapor phase doping.

[0068] In block 520, if Figure 6J As shown, a bottom electrode deposition process is performed to conformally deposit a bottom electrode layer 218 on the exposed surface within the enlarged opening 604 ″. The bottom electrode layer 218 may be formed of titanium nitride (TiN) and have a thickness between approximately 1 nm and 10 nm.

[0069] The bottom electrode deposition process in block 520 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0070] In block 522, if Figure 6K As shown, a capacitor high-k dielectric deposition process is performed to conformally deposit a high-k dielectric layer 222 on the exposed surface of the bottom electrode layer 218 within the enlarged opening 604″ and on the sidewalls of the capacitor slit 602. The high-k dielectric layer 222 can be formed of a high-k dielectric material, such as hafnium oxide (HfO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ) or any combination thereof.

[0071] The capacitor high-k dielectric deposition process in block 522 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.

[0072] In block 524, if Figure 6L As shown, a top electrode deposition process is performed to conformally deposit a top electrode layer 220 on the exposed surface of the high-k dielectric layer 222 within the enlarged opening 604 ″ and within the capacitor slot 602 . The top electrode layer 220 may be formed of titanium nitride (TiN).

[0073] The top electrode deposition process in block 524 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.

[0074] After the deposition process, the semiconductor structure 200 may be planarized by using a chemical mechanical planarization (CMP) process.

[0075] In block 526, if Figure 6M As shown, a bit line (BL) patterning process is performed to form a BL opening 612 .

[0076] The BL patterning process in block 524 may include any suitable lithography and etching process, such as photolithography.

[0077] In block 526, if Figure 6N As shown, a doping process is performed to dope a portion 402A′ of the thicker channel layer 402A inside the offset 212 with an n-type dopant, such as phosphorus (P) or arsenic (As), from a side 614 adjacent to the BL opening 612. The doped portion 402A′ of the thicker channel layer 402A is used as Figure 2B Active region 206 is shown. Sides 610 and 614 of active region 206 act as source / drain.

[0078] The doping process in block 526 may include vapor phase doping.

[0079] In block 528, if Fig.6O As shown, a bit line metal forming process is performed to form a barrier metal layer 616 on the inner surface of the BL opening 612, and to form a bit line metal layer 618 on the exposed surface of the barrier metal layer 616. The bit line metal layer 618 may be formed of a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The barrier metal layer 616 may be formed of a barrier metal material, such as titanium nitride (TiN) or tantalum nitride (TaN). The bit line metal layer 618 and the barrier metal layer 616 act as a contact plug. Figure 1A and Figure 1B The bit line BL is shown.

[0080] The bitline metal formation process in block 528 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0081] After the deposition process, the semiconductor structure 200 may be planarized by using a chemical mechanical planarization (CMP) process.

[0082] Embodiments described herein provide a single-gate three-dimensional (3D) dynamic random access memory (DRAM) device and method for forming a cell transistor and a cell capacitor in a single-gate 3D DRAM device in a dual-color stack mold of, for example, silicon (Si) and silicon germanium (SiGe). Due to the single-gate structure, the word line connected to the gate can be shorter than in a dual-gate structure, and thus the height of each vertical stack of memory cells can be reduced without increasing gate resistance or bit line capacitance. In addition, in a single-gate 3D DRAM device, the active region can be epitaxially grown, and thus the active region can not collapse when the height of each vertical stack of memory cells is reduced.

[0083] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the same is determined by the claims that follow.

Claims

1. A memory cell array, comprising: A plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising: Active area; a cell transistor having a single gate over the active region in the first direction; and A cell capacitor has a bottom electrode layer electrically connected to the active region.

2. The memory cell array of claim 1 , wherein each of the plurality of memory levels further comprises: A word line layer extends from the single gate of the cell transistor along a second direction orthogonal to the first direction.

3. The memory cell array as claimed in claim 1, wherein The active region of each of the plurality of memory levels is located above and in contact with a spacer in the first direction.

4. The memory cell array as claimed in claim 1, wherein The active region includes silicon (Si) or indium gallium zinc oxide (IGZO).

5. The memory cell array as claimed in claim 1, wherein The active region is epitaxially grown.

6. The memory cell array of claim 1, further comprising: A bit line contacts each of the plurality of memory levels, the bit line extending in the first direction.

7. A method for forming a cell transistor in a semiconductor memory device, comprising the steps of: Depositing a stacking mold including a plurality of unit stacks, each unit stack including a thicker channel layer, a thicker sacrificial layer on the thicker channel layer, a thinner channel layer on the thicker sacrificial layer, and a thinner sacrificial layer on the thinner channel layer stacked along a first direction; forming a transistor slit through the stacked mold in the first direction; forming a first recess in the thicker sacrificial layer and a second recess in the thinner sacrificial layer from a sidewall of the transistor slit; partially filling the first groove and completely filling the second groove with a first insulator layer from the sidewalls of the transistor slit; and The first insulator layer on the sidewalls of the transistor slit and in the first groove is removed.

8. The method of claim 7, wherein Each of the thicker channel layers is between 1.1 and 2 times thicker than each of the thinner channel layers, and Each of the thicker sacrificial layers is between 1.1 and 2 times thicker than each of the thinner sacrificial layers.

9. The method of claim 7, wherein The thicker channel layer and the thinner channel layer each include silicon or indium gallium zinc oxide (IGZO), and The thicker sacrificial layer and the thinner sacrificial layer each include silicon germanium (SiGe), silicon oxide (SiO2), borophosphosilicate glass (BPSG), borosilicate glass (BSG), or phosphosilicate glass (PSG).

10. The method of claim 7, wherein The first insulator layer has a thickness between half the thickness of each of the thinner sacrificial layers and half the thickness of each of the thicker sacrificial layers.

11. The method of claim 7, further comprising the steps of: Partially removing a portion of the thicker channel layer adjacent to the first groove in the first direction, and completely removing the thinner channel layer adjacent to the first groove in the first direction; forming a gate oxide layer on the exposed portion of the thicker channel layer; forming a barrier metal layer on an inner surface of the first groove, and forming a word line layer on an exposed surface of the barrier metal layer; and The transistor gap is filled with a second insulator layer.

12. The method of claim 7, wherein said depositing of said stacked mold comprises an epitaxial deposition process.

13. A method for forming a unit capacitor in a semiconductor memory device, comprising the steps of: Depositing a stacking mold including a plurality of unit stacks, each unit stack including a thicker channel layer, a thicker sacrificial layer on the thicker channel layer, a thinner channel layer on the thicker sacrificial layer, and a thinner sacrificial layer on the thinner channel layer stacked along a first direction; forming a transistor slit passing through the stacked mold along the first direction; forming a first opening in the thicker sacrificial layer and a second opening in the thinner sacrificial layer from a sidewall of the capacitor slot; partially filling the first opening and completely filling the second opening with a spacer layer from the sidewalls of the capacitor slit; and The spacer layer on the sidewall of the capacitor slit and within the first opening is removed.

14. The method of claim 13, wherein Each of the thicker channel layers is between 1.1 and 2 times thicker than each of the thinner channel layers, and Each of the thicker sacrificial layers is between 1.1 and 2 times thicker than each of the thinner sacrificial layers.

15. The method of claim 13, wherein The thicker channel layer and the thinner channel layer each include silicon or indium gallium zinc oxide (IGZO), and The thicker sacrificial layer and the thinner sacrificial layer each include silicon germanium (SiGe), silicon oxide (SiO2), borophosphosilicate glass (BPSG), borosilicate glass (BSG), or phosphosilicate glass (PSG).

16. The method of claim 13, wherein The thickness of the spacer layer is between half the thickness of each of the thinner sacrificial layers and half the thickness of each of the thicker sacrificial layers.

17. The method of claim 13, further comprising the steps of: performing a first channel trimming process, comprising the steps of: removing a portion of the thicker channel layer adjacent to the first opening in the first direction from the first opening portion, and completely removing a portion of the thinner channel layer adjacent to the first opening in the first direction; forming an offset on an inner surface of the first opening opposite to the capacitor slit in a second direction orthogonal to the first direction; and A remaining portion of the thicker channel layer adjacent to the first opening in the first direction is removed.

18. The method of claim 17, further comprising the steps of: conformally depositing a bottom electrode layer on the exposed surface within the first opening; conformally depositing a high-k dielectric layer on the exposed surface of the bottom electrode layer within the first opening and on the sidewalls of the capacitor slot; and A top electrode layer is conformally deposited on the exposed surface of the high-k dielectric layer within the first opening and within the capacitor slot.

19. The method of claim 18, further comprising the steps of: forming a bit line opening; and A barrier metal layer is formed on an inner surface of the bit line opening, and a bit line metal layer is formed on an exposed surface of the barrier metal layer.

20. The method of claim 19, further comprising the steps of: after performing the first channel trimming process, doping the remaining portion of the thicker channel layer adjacent to the first opening in the first direction from the first opening; and After forming the bit line opening, the remaining portion of the thicker channel layer adjacent to the first opening is doped in the first direction from the bit line opening.

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