Semiconductor device

Abstract

Provided is a semiconductor device having both low power consumption and high performance. The semiconductor device includes a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer on the first semiconductor layer, a third conductive layer on the second insulating layer, and a first insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer has a first opening to the first conductive layer. The second conductive layer has a second opening. The first opening and the second opening overlap each other when viewed from a plane. The first semiconductor layer is in contact with a top surface of the first conductive layer and a side surface of the first insulating layer in the first opening. The first semiconductor layer is in contact with a side surface of the second conductive layer in the second opening. The first semiconductor layer has a region overlapping the third conductive layer with the second insulating layer interposed therebetween. A side surface of the first insulating layer in the first opening has a region in which an angle formed with a top surface of the first conductive layer is 10 degrees or more and less than 55 degrees.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same. One embodiment of the present invention relates to a transistor and a method for manufacturing the same. One embodiment of the present invention relates to a display device including a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method of the above-mentioned device can be cited.

[0003] Note that in this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (transistor, diode, photodiode, etc.), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes all include semiconductor devices. Background Art

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, by reducing the occupied area of ​​transistors, the pixel size can be reduced, thereby improving the definition. Therefore, micro transistors are required.

[0005] As devices requiring a high-definition display apparatus, for example, devices for virtual reality (VR: Virtual Reality), augmented reality (AR: Augmented Reality), alternative reality (SR: Substitutional Reality), and mixed reality (MR: Mixed Reality) are being actively developed.

[0006] As a display device, for example, a light emitting device including an organic EL (Electro Luminescence) element or a light emitting diode (LED: Light Emitting Diode) has been developed.

[0007] Patent Document 1 discloses a high-definition display device using an organic EL element.

[0008] [Prior technical literature]

[0009] [Patent Document]

[0010] [Patent Document 1] International Patent Application Publication No. 2016 / 038508 Summary of the invention

[0011] Technical problem to be solved by the invention

[0012] One of the purposes of one embodiment of the present invention is to provide a semiconductor device including a transistor of micro size. Another purpose of one embodiment of the present invention is to provide a semiconductor device including a transistor with a short channel length. Another purpose of one embodiment of the present invention is to provide a semiconductor device including a transistor with a large on-state current. Another purpose of one embodiment of the present invention is to provide a semiconductor device including a transistor with high reliability. Another purpose of one embodiment of the present invention is to provide a semiconductor device including a transistor with good electrical characteristics. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a small footprint. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high performance. Another purpose of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high productivity. Another purpose of one embodiment of the present invention is to provide a novel semiconductor device.

[0013] Note that the description of these objectives does not prevent the existence of other objectives. One embodiment of the present invention does not need to achieve all of the above objectives. Objectives other than the above objectives can be extracted from the description of the specification, drawings, and claims.

[0014] Solutions to technical problems

[0015] One embodiment of the present invention is a semiconductor device, which includes a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer on the first semiconductor layer, a third conductive layer on the second insulating layer, and a first insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer has a first opening that reaches the first conductive layer. The second conductive layer has a second opening. The first opening and the second opening overlap each other when viewed from a plane. The first semiconductor layer contacts the top surface of the first conductive layer and the side surface of the first insulating layer in the first opening. The first semiconductor layer contacts the side surface of the second conductive layer in the second opening. The first semiconductor layer has an area that overlaps with the third conductive layer across the second insulating layer. The side surface of the first insulating layer in the first opening has an area where the angle formed with the top surface of the first conductive layer is greater than 10 degrees and less than 55 degrees.

[0016] In the above structure, it is preferred that the thickness of the first insulating layer is greater than or equal to 10 nm and less than 3 μm.

[0017] In the above structure, the first semiconductor layer preferably includes a metal oxide.

[0018] One embodiment of the present invention is a semiconductor device, which includes a first transistor, a second transistor and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer on the first semiconductor layer, and a third conductive layer on the second insulating layer. The second transistor includes a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, a second insulating layer on the second semiconductor layer, and a sixth conductive layer on the second insulating layer. The first insulating layer has a region sandwiched between the first conductive layer and the second conductive layer and a region sandwiched between the fourth conductive layer and the fifth conductive layer. The first insulating layer includes a first opening reaching the first conductive layer and a second opening reaching the fourth conductive layer. The side surface of the first insulating layer in the first opening has a region where the angle formed with the top surface of the first conductive layer is greater than 10 degrees and less than 55 degrees. The side surface of the first insulating layer in the second opening has a region where the angle formed with the top surface of the fourth conductive layer is greater than 55 degrees and less than 90 degrees. The second conductive layer has a third opening. The first opening and the third opening overlap each other when viewed from a plane. The fifth conductive layer has a fourth opening. The second opening and the fourth opening overlap each other when viewed from a plane. The first semiconductor layer contacts the top surface of the first conductive layer and the side surface of the first insulating layer in the first opening. The first semiconductor layer contacts the side surface of the second conductive layer in the third opening. The first semiconductor layer overlaps the third conductive layer via the second insulating layer. The second semiconductor layer contacts the top surface of the fourth conductive layer and the side surface of the first insulating layer in the second opening. The second semiconductor layer contacts the side surface of the fifth conductive layer in the fourth opening. The second semiconductor layer overlaps the sixth conductive layer via the second insulating layer.

[0019] In the above structure, preferably, the second insulating layer has a first region covering the side surface of the first insulating layer in the first opening separated by the first semiconductor layer, a second region covering the top surface of the second conductive layer separated by the first semiconductor layer, a third region covering the side surface of the first insulating layer in the second opening separated by the second semiconductor layer, and a fourth region covering the top surface of the fifth conductive layer separated by the second semiconductor layer, the thickness of the first region is greater than 0.85 times and less than 1.2 times the thickness of the second region, and the thickness of the third region is greater than 0.4 times and less than 0.85 times the thickness of the fourth region.

[0020] In the above structure, preferably, the thickness of the second region is greater than or equal to 10 nm and less than or equal to 200 nm, and the thickness of the fourth region is greater than or equal to 10 nm and less than or equal to 200 nm.

[0021] In the above structure, preferably, the second insulating layer has a first region covering the side surface of the first insulating layer in the first opening separated by the first semiconductor layer, a second region covering the top surface of the first conductive layer separated by the first semiconductor layer, a third region covering the side surface of the first insulating layer in the second opening separated by the second semiconductor layer, and a fourth region covering the top surface of the fourth conductive layer separated by the second semiconductor layer, the thickness of the first region is greater than 0.85 times and less than 1.2 times the thickness of the second region, and the thickness of the third region is greater than 0.4 times and less than 0.85 times the thickness of the fourth region.

[0022] In the above structure, preferably, the thickness of the second region is greater than or equal to 10 nm and less than or equal to 200 nm, and the thickness of the fourth region is greater than or equal to 10 nm and less than or equal to 200 nm.

[0023] In the above structure, preferably, in the first semiconductor layer, the thickness of the area in the first opening that contacts the side surface of the first insulating layer is greater than 0.85 times and less than 1.2 times the thickness of the area in contact with the top surface of the second conductive layer, and in the second semiconductor layer, the thickness of the area in the second opening that contacts the side surface of the first insulating layer is greater than 0.4 times and less than 0.85 times the thickness of the area in contact with the top surface of the fifth conductive layer.

[0024] In the above structure, preferably, the thickness of the region of the first semiconductor layer in contact with the top surface of the second conductive layer is greater than 1 nm and less than 200 nm, and the thickness of the region of the second semiconductor layer in contact with the top surface of the fifth conductive layer is greater than 1 nm and less than 200 nm.

[0025] In the above structure, preferably, in the first semiconductor layer, the thickness of the area in the first opening that contacts the side surface of the first insulating layer is greater than 0.85 times and less than 1.2 times the thickness of the area in contact with the top surface of the first conductive layer, and in the second semiconductor layer, the thickness of the area in the second opening that contacts the side surface of the first insulating layer is greater than 0.4 times and less than 0.85 times the thickness of the area in contact with the top surface of the fourth conductive layer.

[0026] In the above structure, preferably, the thickness of the region of the first semiconductor layer in contact with the top surface of the first conductive layer is greater than 1 nm and less than 200 nm, and the thickness of the region of the second semiconductor layer in contact with the top surface of the fourth conductive layer is greater than 1 nm and less than 200 nm.

[0027] Effects of the Invention

[0028] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor can be provided. In addition, according to one embodiment of the present invention, a semiconductor device including a transistor with a short channel length can be provided. In addition, according to one embodiment of the present invention, a semiconductor device including a transistor with a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device including a transistor with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device including a transistor with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a small footprint can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high performance can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0029] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above effects can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A is a plan view showing an example of a semiconductor device. Figure 1B is a cross-sectional view showing an example of a semiconductor device.

[0031] Figure 2A and Figure 2B is a cross-sectional view showing an example of a semiconductor device. Figure 2C and Figure 2D It is a perspective view showing an example of a semiconductor device.

[0032] Figure 3A is a plan view showing an example of a semiconductor device. Figure 3B is a cross-sectional view showing the structure of a semiconductor device.

[0033] Figure 4A is a plan view showing an example of a semiconductor device. Figure 4B is a cross-sectional view showing the structure of a semiconductor device.

[0034] Figure 5A is a plan view showing an example of a semiconductor device. Figure 5B and Figure 5C is a cross-sectional view showing an example of a semiconductor device.

[0035] Fig. 6Ais a plan view showing an example of a semiconductor device. Figure 6B is a cross-sectional view showing an example of a semiconductor device.

[0036] Figure 7 is a cross-sectional view showing an example of a semiconductor device.

[0037] Fig. 8A and Figure 8B is a cross-sectional view showing an example of a semiconductor device.

[0038] 9A to 9D is a cross-sectional view showing an example of a semiconductor device.

[0039] FIG. 10A to FIG. 10D is a cross-sectional view showing an example of a semiconductor device.

[0040] Fig.11A and Fig. 11B is a cross-sectional view showing an example of a semiconductor device.

[0041] Fig. 12A and Fig. 12B is a cross-sectional view showing an example of a semiconductor device.

[0042] Fig.13A and Fig. 13B is a cross-sectional view showing an example of a semiconductor device.

[0043] Fig.14A and Fig. 14B is a cross-sectional view showing an example of a semiconductor device. Fig. 14C and Fig.14D is a diagram showing an example of a circuit.

[0044] FIG. 15A to FIG. 15D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0045] FIG. 16A to FIG. 16D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0046] FIG. 17A to FIG. 17C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0047] Fig.18A It is a perspective view showing an example of a display device. Fig.18B is a block diagram of a display device.

[0048] Fig.19 It is a perspective view showing an example of a display device.

[0049] Fig. 20A It is the circuit diagram of a latch circuit. Fig. 20BIt is the circuit diagram of the inverter circuit.

[0050] Fig.21 It is the circuit diagram of a sequential circuit.

[0051] Fig.22A and Fig. 22B is a circuit diagram of a pixel circuit.

[0052] FIG. 23A to FIG. 23C is a cross-sectional view showing an example of a display device.

[0053] Fig.24A and Fig. 24B is a cross-sectional view showing an example of a display device.

[0054] Fig.25 is a cross-sectional view showing an example of a display device.

[0055] FIG. 26A to FIG. 26C is a cross-sectional view showing an example of a display device.

[0056] Fig.27A and Fig.27B is a cross-sectional view showing an example of a display device.

[0057] FIG. 28A to FIG. 28F This is a cross-sectional view showing an example of a method for manufacturing a display device.

[0058] FIG. 29A to FIG. 29D is a diagram showing an example of an electronic device.

[0059] FIG. 30A to FIG. 30F is a diagram showing an example of an electronic device.

[0060] FIG. 31A to FIG. 31G is a diagram showing an example of an electronic device. DETAILED DESCRIPTION

[0061] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0062] Note that in the invention structure described below, the same symbols are used to show the same parts or parts with the same function in different drawings, and repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0063] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent its actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0064] In this specification, etc., for the sake of convenience, ordinal numbers such as "first" and "second" are added, but they do not limit the number of components or the order of components (for example, process order or stacking order). In addition, the ordinal numbers added to components in one part of this specification may be inconsistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0065] In addition, depending on the situation or state, the "film" and the "layer" may be interchanged. For example, the "conductive layer" may be replaced with the "conductive film". Also, the "insulating film" may be replaced with the "insulating layer".

[0066] A transistor is a type of semiconductor element and can realize a function of amplifying current or voltage, controlling a switch operation of conduction or non-conduction, etc. The transistor in this specification etc. includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

[0067] In this specification, etc., when describing the connection relationship of a transistor, the expressions "one of the source and the drain" (or the first electrode or the first terminal) and "the other of the source and the drain" (or the second electrode or the second terminal) are used. This is because the source and the drain of a transistor are interchangeable depending on the structure or operating conditions of the transistor. Note that the source and the drain of a transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode, etc., depending on the situation.

[0068] In this specification, "electrode" and "wiring" do not limit their components in terms of function. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" and "wiring" also include a case where a plurality of "electrodes" and "wiring" are formed as one.

[0069] In this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes switching elements such as transistors, resistor elements, coils, capacitors, and other elements having various functions in addition to electrodes and wiring.

[0070] In addition, in this specification, etc., unless otherwise specified, off-state current refers to the leakage current between the source and the drain when the transistor is in the off state (also called non-conducting state or blocking state). In n-channel transistors, the off state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, the off state is when the voltage between the gate and the source is higher than V th ) status.

[0071] In this specification, etc., "the top surface shapes are roughly consistent" means that at least a portion of the edges of each layer in the stack overlap. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern or a portion of the same mask pattern. However, in reality, there are cases where the edges do not overlap, and sometimes the upper layer is located on the inside of the lower layer or the upper layer is located on the outside of the lower layer. In this case, it can also be said that "the top surface shapes are roughly consistent". When the top surface shapes are consistent or roughly consistent, it can also be said that the ends are aligned or roughly aligned.

[0072] In this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the formed surface. For example, it is preferred to have a region in which the angle (also referred to as a taper angle) formed by the inclined side surface and the substrate surface or the formed surface is less than 90 degrees. Here, the side surface, substrate surface, and formed surface of the constituent element do not necessarily have to be completely flat, and may also be a substantially planar shape with a slight curvature or a substantially planar shape with fine concave-convex shapes.

[0073] In this specification, etc., a device manufactured using a metal mask or FMM (Fine Metal Mask) is sometimes referred to as a device having an MM (Metal Mask) structure. In addition, in this specification, etc., a device manufactured without using a metal mask or FMM is sometimes referred to as a device having an MML (Metal Mask Less) structure.

[0074] In this specification, etc., a structure in which light-emitting layers are separately manufactured in light-emitting elements (also called light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. Since the SBS structure can optimize the materials and structures of each light-emitting element, the freedom of choice of materials and structures is increased, and it is easy to achieve improved brightness and reliability.

[0075] In this specification, holes or electrons are sometimes referred to as "carriers". Specifically, a hole injection layer or an electron injection layer is sometimes referred to as a "carrier injection layer", a hole transport layer or an electron transport layer is sometimes referred to as a "carrier transport layer", and a hole blocking layer or an electron blocking layer is sometimes referred to as a "carrier blocking layer". Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer are sometimes not clearly distinguishable based on their cross-sectional shape or characteristics. In addition, sometimes one layer has the functions of two or three of a carrier injection layer, a carrier transport layer, and a carrier blocking layer.

[0076] In this specification, etc., a light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, as the layer included in the EL layer (also referred to as a functional layer), a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer) and a carrier blocking layer (hole blocking layer and electron blocking layer) can be cited. In this specification, etc., a light-receiving element (also referred to as a light-receiving device) includes at least an active layer used as a photoelectric conversion layer between a pair of electrodes. In this specification, etc., one of a pair of electrodes is sometimes referred to as a pixel electrode, and the other is referred to as a common electrode.

[0077] In this specification, etc., the sacrificial layer (also referred to as a mask layer) is located at least above the light-emitting layer (more specifically, a layer processed into an island shape among the layers constituting the EL layer) and has a function of protecting the light-emitting layer during the manufacturing process.

[0078] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is disconnected due to the shape of a formed surface (for example, a step, etc.).

[0079] (Implementation Method 1)

[0080] In this embodiment, a semiconductor device which is one embodiment of the present invention is described with reference to FIGS. 1 to 26 .

[0081] <Structural Example 1>

[0082] A semiconductor device according to one embodiment of the present invention will be described. Figure 1A A top view (also referred to as a plan view) of the semiconductor device 10 is shown. Figure 1B Shown along Figure 1A The cross-sectional view of the cut surface along the dot-dash line A1-A2 shown in FIG. Figure 2A A cross-sectional view along the dot-dash line B1-B2 is shown, Figure 2B A cross-sectional view along the dot-dash line B3-B4 is shown. Figure 1A In the diagram, a portion of the components of the semiconductor device 10 (such as an insulating layer) is omitted. Figure 1ASimilarly, some components are omitted in the following drawings.

[0083] The semiconductor device 10 includes a transistor 100 and a transistor 200 . Figure 2C FIG. 1 is a perspective view showing a transistor 100 included in the semiconductor device 10. Figure 2D FIG. 2 shows a perspective view of transistor 200. Figure 2C and Figure 2D In the figure, description of some components such as substrate and insulating layer is omitted.

[0084] The transistor 100 and the transistor 200 differ in the shape of the opening in which the semiconductor layer is embedded. By making the shapes of the openings different from each other, the channel lengths of the transistor 100 and the transistor 200 can be made different. In addition, the thickness of the gate insulating layer of the transistor 100 and the transistor 200 can be made different. Furthermore, the thickness of the semiconductor layer of the transistor 100 and the transistor 200 can be made different. The transistor 100 includes a conductive layer 112a, a semiconductor layer 108, a conductive layer 112b, an insulating layer 106, and a conductive layer 104. Each layer constituting the transistor 100 may be a single-layer structure or a stacked-layer structure.

[0085] The conductive layer 112a is provided over the substrate 102. The conductive layer 112a is used as one of a source electrode and a drain electrode of the transistor 100.

[0086] The insulating layer 110 is located on the conductive layer 112a and is provided to cover the top surface and side surfaces of the conductive layer 112a.

[0087] The insulating layer 110 preferably has a stacked-layer structure. Figure 1B , etc. show an example in which the insulating layer 110 has a stacked-layer structure including an insulating layer 110 a , an insulating layer 110 b on the insulating layer 110 a , and an insulating layer 110 c on the insulating layer 110 b .

[0088] The insulating layer 110a is located on the conductive layer 112a and is provided to cover the top surface and side surfaces of the conductive layer 112a.

[0089] The insulating layer 110b is disposed on the insulating layer 110a, and the insulating layer 110c is disposed on the insulating layer 110b. The insulating layer 110 is provided with an opening 141 that reaches the conductive layer 112a.

[0090] The conductive layer 112b is located on the insulating layer 110. The conductive layer 112b is provided with an opening 143 overlapping with the opening 141. The conductive layer 112b is used as the other of the source electrode and the drain electrode of the transistor 100. The conductive layer 112b has a region overlapping with the conductive layer 112a via the insulating layer 110. The insulating layer 110 includes a region sandwiched between the conductive layer 112a and the conductive layer 112b. As described later, the insulating layer 110 has a region sandwiched by two conductive layers (the conductive layer 212a and the conductive layer 212b) included in the transistor 200.

[0091] The semiconductor layer 108 is in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110, and the top surface and side surface of the conductive layer 112b. The semiconductor layer 108 is provided so as to cover the opening 141 and the opening 143. The semiconductor layer 108 is provided so as to contact the side surface on the opening 141 side of the insulating layer 110 and the end on the opening 143 side of the conductive layer 112b (it can also be said that a part of the top surface and the side surface on the opening 143 side). The semiconductor layer 108 is in contact with the conductive layer 112a through the opening 141 and the opening 143.

[0092] The insulating layer 106 is located over the semiconductor layer 108 and the conductive layer 112 b. The insulating layer 106 is provided to cover the opening 141 and the opening 143 via the semiconductor layer 108. A portion of the insulating layer 106 functions as a gate insulating layer of the transistor 100. Another portion of the insulating layer 106 functions as a gate insulating layer of the transistor 200.

[0093] The conductive layer 104 is located on the insulating layer 106. The conductive layer 104 overlaps with the semiconductor layer 108 via the insulating layer 106. The conductive layer 104 functions as a gate electrode of the transistor.

[0094] Figure 5A yes Figure 1A An enlarged view of transistor 100 is shown, Figure 5B yes Figure 1B The transistor 100 is shown in an enlarged view along Figure 5A The cross-sectional view of the dotted line A1-A3 is shown. Figure 5C yes Figure 5B An enlarged view of region 41 is shown. Note that Figure 1B In the cross-sectional views shown in FIG. 1 and FIG. 2 , the thickness of each component is sometimes shown thicker for ease of viewing. Figure 5B , Figure 5C In the enlarged views shown in FIG. 1 and FIG. 2 , the thickness of each component may be shown to be thinner than in the view before enlargement.

[0095] Angle th1 is the angle between the side surface of the insulating layer 110 on the side of the opening 141 and the formed surface (here, the top surface of the conductive layer 112a). Angle th1 is preferably larger than angle th2 (the angle between the side surface of the insulating layer 110 on the side of the opening 241 and the formed surface in the transistor 200) described later.

[0096] The transistor 200 includes a conductive layer 212a, a semiconductor layer 208, a conductive layer 212b, an insulating layer 106, and a conductive layer 204. Each layer constituting the transistor 200 may have a single-layer structure or a stacked-layer structure. The conductive layer 212a, the semiconductor layer 208, the conductive layer 212b, and the conductive layer 204 may use the same materials as those that can be used for the conductive layer 112a, the semiconductor layer 108, the conductive layer 112b, and the conductive layer 104.

[0097] The conductive layer 212 a is provided over the substrate 102 . The conductive layer 212 a functions as one of a source electrode and a drain electrode of the transistor 200 .

[0098] The conductive layer 212a and the conductive layer 112a can be formed by processing the same conductive film.

[0099] The insulating layer 110 is located on the conductive layer 212a and is provided to cover the top surface and side surfaces of the conductive layer 112a.

[0100] The insulating layer 110a is located on the conductive layer 212a and is provided to cover the top surface and side surfaces of the conductive layer 212a.

[0101] The insulating layer 110b is disposed on the insulating layer 110a, and the insulating layer 110c is disposed on the insulating layer 110b. The insulating layer 110 is provided with an opening 241 that reaches the conductive layer 212a.

[0102] Fig. 6A yes Figure 1A An enlarged view of transistor 200 is shown. Figure 6B yes Figure 1B The transistor 200 is shown in an enlarged view along Fig. 6A The cross-sectional view of the section taken along the dot-dash line A4-A2 is shown. Figure 7 yes Figure 6B An enlarged view of area 42 is shown.

[0103] Angle th2 is an angle formed between the side surface of the insulating layer 110 on the side of the opening 241 and the formed surface (here, the top surface of the conductive layer 212 a ).

[0104] The angle th2 is preferably smaller than the angle th1. When viewed from a cross section, the channel length L1 of the transistor 100 is equivalent to the length of the side of the opening 141 of the insulating layer 110. In addition, when viewed from a cross section, the channel length L2 of the transistor 200 is equivalent to the length of the side of the opening 241 of the insulating layer 110. By making the angle th2 smaller than the angle th1, the length of the side of the opening 241 of the insulating layer 110 can be made longer than the length of the side of the opening 141. Thus, the channel length L2 of the transistor 200 can be made longer than the channel length L1 of the transistor 100.

[0105] The conductive layer 212b is located over the insulating layer 110. The conductive layer 212b has an opening 243 that overlaps with the opening 241. The conductive layer 212b serves as the other of a source electrode and a drain electrode of the transistor 200. The conductive layer 212b has a region that overlaps with the conductive layer 212a with the insulating layer 110 interposed therebetween.

[0106] The insulating layer 110 includes a region sandwiched between the conductive layer 112a and the conductive layer 112b and a region sandwiched between the conductive layer 212a and the conductive layer 212b.

[0107] The conductive layer 212b and the conductive layer 112b can be formed by processing the same conductive film.

[0108] The semiconductor layer 208 is in contact with the top surface of the conductive layer 212a, the side surface of the insulating layer 110, and the top surface and side surface of the conductive layer 212b. The semiconductor layer 208 is provided in a manner covering the opening 241 and the opening 243. The semiconductor layer 208 is provided in a manner in contact with the side surface on the side of the opening 241 in the insulating layer 110 and the end portion on the side of the opening 143 in the conductive layer 212b (it can also be said that it is a part of the top surface and the side surface on the side of the opening 243). The semiconductor layer 208 is in contact with the conductive layer 212a through the opening 241 and the opening 243.

[0109] The semiconductor layer 208 and the semiconductor layer 108 can be formed by processing the same semiconductor film.

[0110] When a film is formed in a manner covering the side wall of the opening, the coverage of the film can be improved by forming the side wall into a tapered shape to reduce the angle between the side wall and the formed surface. However, when the side wall is steeper, the coverage is reduced and the thickness may become thinner. Therefore, when the angle th1 is greater than the angle th2 and the side wall of the opening 141 is steeper than the opening 241, the semiconductor layer 108 may become thinner than the semiconductor layer 208.

[0111] The insulating layer 106 is located over the semiconductor layer 208 and the conductive layer 212b. The insulating layer 106 is provided to cover the opening 241 and the opening 243 via the semiconductor layer 208. As described above, a portion of the insulating layer 106 functions as a gate insulating layer of the transistor 100, and another portion functions as a gate insulating layer of the transistor 200.

[0112] Note that the thickness of the insulating layer 106 in the region covering the side wall of the opening 141 may be different from the thickness of the insulating layer 106 in the region covering the side wall of the opening 241. Specifically, for example, in the opening 141, the side wall is steeper than that of the opening 241, and the insulating layer 106 covering the side wall of the opening may be thinner.

[0113] The conductive layer 204 is located on the insulating layer 106. The conductive layer 204 overlaps with the semiconductor layer 208 via the insulating layer 106. The conductive layer 204 functions as a gate electrode of the transistor.

[0114] The conductive layer 204 and the conductive layer 104 can be formed by processing the same conductive film.

[0115] Conductive layer 112a, conductive layer 112b, and conductive layer 104 can all be used as wiring, and transistor 100 can be arranged in a region where these wirings overlap. In addition, conductive layer 212a, conductive layer 212b, and conductive layer 204 can all be used as wiring, and transistor 200 can be arranged in a region where these wirings overlap. That is, in a circuit including transistor 100, transistor 200, and wiring, the occupied area of ​​transistor 100, transistor 200, and wiring can be reduced. Therefore, the occupied area of ​​the circuit can be reduced to realize a small semiconductor device.

[0116] For example, when a semiconductor device according to one embodiment of the present invention is used in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be realized. In addition, for example, when a semiconductor device according to one embodiment of the present invention is used in a drive circuit (for example, one or both of a gate line drive circuit and a source line drive circuit) of a display device, the area occupied by the drive circuit can be reduced, and a display device with a narrow frame can be realized.

[0117] There is no particular limitation on the top surface shape of the openings 141, 143, 241, and 243. The openings 141, 143, 241, and 243 may be, for example, polygonal shapes such as circles, ellipses, triangles, quadrilaterals (including rectangles, rhombuses, squares), pentagons, or shapes with rounded corners of these polygons. In addition, the polygons may be concave polygons (polygons with at least one internal angle exceeding 180 degrees) or convex polygons (polygons with internal angles of less than 180 degrees). Figure 1AAs shown in the figures, the top surface shapes of the openings 141, 143, 241 and 243 are preferably circular. By making the top surface shape of the openings circular, the processing accuracy when forming the openings can be improved, thereby forming fine openings. Note that in this specification, the circle is not limited to a perfect circle.

[0118] In this specification, the top surface shape refers to the shape when viewed from a plane. Figure 1B In the structure shown in the figure, the shape of the top surface end of the insulating layer (here, insulating layer 110) sandwiched by the conductive layer 112a and the conductive layer 112b on the side of the opening 141 can be the top surface shape of the opening 141. Alternatively, for example, the shape of the bottom surface end of the insulating layer sandwiched by the conductive layer 112a and the conductive layer 112b on the side of the opening 141 can be the top surface shape of the opening 141.

[0119] Figure 1A The shape of the top surface end portion on the opening 141 side of the insulating layer 110 is represented by a shape 141t. Also, the shape of the bottom surface end portion on the opening 143 side of the conductive layer 112b is represented by a shape 143b. Also, the shape of the top surface end portion on the opening 241 side of the insulating layer 110 is represented by a shape 241t. Also, the shape of the bottom surface end portion on the opening 243 side of the conductive layer 212b is represented by a shape 243b.

[0120] like Figure 1A As shown, the shape 141t can be made consistent or substantially consistent with the shape 143b. Figure 1B As shown in FIG. 1 , the bottom surface end of the conductive layer 112b on the side of the opening 143 is preferably consistent or substantially consistent with the top surface end of the insulating layer 110 on the side of the opening 141. The bottom surface of the conductive layer 112b refers to the surface on the side of the insulating layer 110. The top surface of the insulating layer 110 refers to the surface on the side of the conductive layer 112b.

[0121] In addition, the shape 141t and the shape 143b may not be consistent. In addition, when the top surfaces of the openings 141 and 143 are circular, the openings 141 and 143 may be concentric circles or not.

[0122] like Figure 1A As shown, the shape 241t can be made consistent or substantially consistent with the shape 243b. Figure 1B As shown in FIG. 1 , it is preferred that the bottom surface end of the conductive layer 212b on the side of the opening 243 is consistent or substantially consistent with the top surface end of the insulating layer 110 on the side of the opening 241. The bottom surface of the conductive layer 212b refers to the surface on the side of the insulating layer 110. The top surface of the insulating layer 110 refers to the surface on the side of the conductive layer 212b.

[0123] The shape 241t and the shape 243b may not be consistent. In addition, when the top surfaces of the openings 241 and 243 are circular, the openings 241 and 243 may be concentric circles or not.

[0124] In the opening 241 , the opening size of the insulating layer 110 is greatly different between the shape of the top surface end portion and the shape of the bottom surface end portion on the opening 241 side. Figure 1A In FIG. 2 , the shape of the bottom end portion of the insulating layer 110 on the opening 241 side in the opening 241 is shown as a shape 241 b .

[0125] Transistor 100 and transistor 200 are so-called top-gate transistors having a gate electrode above the semiconductor layer. Furthermore, since the bottom surface of the semiconductor layer is in contact with the source electrode and the drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor. In addition, in transistor 100 and transistor 200, the heights of the source electrode and the drain electrode relative to the surface of the substrate 102 on which the surface is formed are different from each other, and the drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. It can also be said that in transistor 100 and transistor 200, the drain current flows in the longitudinal direction or the approximately longitudinal direction. Therefore, transistor 100 can be said to be a vertical channel transistor or VFET (Vertical Field Effect Transistor: vertical field effect transistor).

[0126] The transistor 100 can control the channel length by the thickness of the insulating layer 110 and the angle between the sidewall of the opening 141 provided in the insulating layer 110 and the formed surface. In addition, the transistor 200 can control the channel length by the thickness of the insulating layer 110 and the angle between the sidewall of the opening 241 provided in the insulating layer 110 and the formed surface. Therefore, in the transistor 100 and the transistor 200, a transistor having a channel length shorter than the limiting resolution of the exposure device used in the manufacture of the transistor can be manufactured with high precision. Specifically, a transistor with an extremely short channel length that cannot be achieved by the exposure device used in the mass production of existing flat panel displays (for example, a minimum line width of about 2μm or 1.5μm) can be realized. In addition, a transistor with a channel length of less than 10nm can also be realized without using a very expensive exposure device used in the most advanced LSI technology. In addition, the unevenness of characteristics between multiple transistors 100 and multiple transistors 200 can be reduced. As a result, the operation of the semiconductor device including the transistor 100 and the transistor 200 is stable and the reliability is improved. Furthermore, when the variation in characteristics is reduced, the degree of freedom in circuit design is increased, and the operating voltage of the semiconductor device can be reduced, thereby reducing the power consumption of the semiconductor device.

[0127] By shortening the channel length, the on-state current of the transistor can be increased. By using transistors, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small semiconductor device can be realized. For example, when a semiconductor device of one embodiment of the present invention is used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced when the number of wirings increases, thereby suppressing display unevenness. In addition, since the area occupied by the circuit can be reduced, the frame of the display device can be reduced.

[0128] In the transistor 100 and the transistor 200, the source electrode, the semiconductor layer, and the drain electrode can be overlapped and provided, so that the occupied area can be significantly reduced compared with a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0129] Although Figure 1B , etc. show an example in which the end of the semiconductor layer 108 is located on the conductive layer 112b and the semiconductor layer 108 has an area in contact with the top surface of the conductive layer 112b, but the present invention is not limited to this. The semiconductor layer 108 may also cover the end of the conductive layer 112b, the end of the semiconductor layer 108 may be located outside the end of the conductive layer 112b, and the semiconductor layer 108 may have an area in contact with the top surface of the insulating layer 110. Similarly, although Figure 1B etc. show an example in which the end of the semiconductor layer 208 is located on the conductive layer 212b and the semiconductor layer 208 has an area in contact with the top surface of the conductive layer 212b, but the semiconductor layer 208 may also cover the end of the conductive layer 212b, the end of the semiconductor layer 208 may be located outside the end of the conductive layer 212b, and the semiconductor layer 208 may be in contact with the top surface of the insulating layer 110.

[0130] Figure 1B , etc. show an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the opening 141 and the opening 143, but one embodiment of the present invention is not limited to this. A structure in which a step is formed by the insulating layer 110, the conductive layer 112b, and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are arranged along the step may also be adopted. Similarly, a structure in which a step is formed by the insulating layer 110, the conductive layer 212b, and the conductive layer 212a, and the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 are arranged along the step may also be adopted.

[0131] In a semiconductor device of one embodiment of the present invention, a transistor 100 having a short channel length and a transistor 200 having a long channel length can be formed separately. For example, by using the transistor 100 as a transistor requiring a large on-state current and using the transistor 200 as a transistor requiring a high saturation characteristic, a high-performance semiconductor device can be realized.

[0132] In addition, in a semiconductor device of one embodiment of the present invention, the thickness of the gate insulating layer of transistor 100 can be made thinner than the thickness of the gate insulating layer of transistor 200. By forming the thickness of the gate insulating layer thin, the on-state current of the transistor can be increased and the operating speed can be improved. In addition, in transistor 100, not only can the gate insulating layer be formed thin, but the channel length can also be further shortened, so the on-state current can be further increased and the operating speed can be faster. In addition, since the thickness of the gate insulating layer of transistor 200 can be made thicker than the thickness of the gate insulating layer of transistor 100, the gate withstand voltage of the transistor can be improved. For example, by using transistor 200 as a transistor to which a high voltage is applied and using transistor 100 as a transistor that needs to operate at high speed, a semiconductor device that operates at high speed and has high reliability can be realized.

[0133] In the semiconductor device of one embodiment of the present invention, the thickness of the semiconductor layer 108 can be made thinner than the thickness of the semiconductor layer 208. By reducing the thickness of the semiconductor layer, for example, the diameter of the opening 141 can be reduced, whereby the area occupied by the transistor 100 can be reduced.

[0134] The insulating layer 195 is provided so as to cover the transistor 100 and the transistor 200. The insulating layer 195 functions as a protective layer of the transistor 100 and the transistor 200.

[0135] The detailed structures of the transistor 100 and the transistor 200 are described.

[0136] First, refer to Figure 5A and Figure 5B The detailed structure of the transistor 100 will be described.

[0137] In the semiconductor layer 108, the region in contact with the conductive layer 112a is used as one of the source region and the drain region, the region in contact with the conductive layer 112b is used as the other of the source region and the drain region, and the region between the source region and the drain region is used as a channel formation region.

[0138] The channel length of transistor 100 is the distance between the source region and the drain region. Figure 5B The dotted double arrow in FIG. 1 shows a channel length L1 of the transistor 100. The channel length L1 can be said to be the shortest distance between a region of the semiconductor layer 108 that contacts the conductive layer 112a and a region that contacts the conductive layer 112b in a cross section.

[0139] The channel length L1 of the transistor 100 corresponds to the length of the side surface of the insulating layer sandwiched between the conductive layer 112a and the conductive layer 112b on the side of the opening 141 when viewed from a cross section. In other words, the channel length L1 is determined by the thickness T1 of the insulating layer sandwiched between the conductive layer 112a and the conductive layer 112b (here, the thickness of the insulating layer 110) and the angle th1 formed by the side surface of the insulating layer on the side of the opening 141 and the formed surface (here, the top surface of the conductive layer 112a).

[0140] Figure 5A and Figure 5B In FIG. 1 , a width D143 b of the shape 143 b is indicated by a double-dot chain line double arrow as the width of the opening 143 . Figure 5A An example is shown in which the top surface shape of the opening 141 and the opening 143 is circular, and the width D143b is equivalent to the diameter of the circle. In addition, the channel width W1 of the transistor 100 is the circumference of the circle. That is, the channel width W1 is π×D143b. In this way, when the top surface shape of the opening 141 and the opening 143 is circular, a transistor with a shorter channel width can be realized compared to using other shapes such as polygons. In this way, by forming the shape of the opening into a desired shape such as a circle or a polygon, the channel width can be changed without greatly changing the diameter of the transistor.

[0141] Note that the diameter of the opening 141 is sometimes different from the diameter of the opening 143 .

[0142] Next, refer to Fig. 6A , Figure 6B and Figure 7 The detailed structure of the transistor 200 will be described.

[0143] In the semiconductor layer 208, the region in contact with the conductive layer 212a is used as one of the source region and the drain region, the region in contact with the conductive layer 212b is used as the other of the source region and the drain region, and the region between the source region and the drain region is used as a channel formation region.

[0144] The channel length of transistor 200 is the distance between the source region and the drain region. Figure 6B The dotted double arrow in FIG. 2 shows the channel length L2 of the transistor 200. The channel length L2 can be said to be the shortest distance between the region of the semiconductor layer 208 in contact with the conductive layer 212a and the region in contact with the conductive layer 212b when viewed from a cross section.

[0145] The channel length L2 of the transistor 200 corresponds to the length of the side surface of the insulating layer sandwiched between the conductive layer 212a and the conductive layer 212b on the side of the opening 241 when viewed from a cross section. In other words, the channel length L2 is determined by the thickness T1 of the insulating layer sandwiched between the conductive layer 212a and the conductive layer 212b (here, the thickness of the insulating layer 110) and the angle th2 formed by the side surface of the insulating layer on the side of the opening 241 and the formed surface (here, the top surface of the conductive layer 212a).

[0146] Fig. 6A and Figure 6B In FIG. 2 , as the width of the opening 243 , a width D243 b of the shape 243 b is indicated by a double-pointed dashed line double arrow. Fig. 6A An example is shown in which the top surface shapes of the opening 241 and the opening 243 are circular.

[0147] Note that the diameter of the opening 241 is sometimes different from the diameter of the opening 243 .

[0148] In addition, the diameter of the opening 141, the diameter of the opening 143, the diameter of the opening 241, and the diameter of the opening 243 sometimes change in the depth direction. In the transistor 200, since the angle th2 is small, the diameter of the opening 241 and the diameter of the opening 243 sometimes change particularly significantly in the depth direction. As the diameter of the opening, for example, the average value of the diameter of the highest position, the diameter of the lowest position, and the diameter at the midpoint of the insulating layer 110 when viewed from the cross section can be used. Alternatively, as the diameter of the opening, for example, any diameter of the highest position, the diameter of the lowest position, or the diameter at the midpoint of the insulating layer 110 when viewed from the cross section can be used. Fig. 6A , as the width of the opening 241 , a width D241t at the highest position and a width D241b at the lowest position of the insulating layer 110 when viewed from a cross section are shown. The width D241t is larger than the width D241b.

[0149] Fig. 6A In the embodiment, the top surface of the lower end of the opening 243 is circular, and the width D243b is equivalent to the diameter of the circle. The length of the circumference of the circle may be, for example, the channel width of the transistor 200 (hereinafter referred to as the channel width W2). The channel width W2 is π×D243b.

[0150] Alternatively, the channel width of the transistor 200 can be calculated using the length of the circumference of the lower end of the opening 241. The top surface of the lower end of the opening 241 is circular, and the width D241b is equivalent to the diameter of the circle. The length of the circumference of the circle can be, for example, the channel width of the transistor 200 (hereinafter referred to as the channel width W2b). The channel width W2b is π×D241b.

[0151] Alternatively, the average value of the channel width W2 and the channel width W2 b may be regarded as the channel width of the transistor 200 .

[0152] When the top surfaces of the openings 241 and 243 are rounded, a transistor with a shorter channel width can be realized compared to other shapes.

[0153] exist Fig. 6A and Figure 6B In the structure shown, the width D243b is consistent with the width D241t.

[0154] in addition, Fig. 8A 2 shows an example in which the end of the insulating layer 110 on the semiconductor layer 208 side is located inside the end of the conductive layer 212b on the semiconductor layer 208 side. Fig. 8A In the structure shown, the width D241t is narrower than the width D243b. Fig. 8A In the structure shown, the diameter of the top surface end of the insulating layer 110 on the opening 241 side is smaller than the diameter of the bottom surface end of the conductive layer 212 b on the opening 243 side.

[0155] in addition, Figure 8B 2 shows an example in which the end of the conductive layer 212 b on the semiconductor layer 208 side is located inside the end of the insulating layer 110 on the semiconductor layer 208 side. Figure 8B In the structure shown, the width D241t is wider than the width D243b. Figure 8B In the structure shown, the diameter of the top surface end of the insulating layer 110 on the opening 241 side is larger than the diameter of the bottom surface end of the conductive layer 212 b on the opening 243 side.

[0156] Note that Figure 5B In the embodiment of the present invention, the side surface of the opening 141 of the insulating layer 110 is a straight line in cross section, but one embodiment of the present invention is not limited thereto. When viewed from a cross section, the side surface of the opening 141 of the insulating layer 110 may be a curved line, or may have both a straight line area and a curved line area. Figure 6B The side shape of the opening 241 of the insulating layer 110 is a straight line when viewed from a cross section, but one embodiment of the present invention is not limited to this. The side shape of the opening 241 of the insulating layer 110 may be a curve when viewed from a cross section, or the side shape may include both a straight line region and a curved line region. In addition, the curved line region may have various curves such as a convex curve and a concave curve. In addition, the side shape may have more than two straight line regions. In addition, the side shape may have more than two curved line regions.

[0157] Fig.9A and Fig. 10AEach of the examples shows an example in which the shape of the side surface of the insulating layer 110 on the opening 241 side has a curved region when the transistor 200 is viewed in cross section. Fig. 9B yes Fig.9A An enlarged view of the region 43 is shown, Fig. 10B yes Fig. 10A An enlarged view of area 44 is shown.

[0158] Fig.9A An example is shown in which the shape of the side surface of the opening 241 side of the insulating layer 110 has a curved area that is convex toward the outside of the insulating layer 110 when the transistor 200 is viewed from a cross section. For example, the angle th2 can be obtained by drawing a tangent to a line along the shape of the side surface and calculating the angle between the tangent and the formed surface (here, the top surface of the conductive layer 212a). Fig. 9C This is an example in which the angle th2 is obtained by drawing a tangent line in a region where the side surface contacts the top surface of the conductive layer 212 a . Fig.9D This is an example of obtaining the angle th2 by drawing a tangent line in a region near the midpoint of the depth of the insulating layer 110, which is smaller than Fig. 9C The angle th2 found in .

[0159] Fig. 10A An example is shown in which the shape of the side surface of the insulating layer 110 on the opening 241 side when the transistor 200 is viewed in cross section has a curved region that is convex toward the inside of the insulating layer 110 (concave toward the outside of the insulating layer). Fig. 10C This is an example in which the angle th2 is obtained by drawing a tangent line in a region where the side surface contacts the top surface of the conductive layer 212 a . Fig. 10D This is an example of obtaining the angle th2 by cutting a line in a region near the midpoint of the depth of the insulating layer 110, which is greater than Fig. 10C The angle th2 found in .

[0160] Alternatively, when the transistor 200 is viewed in cross section, the top surface end and the bottom surface end of the opening 241 of the insulating layer 110 may be connected by a straight line, and the angle between the straight line and the top surface of the conductive layer 212 a may be defined as angle th2 .

[0161] The channel length L1 may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L1 may be 100 nm or more and 1 μm or less.

[0162] The channel length L1 can be controlled by adjusting the thickness T1 and the angle th1. In addition, the ratio of the channel length L2 to the channel length L1 can be controlled by adjusting the relationship between the angle th1 and the angle th2. Figure 5B and Figure 6B The double-dash arrow in FIG. 1 represents the thickness T1.

[0163] Thickness T1 may be, for example, 10 nm or more, 50 nm or more, 100 nm or more, 150 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 3.0 μm, 2.5 μm or less, 2.0 μm or less, 1.5 μm or less, 1.2 μm or less, or 1.0 μm or less.

[0164] The angle th1 is preferably 90 degrees or a value in the vicinity thereof. Alternatively, the angle th1 is preferably 55 degrees or more, more preferably 60 degrees or more, more preferably 65 degrees or more, more preferably 70 degrees or more, and more preferably 90 degrees or less. Alternatively, the angle th1 may be less than 90 degrees, less than 85 degrees, less than 80 degrees, or less than 75 degrees.

[0165] The angle th2 is preferably a value greater than 0 degrees and smaller than the angle th1. The angle th2 is preferably less than 55 degrees, more preferably less than 50 degrees, more preferably less than 45 degrees, and more preferably less than 40 degrees. In addition, the angle th2 may be, for example, greater than 10 degrees, greater than 15 degrees, or greater than 20 degrees.

[0166] The channel length L2 is, for example, 1.2 times, 1.3 times, 1.4 times, or 1.5 times greater than the channel length L1.

[0167] In addition, the channel length L2 is, for example, 6 times or less, 4 times or less, or 3 times or less of the channel length L1.

[0168] When the opening 143 and the opening 243 are formed by photolithography, the width D143b of the opening 143 and the width D243b of the opening 243 are greater than the limiting resolution of the exposure device. The width D143b may be, for example, greater than 20 nm, greater than 30 nm, greater than 50 nm, greater than 100 nm, greater than 200 nm, greater than 300 nm, greater than 400 nm, or greater than 500 nm and less than 5.0 μm, less than 4.5 μm, less than 4.0 μm, less than 3.5 μm, less than 3.0 μm, less than 2.5 μm, less than 2.0 μm, less than 1.5 μm, or less than 1.0 μm. In addition, the width D243b can be, for example, greater than 30 nm, greater than 50 nm, greater than 100 nm, greater than 200 nm, greater than 300 nm, greater than 400 nm or greater than 500 nm and less than 5.0 μm, less than 4.5 μm, less than 4.0 μm, less than 3.5 μm, less than 3.0 μm, less than 2.5 μm, less than 2.0 μm, less than 1.5 μm or less than 1.0 μm.

[0169] Note that although Figure 1A , Figure 1BThe example in which the width D243b is wider than the width D143b is shown in FIG. 3 , however, the width D243b may be substantially equal to the width D143b as shown in FIG. 3 . In addition, the width D243b may be narrower than the width D143b.

[0170] Next, refer to Figure 5B The thickness of the gate insulating layer of the transistor 100 is described. The insulating layer 106 sandwiched between the conductive layer 104 and the semiconductor layer 108 serving as a gate electrode serves as a gate insulating layer. The thickness of the gate insulating layer is the shortest distance between the conductive layer 104 and the semiconductor layer 108 when viewed in cross section.

[0171] Depending on the angle th1, the angle th2, and the method of forming the insulating layer 106, the thickness of the gate insulating layer may differ.

[0172] Fig.11A The diagram is for explaining the thickness of the semiconductor layer and the thickness of the gate insulating layer of the transistor 100 .

[0173] The thickness of the semiconductor layer 108 on the top surface of the conductive layer 112b, the side surface of the opening 141 of the insulating layer 110, and the top surface of the conductive layer 112a is thickness B1, thickness B2, and thickness B3. The thickness B2 is sometimes thinner than the thickness B1. The thickness B2 is, for example, 0.4 times or more and 0.85 times or less of the thickness B1. In addition, the thickness B2 is sometimes thinner than the thickness B3. The thickness B2 is, for example, 0.4 times or more and 0.85 times or less of the thickness B3.

[0174] The thickness of the insulating layer 106 on the top surface of the conductive layer 112b, the side surface of the opening 141 of the insulating layer 110, and the top surface of the conductive layer 112a is thickness A1, thickness A2, and thickness A3. The thickness A2 is sometimes thinner than the thickness A1. For example, the thickness A2 is 0.4 times or more and 0.85 times or less of the thickness A1. In addition, the thickness A2 is sometimes thinner than the thickness A3. For example, the thickness A2 is 0.4 times or more and 0.85 times or less of the thickness A3.

[0175] Fig. 11B The diagram is for explaining the thickness of the semiconductor layer and the thickness of the gate insulating layer of the transistor 200 .

[0176] The thickness of the semiconductor layer 208 on the top surface of the conductive layer 212b, the side surface of the opening 241 of the insulating layer 110, and the top surface of the conductive layer 212a is thickness B11, thickness B12, and thickness B13. Thickness B12 is, for example, greater than 0.85 times and less than 1.2 times the thickness B11. Thickness B12 is, for example, greater than 0.85 times and less than 1.2 times the thickness B13.

[0177] The thickness of the insulating layer 106 on the top surface of the conductive layer 212b, the side surface of the opening 241 of the insulating layer 110, and the top surface of the conductive layer 212a is thickness A11, thickness A12, and thickness A13. Thickness A12 is, for example, greater than 0.85 times and less than 1.2 times thickness A11. Thickness A12 is, for example, greater than 0.85 times and less than 1.2 times thickness A3.

[0178] The components included in the semiconductor device of this embodiment will be described below.

[0179] [Semiconductor layer 108 and semiconductor layer 208]

[0180] There is no particular limitation on the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208. For example, a semiconductor composed of a single element or a compound semiconductor can be used. Examples of semiconductors composed of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. In addition, examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. Note that these semiconductor materials may also contain impurities as dopants.

[0181] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part thereof) can be used. When a single crystal semiconductor or a crystalline semiconductor is used, degradation of transistor characteristics can be suppressed, so it is preferred.

[0182] The semiconductor layer 108 and the semiconductor layer 208 preferably both include a metal oxide (also referred to as an oxide semiconductor) exhibiting semiconductor characteristics.

[0183] The band gap of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.

[0184] As metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208, for example, indium oxide, gallium oxide, and zinc oxide can be cited. The metal oxide preferably contains at least indium or zinc. In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Element M is a metal element or a semi-metal element having a high bond energy with oxygen, for example, a metal element or a semi-metal element having a higher bond energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. Note that in this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and the "metal elements" recorded in this specification, etc. sometimes include semi-metal elements.

[0185] The semiconductor layer 108 and the semiconductor layer 208 can use, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO or IAGZO), etc. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0186] When the ratio of the number of atoms of indium to the total number of atoms of all metal elements in the metal oxide is increased, the field effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0187] Note that the metal oxide may also replace indium or contain one or more metal elements with a large period number in the periodic table in addition to indium. There is a tendency that the greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0188] The metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may be improved by increasing the carrier concentration or narrowing the band gap. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0189] When the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide is increased, the metal oxide has high crystallinity and diffusion of impurities in the metal oxide can be suppressed. Therefore, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0190] When the ratio of the number of atoms of the element M in the metal oxide relative to the sum of the number of atoms of all metal elements is increased, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be formed. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0191] The electrical characteristics and reliability of the transistor differ depending on the composition of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required for the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be achieved.

[0192] In the composition analysis of metal oxides, for example, energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectrometry), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. Alternatively, multiple of the above methods can be combined for analysis. Note that the actual content of elements with low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content, difficult to quantify or undetectable.

[0193] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of the atomic ratio of the metal elements in such an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and compositions close thereto. In addition, the composition in the vicinity includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current and field effect mobility of the transistor can be improved.

[0194] The atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such an In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, and compositions near these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0195] Note that when a plurality of metal elements are included as the element M, the sum of the ratios of the number of atoms of the metal elements may be the ratio of the number of atoms of the element M.

[0196] In this specification, etc., the ratio of the number of atoms of indium to the total number of atoms of all metal elements contained may be described as the content rate of indium. The same applies to other metal elements.

[0197] The metal oxide is preferably formed by sputtering or atomic layer deposition (ALD). Note that when the metal oxide is formed by sputtering, the composition of the deposited metal oxide is sometimes different from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide is sometimes reduced to about 50% of that in the sputtering target.

[0198] The semiconductor layer 108 and the semiconductor layer 208 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 may also be the same or substantially the same. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0199] The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 may also be different from each other. For example, it is preferred to use a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto disposed on the first metal oxide layer. In addition, it is particularly preferred to use gallium, aluminum or tin as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide and IGZO and any one selected from IAZO, IAGZO and ITZO (registered trademark) may be used.

[0200] In addition, the semiconductor layer 108 and the semiconductor layer 208 may both have a stacked structure of two or more layers. As such a stacked structure, for example, a three-layer stacked structure can be cited, in which a semiconductor layer having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the first layer, a semiconductor layer having an atomic ratio of metal elements of In:Zn=4:1 is used as the second layer, and a semiconductor layer having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the third layer. In addition, the band gap of the semiconductor layer of the first layer and the third layer is preferably larger than the band gap of the semiconductor layer of the second layer. By adopting this structure, the second layer can be used as the main current path, so a so-called buried channel structure can be realized.

[0201] The semiconductor layer 108 and the semiconductor layer 208 preferably include a crystalline metal oxide layer. Examples of the structure of the crystalline metal oxide include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nanocrystal (nc) structure. By using a crystalline metal oxide layer for the semiconductor layer 108, the defect state density in the semiconductor layer 108 can be reduced, thereby realizing a semiconductor device with high reliability.

[0202] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 108 and the semiconductor layer 208, the lower the defect state density in the semiconductor layer 108. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0203] When a metal oxide layer is formed by sputtering, the higher the substrate temperature (stage temperature) when the metal oxide layer is formed, the more crystalline the metal oxide layer can be formed. In addition, the higher the flow rate ratio of the oxygen gas relative to the entire deposition gas used when forming the metal oxide layer (hereinafter also referred to as the oxygen flow rate ratio) or the oxygen partial pressure in the processing chamber is, the more crystalline the metal oxide layer can be formed.

[0204] The semiconductor layer 108 and the semiconductor layer 208 may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure may have a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, and the second metal oxide layer may include a region whose crystallinity is higher than that of the first metal oxide layer. Alternatively, the second metal oxide layer may include a region whose crystallinity is lower than that of the first metal oxide layer. In this case, the compositions of the first metal oxide layer and the second metal oxide layer may also be different, the same, or substantially the same.

[0205] The thickness of the semiconductor layer 108 and the semiconductor layer 208 is preferably 1 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less. Note that the thickness of the semiconductor layer 108 and the semiconductor layer 208 may be the same or different.

[0206] Note that the thickness of different regions of the semiconductor layer 108 and the semiconductor layer 208 may be different. For example, the thickness of some regions may be greater than 0.4 times and less than 1.2 times the above thickness range.

[0207] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, thereby forming an oxygen vacancy (V) in the oxide semiconductor. O In addition, sometimes hydrogen enters the defect in the oxygen vacancy (hereinafter referred to as V O H) is used as a donor to generate electrons as carriers. In addition, sometimes electrons as carriers are generated due to the bonding of a portion of hydrogen to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have a normally-on characteristic. In addition, because the hydrogen in the oxide semiconductor is easily moved due to heat, electric field, etc., when the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0208] When an oxide semiconductor is used as the semiconductor layer 108 and the semiconductor layer 208, it is preferable to minimize the V O H to make it high purity intrinsic or substantially high purity intrinsic. In this way, in order to obtain V O For an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to repair oxygen vacancies. O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor to impart stable electrical characteristics. Note that a process of supplying oxygen to an oxide semiconductor to repair oxygen vacancies is sometimes referred to as an oxidation treatment.

[0209] When an oxide semiconductor is used as the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration of the oxide semiconductor in the region to be used as the channel formation region is preferably 1×10 18 cm -3 Below, more preferably below 1×10 17 cm -3 , and more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , and more preferably less than 1×10 12 cm -3 There is no limitation on the lower limit of the carrier concentration of the oxide semiconductor in the region serving as the channel formation region, but it can be set to 1×10 -9 cm -3 .

[0210] Compared with transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a very high field effect mobility. In addition, the off-state current of the OS transistor is extremely small, and the charge stored in the capacitor connected in series with the transistor can be maintained for a long period of time. In addition, by using OS transistors, the power consumption of semiconductor devices can be reduced.

[0211] OS transistors have little change in electrical characteristics due to exposure to radiation, that is, they have high tolerance to radiation, so they can be appropriately used in environments where radiation may be incident. OS transistors can also be said to have high reliability with respect to radiation. For example, OS transistors are suitable for pixel circuits of flat-panel detectors of X-rays. In addition, OS transistors are suitable for semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0212] Examples of silicon that can be used for the semiconductor layer 108 and the semiconductor layer 208 include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon).

[0213] A transistor using amorphous silicon as the semiconductor layer 108 and the semiconductor layer 208 can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon in the semiconductor layer 108 and the semiconductor layer 208 has high field effect mobility and can operate at high speed. In addition, compared with a transistor using amorphous silicon, a transistor using microcrystalline silicon in the semiconductor layer 108 and the semiconductor layer 208 has high field effect mobility and can operate at high speed.

[0214] The semiconductor layer 108 and the semiconductor layer 208 may also include a layered material used as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals bonds that are weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0215] As the above-mentioned layered material, for example, graphene, silicene, chalcogenides, etc. can be cited. Chalcogenides are compounds containing oxygen group elements (belonging to group 16 elements). In addition, as chalcogenides, transition metal chalcogenides, group 13 chalcogenides, etc. can be cited. As transition metal chalcogenides that can be used as semiconductor layers of transistors, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0216] The semiconductor layer 108 and the semiconductor layer 208 are preferably formed in the same process. Therefore, the semiconductor layer 108 and the semiconductor layer 208 are preferably made of the same material.

[0217] Alternatively, the semiconductor layer 108 and the semiconductor layer 208 may be formed in different steps. In this case, the semiconductor layer 108 and the semiconductor layer 208 may be formed using different materials.

[0218] [Insulating layer 110]

[0219] As each layer constituting the insulating layer 110, an inorganic insulating film is preferably used. As the inorganic insulating film, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be cited. As the oxide insulating film, for example, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film can be cited. As the nitride insulating film, for example, a silicon nitride film and an aluminum nitride film can be cited. As the oxynitride insulating film, for example, a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film can be cited. As the nitride oxide insulating film, for example, a silicon oxynitride film and an aluminum oxynitride film can be cited.

[0220] In this specification, etc., oxynitride refers to a material containing more oxygen than nitrogen in its composition. Nitride oxide refers to a material containing more nitrogen than oxygen in its composition. For example, silicon oxynitride refers to a material containing more oxygen than nitrogen in its composition, and silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition.

[0221] The analysis of the composition can be performed, for example, using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), or energy dispersive X-ray spectroscopy (EDX). For example, when the content of the target element is high (for example, 0.5 atomic% or more or 1 atomic%), XPS is preferably used. On the other hand, when the content of the target element is low (for example, 0.5 atomic% or less or 1 atomic%), SIMS is preferably used. The analysis of the composition preferably uses multiple analysis methods. For example, it is more preferable to perform a composite analysis using both SIMS and XPS.

[0222] The insulating layer 110 has a portion in contact with the semiconductor layer 108. When an oxide semiconductor is used as the semiconductor layer 108, in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110, an oxide or an oxynitride is used in at least a portion of the portion of the insulating layer 110 in contact with the semiconductor layer 108. Specifically, it is preferable to use an oxide or an oxynitride in a portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108. The channel formation region is a high resistance region with a low carrier concentration. It can be said that the channel formation region is i-type (intrinsic) or substantially i-type.

[0223] The insulating layer 110b is preferably a layer containing oxygen. The insulating layer 110b preferably has a region containing more oxygen than at least one of the insulating layer 110a and the insulating layer 110c. In particular, the insulating layer 110b preferably has a region containing more oxygen than the insulating layer 110a and the insulating layer 110c.

[0224] The insulating layer 110b preferably uses any one or more of the above-mentioned oxide insulating film and oxynitride insulating film. Specifically, the insulating layer 110b preferably uses one or both of a silicon oxide film and an oxynitride silicon film. By increasing the oxygen content of the insulating layer 110b, an i-type region is easily formed in the region in contact with the insulating layer 110b in the semiconductor layer 108 and in the vicinity thereof.

[0225] The insulating layer 110 b is preferably a film that releases oxygen by heating. Since the insulating layer 110 b releases oxygen due to heat applied in the manufacturing process of the transistor 100, oxygen can be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110 b to the semiconductor layer 108, especially to the channel formation region of the semiconductor layer 108, oxygen vacancies (V O ) and V O H, thereby achieving a transistor with good electrical characteristics and high reliability.

[0226] For example, oxygen can be supplied to the insulating layer 110 b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by depositing an oxide film on the top surface of the insulating layer 110 b by sputtering in an oxygen atmosphere. The oxide film can then be removed.

[0227] The insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method. In particular, by using a sputtering method and a deposition method that does not use a hydrogen-containing gas as a deposition gas, a film containing very little hydrogen can be achieved. Therefore, the semiconductor layer 108 can be prevented from being supplied with hydrogen, thereby stabilizing the electrical characteristics of the transistor 100.

[0228] As described above, the channel length L1 of the transistor 100 can be made extremely small. When the channel length L1 is small, oxygen vacancies (V O ) and V O H has a particularly large influence on electrical characteristics and reliability. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, at least oxygen vacancies (V O ) and V O H increases in a region of the semiconductor layer 108 that is in contact with the insulating layer 110b. Therefore, a transistor with a short channel length and excellent electrical characteristics and high reliability can be achieved.

[0229] It is preferable to use a film that does not easily diffuse oxygen as the insulating layer 110a and the insulating layer 110c. Thus, it is possible to prevent the oxygen in the insulating layer 110b from passing through the insulating layer 110a and the insulating layer 106 due to heating. In other words, the insulating layer 110b is sandwiched between the insulating layer 110a and the insulating layer 110c, into which oxygen does not easily diffuse, so that the oxygen in the insulating layer 110b can be confined. Thus, oxygen can be efficiently supplied to the semiconductor layer 108.

[0230] The insulating layer 110a and the insulating layer 110c are preferably made of a film into which hydrogen is not easily diffused. Thus, diffusion of hydrogen from the outside of the transistor through the insulating layer 110a and the insulating layer 110c into the semiconductor layer 108 can be suppressed.

[0231] The insulating layer 110a and the insulating layer 110c preferably use any one or more of the above-mentioned oxide insulating film, nitride insulating film, oxynitride insulating film, and nitride oxide insulating film, and preferably use any one or more of the above-mentioned silicon nitride film, silicon nitride oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, aluminum nitride film, hafnium oxide film, and hafnium aluminate film. In particular, the silicon nitride film and the silicon nitride oxide film are suitable for the insulating layer 110a and the insulating layer 110c because they have the characteristics of small amounts of impurities (for example, water and hydrogen) released from themselves and oxygen and hydrogen are not easily permeable. Note that the insulating layer 110a and the insulating layer 110c may use the same material or different materials.

[0232] Here, due to the oxygen contained in the insulating layer 110b, the conductive layer 112a and the conductive layer 112b are oxidized, and the resistance sometimes increases. By providing the insulating layer 110a between the insulating layer 110b and the conductive layer 112a, it is possible to suppress the conductive layer 112a from being oxidized and the resistance from increasing. In addition, by providing the insulating layer 110c between the insulating layer 110b and the conductive layer 112b, it is possible to suppress the conductive layer 112b from being oxidized and the resistance from increasing. At the same time, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is increased, and oxygen vacancies in the semiconductor layer 108 can be reduced.

[0233] The thickness of the insulating layer 110a and the insulating layer 110c is preferably 5 nm or more and 150 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 70 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 10 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less. By making the thickness of the insulating layer 110a and the insulating layer 110c within the above range, oxygen vacancies in the semiconductor layer 108, especially in the channel formation region, can be reduced.

[0234] For example, a silicon nitride film is preferably used for the insulating layer 110 a and the insulating layer 110 c , and a silicon oxynitride film is preferably used for the insulating layer 110 a .

[0235] Note that in this embodiment, the insulating layer 110 has a three-layer stacked structure, but one embodiment of the present invention is not limited thereto. The insulating layer 110 may have a single-layer structure or a stacked structure of two, four, or five or more layers. The insulating layer 110 preferably includes at least the insulating layer 110b.

[0236] The insulating layer 110c may also be a film that releases hydrogen when heated. When the insulating layer 110c releases hydrogen due to heat applied in the manufacturing process of the transistor 100, hydrogen can be supplied to the semiconductor layer 108 and the semiconductor layer 208. Thus, a low resistance region can be formed near a region of the semiconductor layer 108 in the transistor 100 that is in contact with the conductive layer 112b and near a region of the semiconductor layer 208 in the transistor 200 that is in contact with the conductive layer 212b.

[0237] Similarly, by using a film that releases hydrogen when heated as the insulating layer 110a, a low resistance region can be formed near the region of the semiconductor layer 108 in the transistor 100 that is in contact with the conductive layer 112a and near the region of the semiconductor layer 208 in the transistor 200 that is in contact with the conductive layer 212a.

[0238] The insulating layer 110b preferably uses a film with a low hydrogen content. By using a film with a low hydrogen content as the insulating layer 110b, hydrogen can be prevented from diffusing into a region of the semiconductor layer 108 where a gate electric field is sufficiently applied (a region where an i-type is desired), thereby making the channel formation region an i-type region.

[0239] Fig. 12A yes Figure 5B An enlarged view of the region 41 is shown, Fig. 12B yes Figure 6B The enlarged view of the region 42 shown shows an example in which a film that releases hydrogen when heated is used as the insulating layer 110a and the insulating layer 110c.

[0240] like Fig. 12A As shown, in the semiconductor layer 108 of the transistor 100, the region in contact with the insulating layer 110a and the insulating layer 110c is reduced in resistance and does not become a channel formation region, so that the channel formation region is smaller than that of the semiconductor layer 108 of the transistor 100. Figure 5C In addition, Fig. 12B As shown, in the semiconductor layer 208 of the transistor 200, the region in contact with the insulating layer 110a and the insulating layer 110c is reduced in resistance and does not become a channel formation region, so that the channel formation region is smaller than that of the transistor 200. Figure 7 The short one.

[0241] In addition, Fig. 12AIn the structural example of the transistor 100 shown, when the conductive layer 112a is used as a drain electrode, it can be considered that the semiconductor layer 108 has a low resistance region between the region in contact with the drain electrode and the channel formation region. As a result, it is not easy to generate a high electric field near the drain region, and the generation of hot carriers is suppressed, thereby suppressing the degradation of the transistor. In addition, when the conductive layer 112b is used as a drain electrode, it can be considered that the semiconductor layer 108 has a low resistance region between the region in contact with the drain electrode and the channel formation region. As a result, it is not easy to generate a high electric field near the drain region, and the generation of hot carriers is suppressed, thereby suppressing the degradation of the transistor. Regardless of which of the conductive layer 112a and the conductive layer 112b is the drain electrode, the transistor 100 can achieve high reliability. As a result, the design freedom of the semiconductor device can be improved.

[0242] In addition, Fig. 12B In the structural example of the transistor 200 shown, when the conductive layer 212a is used as a drain electrode, it can be considered that the semiconductor layer 208 has a low resistance region between the region in contact with the drain electrode and the channel formation region. As a result, it is not easy to generate a high electric field near the drain region and the generation of hot carriers can be suppressed, thereby suppressing transistor degradation. In addition, when the conductive layer 212b is used as a drain electrode, it can also be said that the semiconductor layer 208 has a low resistance region between the region in contact with the drain electrode and the channel formation region. As a result, it is not easy to generate a high electric field near the drain region and the generation of hot carriers can be suppressed, thereby suppressing transistor degradation. Whether the conductive layer 212a is a drain electrode or the conductive layer 212b is a drain electrode, the transistor 200 can have high reliability. Therefore, the design freedom of the semiconductor device can be improved.

[0243] In addition, the insulating layer 110c may have a stacked structure of two or more layers. For example, the insulating layer 110c may have a stacked structure of two layers, namely, an insulating layer 110c1 and an insulating layer 110c2 on the insulating layer 110c1.

[0244] In addition, the insulating layer 110a may also have a stacked structure of two or more layers. For example, the insulating layer 110a may have a stacked structure of two layers, namely, an insulating layer 110a1 and an insulating layer 110a2 on the insulating layer 110a1.

[0245] Fig.13A yes Figure 5B An enlarged view of the region 41 is shown, Fig. 13B yes Figure 6B The enlarged view of the region 42 shown shows an example in which the insulating layer 110a has a two-layer stacked structure of the insulating layer 110a1 and the insulating layer 110a2 on the insulating layer 110a1, and the insulating layer 110c has a two-layer stacked structure of the insulating layer 110c1 and the insulating layer 110c2 on the insulating layer 110c1.

[0246] The insulating layer 110c2 is preferably a film that releases hydrogen when heated. Thus, a low resistance region can be formed near a region of the semiconductor layer 108 in the transistor 100 that contacts the conductive layer 112b and near a region of the semiconductor layer 208 in the transistor 200 that contacts the conductive layer 212b, and when the conductive layer 112b is used as a drain electrode of the transistor 100 and the conductive layer 212b is used as a drain electrode of the transistor 200, generation of hot carriers can be suppressed.

[0247] In addition, the insulating layer 110c1 preferably has a region with a lower hydrogen content than the insulating layer 110c2. Thus, it is possible to suppress the diffusion of hydrogen from the insulating layer 110c2 to a region (desirably formed into an i-type region) in the insulating layer 110b and the semiconductor layer of the transistor (the semiconductor layer 108 of the transistor 100 or the semiconductor layer 208 of the transistor 200) to which a gate electric field is sufficiently applied.

[0248] The insulating layer 110a1 is preferably a film that releases hydrogen when heated. As a result, a low resistance region can be formed near a region of the semiconductor layer 108 in the transistor 100 that is in contact with the conductive layer 112a and near a region of the semiconductor layer 208 in the transistor 200 that is in contact with the conductive layer 212a. When the conductive layer 112a is used as a drain electrode of the transistor 100 and the conductive layer 212a is used as a drain electrode of the transistor 200, generation of hot carriers can be suppressed.

[0249] The insulating layer 110a2 preferably has a region with a lower hydrogen content than the insulating layer 110a1. Thus, diffusion of hydrogen from the insulating layer 110a1 to the insulating layer 110b and the region (desirably i-type region) in the semiconductor layer of the transistor (the semiconductor layer 108 of the transistor 100 or the semiconductor layer 208 of the transistor 200) where a gate electric field is sufficiently applied can be suppressed.

[0250] As a film that releases hydrogen when heated, one or more of the above-mentioned oxide insulating film, nitride insulating film, oxynitride insulating film and nitride oxide insulating film can be used, and one or more of the above-mentioned silicon nitride film, silicon nitride oxide film, oxynitride silicon film, aluminum oxide film, oxynitride aluminum film, aluminum nitride film, hafnium oxide film and hafnium aluminate film can also be used.

[0251] As the film that releases hydrogen when heated, it is preferable to use one or more of a nitride insulating film and a nitride oxide insulating film. Specifically, it is preferable to use one or both of a silicon nitride film and a silicon nitride oxide film.

[0252] In addition, silicon nitride film and silicon oxynitride film can realize a film that releases more hydrogen by changing the deposition conditions (for example, the deposition gas or the power during deposition). In addition, a film that releases less impurities (for example, water and hydrogen) and through which oxygen and hydrogen do not easily pass can be realized by changing the deposition conditions.

[0253] Thus, when a silicon nitride film or a silicon nitride oxide film is used for the insulating layer 110a1 and the insulating layer 110c2, a film that releases a large amount of hydrogen can be used. When a silicon nitride film or a silicon nitride oxide film is used for the insulating layer 110a2 and the insulating layer 110c1, a film that releases a small amount of its own impurities (for example, water and hydrogen) and through which oxygen and hydrogen do not easily pass can be used.

[0254] The hydrogen content is lower than that of main components constituting the insulating layer (for example, nitrogen and silicon in the silicon nitride layer). Therefore, the hydrogen contents of the layers constituting the insulating layer 110 are preferably compared by SIMS analysis.

[0255] In addition, among the layers constituting the insulating layer 110, even if the layers have the same main component (for example, a silicon nitride layer), it is possible to distinguish the two layers based on the difference in brightness by observing the cross section using a scanning transmission electron microscope (STEM) or the like. For example, in a transmission electron (TE) image, it is sometimes observed that a silicon nitride film (or silicon oxynitride film) that releases a large amount of hydrogen has a higher brightness than a silicon nitride film (or silicon oxynitride film) that releases a small amount of its own impurities (for example, water and hydrogen) and through which oxygen and hydrogen do not easily pass.

[0256] [Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a, and conductive layer 212b]

[0257] Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a and conductive layer 212b may have a single-layer structure or a stacked structure of two or more layers. As materials that can be used for conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a and conductive layer 212b, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, ruthenium and niobium and alloys containing one or more of the above metals as components can be cited. Low-resistance conductive materials containing one or more of copper, silver, gold and aluminum can be appropriately used for conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a and conductive layer 212b. In particular, copper or aluminum has advantages in mass production and is therefore preferred.

[0258] Conductive layers 112a, 112b, 104, 204, 212a, and 212b may be made of conductive metal oxides (also referred to as oxide conductors). Examples of oxide conductors (OC) include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also referred to as ITO or ITSO containing silicon), zinc oxide to which gallium is added, and In-Ga-Zn oxide. In particular, conductive oxides containing indium are preferably used because they have high conductivity.

[0259] For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies to form donor energy levels near the conduction band. As a result, the conductivity of the metal oxide increases, and the metal oxide becomes a conductor. Metal oxides that can become conductors are called oxide conductors.

[0260] As the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, a stacked-layer structure of a conductive film containing the above-mentioned oxide conductor (metal oxide) and a conductive film containing a metal or an alloy may be used. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0261] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta or Ti) may be applied as the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a and the conductive layer 212b. By using the Cu-X alloy film, processing can be performed using a wet etching method, thereby reducing manufacturing costs.

[0262] Note that materials used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may all be the same or at least part of them may be different.

[0263] Note that in this specification and the like, different materials refer to materials having different constituent elements or materials having the same constituent elements but different compositions.

[0264] The conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108. In addition, the conductive layer 212a and the conductive layer 212b have a region in contact with the semiconductor layer 208. In the case where an oxide semiconductor is used as the semiconductor layer 108, there is the following concern: when an easily oxidized metal (for example, aluminum) is used as the conductive layer 112a or the conductive layer 112b, an insulating oxide (for example, aluminum oxide) is formed between the conductive layer 112a and the semiconductor layer 108 or between the conductive layer 112b and the semiconductor layer 108, thereby hindering their conduction. Therefore, the conductive layer 112a and the conductive layer 112b preferably use a conductive material that is not easily oxidized or a conductive material that maintains low resistance even if oxidized. In addition, when the semiconductor layer 208 uses an oxide semiconductor, the conductive layer 212a and the conductive layer 212b are also the same. It is preferred that the conductive layer 212a and the conductive layer 212b use a conductive material that is not easily oxidized or a conductive material that maintains low resistance even if oxidized.

[0265] As the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b, for example, one or more of titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferably used. These materials are conductive materials that are not easily oxidized or conductive materials that maintain low resistance even if oxidized, and therefore are preferred.

[0266] The above-mentioned oxide conductors can be used for the conductive layers 112a, 112b, 212a, and 212b. Specifically, one or more of indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide added with gallium can be used.

[0267] Conductive layer 112a, conductive layer 112b, conductive layer 212a, and conductive layer 212b may also be made of a nitride conductor, such as tantalum nitride or titanium nitride.

[0268] The conductive layer 112a and the conductive layer 112b may both have a stacked structure. When a stacked structure is adopted, at least one side in contact with the semiconductor layer 108 is preferably made of a conductive material that is not easily oxidized or a conductive material that maintains low resistance even if oxidized. For example, the conductive layer 112a may have a stacked structure of an aluminum film and a titanium film on the aluminum film. The titanium film has a region in contact with the semiconductor layer 108. In addition, the conductive layer 112a may have a stacked structure of a first titanium film, an aluminum film on the first titanium film, and a second titanium film on the aluminum film. The second titanium film has a region in contact with the semiconductor layer 108.

[0269] The conductive layer 212a and the conductive layer 212b may both have a stacked structure. When a stacked structure is used, at least one side in contact with the semiconductor layer 208 preferably uses a conductive material that is not easily oxidized or a conductive material that maintains low resistance even if oxidized. For example, the conductive layer 212a may have a stacked structure of an aluminum film and a titanium film on the aluminum film. The titanium film has a region in contact with the semiconductor layer 208. In addition, the conductive layer 212a may have a stacked structure of a first titanium film, an aluminum film on the first titanium film, and a second titanium film on the aluminum film. The second titanium film has a region in contact with the semiconductor layer 208.

[0270] [Insulating layer 106]

[0271] The insulating layer 106 may have a single-layer structure or a stacked-layer structure of two or more layers. The insulating layer 106 preferably includes one or more inorganic insulating films. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. The insulating layer 106 may use a material that can be used for the insulating layer 110.

[0272] The insulating layer 106 has a region in contact with the semiconductor layer 108 and the semiconductor layer 208. When the semiconductor layer 108 and the semiconductor layer 208 use an oxide semiconductor, it is preferable that at least one of the films constituting the insulating layer 106 that is in contact with the semiconductor layer 108 or the semiconductor layer 208 is formed using the above-described oxide insulating film and oxynitride insulating film. In addition, it is more preferable that the insulating layer 106 use a film that releases oxygen by heating.

[0273] Specifically, when the insulating layer 106 has a single-layer structure, the insulating layer 106 is preferably formed using a silicon oxide film or a silicon oxynitride film.

[0274] The insulating layer 106 may have a stacked-layer structure of an oxide insulating film or an oxynitride insulating film in contact with the semiconductor layer 108, and a nitride insulating film or an oxynitride insulating film in contact with the conductive layer 104 and the conductive layer 204. As the oxide insulating film or the oxynitride insulating film, for example, a silicon oxide film or a silicon oxynitride film is preferably used. As the nitride insulating film or the oxynitride insulating film, a silicon nitride film or a silicon oxynitride film is preferably used.

[0275] The silicon nitride film and the silicon nitride oxide film have characteristics that the amount of impurities (for example, water and hydrogen) released from the film is small and oxygen and hydrogen are not easily permeable, and thus can be suitably used as the insulating layer 106. Since the diffusion of impurities from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 208 is suppressed, good electrical characteristics of the transistor can be achieved and reliability can be improved.

[0276] Note that in a micro transistor, when the thickness of the gate insulating layer is small, the leakage current sometimes increases. By using a material with a high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. As high-k materials that can be used for the insulating layer 106, for example, gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium can be cited.

[0277] [Insulation layer 195]

[0278] The insulating layer 195 used as a protective layer of the transistor 100 and the transistor 200 is preferably made of a material in which impurities are not easily diffused. By providing the insulating layer 195, it is possible to effectively suppress the diffusion of impurities from the outside into the transistor, thereby improving the reliability of the display device. Examples of the impurities include water and hydrogen.

[0279] The insulating layer 195 may be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, the insulating layer 195 may appropriately use an inorganic material such as an oxide, an oxynitride, an oxynitride, or a nitride. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate may be used. As an organic material, for example, one or more of an acrylic resin and a polyimide resin may be used. As an organic material, a photosensitive material may also be used. In addition, two or more of the above-mentioned insulating films may also be stacked. The insulating layer 195 may also have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0280] [Substrate 102]

[0281] Although there is no particular limitation on the material of the substrate 102, it is at least required to have heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate or polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate can be used as the substrate 102. In addition, a semiconductor element may be provided on the substrate 102. Note that the shape of the semiconductor substrate and the insulating substrate may be circular or square.

[0282] As the substrate 102, a flexible substrate may be used, and the transistor 100 and the transistor 200 may be directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the transistor 200. By providing the peeling layer, a part or all of the semiconductor device may be manufactured on the peeling layer, and then it may be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the transistor 200 may also be transferred to a substrate with low heat resistance or a flexible substrate.

[0283] <Structure Example 2>

[0284] Figure 4A A top view of a semiconductor device 10 according to one embodiment of the present invention is shown. Figure 4B Shown along Figure 4A The cross-sectional view is a cross-sectional view taken along the dashed line A1 - A2 shown.

[0285] Figure 4A and Figure 4B The semiconductor device 10 shown includes a transistor 100 and a transistor 200. The semiconductor device 10 is similar to the semiconductor device 100 in that it mainly includes a conductive layer 103, a conductive layer 203 and an insulating layer 107. Figure 1A and Figure 1B The semiconductor device 10 shown in the figure is different.

[0286] Figure 4A and Figure 4B The transistor 100 shown includes a conductive layer 103 and an insulating layer 107 between the conductive layer 112a and the insulating layer 110. Figure 4A and Figure 4B The transistor 200 shown includes a conductive layer 203 and an insulating layer 107 between the conductive layer 212 a and the insulating layer 110 .

[0287] The insulating layer 107 includes a region located on the conductive layer 112a and a region located on the conductive layer 212a. The insulating layer 107 includes a region provided to cover the top surface and side surfaces of the conductive layer 112a and a region provided to cover the top surface and side surfaces of the conductive layer 212a.

[0288] Conductive layer 103 is located on insulating layer 107. Conductive layer 112a and conductive layer 103 are electrically insulated from each other by insulating layer 107. An opening 148 that reaches insulating layer 107 is provided in a region of conductive layer 103 that overlaps with conductive layer 112a.

[0289] Conductive layer 203 is located on insulating layer 107. Conductive layer 212a and conductive layer 203 are electrically insulated from each other by insulating layer 107. An opening 248 that reaches insulating layer 107 is provided in a region of conductive layer 203 that overlaps with conductive layer 212a.

[0290] The insulating layer 110 is provided on the insulating layer 107, the conductive layer 103, and the conductive layer 203. The insulating layer 110 is provided so as to cover the top surface and the side surface of the conductive layer 103, the top surface and the side surface of the conductive layer 203, and the top surface of the insulating layer 107. The insulating layer 110 and the insulating layer 107 have openings 141 that reach the conductive layer 112a in the regions overlapping with the conductive layer 112a. In addition, the insulating layer 110 and the insulating layer 107 have openings 241 that reach the conductive layer 212a in the regions overlapping with the conductive layer 212a.

[0291] The insulating layer 110a is located on the insulating layer 107, the conductive layer 103, and the conductive layer 203. The insulating layer 110a includes a region provided so as to cover the top surface and the side surface of the conductive layer 103 and a region provided so as to cover the top surface and the side surface of the conductive layer 203. The insulating layer 110a is provided so as to cover a part of the opening 148. The insulating layer 110a is in contact with the insulating layer 107 through the opening 148. In addition, the insulating layer 110a is provided so as to cover a part of the opening 248. The insulating layer 110a is in contact with the insulating layer 107 through the opening 248.

[0292] The top surface shapes of the openings 148 and 248 are not particularly limited. The top surface shape of the opening 148 may be a shape that can be used for the openings 141 and 143. Figure 4A As shown, the top surface shapes of the openings 141, 143, and 148 are preferably circular. By making the top surface shape of the openings circular, the top surface shape of the opening 248 can be made into a shape that can be used for the openings 241 and 243. Figure 4A As shown, it is preferred that the top surfaces of the openings 241, 243, and 248 are all circular. When the top surfaces of the openings are circular, the processing accuracy when forming the openings can be improved, and fine openings can be formed.

[0293] In this specification and the like, the top surface shape of the opening 148 refers to the shape of the top surface end portion or the shape of the bottom surface end portion of the conductive layer 103 on the opening 148 side. Figure 4A A shape 148t of the top surface end portion of the conductive layer 103 on the opening 148 side is shown. In this specification, etc., the top surface shape of the opening 248 refers to the shape of the top surface end portion or the shape of the bottom surface end portion of the conductive layer 103 on the opening 248 side. Figure 4A The shape 248t of the top surface end portion of the conductive layer 203 on the opening 248 side is shown.

[0294] When the top surface shapes of the openings 141 and 148 are circular, the openings 141 and 148 are preferably concentric circles. Thus, the shortest distances between the semiconductor layer 108 and the conductive layer 103 on the left and right sides of the opening 141 can be equal when viewed in cross section. In addition, the openings 141 and 148 are sometimes not concentric circles. In addition, when the top surface shapes of the openings 241 and 248 are circular, the openings 241 and 248 are preferably concentric circles. Thus, the shortest distances between the semiconductor layer 208 and the conductive layer 203 on the left and right sides of the opening 241 when viewed in cross section can be equal. In addition, the openings 241 and 248 are sometimes not concentric circles.

[0295] In the transistor 100, the semiconductor layer 108 has a region that overlaps with the conductive layer 104 via the insulating layer 106 and overlaps with the conductive layer 103 via a portion of the insulating layer 110 (particularly, the insulating layer 110a and the insulating layer 110b). In other words, the semiconductor layer 108 includes a region sandwiched between the conductive layer 104 and the conductive layer 103, the insulating layer 106 is sandwiched between the region and the conductive layer 104, and a portion of the insulating layer 110 (particularly, the insulating layer 110a and the insulating layer 110b) is sandwiched between the region and the conductive layer 103.

[0296] The conductive layer 103 functions as a back gate electrode of the transistor 100. In addition, a portion of the insulating layer 110 functions as a back gate insulating layer of the transistor 100.

[0297] In the transistor 200, the semiconductor layer 208 has a region that overlaps with the conductive layer 204 via the insulating layer 106 and overlaps with the conductive layer 203 via a portion of the insulating layer 110 (particularly, the insulating layer 110a and the insulating layer 110b). In other words, the semiconductor layer 208 includes a region sandwiched between the conductive layer 204 and the conductive layer 203, the insulating layer 106 is sandwiched between the region and the conductive layer 204, and a portion of the insulating layer 110 (particularly, the insulating layer 110a and the insulating layer 110b) is sandwiched between the region and the conductive layer 203.

[0298] The conductive layer 203 functions as a back gate electrode of the transistor 200. In addition, a portion of the insulating layer 110 functions as a back gate insulating layer of the transistor 200.

[0299] The conductive layer 103 and the conductive layer 203 can use the materials that can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 212b, the conductive layer 104, and the conductive layer 204.

[0300] By providing a back gate electrode for the transistor 100, the potential on the back channel side of the semiconductor layer can be fixed, thereby improving the saturation characteristics of the Id-Vd characteristics of the transistor 100. By fixing the potential on the back channel side of the semiconductor layer 108, the threshold voltage drift can be suppressed. By suppressing the drift of the threshold voltage of the transistor 100, a transistor with a small off-current can be realized.

[0301] Note that in this specification and the like, a transistor may be expressed as “having a high saturation characteristic” or “having a high saturation characteristic” when a current change in a saturation region of the Id-Vd characteristic of the transistor is small.

[0302] The insulating layer 107 can use a material that can be used for the insulating layer 110. The insulating layer 107 is preferably an insulating layer containing nitrogen. The insulating layer 107 is preferably a material that can be used for the insulating layer 110a and the insulating layer 110c. For example, silicon nitride is preferably used for the insulating layer 107. Note that although the insulating layer 107 having a single-layer structure is shown in this embodiment, one embodiment of the present invention is not limited to this. The insulating layer 107 may have a stacked-layer structure of two or more layers.

[0303] In transistor 100 and transistor 200, a structure in which a back gate electrode is electrically connected to a source electrode or a drain electrode can be adopted. By electrically connecting the back gate electrode to the source electrode, the threshold voltage drift of the transistor can be suppressed. In addition, the reliability of the transistor can be improved.

[0304] In addition, a structure in which a back gate electrode is electrically connected to a gate electrode can be adopted in the transistor 100 and the transistor 200. By electrically connecting the back gate electrode to the gate electrode, the on-state current of the transistor can be increased.

[0305] By providing an opening in a region of the insulating layer 107 that overlaps with the conductive layer 112a and providing the conductive layer 103 to cover the opening, the conductive layer 103 can be in contact with the conductive layer 112a.

[0306] By providing an opening in a region of the insulating layer 110 that overlaps with the conductive layer 103 and providing the conductive layer 112 b to cover the opening, the conductive layer 103 and the conductive layer 112 b can be in contact with each other.

[0307] Openings are provided in regions of the insulating layer 106 and the insulating layer 110 that overlap with the conductive layer 103 , and the conductive layer 104 is provided to cover the openings, so that the conductive layer 103 and the conductive layer 104 can be in contact with each other.

[0308] By providing an opening in a region of the insulating layer 107 that overlaps with the conductive layer 212a and providing the conductive layer 203 to cover the opening, the conductive layer 203 can be in contact with the conductive layer 212a.

[0309] By providing an opening in a region of the insulating layer 110 that overlaps with the conductive layer 203 and providing the conductive layer 212 b to cover the opening, the conductive layer 203 and the conductive layer 212 b can be in contact with each other.

[0310] By providing openings in the insulating layer 106 and the insulating layer 110 in regions overlapping with the conductive layer 203 and providing the conductive layer 204 to cover the openings, the conductive layer 203 and the conductive layer 204 can be in contact with each other.

[0311] The thickness of the conductive layer 103 is preferably 0.5 times or more, more preferably 1.0 times or more, and further preferably more than 1.0 times the channel length L1, and is preferably 2.0 times or less, more preferably 1.5 times or less, and further preferably 1.2 times or less. Thus, the region of the semiconductor layer 108 that overlaps with the conductive layer 104 via the insulating layer 106 and overlaps with the conductive layer 103 via the insulating layer 110 can be fully expanded. Thus, the potential on the back channel side of the semiconductor layer 108 can be more reliably controlled.

[0312] The thickness of the conductive layer 103 may be greater than the thickness of the insulating layer 110. Thus, the potential on the back channel side of the semiconductor layer 108 can be fixed over a wide range between the source region and the drain region in the semiconductor layer 108.

[0313] Figure 4A and Figure 4B The transistor 100 in FIG. 1 has a region where a conductive layer 103, an insulating layer 110, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104 overlap in sequence in one direction, and no other layers are included therebetween. The direction may be a direction perpendicular to the channel length L1. By expanding the region, the potential on the back channel side of the semiconductor layer 108 can be more reliably controlled.

[0314] The thickness of the conductive layer 103 may be greater than the sum of the thickness of a portion in contact with the conductive layer 112 a inside the opening 141 in the semiconductor layer 108 and the thickness of the insulating layer 106 in contact with the portion.

[0315] The thickness of the conductive layer 203 is preferably 0.5 times or more, more preferably 1.0 times or more, and further preferably more than 1.0 times the channel length L2, and is preferably 2.0 times or less, more preferably 1.5 times or less, and further preferably 1.2 times or less. Thus, the region of the semiconductor layer 208 that overlaps with the conductive layer 204 via the insulating layer 106 and overlaps with the conductive layer 203 via the insulating layer 110 can be fully expanded. Therefore, the potential on the back channel side of the semiconductor layer 208 can be more reliably controlled.

[0316] The thickness of the conductive layer 203 may be greater than the thickness of the insulating layer 110. Thus, the potential on the back channel side of the semiconductor layer 208 can be fixed over a wide range between the source region and the drain region in the semiconductor layer 208.

[0317] Figure 4A and Figure 4B The transistor 200 in the embodiment has a region where a conductive layer 203, an insulating layer 110, a semiconductor layer 208, an insulating layer 106, and a conductive layer 204 are sequentially overlapped in one direction without any other layers therebetween. The direction may be a direction perpendicular to the channel length L2. By expanding the region, the potential on the back channel side of the semiconductor layer 208 can be more reliably controlled.

[0318] The thickness of the conductive layer 203 may be greater than the sum of the thickness of a portion in contact with the conductive layer 212 a inside the opening 241 in the semiconductor layer 208 and the thickness of the insulating layer 106 in contact with the portion.

[0319] Here, the conductive layer 103 is oxidized due to oxygen contained in the insulating layer 110b, and the resistance may increase. By providing the insulating layer 110a between the insulating layer 110b and the conductive layer 103, the conductive layer 103 can be prevented from being oxidized and the resistance can be prevented from being increased. In addition, by providing the insulating layer 110c between the insulating layer 110b and the conductive layer 112b, the conductive layer 112b can be prevented from being oxidized and the resistance can be prevented from being increased. At the same time, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is increased, and oxygen vacancies in the semiconductor layer 108 can be reduced.

[0320] <Structure Example 3>

[0321] Fig.14A A cross-sectional view showing a structure including transistor 200 ( 1 ) and transistor 200 ( 2 ) is shown.

[0322] Transistor 200(1) and transistor 200(2) can refer to the transistor 200 described previously, and the difference between them and the transistor 200 described previously is that: instead of including conductive layer 212b separately, a conductive layer 212b_A shared by the two transistors is provided; instead of including conductive layer 204 separately, a conductive layer 204_A shared by the two transistors is provided.

[0323] exist Fig.14A In the embodiment, part of the conductive layer 212b_A functions as one of the source electrode and the drain electrode of the transistor 200(1), and the other part functions as one of the source electrode and the drain electrode of the transistor 200(2).

[0324] In addition, Fig.14AIn the embodiment, a portion of the conductive layer 204_A is used as a gate electrode of the transistor 200(1), and another portion is used as a gate electrode of the transistor 200(2).

[0325] Since the transistor 200 ( 1 ) and the transistor 200 ( 2 ) share a gate electrode and have one of a source electrode and a drain electrode electrically connected to each other, it can be said that they are connected in series. Fig. 14C An example of a circuit diagram corresponding to transistor 200(1) and transistor 200(2) connected in series is shown. P is a wiring corresponding to conductive layer 212a in transistor 200(1), Q is a wiring corresponding to conductive layer 212a in transistor 200(2), and G is a wiring corresponding to conductive layer 204_A.

[0326] You can Fig. 14C The two transistors connected in series are shown as Fig.14D A transistor 200A is shown. When the channel length of the two transistors is L and the channel width is W, it can be considered that the channel length of the transistor 200A is 2×L and the channel width is W.

[0327] Fig. 14B The structure shown includes a transistor 200(1) and a transistor 200(2). The transistor 200(1) and the transistor 200(2) can refer to the transistor 200 described previously, and the difference between them and the transistor 200 described previously is that instead of including the conductive layer 212a separately, a conductive layer 212a_A shared by the two transistors is provided; instead of including the conductive layer 204 separately, a conductive layer 204_A shared by the two transistors is provided.

[0328] exist Fig. 14C In the example, when P is the wiring corresponding to the conductive layer 212b in the transistor 200(1), Q is the wiring corresponding to the conductive layer 212b in the transistor 200(2), and G is the wiring corresponding to the conductive layer 204_A, Fig. 14C The structure shown is the same as Fig. 14B The structure shown.

[0329] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0330] (Implementation Method 2)

[0331] In this embodiment, a method for manufacturing a display device according to one embodiment of the present invention is described with reference to Fig. 15 to Fig. 17. Note that regarding materials and formation methods of each component, parts that are the same as those described in Embodiment 1 may be omitted.

[0332] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed by sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition) method, vacuum evaporation method, pulsed laser deposition (PLD: Pulsed Laser Deposition) method, ALD method, etc. CVD methods include PECVD method and thermal CVD method, etc. In addition, as one of the thermal CVD methods, there is metal organic chemical vapor deposition (MOCVD: Metal Organic CVD) method.

[0333] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using wet deposition methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or doctor knife coating.

[0334] When processing a thin film constituting a semiconductor device, photolithography or the like can be used. Alternatively, the thin film can be processed by nanoimprinting, sandblasting, lift-off, etc. In addition, an island-shaped thin film can be directly formed by a deposition method using a shadow mask such as a metal mask.

[0335] There are two typical photolithography methods. One is to form a resist mask on a thin film to be processed, process the thin film by etching, etc., and remove the resist mask. The other is to deposit a photosensitive thin film, then expose and develop it, and process the thin film into a desired shape.

[0336] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm) or a mixture of these lights can be used. In addition, ultraviolet light, KrF laser or ArF laser, etc. can also be used. In addition, liquid immersion exposure technology can also be used for exposure. In addition, as the light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-violet) light or X-rays can also be used. In addition, instead of the light used for exposure, an electron beam can also be used. When extreme ultraviolet light, X-rays or electron beams are used, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0337] As a method for etching the thin film, a dry etching method, a wet etching method, a sand blast method, or the like can be used.

[0338] <Manufacturing method example 1>

[0339] Below, with Figure 1BThe manufacturing method will be described using the semiconductor device 10 shown in A as an example.

[0340] FIG. 15A to FIG. 17C Each of the drawings is a diagram for explaining a method for manufacturing the semiconductor device 10. Each of the drawings is a cross-sectional view taken along a dashed line A1-A2.

[0341] First, the conductive layer 112a and the conductive layer 212a are formed over the substrate 102, and the insulating film 110af to be the insulating layer 110a and the insulating film 110bf to be the insulating layer 110b are formed over the conductive layer 112a and the conductive layer 212a.

[0342] The conductive film to be the conductive layer 112a and the conductive layer 212a is preferably formed by, for example, a sputtering method. A resist mask is formed on the conductive film by a photolithography step, and then the conductive film is processed, whereby the conductive layer 112a and the conductive layer 212a can be formed.

[0343] When forming the insulating film 110af and the insulating film 110bf, for example, a sputtering method or a PECVD method is preferably used. After forming the insulating film 110af, it is preferable to continuously form the insulating film 110bf in a vacuum so that the surface of the insulating film 110af is not exposed to the atmosphere. By continuously forming the insulating film 110af and the insulating film 110bf, it is possible to suppress impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic matter.

[0344] The substrate temperature when forming the insulating film 110af and the insulating film 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, more preferably 250° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 400° C. or lower, and more preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature when forming the insulating film 110af and the insulating film 110bf within the above range, the release of impurities (for example, water and hydrogen) from the insulating film 110af and the insulating film 110bf themselves can be reduced, thereby suppressing the diffusion of impurities into the semiconductor layer 108. Therefore, a transistor having good electrical characteristics and high reliability can be realized.

[0345] After the insulating film 110bf is formed, oxygen may also be supplied to the insulating film 110bf. As a method for supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment may be used. As a plasma treatment, it is preferred to use a device that plasma-izes an oxygen gas with a high-frequency power. As a device that plasma-izes a gas with a high-frequency power, for example, a PECVD device, a plasma etching device, and a plasma ashing device may be cited. The plasma treatment is preferably carried out in an oxygen-containing atmosphere. For example, it is preferred to carry out the plasma treatment in an atmosphere containing one or more of oxygen, nitrous oxide (N2O), nitrogen dioxide (NO2), carbon monoxide, and carbon dioxide.

[0346] Note that the plasma treatment may be continuously performed in a vacuum without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD device is used to form the insulating film 110bf, the plasma treatment is preferably performed using the PECVD device. This can improve productivity.

[0347] Alternatively, a metal oxide layer may be formed after the insulating film 110bf is formed. By forming the metal oxide layer, oxygen can be supplied to the insulating film 110bf.

[0348] There is no limitation on the conductivity of the metal oxide layer. The metal oxide layer may use at least one of an insulating film, a semiconductor film, and a conductive film. The metal oxide layer may use, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO).

[0349] As the metal oxide layer, an oxide material containing one or more elements common to the semiconductor layer 108 and the semiconductor layer 208 is preferably used. In particular, an oxide semiconductor material that can be used for the semiconductor layer 108 and the semiconductor layer 208 is preferably used.

[0350] When forming the metal oxide layer, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the processing chamber of the deposition device (oxygen flow rate ratio) or the oxygen partial pressure in the processing chamber is, the greater the amount of oxygen supplied to the insulating film 110af can be. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more and 100% or less, and further preferably 90% or more and 100% or less. In particular, it is preferred to set the oxygen flow rate ratio to 100% to make the oxygen partial pressure as close to 100% as possible.

[0351] In this way, by forming the metal oxide layer by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf while preventing oxygen from being separated from the insulating film 110bf when the metal oxide layer is formed. As a result, a large amount of oxygen can be enclosed in the insulating film 110bf. In addition, a large amount of oxygen can be supplied to the semiconductor layer 108 by the subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. O H, and a transistor with good electrical characteristics and high reliability can be realized.

[0352] It is preferable to perform the heat treatment after forming the metal oxide layer. By performing the heat treatment after forming the metal oxide layer, oxygen can be efficiently supplied from the metal oxide layer to the insulating film 110bf.

[0353] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, more preferably 250° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 400° C. or lower, and more preferably 350° C. or higher and 400° C. or lower. The heat treatment may be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. As a nitrogen-containing atmosphere or an oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may also be used. Note that the content of hydrogen or oxygen in the atmosphere is preferably as small as possible. As the atmosphere, a high-purity gas having a dew point of -60° C. or lower, preferably -100° C. or lower is preferably used. By using an atmosphere containing as little hydrogen, water, or the like as possible, it is possible to prevent hydrogen, water, or the like from being absorbed by the insulating film 110 bf or the like as much as possible. An oven, a rapid thermal annealing (RTA: Rapid Thermal Annealing) device, or the like may be used for the heat treatment. By using an RTA device, the heat treatment time may be shortened.

[0354] After the metal oxide layer is formed or after the above-mentioned heat treatment, oxygen may be supplied to the insulating film 110bf through the metal oxide layer. As a method for supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment may be used. For plasma treatment, the above description may be referred to, so its detailed description is omitted.

[0355] Next, the metal oxide layer is removed after the formation or after the above-mentioned heat treatment or after the above-mentioned supply of oxygen. There is no particular limitation on the method for removing the metal oxide layer, but a wet etching method is preferably used. By using a wet etching method, it is possible to suppress the insulating film 110bf from being etched when removing the metal oxide layer. Therefore, it is possible to suppress the thickness of the insulating film 110bf from becoming smaller, and the thickness of the insulating layer 110b can be made uniform.

[0356] The oxygen supply treatment of the insulating film 110bf is not limited to the above method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. are supplied to the insulating film 110bf by ion doping, ion implantation, plasma treatment, etc. In addition, after a film for inhibiting oxygen detachment is formed on the insulating film 110bf, oxygen is supplied to the insulating film 110bf through the film. It is preferred to remove the film after supplying oxygen. As the above-mentioned film for inhibiting oxygen detachment, a conductive film or semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt or tungsten can be used.

[0357] Next, an insulating film 110 cf serving as the insulating layer 110 c is formed on the insulating film 110 bf .

[0358] The insulating film 110 cf can be formed by, for example, sputtering or PECVD.

[0359] Next, a conductive film to be the conductive layer 112b and the conductive layer 212b is formed over the insulating film 110cf. The conductive film can be formed by, for example, a sputtering method.

[0360] Next, the conductive film is processed to form conductive layers 112b_e and 212b_e ( Fig.15A ). Conductive layer 112b_e becomes conductive layer 112b later, and conductive layer 212b_e becomes conductive layer 212b later. Conductive layer 112b_e and conductive layer 212b_e can be formed by, for example, wet etching. Alternatively, dry etching can be used.

[0361] Next, a resist mask 190A is formed on the conductive layer 112b_e, the conductive layer 212b_e, and the insulating film 110cf. Fig.15A ).

[0362] Next, a portion of the conductive layer 112b-e is removed using the resist mask 190A, thereby forming the conductive layer 112b having the opening 143. The conductive layer 112b can be formed by a wet etching method. Alternatively, a dry etching method can also be used.

[0363] Next, the insulating film 110cf, the insulating film 110bf, and a portion of the insulating film 110af are removed to form an opening 141 ( Fig. 15B ). The insulating film 110cf, the insulating film 110bf, and the insulating film 110af after the opening 141 is formed are represented by the insulating layer 110cg, the insulating layer 110bg, and the insulating layer 110ag, respectively. The opening 141 is provided in a region overlapping with the opening 143. The formation of the opening 141 exposes the conductive layer 112a. The dry etching method is applicable to the formation of the insulating layer 110cg, the insulating layer 110bg, and the insulating layer 110ag.

[0364] The opening 141 can be formed using, for example, the resist mask 190A. Alternatively, the opening 141 can be formed using a resist mask different from the resist mask 190A.

[0365] For example, the resist mask 190A may be removed after the opening 141 is formed. Alternatively, the resist mask 190A may be removed after the opening 143 is formed and before the insulating layer 110cg, before the insulating layer 110bg, or before the insulating layer 110ag is formed.

[0366] Furthermore, a portion of the conductive layer 112a in a region overlapping with the opening 141 may be removed when or after the opening 141 is formed. By making the thickness of the conductive layer 112a in a region in contact with the bottom surface of the semiconductor layer 108 thinner than the thickness of the region not in contact with the semiconductor layer 108, an electric field applied to the gate electrode in a channel formation region near the conductive layer 112a can be enhanced, thereby increasing the on-state current of the transistor.

[0367] Next, a resist mask 190B is formed on the conductive layer 112b, the conductive layer 212b_e, and the insulating layer 110cg ( Fig. 15C ).

[0368] Next, a portion of the conductive layer 212b_e is removed using the resist mask 190B, thereby forming an opening in the conductive layer 212b_e. The formation of the opening is suitable for using a wet etching method. Alternatively, the formation of the opening can also use a dry etching method. Here, the opening provided in the conductive layer 212b_e can be, for example, an opening smaller than the opening 243. In the formation process of the insulating layer 110 described later, the end of the opening can be retreated, thereby forming the opening 243.

[0369] Next, the insulating layer 110cg, the insulating layer 110bg, and a portion of the insulating layer 110ag are removed to form the insulating layer 110 having the opening 241 ( Fig.15D ). The opening 241 is provided in a region overlapping with the opening in the conductive layer 212b-e. The formation of the opening 241 exposes the conductive layer 212a. The formation of the insulating layer 110 is suitable for using a dry etching method.

[0370] The opening 241 can be formed using, for example, the resist mask 190B. Alternatively, the opening 241 can be formed using a resist mask different from the resist mask 190B.

[0371] For example, the resist mask 190B may be removed after forming the opening 241. Alternatively, the resist mask 190B may be removed after forming the opening 243 and before forming the insulating layer 110c, before forming the insulating layer 110b, or before forming the insulating layer 110a.

[0372] When forming the insulating layer 110, it is preferable to process the insulating layer 110 so that the side surface of the opening 241 has a tapered shape. In addition, it is preferable to process the insulating layer 110 so that the angle between the side surface of the opening 241 and the formed surface is small. When forming the opening 241 using a resist mask, the insulating layer 110 can be processed under conditions that the resist mask is easy to retreat (shrink), so that the angle between the side surface of the insulating layer 110 and the formed surface can be made small.

[0373] In forming the insulating layer 110, when the resist mask is made to recede, etching can be performed in such a manner that the opening provided in the conductive layer 212b-e also recedes. Here, when the conductive layer 212b-e does not recede or the amount of recede is small, for example, Figure 8B As shown in FIG. 24, the end of the conductive layer 212b in the opening 243 may be located outside the end of the insulating layer 110 in the opening 241. On the other hand, when the amount of retreat of the conductive layer 212b-e is large, for example, Fig. 8A As shown, a structure may be formed in which the end of the conductive layer 212 b in the opening 243 is located inside the end of the insulating layer 110 in the opening 241 .

[0374] Note that the method for manufacturing the conductive layer 212b is not limited to the method in which the end of the opening in the conductive layer 212b-e is made to recede when the insulating layer 110 is formed. For example, the conductive layer 212b having the opening 243 may be provided in advance before the insulating layer 110 is formed. Alternatively, the opening in the conductive layer 212b-e may be made to recede after the insulating layer 110 is formed.

[0375] For example, you can also replace FIG. 15C to FIG. 15D The process is as follows FIG. 16A to FIG. 16D The conductive layer 212b and the insulating layer 110 are formed by a process. FIG. 15C to FIG. 15D In the process of forming the insulating layer 110, an example of forming an opening of the conductive layer 212b by retreating the resist mask 190B is shown. FIG. 16A to FIG. 16D The step of FIG. 1 shows an example in which an opening having a desired size is formed in the conductive layer 212 b in advance and then the insulating layer 110 is formed.

[0376] First, a resist mask 190C is formed on the conductive layer 112b, the conductive layer 212b-e, and the insulating layer 110cg. Fig.16A ).

[0377] Next, a portion of the conductive layer 212b-e is removed using the resist mask 190C, thereby forming the conductive layer 212b ( Fig. 16B ).

[0378] Next, a resist mask 190D is formed on the conductive layer 112b, the conductive layer 212b, and the insulating layer 110cg. Fig. 16C ). Here, the end of the opening of the resist mask 190D is set inside the end of the opening 243 of the conductive layer 212b.

[0379] Next, the insulating layer 110cg, the insulating layer 110bg, and a portion of the insulating layer 110ag are removed using the resist mask 190D, thereby forming the insulating layer 110 ( Fig.16D ). In the formation of the insulating layer 110, it is preferable to perform processing in a manner that the resist mask 190D is retreated. In addition, since the end of the opening of the resist mask 190D is set on the inner side of the end of the opening 243 of the conductive layer 212b, as long as the retreat amount of the resist mask 190D is within the range that does not expose the top surface and the side surface of the conductive layer 212b, the top surface and the side surface of the conductive layer 212b can be kept covered by the resist mask 190D.

[0380] In addition, when the insulating layer 110 is formed, the side surface of the conductive layer 212b may be exposed in the process of retreating the resist mask 190D. In this case, the end of the opening 243 of the conductive layer 212b may retreat to make the opening larger. In other words, Fig.16D The size of the opening of the conductive layer 212b may be larger than Fig. 16B The size of the opening of the conductive layer 212b is large.

[0381] When the etching conditions for forming the insulating layer 110 are such that the conductive layer 212b is not easily retracted, by using FIG. 16A to FIG. 16D The manufacturing method shown can well manufacture a display device which is one embodiment of the present invention.

[0382] in addition, Fig.16D As an example, the end of the bottom surface of the conductive layer 212b in the opening 243 is located inside the end of the top surface of the insulating layer 110 in the opening 241. However, the pattern of the resist mask 190C, the pattern of the resist mask 190D, the etching conditions of the conductive layer 212b_e, and the etching conditions of the insulating layer 110cg, the insulating layer 110bg, and the insulating layer 110ag may be adjusted to form a structure in which the end of the bottom surface of the conductive layer 212b in the opening 243 is located outside the end of the top surface of the insulating layer 110 in the opening 241, or the end of the bottom surface of the conductive layer 212b in the opening 243 is roughly consistent with the end of the top surface of the insulating layer 110 in the opening 241.

[0383] As mentioned above, through FIG. 15C to FIG. 15D or FIG. 16A to FIG. 16DThe illustrated method may form a conductive layer 212 b having an opening 243 and an insulating layer 110 having an opening 241 .

[0384] Next, a metal oxide film 108f ( 108f ) serving as the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the openings 141 , 143 , 241 , and 243 . Fig.17A The metal oxide film 108f is provided in contact with the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the conductive layer 212b, the top surface and side surfaces of the insulating layer 110, the top surface of the conductive layer 112a, and the top surface of the conductive layer 212a.

[0385] Next, a portion of the metal oxide film 108f is removed using a resist mask or the like, thereby forming the semiconductor layer 108 and the semiconductor layer 208. The semiconductor layer 108 and the semiconductor layer 208 are preferably formed by using a wet etching method.

[0386] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method.

[0387] The metal oxide film 108f is preferably a dense film with as few defects as possible. In addition, the metal oxide film 108f is preferably a high-purity film in which impurities containing hydrogen elements are reduced as much as possible. In particular, a crystalline metal oxide film is preferably used as the metal oxide film 108f.

[0388] When the metal oxide film 108f is formed, an oxygen gas is preferably used. When the metal oxide film 108f is formed using an oxygen gas, oxygen can be well supplied to the insulating layer 110. For example, when an oxide is used for the insulating layer 110b, oxygen can be well supplied to the insulating layer 110b.

[0389] By supplying oxygen to the insulating layer 110 b, oxygen can be supplied to the semiconductor layer 108 and the semiconductor layer 208 in a subsequent step, thereby reducing oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208. O H.

[0390] When forming the metal oxide film 108f, oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) may also be mixed. Note that the higher the proportion of oxygen gas to the overall deposition gas (oxygen flow ratio) when forming the metal oxide film, the higher the crystallinity of the metal oxide film can be, and a transistor with high reliability can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, and thus a transistor with a large on-state current can be realized. For example, a stacked structure of two or more metal oxide layers with different crystallinity can be formed by changing the oxygen flow ratio.

[0391] When the substrate temperature is high when forming the metal oxide film, a metal oxide film with higher crystallinity and higher density can be formed. On the other hand, as the substrate temperature becomes lower, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0392] The substrate temperature when forming the metal oxide film 108f is preferably room temperature or higher and 250° C. or lower, more preferably room temperature or higher and 200° C. or lower, and further preferably room temperature or higher and 140° C. or lower. For example, the substrate temperature is preferably room temperature or higher and 140° C. or lower, thereby improving productivity. In addition, by setting the substrate temperature to room temperature or forming the metal oxide film without heating the substrate, crystallinity can be reduced.

[0393] When the metal oxide film 108f is formed by the ALD method, it is preferable to use a deposition method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it has extremely high step coverage. In addition, the PEALD method is preferable because it not only has extremely high step coverage but also allows low-temperature deposition.

[0394] The metal oxide film can be formed by, for example, an ALD method using a precursor containing constituent metal elements and an oxidant.

[0395] For example, when forming In-Ga-Zn oxide, three precursors including a precursor containing indium, a precursor containing gallium, and a precursor containing zinc may be used. Alternatively, two precursors including a precursor containing indium and a precursor containing gallium and zinc may be used.

[0396] Examples of the precursor containing indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedione)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0397] Examples of the precursor containing gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedione)gallium, dimethylgallium chloride, diethylgallium chloride, and gallium(III) chloride.

[0398] Examples of the precursor containing zinc include dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptanedione) zinc, and zinc chloride.

[0399] Examples of the oxidizing agent include ozone, oxygen, and water.

[0400] As a method for controlling the composition of the obtained film, one or more of the type of source gas, the flow ratio of the source gas, the time of flowing the source gas, and the order of flowing the source gas can be exemplified. By adjusting these, a film with a continuously changing composition can be formed. In addition, films with different compositions can also be deposited continuously.

[0401] Note that in the case where the metal oxide film 108f has a stacked-layer structure, it is preferable that, after depositing the metal oxide film of the lower layer, the metal oxide film of the upper layer is continuously deposited without exposing its surface to the atmosphere.

[0402] Before depositing the metal oxide film 108f, it is preferred to perform at least one of a treatment for removing water, hydrogen, organic matter, etc. adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen to the insulating layer 110. For example, a heat treatment may be performed at a temperature of 70°C or higher and 200°C or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment may be performed in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 110 by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). When a plasma treatment containing nitrous oxide gas is performed, organic matter on the surface of the insulating layer 110 may be appropriately removed and oxygen may be supplied to the insulating layer 110. Preferably, after such a treatment, the metal oxide film 108f is continuously deposited in a manner that does not expose the surface of the insulating layer 110 to the atmosphere.

[0403] It is preferable to perform heat treatment after the metal oxide film 108f is deposited or after the metal oxide film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208. By heat treatment, hydrogen or water contained in the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108 can be removed. In addition, by heat treatment, the film quality of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 is sometimes improved (for example, defects are reduced or crystallinity is improved).

[0404] By heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layers 108 and 208. In this case, it is more preferable to perform heat treatment after the metal oxide film 108f is formed and before it is processed into the semiconductor layers 108 and 208. For the heat treatment, refer to the above description.

[0405] Note that this heat treatment may not be performed. In addition, it is also possible not to perform heat treatment in this process and use the heat treatment performed in a later process as the heat treatment in this process. Sometimes, a process at a high temperature in a later process (for example, a deposition process) may be used as the heat treatment in this process.

[0406] Next, the insulating layer 106 is formed so as to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110. Fig. 17B ) When forming the insulating layer 106, for example, a PECVD method or an ALD method is preferably used.

[0407] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 is preferably used as a barrier film for suppressing diffusion of oxygen. By providing the insulating layer 106 with a function of suppressing diffusion of oxygen, it is possible to suppress diffusion of oxygen from the upper side of the insulating layer 106 into the conductive layer 104 and the conductive layer 204 to cause oxidation of the conductive layer 104 and the conductive layer 204. As a result, a transistor having good electrical characteristics and high reliability can be achieved.

[0408] Note that in this specification, etc., a barrier film refers to a film having barrier properties. For example, an insulating layer having barrier properties may be referred to as a barrier insulating layer. In this specification, etc., barrier properties refer to one or both of a function of suppressing diffusion of a corresponding substance (also referred to as low permeability) and a function of capturing or fixing (also referred to as gettering) a corresponding substance.

[0409] By increasing the temperature at which the insulating layer 106 serving as a gate insulating layer is formed, an insulating layer with fewer defects can be formed. However, when the temperature at which the insulating layer 106 is formed is high, oxygen is released from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208 may O H increases. The substrate temperature when forming the insulating layer 106 is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., more preferably 250° C. to 450° C., more preferably 300° C. to 450° C., more preferably 300° C. to 400° C. When the substrate temperature when forming the insulating layer 106 is within the above range, it is possible to reduce defects in the insulating layer 106 while suppressing the separation of oxygen from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor having good electrical characteristics and high reliability can be realized.

[0410] Before forming the insulating layer 106, the sides and surfaces of the semiconductor layer 108 and the semiconductor layer 208 may be subjected to plasma treatment. By this plasma treatment, impurities such as water adsorbed on the sides and surfaces of the semiconductor layer 108 and the semiconductor layer 208 can be reduced. Therefore, impurities in the interface between the semiconductor layer 108 and the insulating layer 106 and the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, so that a transistor with high reliability can be realized. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. The plasma treatment and the deposition of the insulating layer 106 are preferably performed continuously without being exposed to the atmosphere.

[0411] Next, a conductive film to be the conductive layer 104 and the conductive layer 204 is formed over the insulating layer 106 and the conductive film is processed, whereby the conductive layer 104 and the conductive layer 204 are formed.

[0412] Next, an insulating layer 195 is formed to cover the conductive layer 104, the conductive layer 204, and the insulating layer 106 ( Fig. 17C ) The insulating layer 195 can be formed by a PECVD method.

[0413] The semiconductor device 10 can be manufactured through the above steps.

[0414] This embodiment mode can be combined with other embodiment modes as appropriate.

[0415] (Implementation 3)

[0416] In this embodiment, a display device using a semiconductor device which is one embodiment of the present invention is described with reference to FIGS. 18 to 28 .

[0417] The display device of this embodiment mode may be a high-resolution display device or a large display device. Therefore, for example, the display device of this embodiment mode may be used as a display portion of the following devices: electronic devices with a large screen such as television devices, desktop or notebook personal computers, displays for computers, etc., digital signage, large-scale game machines such as pinball machines, etc.; digital cameras; digital video cameras; digital photo frames; mobile phones; portable game machines; portable information terminals; and sound reproduction devices.

[0418] The display device of this embodiment can be a high-definition display device. Therefore, for example, the display device of this embodiment can be used as a display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, and a display unit of wearable devices that can be worn on the head such as VR devices such as head-mounted displays (HMDs) and glasses-type AR devices.

[0419] A semiconductor device of one embodiment of the present invention can be used in a display device or a module including the display device. As a module including the display device, there can be cited a module in which the display device is equipped with a connector such as a flexible printed circuit (FPC) or TCP (Tape Carrier Package), a module in which an integrated circuit (IC) is installed by a COG (Chip On Glass) method or a COF (Chip On Film) method, etc.

[0420] Fig.18A It is a perspective view of the display device 50A.

[0421] The display device 50A has a structure in which a substrate 152 and a substrate 151 are bonded together. Fig.18A In FIG. 1 , the substrate 152 is indicated by a dotted line.

[0422] The display device 50A includes a display portion 162 , a connection portion 140 , a peripheral circuit portion 164 , wiring 165 , and the like. Fig.18A An example is shown in which the FPC 172 is mounted on the display device 50A.

[0423] The connection portion 140 is disposed outside the display portion 162. The connection portion 140 may be disposed along one side or multiple sides of the display portion 162. There may also be one or more connection portions 140. Fig.18A The example in which the connection part 140 is provided so as to surround the four sides of the display part is shown. In the connection part 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0424] The peripheral circuit unit 164 includes, for example, a scanning line driver circuit (also referred to as a gate driver). Alternatively, the peripheral circuit unit 164 may include both a scanning line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0425] The wiring 165 has a function of supplying signals and power to the display portion 162 and the peripheral circuit portion 164 . The signals and power are input to the wiring 165 from the outside through the FPC 172 .

[0426] In addition, if Fig.19 As shown, in addition to the FPC 172, an IC 173 may be mounted on the display device 50A.

[0427] exist Fig.19 In the structure shown in the figure, the signal and power supplied to the display unit 162 and the peripheral circuit unit 164 are input to the wiring 165 via the IC 173. Fig.18A and Fig.18BThe structure shown is regarded as a display module including a display device, an FPC, etc.

[0428] Fig.18A An example is shown in which IC 173 is provided on substrate 151 by COG method or COF method. For example, an IC including one or both of a scanning line driver circuit and a signal line driver circuit can be used as IC 173. Note that the IC can also be mounted on FPC by COF method or the like.

[0429] The semiconductor device according to one embodiment of the present invention can be used for, for example, one or both of the display portion 162 and the peripheral circuit portion 164 of the display device 50A.

[0430] The display unit 162 is an image display region in the display device 50A, and includes a plurality of pixels 210 arranged periodically. Fig.18A An enlarged view of one pixel 210 is shown in FIG.

[0431] There is no particular limitation on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement.

[0432] Fig.18A The pixel 210 shown includes a sub-pixel 230R that represents red light, a sub-pixel 230G that represents green light, and a sub-pixel 230B that represents blue light. The pixel 230R, the pixel 230G, and the pixel 230B are all used as sub-pixels.

[0433] The pixel 230R, the pixel 230G, and the pixel 230B each include a display element and a circuit for controlling driving of the display element.

[0434] Various elements can be used as display elements, for example, liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electro Mechanical Systems) elements of shutter mode or light interference mode, display elements using microcapsule mode, electrophoresis mode, electrowetting mode or electronic powder fluid (registered trademark) mode, etc. can also be used. In addition, QLED (Quantum-dot LED) using light source and color conversion technology using quantum dot materials can also be used.

[0435] Examples of display devices using a liquid crystal element include a transmissive liquid crystal display device, a reflective liquid crystal display device, and a semi-transmissive liquid crystal display device.

[0436] Examples of the light emitting element include self-luminous light emitting elements such as LED (Light Emitting Diode), OLED (Organic LED), and semiconductor lasers. Examples of the LED include miniature LEDs and micro LEDs.

[0437] Examples of the light-emitting substance contained in the light-emitting element include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0438] The light emitting element may emit light of infrared, red, green, blue, cyan, magenta, yellow or white, etc. In addition, when the light emitting element has a microcavity structure, the color purity can be further improved.

[0439] Of a pair of electrodes included in the light emitting element, one electrode is used as an anode and the other electrode is used as a cathode.

[0440] In this embodiment, description is mainly given by taking the case where a light-emitting element is used as a display element as an example.

[0441] The circuit in the display device of one embodiment of the present invention may use various logic circuits. Examples of the logic circuit include: combinational circuits such as an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit; sequential circuits such as a trigger circuit, a latch circuit, a counting circuit, a register circuit, and a shift register circuit; and buffer circuits.

[0442] Fig.18B 1 is a block diagram for explaining a display device 50A. The display device 50A includes a display unit 162 and a peripheral circuit unit 164. The display unit 162 includes a plurality of pixels 230 (pixel 230[1,1] to pixel 230[m,n], where m and n are independently integers greater than 2) arranged periodically. Fig.18B , the pixel 230 in the 1st row and the nth column is recorded as pixel 230[1,n], the pixel 230 in the mth row and the 1st column is recorded as pixel 230[m,1], and the pixel 230 in the mth row and the nth column is recorded as pixel 230[m,n]. The peripheral circuit unit 164 includes a first driving circuit unit 231 and a second driving circuit unit 232.

[0443] The circuit included in the first driving circuit portion 231 is used as, for example, a scanning line driving circuit. The circuit included in the second driving circuit portion 232 is used as, for example, a signal line driving circuit. Note that a certain circuit may be provided at a position opposite to the first driving circuit portion 231 across the display portion 162. A certain circuit may be provided at a position opposite to the second driving circuit portion 232 across the display portion 162.

[0444] As the peripheral circuit portion 164, various circuits such as a shift register circuit, a level converter circuit, an inverter circuit, a latch circuit, an analog switch circuit, and a demultiplexing circuit can be used. Transistors and capacitors can be used in the peripheral circuit portion 164. A transistor of one embodiment of the present invention can be used in the peripheral circuit portion 164 and the pixel 230.

[0445] The scanning line driving circuit may be configured to include at least a shift register, for example. Alternatively, the signal line driving circuit may be configured to include a shift register, a digital-to-analog conversion circuit, a latch circuit, and the like.

[0446] The display device 50A includes a wiring 236 and a wiring 238 arranged substantially in parallel. The potential of the wiring 236 is controlled by a circuit included in the first drive circuit unit 231, and the potential of the wiring 238 is controlled by a circuit included in the second drive circuit unit 232. Fig.18B 2 shows an example in which the wiring 236 and the wiring 238 are connected to the pixel 230. However, the wiring 236 and the wiring 238 are just an example, and the wiring connected to the pixel 230 is not limited to the wiring 236 and the wiring 238.

[0447] <Configuration Example of Peripheral Driver Circuit>

[0448] The following describes a configuration example that can be used for a peripheral driver circuit.

[0449] Fig. 20A : is a circuit diagram showing a configuration example of the latch circuit LAT. Fig. 20A The latch circuit LAT shown includes a transistor Tr31, a transistor Tr33, a transistor Tr35, a transistor Tr36, a capacitor C31, and an inverter circuit INV. Fig. 20A In FIG. 1 , a node electrically connecting one of the source and the drain of the transistor Tr33, the gate of the transistor Tr35, and one electrode of the capacitor C31 is referred to as a node N.

[0450] exist Fig. 20AIn the latch circuit LAT shown, when a high potential signal is input to the terminal SMP, the transistor Tr33 becomes an on state. Therefore, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and the data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After writing data to the latch circuit LAT, by making the potential of the terminal SMP a low potential, the transistor Tr33 becomes a closed state. Therefore, the potential of the node N is maintained, and the data written to the latch circuit LAT is maintained. Specifically, for example, when the potential of the node N is a low potential, the latch circuit LAT can maintain data "0", and when the potential of the node N is a high potential, the latch circuit LAT can maintain data "1".

[0451] The transistor Tr33 preferably uses a transistor with low off-state current. The transistor Tr33 can appropriately use an OS transistor. Therefore, the latch circuit LAT can hold data for a long period of time. Therefore, the frequency of rewriting data to the latch circuit LAT can be reduced.

[0452] In this specification, etc., "writing data to the latch circuit LAT so that the signal input from the terminal SP2 is output to the terminal LLIN" is sometimes referred to as "writing data to the latch circuit LAT". That is, for example, "writing data "1" to the latch circuit LAT" is sometimes referred to as "writing data to the latch circuit LAT".

[0453] In the latch circuit LAT, a semiconductor device according to one embodiment of the present invention can be appropriately used. For example, transistors Tr31, Tr33, Tr35, and Tr36 can be used. Figure 1B The transistor 100 or the transistor 200 shown in the figure.

[0454] Fig. 20B 1 and 2 show a configuration example of an inverter circuit INV. The inverter circuit INV includes a transistor Tr41, a transistor Tr43, a transistor Tr45, a transistor Tr47, and a capacitor C41.

[0455] When the latch circuit LAT has Fig. 20A The structure shown in FIG. 1 and the inverter circuit INV have Fig. 20B In the structure shown, transistors of the same polarity, such as n-channel transistors, are used as transistors in the latch circuit LAT. Therefore, for example, in addition to the transistor Tr33, the transistor Tr31, the transistor Tr35, the transistor Tr36, the transistor Tr41, the transistor Tr43, the transistor Tr45, and the transistor Tr47 can also be OS transistors. Therefore, all transistors in the latch circuit LAT can be manufactured by the same process.

[0456] In the inverter circuit INV, the semiconductor device according to one embodiment of the present invention can be appropriately used. For example, one or more of the transistor Tr41, the transistor Tr43, the transistor Tr45, and the transistor Tr47 can be used. Figure 1B The transistor 100 or the transistor 200 shown in the figure.

[0457] Fig.21 2 shows a structural example of a sequential circuit 20. The sequential circuit 20 includes a circuit 11 and a circuit 12. The circuit 11 and the circuit 12 are electrically connected via wiring 15a and wiring 15b. Fig.21 The structure shown can sometimes constitute a circuit such as a shift register.

[0458] The circuit 12 has a function of outputting a first signal and a second signal to the wiring 15a and the wiring 15b, respectively, according to the potential of the signal LIN and the potential of the signal RIN. Here, the second signal is a signal that inverts the first signal. That is, when the first signal and the second signal each have two potentials of a high potential and a low potential, when a high potential is output from the circuit 12 to the wiring 15a, a low potential is output to the wiring 15b, and when a low potential is output from the circuit 12 to the wiring 15a, a high potential is output to the wiring 15b.

[0459] The circuit 11 includes a transistor 21, a transistor 22, and a capacitor C1. The transistor 21 and the transistor 22 are each an n-channel transistor. As a semiconductor having a channel, the transistor 21 and the transistor 22 can appropriately use a metal oxide (hereinafter also referred to as an oxide semiconductor) having semiconductor characteristics. In addition, it is not limited to oxide semiconductors, and semiconductors such as silicon (single crystal silicon, polycrystalline silicon, or amorphous silicon) and germanium can be used, and compound semiconductors can also be used.

[0460] The transistor of one embodiment of the present invention is applicable to the transistor 21 and the transistor 22. For example, Figure 1B The transistor 100 or transistor 200 shown in FIG. 1 is applicable to the transistor 21. In addition, the transistor 21 preferably has a back gate. Therefore, for example, Figure 4B The transistor 100 or the transistor 200 shown in the above description is applicable to the transistor 21 .

[0461] The transistor 21 includes a pair of gates (hereinafter referred to as the first gate and the second gate). In the transistor 21, the first gate is electrically connected to the wiring 15b, the second gate is electrically connected to one of the source and drain of the transistor 21 and the wiring supplied with the potential VSS (also referred to as the first potential), and the other of the source and drain is electrically connected to one of the source and drain of the transistor 22. In the transistor 22, the gate is electrically connected to the wiring 15a, and the other of the source and drain is electrically connected to the wiring supplied with the signal CLK. The capacitor C1 includes a pair of electrodes, one of which is electrically connected to one of the source and drain of the transistor 22 and the other of the source and drain of the transistor 21, and the other of which is electrically connected to the gate of the transistor 22 and the wiring 15a. In addition, the other of the source and drain of the transistor 21, one of the source and drain of the transistor 22, and one of the electrodes of the capacitor C1 are electrically connected to the output terminal OUT. Note that the output terminal OUT is a portion supplied with the output potential from the circuit 11, and may also be a portion of the wiring or a portion of the electrode.

[0462] The other of the source and drain of the transistor 22 is alternately supplied with the second potential and the third potential as the signal CLK. The second potential can be a potential higher than the potential VSS (e.g., potential VDD). The third potential can be a potential lower than the second potential. As the third potential, the potential VSS can be appropriately used. Note that a structure in which the potential VDD is supplied to the other of the source and drain of the transistor 22 instead of the signal CLK can also be adopted.

[0463] When the wiring 15a is supplied with a high potential and the wiring 15b is supplied with a low potential, the transistor 22 is turned on and the transistor 21 is turned off. At this time, the output terminal OUT and the wiring supplied with the signal CLK are turned on.

[0464] In the circuit 11, the output terminal OUT and the gate of the transistor 22 are electrically connected through the capacitor C1, so as the potential of the output terminal OUT rises due to the bootstrap effect, the gate potential of the transistor 22 rises. Here, in the case where the capacitor C1 is not included, when the second potential of the signal CLK and the high potential supplied to the wiring 15a use the same potential (potential VDD), the potential of the output terminal OUT will be a potential obtained by subtracting the threshold voltage of the transistor 22 from the potential VDD. However, by including the capacitor C1, the potential of the gate of the transistor 22 rises to a potential close to twice the potential VDD (specifically, a potential close to twice the difference between the potential VDD and the potential VSS or a potential close to twice the difference between the potential VDD and the third potential), so the potential VDD can be output to the output terminal OUT without being affected by the threshold voltage of the transistor 22. As a result, a timing circuit 20 with high output performance can be realized without increasing the types of power supply potentials.

[0465] On the other hand, when low potential and high potential are supplied to wiring 15a and wiring 15b, respectively, transistor 22 becomes non-conductive and transistor 21 becomes conductive. At this time, output terminal OUT and the wiring supplied with potential VSS become conductive, and potential VSS is output to output terminal OUT.

[0466] Here, the timing circuit 20 can be used as a driving circuit of a display device. In particular, it can be appropriately used as a scan line driving circuit. At this time, when the output terminal OUT is connected to the scan lines of a plurality of pixels connected to the display device, the duty cycle of the output signal output from the timing circuit 20 to the output terminal OUT is significantly smaller than the duty cycle of the signal CLK, etc. At this time, the period during which the transistor 21 is in the on state is significantly longer than the period during which it is in the non-conducting state. That is, the period during which the first gate of the transistor 21 is supplied with a high potential is significantly longer than the period during which it is supplied with a low potential. By using a transistor of one embodiment of the present invention as the transistor 21, the degradation of the transistor characteristics in the state in which the first gate is supplied with a high potential can be suppressed.

[0467] In addition, by using a transistor of one embodiment of the present invention as transistor 21, it is possible to appropriately prevent the threshold voltage from becoming a negative value, thereby making it easy for transistor 21 to have a normally closed characteristic. When transistor 21 has a normally open characteristic, when the voltage of the other gate and source of transistor 21 is 0V, a leakage current between the source and the drain is generated and the potential of the output terminal OUT cannot be maintained. Therefore, in order to turn transistor 21 off, it is necessary to supply a potential lower than the potential VSS to the other gate of transistor 21, and multiple power supplies are required. By using a transistor of one embodiment of the present invention as transistor 21, a timing circuit 20 with high output performance can be realized without increasing the types of power supply potentials.

[0468] In addition, by using the transistor of one embodiment of the present invention as the transistor 21, the saturation characteristic of the transistor 21 can be improved. This makes it easier to design the circuit 11, and the circuit 11 can be operated stably.

[0469] By using transistor 100, the occupied area can be reduced, so that a display device with a narrow frame can be realized. In addition, as a transistor required to have a large on-state current, transistor 100 can be appropriately used. Furthermore, as a transistor required to have a high saturation characteristic, transistor 200 can be appropriately used. Thus, a high-performance display device can be realized.

[0470] <Configuration Example of Pixel Circuit>

[0471] Fig.22A The figure shows an example of the structure of the pixel 230. The pixel 230 includes a pixel circuit 51 and a light emitting device 61.

[0472] Fig.22A The pixel circuit 51 shown is a 2Tr1C type pixel circuit including a transistor 52A, a transistor 52B, and a capacitor 53 .

[0473] One of the source and drain of the transistor 52A is electrically connected to the gate of the transistor 52B and one terminal of the capacitor 53. The other of the source and drain electrodes of the transistor 52A is electrically connected to the wiring SL. The gate of the transistor 52A is electrically connected to the wiring GL. One of the source and drain electrodes of the transistor 52B and the other terminal of the capacitor 53 are electrically connected to the anode of the light emitting device 61. The other of the source and drain electrodes of the transistor 52B is electrically connected to the wiring ANO. The cathode of the light emitting device 61 is electrically connected to the wiring VCOM.

[0474] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring for supplying a potential for supplying a current to the light emitting device 61. The transistor 52A has a function of controlling the conduction state or non-conduction state between the wiring SL and the gate of the transistor 52B according to the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0475] The transistor 52B has a function of controlling the amount of current flowing through the light emitting device 61. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of light emitted by the light emitting device 61 is controlled according to an image signal supplied to the gate of the transistor 52B.

[0476] A part or all of the transistors included in the pixel circuit 51 may be provided with a back gate electrode. Fig.22A The pixel circuit 51 shown in the figure shows a structure in which the transistor 52B includes a back gate electrode and the back gate electrode is electrically connected to one of the source and the drain of the transistor 52B. Alternatively, the back gate electrode of the transistor 52B may be electrically connected to the gate electrode of the transistor 52B.

[0477] The above semiconductor device can be applied to the pixel circuit 51. For example, as the transistor 52A, Figure 1B The transistor 100 shown in the figure above may be replaced by the transistor 200 as the transistor 52B.

[0478] Fig. 22B Shown with Fig.22A The pixel 230 shown in FIG.

[0479] Fig. 22B The pixel circuit 51A shown is Fig.22AThe pixel circuit 51 shown mainly differs in that a transistor 52C is included. The pixel circuit 51A is a 3Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53.

[0480] One of the source electrode and the drain electrode of the transistor 52C is electrically connected to the other of the source electrode and the drain electrode of the transistor 52B. The other of the source electrode and the drain electrode of the transistor 52C is electrically connected to the wiring V0. For example, the wiring V0 is supplied with a reference potential.

[0481] The transistor 52C has a function of controlling the conduction state or non-conduction state between one of the source electrode and the drain electrode of the transistor 52B and the wiring V0 according to the potential of the wiring GL. The reference potential of the wiring V0 supplied by the transistor 52C can suppress the variation of the gate-source potential of the transistor 52B.

[0482] In addition, the wiring V0 can be used to obtain a current value that can be used for setting pixel parameters. Specifically, the wiring V0 can be used as a monitoring line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the outside.

[0483] Preferably, the saturation characteristic of the transistor 52B used as a driving transistor for controlling the current flowing through the light emitting device 61 is higher than that of the transistor 52A used as a selection transistor for controlling the selection state of the pixel 230. By using the transistor 200 having a long channel length as the transistor 52B, a highly reliable display device can be provided. In addition, by using the transistor 100 as the transistor 52A and the transistor 52C, the occupied area of ​​the pixel circuit 51A can be reduced, thereby realizing a high-definition display device.

[0484] Note that the transistor 100 may be used as the transistor 52B. By using the transistor 100 having a short channel length as the transistor 52B, a display device with high brightness can be realized. In addition, the area occupied by the pixel circuit 51A can be reduced, thereby realizing a high-definition display device.

[0485] The above semiconductor device can be applied to the pixel circuit 51A. For example, the transistor 52A and the transistor 52C can be used. Figure 1B The transistor 100 shown in the figure can be used as the transistor 52B. Figure 4B The transistor 200 is shown in FIG.

[0486] Note that there is no particular limitation on the pixel circuit that can be used in one embodiment of the present invention.

[0487] Fig.23A A configuration example of a display device according to one embodiment of the present invention is shown. Fig.23A It is a cross-sectional view of the peripheral circuit portion 164 and the display portion 162 .

[0488] In the display unit 162, a transistor 100 and a transistor 200 are provided on a substrate 102. Both the transistor 100 and the transistor 200 in the display unit can be used as transistors in a pixel circuit. In addition, the display unit may also adopt a structure including only the transistor 100 or a structure including only the transistor 200. By including the transistor 200 with high saturation characteristics in the display unit, for example, a display device with high display quality and high reliability of multiple grayscales can be realized.

[0489] Fig.23A FIG. 1 shows one transistor 100 in the peripheral circuit unit 164. In addition, the peripheral circuit unit 164 preferably includes more than one transistor 100. In addition, although Fig.23A Although not shown in the figures, the peripheral circuit unit 164 may also include a transistor 200 .

[0490] in addition, Fig.23A One transistor 100 and one transistor 200 are shown in the pixel circuit of the display portion 162, wherein the transistor 100 is used for the transistor 52A of the pixel circuit 51, and the transistor 200 is used for the transistor 52B of the pixel circuit 51. Note that Fig.23A 100 and the transistor 200 are omitted in the figure. For example, a first opening reaching the conductive layer 112 b and a second opening reaching the conductive layer 204 are provided in the insulating layer 195. By providing a first wiring on the insulating layer 195 so as to cover the first opening and the second opening, the conductive layer 112 b and the conductive layer 204 can be electrically connected through the first wiring.

[0491] Fig.23A The capacitors in the pixel circuit are omitted.

[0492] An insulating layer 195 is provided to cover the transistor 100 and the transistor 200 , and an insulating layer 235 is provided to cover the insulating layer 195 . A light emitting device 61 may be provided on the insulating layer 235 . Fig.23A The pixel electrode 111 used as one electrode of the light-emitting device 61 is shown. The pixel electrode 111 is electrically connected to the conductive layer 212a through the opening 135 provided in the insulating layer 110, the insulating layer 106, the insulating layer 195, and the insulating layer 235. The insulating layer 235 has a function of reducing the unevenness caused by the transistor to make the formed surface of the light-emitting device 61 flatter. In addition, in this specification, etc., the insulating layer 235 is sometimes described as a flattening layer.

[0493] The insulating layer 235 is suitable for using an organic insulating film. As materials that can be used for the organic insulating film, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of these resins can be used. In addition, the insulating layer 235 can also adopt a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 is preferably used as an etching protection layer. Thus, when the pixel electrode 111 is formed, the formation of a concave portion in the insulating layer 235 can be suppressed. Alternatively, a concave portion can be provided in the insulating layer 235 when the pixel electrode 111 is formed.

[0494] The insulating layer 235 may also have a stacked structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 235 may have a stacked structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 235, it can be used as an etching protection layer. Thus, it is possible to prevent a portion of the insulating layer 235 from being etched when the pixel electrode 111 is formed, thereby preventing the flatness of the insulating layer 235 from being reduced.

[0495] In addition, if Fig. 23B As shown, transistor 200 may be used for both transistor 52A and transistor 52B.

[0496] In addition, in the transistor 200 used as the transistor 52B, the conductive layer 212a may be replaced by a Fig.23C As shown, a structure in which the conductive layer 212 b is connected to the pixel electrode 111 is adopted. Fig.23C The pixel electrode 111 shown is electrically connected to the conductive layer 212 b through an opening 136 provided in the insulating layer 106 , the insulating layer 195 , and the insulating layer 235 .

[0497] A display device according to one embodiment of the present invention may also adopt any of the following structures: a top emission type that emits light in a direction opposite to a substrate on which a light-emitting device is formed, a bottom emission type that emits light to one side of a substrate on which a light-emitting device is formed, or a dual emission type that emits light to both sides.

[0498] <Configuration Example 1 of Display Device>

[0499] Fig.24A An example of a cross section of a portion of a region including the FPC 172 , a portion of the peripheral circuit portion 164 , a portion of the display portion 162 , a portion of the connection portion 140 , and a portion of a region including an end portion of the display device 50A is shown.

[0500] Fig.24AThe display device 50A shown includes transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, 130B, etc. between substrates 151 and 152. The light-emitting element 130R is a display element included in the pixel 230R that emits red light, the light-emitting element 130G is a display element included in the pixel 230G that emits green light, and the light-emitting element 130B is a display element included in the pixel 230B that emits blue light.

[0501] The display device 50A adopts an SBS structure. In the SBS structure, the material and structure of each light emitting element can be optimized separately, the degree of freedom in selecting materials and structures is increased, and it becomes easy to improve brightness and reliability.

[0502] The display device 50A adopts a top emission type. In the top emission type, transistors and the like can be arranged so as to overlap with the light emitting region of the light emitting element, so that the aperture ratio of the pixel can be further increased compared with the bottom emission type.

[0503] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over the substrate 151. These transistors can be manufactured using the same material and the same process.

[0504] As any one or more of the transistors 205D, 205R, 205G, and 205B, one or more of the transistors 100 and 200 described above can be used. For example, in the display unit 162, as the transistors 205R, 205G, and 205B used as the driving circuits of the light-emitting elements 130R, 130G, and 130B, the transistor 200 having high saturation characteristics can be appropriately used. Thus, a high-reliability display device can be realized. By using the above-mentioned transistors 100 to 100 in the peripheral circuit unit 164, a display device that operates at a high speed can be realized. Furthermore, the occupied area of ​​the peripheral circuit unit 164 can be reduced, and the frame can be reduced.

[0505] Sometimes, the transistor provided in the peripheral circuit portion 164 needs to have a larger on-state current than the transistor provided in the display portion 162. It is preferable to use a transistor with a short channel length in the peripheral circuit portion 164. For example, the above-mentioned transistor 100 can be appropriately used in the peripheral circuit portion 164. By using the transistor 100 in the peripheral circuit portion 164, the occupied area can be reduced, thereby realizing a display device with a narrow frame. In addition, as a transistor provided in the display portion 162, the above-mentioned transistor 200 can be appropriately used. Fig.24AThe transistor 100 is used as the transistor 205D, and the transistor 200 is used as the transistor 205R, the transistor 205G, and the transistor 205B. The transistor 100 may be used in the display portion 162 , and the transistor 200 may be used in the peripheral circuit portion 164 .

[0506] Note that the transistor included in the display device in this embodiment is not limited to the transistor included in the semiconductor device of one embodiment of the present invention. For example, the transistor included in the semiconductor device of one embodiment of the present invention and the transistor of other structures may be combined. The display device of this embodiment may include, for example, any one or more of a planar transistor, a staggered transistor, and an inversely staggered transistor. The transistor included in the display device of this embodiment may have any one of a top gate type and a bottom gate type. Alternatively, a gate may be provided above and below the semiconductor layer forming the channel.

[0507] OS transistors can be used as the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B as appropriate.

[0508] The display device of this embodiment may also include a transistor (Si transistor) using silicon for the channel formation region. Examples of silicon include single crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor including LTPS in the semiconductor layer (hereinafter also referred to as LTPS transistor) may be used. The LTPS transistor has high field effect mobility and good frequency characteristics.

[0509] When the luminous brightness of the light-emitting element included in the pixel circuit is increased, the amount of current flowing through the light-emitting element needs to be increased. To this end, it is necessary to increase the source-drain voltage of the driving transistor included in the pixel circuit. Because the source-drain withstand voltage of the OS transistor is higher than that of the Si transistor, a high voltage can be applied to the source-drain of the OS transistor. Thus, by using the OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting element can be increased to improve the luminous brightness of the light-emitting element.

[0510] When the transistor operates in the saturation region, the OS transistor can make the change in the source-drain current for the change in the gate-source voltage smaller than the Si transistor. Therefore, by using the OS transistor as the driving transistor included in the pixel circuit, the current flowing through the source-drain can be determined in detail according to the change in the gate-source voltage, so the amount of current flowing through the light-emitting element can be controlled. As a result, the number of grayscales of the pixel circuit can be increased.

[0511] Regarding the saturation characteristics of the current flowing when the transistor operates in the saturation region, compared with the Si transistor, the OS transistor can make a stable current (saturation current) flow even if the source-drain voltage is gradually increased. Therefore, by using the OS transistor as a driving transistor, even if, for example, the current-voltage characteristics of the EL element are uneven, a stable current can flow through the light-emitting element. That is, when the OS transistor operates in the saturation region, even if the source-drain voltage is changed, the source-drain current remains almost unchanged, so the light-emitting brightness of the light-emitting element can be stabilized.

[0512] The transistors included in the peripheral circuit unit 164 and the transistors included in the display unit 162 may have the same structure or different structures. The plurality of transistors included in the peripheral circuit unit 164 may have the same structure or two or more different structures. Similarly, the plurality of transistors included in the display unit 162 may have the same structure or two or more different structures.

[0513] All transistors included in the display portion 162 may be OS transistors, all transistors included in the display portion 162 may be Si transistors, some transistors included in the display portion 162 may be OS transistors and the remaining transistors may be Si transistors.

[0514] For example, by using both LTPS transistors and OS transistors in the display unit 162, a display device with low power consumption and high driving capability can be realized. In addition, a structure combining LTPS transistors and OS transistors is sometimes called LTPO. The same is true for the peripheral circuit unit 164. All transistors can be OS transistors, all transistors included in the peripheral circuit unit 164 can be Si transistors, and some transistors included in the peripheral circuit unit 164 can also be OS transistors and the remaining transistors can also be Si transistors.

[0515] An insulating layer 195 is provided to cover the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B, and an insulating layer 235 is provided over the insulating layer 195 .

[0516] The light emitting element 130R, the light emitting element 130G, and the light emitting element 130B are provided on the insulating layer 235 .

[0517] The light emitting element 130R includes a pixel electrode 111R on the insulating layer 235 , an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. Fig.24A The light emitting element 130R shown emits red light (R). The EL layer 113R includes a light emitting layer that emits red light.

[0518] The light emitting element 130G includes a pixel electrode 111G on the insulating layer 235 , an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. Fig.24A The light emitting element 130G shown emits green light (G). The EL layer 113G includes a light emitting layer that emits green light.

[0519] The light-emitting element 130B includes a pixel electrode 111B on the insulating layer 235 , an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. Fig.24A The light emitting element 130B shown emits blue light (B). The EL layer 113B includes a light emitting layer that emits blue light.

[0520] Note that Fig.24A EL layers 113R, 113G, and 113B are shown as having the same thickness, but the present invention is not limited thereto. The thickness of each film of EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the film thickness corresponding to the optical path length of light emitted by EL layers 113R, 113G, and 113B. Thus, a microcavity structure can be realized to improve the color purity of light emitted from each light-emitting element.

[0521] Pixel electrode 111R is electrically connected to conductive layer 112b of transistor 205R via openings provided in insulating layer 195 and insulating layer 235. Similarly, pixel electrode 111G is electrically connected to conductive layer 112b of transistor 205G, and pixel electrode 111B is electrically connected to conductive layer 112b of transistor 205B.

[0522] Each end of the pixel electrodes 111R, 111G, and 111B is covered by an insulating layer 237. The insulating layer 237 is used as a partition wall (also called a bank, a dam, or a spacer). The insulating layer 237 can be set to a single-layer structure or a stacked-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the insulating layer 237 can use a material that can be used for the insulating layer 235. The insulating layer 237 can electrically insulate the pixel electrode from the common electrode. In addition, the insulating layer 237 can electrically insulate the light-emitting elements adjacent to each other.

[0523] The common electrode 115 is a continuous film shared by the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is electrically connected to the conductive layer 123 provided in the connection portion 140. The conductive layer 123 is preferably formed using the same material and the same process as the pixel electrodes 111R, 111G, and 111B.

[0524] In the display device of one embodiment of the present invention, a conductive film that transmits visible light is used as the electrode on the light extraction side of the pixel electrode and the common electrode. In addition, a conductive film that reflects visible light is preferably used as the electrode on the side that does not extract light.

[0525] The electrode on the side that does not extract light may also be a conductive film that transmits visible light. In this case, it is preferable to configure the electrode between the reflective layer and the EL layer. In other words, the light emitted by the EL layer can also be reflected by the reflective layer and extracted from the display device.

[0526] As the material for forming a pair of electrodes of the light-emitting element, metals, alloys, conductive compounds and mixtures thereof can be appropriately used. As the material, specifically, metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium and neodymium and alloys appropriately combined therewith can be cited. In addition, as the material, indium tin oxide (also referred to as In-Sn oxide, ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide) and In-W-Zn oxide can be cited. In addition, as the material, aluminum alloys (aluminum alloys) such as aluminum, nickel and lanthanum alloys (Al-Ni-La), silver and magnesium alloys and silver, palladium and copper alloys (also referred to as Ag-Pd-Cu, APC) and other silver-containing alloys can be cited. In addition, examples of the material include elements belonging to Group 1 or Group 2 of the periodic table that are not listed above (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, alloys of appropriately combined elements, and graphene.

[0527] The light-emitting element preferably adopts a microcavity resonator (microcavity) structure. Therefore, one of a pair of electrodes included in the light-emitting element preferably includes an electrode having visible light transmittance and reflectivity (semi-transmissive-semi-reflective electrode), and the other preferably includes an electrode having visible light reflectivity (reflective electrode). When the light-emitting element has a microcavity structure, the light emitted from the light-emitting layer can be resonated between the two electrodes, and the light emitted from the light-emitting element can be enhanced.

[0528] The light transmittance of the transparent electrode is 40% or more. For example, an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more is preferably used as a transparent electrode of a light-emitting element. The reflectivity of the semi-transmissive-semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectivity of the reflective electrode to visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1×10 -2 Ωcm or less.

[0529] The EL layers 113R, 113G, and 113B are all arranged in an island shape. Fig.24A In the embodiment, the ends of the adjacent EL layers 113R overlap with the ends of the EL layers 113G, the ends of the adjacent EL layers 113G overlap with the ends of the EL layers 113B, and the ends of the adjacent EL layers 113R overlap with the ends of the EL layers 113B. Fig.24A As shown in FIG. 1 , when an island-shaped EL layer is deposited using a high-definition metal mask, the ends of adjacent EL layers may overlap each other, but the present invention is not limited to this. That is, adjacent EL layers may not overlap each other but may be separated. In addition, in a display device, there may be both overlapping portions of adjacent EL layers and separated portions of adjacent EL layers not overlapping each other.

[0530] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer contains one or more light-emitting substances. As the light-emitting substance, a substance that emits light in a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. In addition, as the light-emitting substance, a substance that emits near-infrared light can also be used.

[0531] Examples of the light-emitting substance include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0532] The light-emitting layer may contain one or more organic compounds (host material, auxiliary material, etc.) in addition to the light-emitting substance (guest material). As one or more organic compounds, one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) may be used. In addition, as one or more organic compounds, a bipolar substance (a substance with high electron transport properties and hole transport properties) or a TADF material may also be used.

[0533] For example, the light-emitting layer preferably includes a combination of a phosphorescent material, a hole transport material that easily forms an exciplex, and an electron transport material. By adopting such a structure, light emission by ExTET (Exciplex-Triplet Energy Transfer) utilizing energy transfer from the exciplex to the luminescent substance (phosphorescent material) can be efficiently obtained. In addition, by selecting a combination of light whose wavelength overlaps with the absorption band on the lowest energy side of the luminescent substance as the exciplex, energy transfer can be smoothed, thereby efficiently obtaining light emission. By adopting the above structure, high efficiency, low voltage drive, and long life of the light-emitting element can be achieved at the same time.

[0534] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer). In addition, the EL layer may also include one or both of a bipolar material and a TADF material.

[0535] The light emitting element may use a low molecular weight compound or a high molecular weight compound, and may further contain an inorganic compound. The layers constituting the light emitting element may be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet, or coating.

[0536] The light-emitting element can adopt a single structure (a structure with only one light-emitting unit) or a series structure (a structure including multiple light-emitting units). The light-emitting unit includes at least one light-emitting layer. The series structure has a structure in which multiple light-emitting units are connected in series through a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes. By adopting a series structure, a light-emitting element that can emit light with high brightness can be realized. In addition, the series structure can improve reliability because it can reduce the current required to obtain the same brightness compared to the single structure. In addition, the series structure can also be called a stacked structure.

[0537] exist Fig.24A When a tandem-structured light-emitting element is used, it is preferred that the EL layer 113R include a plurality of light-emitting units emitting red light, the EL layer 113G include a plurality of light-emitting units emitting green light, and the EL layer 113B include a plurality of light-emitting units emitting blue light.

[0538] A protective layer 131 is provided on the light emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded by an adhesive layer 142. The substrate 152 is provided with a light shielding layer 117. As a seal for the light emitting element, for example, a solid sealing structure or a hollow sealing structure can be adopted. Fig.24A In the embodiment, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, that is, a solid sealing structure is adopted. Alternatively, a hollow sealing structure in which the space is filled with an inert gas (nitrogen or argon, etc.) can also be adopted. In this case, the adhesive layer 142 can also be arranged in a manner that does not overlap with the light-emitting element. In addition, a resin different from the adhesive layer 142 arranged in a frame shape can also be used to fill the space.

[0539] The protective layer 131 is provided at least in the display portion 162, and is preferably provided in a manner covering the entire display portion 162. The protective layer 131 is preferably provided in a manner covering the connection portion 140 and the peripheral circuit portion 164 in addition to the display portion 162. In addition, the protective layer 131 is preferably provided in a manner extending to the end of the display device 50A. On the other hand, in order to electrically connect the FPC 172 and the conductive layer 166, there is a portion in the connection portion 168 where the protective layer 131 is not provided.

[0540] By providing the protective layer 131 on the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B, the reliability of the light emitting elements can be improved.

[0541] The protective layer 131 may have a single layer structure or a stacked layer structure of two or more layers. There is no limitation on the conductivity of the protective layer 131. As the protective layer 131, at least one of an insulating film, a semiconductor film, and a conductive film may be used.

[0542] When the protective layer 131 includes an inorganic film, degradation of the light emitting element can be suppressed, such as preventing oxidation of the common electrode 115 and suppressing impurities (moisture, oxygen, etc.) from entering the light emitting element, thereby improving the reliability of the display device.

[0543] The protective layer 131 may be formed of an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes a nitride insulating film or a nitride oxide insulating film, and more preferably includes a nitride insulating film.

[0544] An inorganic film including ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO may be used as the protective layer 131. The inorganic film preferably has a high resistance, and more specifically, the inorganic film preferably has a resistance higher than that of the common electrode 115. The inorganic film may further include nitrogen.

[0545] When light emitted from the light emitting element is extracted through the protective layer 131, the protective layer 131 preferably has high visible light transmittance. For example, ITO, IGZO, and alumina are inorganic materials with high visible light transmittance and are therefore preferred.

[0546] As the protective layer 131, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using this stacked structure, impurities (water, oxygen, etc.) can be suppressed from entering the EL layer.

[0547] Furthermore, the protective layer 131 may include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film. Examples of the organic film that can be used for the protective layer 131 include an organic insulating film that can be used for the insulating layer 235 .

[0548] A connection portion 168 is provided in a region of the substrate 151 that does not overlap with the substrate 152. In the connection portion 168, the wiring 165 is electrically connected to the FPC 172 through the conductive layer 166 and the connection layer 242. The conductive layer 166 shows an example of a single-layer structure having a conductive layer obtained by processing the same conductive film as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B. The conductive layer 166 is exposed on the top surface of the connection portion 168. Therefore, the connection portion 168 can be electrically connected to the FPC 172 through the connection layer 242.

[0549] The wiring 165 is electrically connected to the transistor included in the peripheral circuit portion 164 . Fig.24A 14 shows a structure in which the conductive layer 112b included in the transistor 205D is extended to function as a wiring 165. Note that the structure of the wiring 165 is not limited to this.

[0550] The display device 50A adopts a top emission type. The light emitted by the light emitting element is emitted to the side of the substrate 152. The substrate 152 is preferably made of a material with high visible light transmittance. The pixel electrodes 111R, 111G, and 111B include a material that reflects visible light, and the counter electrode (common electrode 115) includes a material that transmits visible light.

[0551] It is preferable that a light shielding layer 117 is provided on the surface of the substrate 152 on the substrate 151 side. The light shielding layer 117 can be provided between adjacent light emitting elements or at a position overlapping with the connection portion 140, the peripheral circuit portion 164, and the like.

[0552] Alternatively, a coloring layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When the color filter is provided so as to overlap with the light-emitting element, the color purity of light emitted from the pixel can be improved.

[0553] In addition, various optical components can be arranged on the outside of the substrate 152 (the surface on the opposite side of the substrate 151). As optical components, for example, polarizers, phase difference plates, light diffusion layers (diffusion films, etc.), anti-reflection layers, and light-focusing films (condensing films) can be cited. In addition, surface protective layers such as antistatic films that inhibit the adhesion of dust, water-repellent films that are not easily soiled, hard coatings that inhibit damage during use, and impact-absorbing layers can also be arranged on the outside of the substrate 152. For example, by providing a glass layer or a silicon dioxide layer (SiO xLayer), which can prevent the surface from being dirty or damaged, is preferred. In addition, DLC (diamond-like carbon), aluminum oxide (AlO x ), polyester materials or polycarbonate materials, etc. In addition, as the surface protection layer, it is preferred to use a material with high transmittance to visible light. In addition, the surface protection layer is preferably made of a material with high hardness.

[0554] Glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, etc. can be used for the substrate 151 and the substrate 152, respectively. A material that transmits the light is used for the substrate on the side where the light is taken out from the light-emitting element. By using a flexible material for the substrate 151 and the substrate 152, the flexibility of the display device can be improved, thereby realizing a flexible display. A polarizing plate can also be used as at least one of the substrate 151 and the substrate 152.

[0555] As the substrate 151 and the substrate 152, the following materials can be used respectively: polyester resins such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyether sulfone (PES) resins, polyamide resins (nylon, aramid, etc.), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, and cellulose nanofibers, etc. In addition, glass having a thickness that allows flexibility can be used as at least one of the substrates 151 and 152.

[0556] When a circular polarizer is overlapped on a display device, it is preferred to use a substrate with high optical isotropy as the substrate included in the display device. The substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). As films with high optical isotropy, triacetyl cellulose (TAC, also called triacetyl cellulose) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic resin films can be cited.

[0557] As the adhesive layer 142, various curing adhesives such as light curing adhesives such as ultraviolet curing adhesives, reaction curing adhesives, heat curing adhesives, anaerobic adhesives, etc. can be used. As these adhesives, epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, EVA (ethylene-vinyl acetate) resins, etc. can be cited. In particular, it is preferred to use materials with low moisture permeability such as epoxy resins. In addition, two-liquid mixed resins can also be used. In addition, adhesive sheets, etc. can also be used.

[0558] As the connection layer 242 , an anisotropic conductive film (ACF: Anisotropic Conductive Film), anisotropic conductive paste (ACP: Anisotropic Conductive Paste), or the like can be used.

[0559] <Configuration Example 2 of Display Device>

[0560] Fig. 24B The display device 50B shown in the figure is mainly different from the display device 50A in that a light-emitting element including an EL layer 113 shared by the light-emitting elements and a coloring layer (color filter, etc.) are used in the sub-pixels of each color. Note that in the description of the display device described later, the description of the same parts as the display device described previously may be omitted.

[0561] Fig. 24B The display device 50B shown is Fig.24A The difference between the display device 50A in the embodiment is that the display device 50B includes transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, 130B, a coloring layer 132R that transmits red light, a coloring layer 132G that transmits green light, and a coloring layer 132B that transmits blue light between substrates 151 and 152. Note that Fig. 24B Extract and Fig.24A Different points are illustrated. Fig. 24B The structure shown can be combined with Fig.24A The structure shown includes the region of the FPC 172, the peripheral circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display portion 162, the connection portion 140, and the end portion.

[0562] The light emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. Light emitted by the light emitting element 130R is extracted as red light to the outside of the display device 50B through the coloring layer 132R.

[0563] The light emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. Light emitted by the light emitting element 130G is extracted as green light to the outside of the display device 50B through the coloring layer 132G.

[0564] The light emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. Light emitted by the light emitting element 130B is extracted as blue light to the outside of the display device 50B through the coloring layer 132B.

[0565] The light emitting elements 130R, 130G, and 130B share the EL layer 113 and the common electrode 115. Compared with a structure in which each sub-pixel of each color is provided with a different EL layer, a structure in which each sub-pixel of each color shares the EL layer 113 can reduce the number of manufacturing steps.

[0566] For example, Fig. 24B The light emitting elements 130R, 130G, and 130B shown emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0567] The white light-emitting element preferably includes two or more light-emitting layers. In the case of using two light-emitting layers to obtain white light, the light-emitting layers can be selected in such a way that the light-emitting colors of the two light-emitting layers are in a complementary color relationship. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer in a complementary color relationship, a structure in which the light-emitting element as a whole emits white light can be obtained. In addition, in the case of using three or more light-emitting layers to obtain white light, the light-emitting colors of the three or more light-emitting layers are combined to obtain a structure in which the light-emitting element as a whole emits white light.

[0568] The EL layer 113 preferably includes, for example, a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light having a longer wavelength than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0569] The light-emitting element emitting white light preferably adopts a series structure. Specifically, it can adopt: a two-stage series structure including a light-emitting unit emitting yellow light and a light-emitting unit emitting blue light; a two-stage series structure including a light-emitting unit emitting red light and green light and a light-emitting unit emitting blue light; a three-stage series structure including a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light or green light, and a light-emitting unit emitting blue light in sequence; or a three-stage series structure including a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light or green light and red light, and a light-emitting unit emitting blue light in sequence, etc. For example, as the number of layers and color sequence of the light-emitting unit, there can be cited a two-stage structure in which B and Y are stacked from the anode side, a two-stage structure in which B and the light-emitting unit X are stacked, a three-stage structure in which B, Y and B are stacked, and a three-stage structure in which B, X and B are stacked. As the number of layers and color sequence of the light-emitting layer in the light-emitting unit X, there can be adopted a two-stage structure in which R and Y are stacked from the anode side, a two-stage structure in which R and G are stacked, a two-stage structure in which G and R are stacked, a three-stage structure in which G, R and G are stacked, or a three-stage structure in which R, G and R are stacked. In addition, another layer may be provided between two light-emitting layers.

[0570] Or, for example Fig. 24B The light-emitting elements 130R, 130G, and 130B shown emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. With respect to the pixel 230B that presents blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, with respect to the pixel 230R that presents red light and the pixel 230G that presents green light, by providing a color conversion layer between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or 130G can be converted into light with a longer wavelength and extracted as red light or green light. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer on the light-emitting element 130R and the substrate 152, and to provide a coloring layer 132G between the color conversion layer on the light-emitting element 130G and the substrate 152. A portion of the light emitted by the light-emitting element is sometimes transmitted without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer through the coloring layer, the coloring layer can absorb light other than the desired color light, thereby improving the color purity of the light presented by the sub-pixel.

[0571] <Configuration Example 3 of Display Device>

[0572] Fig.25 The main difference between the illustrated display device 50C and the display device 50B is that the former is a bottom emission type display device.

[0573] Light emitted by the light emitting element is emitted toward the substrate 151. A material having high visible light transmittance is preferably used for the substrate 151. On the other hand, there is no limitation on the light transmittance of the material used for the substrate 152.

[0574] A light shielding layer 117 is preferably formed between the substrate 151 and the transistor. Fig.25 The following example is shown: a light shielding layer 117 is provided on a substrate 151, an insulating layer 153 is provided on the light shielding layer 117, and a transistor 205D, a transistor 205R (not shown), a transistor 205G, and a transistor 205B are provided on the insulating layer 153. In addition, a coloring layer 132R, a coloring layer 132G, and a coloring layer 132B are provided on the insulating layer 195, and an insulating layer 235 is provided on the coloring layers 132R, the coloring layer 132G, and the coloring layer 132B.

[0575] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113 , and a common electrode 115 .

[0576] The light emitting element 130B overlapping the colored layer 132B includes a pixel electrode 111B, an EL layer 113 , and a common electrode 115 .

[0577] The pixel electrodes 111G and 111B are each made of a material having high visible light transmittance. The common electrode 115 is preferably made of a material that reflects visible light. Since a metal with low resistivity can be used for the common electrode 115 in a bottom emission display device, a voltage drop caused by the resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.

[0578] <Configuration Example 4 of Display Device>

[0579] Fig.26A The main difference between the display device 50D shown and the display device 50A is that the former includes a light receiving element 130S.

[0580] The display device 50D includes a light-emitting element and a light-receiving element in a pixel. In the display device 50D, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, the organic photodiode can be installed in the display device using the organic EL element.

[0581] In the display device 50D in which pixels include a light-emitting element and a light-receiving element, the pixels have a light-receiving function, so the display device can detect the contact or approach of an object while displaying an image. Therefore, the display unit 162 has one or both of a camera function and a sensing function in addition to an image display function. For example, instead of displaying an image in all sub-pixels included in the display device 50D, a part of the sub-pixels can be used as a light source to emit light, another part of the sub-pixels can be used for light detection, and the remaining sub-pixels can be used to display an image.

[0582] Therefore, it is not necessary to separately provide a light receiving unit and a light source with the display device 50D, and the number of components of the electronic device can be reduced. For example, it is not necessary to separately provide a biometric device installed in the electronic device or an electrostatic capacitive touch panel for scrolling, etc. Therefore, by using the display device 50D, an electronic device with reduced manufacturing cost can be provided.

[0583] When the light receiving element is used for the image sensor, the display device 50D can capture images using the light receiving element. For example, the image sensor can be used to capture images for personal identification using fingerprints, palm prints, irises, vein shapes (including vein shapes, artery shapes) or faces.

[0584] The light receiving element can be used for a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a floating sensor, a floating touch sensor, a non-touch sensor), etc. A touch sensor can detect an object when the object (a finger, a hand, a pen, etc.) directly contacts the display device. In addition, a non-contact sensor can detect the object even if the object does not contact the display device.

[0585] The light emitting element 130S includes a pixel electrode 111S on the insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Ln is incident on the functional layer 113S from the outside of the display device 50D.

[0586] The pixel electrode 111S is electrically connected to the conductive layer 112 b included in the transistor 205S through openings provided in the insulating layer 195 and the insulating layer 235 .

[0587] The end portion of the pixel electrode 111S is covered with the insulating layer 237 .

[0588] The common electrode 115 is a continuous film shared by the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B. The common electrode 115 shared by the light emitting element and the light receiving element is electrically connected to the conductive layer 123 provided in the connection portion 140 .

[0589] The functional layer 113S includes at least an active layer (also referred to as a photoelectric conversion layer). The active layer includes a semiconductor. As the semiconductor, inorganic semiconductors such as silicon and organic semiconductors including organic compounds can be cited. In this embodiment, an example of using an organic semiconductor as a semiconductor contained in the active layer is shown. By using an organic semiconductor, the light-emitting layer and the active layer can be formed by the same method (e.g., vacuum evaporation method), and the manufacturing equipment can be used together, so it is preferred.

[0590] The functional layer 113S may also include a layer containing a substance with high hole transport properties, a substance with high electron transport properties, or a bipolar substance (a substance with high electron transport properties and hole transport properties) as a layer other than the active layer. In addition, without limitation thereto, a layer containing a substance with high hole injection properties, a hole blocking material, a substance with high electron injection properties, or an electron blocking material may also be included. As a layer other than the active layer included in the light-receiving element, for example, the above-mentioned material that can be used for the light-emitting element can be used.

[0591] The light receiving element may use a low molecular weight compound or a high molecular weight compound, and may also contain an inorganic compound. The layer constituting the light receiving element may be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet, or coating.

[0592] When part of the peripheral region of the functional layer 113S of the light receiving element is covered by the light shielding layer 117, the range in which the light receiving element detects light can be controlled. The light shielding layer 117 has openings in a region overlapping with the EL layer of the light emitting element and a region overlapping with the functional layer 113S. Fig.26A An example is shown in which the width Ws of the opening overlapping the functional layer 113S is narrower than the width We of the opening overlapping the EL layer. For example, when the width Ws is narrow, the resolution of the light receiving element is improved in some cases.

[0593] Fig.26B and Fig.26C The display device 50D shown includes a layer 353 having a light receiving element, a circuit layer 355 , and a layer 357 having a light emitting element between a substrate 151 and a substrate 152 .

[0594] The layer 353 includes, for example, the light receiving element 130S. The layer 357 includes, for example, the light emitting elements 130R, 130G, and 130B.

[0595] The circuit layer 355 includes a circuit for driving the light receiving element and a circuit for driving the light emitting element. The circuit layer 355 includes, for example, transistors 205R, 205G, and 205B. In addition, one or more switches, transistors, capacitors, resistors, wiring, terminals, etc. may be provided in the circuit layer 355.

[0596] Fig.26BThis is an example of using the light receiving element 130S as a touch sensor. Fig.26B As shown, when the finger 352 touching the display device 50D reflects the light emitted by the light emitting element in the layer 357, the light receiving element in the layer 353 detects the reflected light. Thus, it is possible to detect that the finger 352 has touched the display device 50D.

[0597] Fig.26C This is an example of using the light receiving element 130S as a non-contact sensor. Fig.26C As shown, when a finger 352 approaching (ie, not touching) the display device 50D reflects light emitted by the light emitting element in the layer 357 , the light receiving element in the layer 353 detects the reflected light.

[0598] <Configuration Example 5 of Display Device>

[0599] Fig.27A The display device 50E shown is an example of a device using an MML (Metal Mask Less) structure. That is, the display device 50E includes a light-emitting element that is not manufactured using a high-precision metal mask. Note that the stacked structure from the substrate 151 to the insulating layer 235 and the stacked structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, so the description thereof is omitted.

[0600] exist Fig.27A In the embodiment, light emitting elements 130R, 130G, and 130B are disposed on the insulating layer 235 .

[0601] The light emitting element 130R includes a conductive layer 124R on the insulating layer 235 , a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114 . Fig.27A The light emitting element 130R shown emits red light (R). The layer 133R includes a light emitting layer that emits red light. In the light emitting element 130R, the layer 133R and the common layer 114 may be collectively referred to as an EL layer. One or both of the conductive layer 124R and the conductive layer 126R may be referred to as a pixel electrode.

[0602] The light emitting element 130G includes a conductive layer 124G on the insulating layer 235 , a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114 . Fig.27A The light emitting element 130G shown emits green light (G). The layer 133G includes a light emitting layer that emits green light. In the light emitting element 130G, the layer 133G and the common layer 114 can be collectively referred to as an EL layer. One or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

[0603] The light emitting element 130B includes a conductive layer 124B on the insulating layer 235 , a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114 . Fig.27A The light emitting element 130B shown emits blue light (B). Layer 133B includes a light emitting layer that emits blue light. In the light emitting element 130B, layer 133B and common layer 114 may be collectively referred to as an EL layer. One or both of conductive layer 124B and conductive layer 126B may be referred to as a pixel electrode.

[0604] In this specification and the like, an island-shaped layer provided for each light-emitting element in the EL layer included in the light-emitting element is referred to as a layer 133R, a layer 133G, or a layer 133B, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 114. In addition, in this specification and the like, the layer 133R, the layer 133G, and the layer 133B not including the common layer 114 may be referred to as an island-shaped EL layer, an EL layer formed in an island shape, or the like.

[0605] Layer 133R, layer 133G, and layer 133B are separated from each other. By providing an island-shaped EL layer in each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. Therefore, unintentional light emission caused by crosstalk can be suppressed, thereby realizing a display device with a very high contrast.

[0606] In addition, Fig.27A In FIG. 1 , the film thicknesses of the layers 133R, 133G, and 133B are shown as being the same, but the present invention is not limited thereto. The film thicknesses of the layers 133R, 133G, and 133B may be different from each other.

[0607] Conductive layer 124R is electrically connected to conductive layer 112b included in transistor 205R via openings provided in insulating layer 195 and insulating layer 235. Similarly, conductive layer 124G is electrically connected to conductive layer 112b included in transistor 205G, and conductive layer 124B is electrically connected to conductive layer 112b included in transistor 205B.

[0608] Conductive layers 124R, 124G, and 124B are formed to cover the openings provided in insulating layer 235. Concave portions of conductive layers 124R, 124G, and 124B are filled with layer 128, respectively.

[0609] Layer 128 has the function of flattening the concave portions of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B electrically connected to conductive layers 124R, 124G, and 124B are provided on conductive layers 124R, 124G, and 124B and layer 128. Therefore, the region overlapping the concave portions of conductive layers 124R, 124G, and 124B can also be used as a light-emitting region, thereby increasing the aperture ratio of the pixel. Conductive layers 124R and 126R are preferably conductive layers used as reflective electrodes.

[0610] Layer 128 may be an insulating layer or a conductive layer. Layer 128 may be formed of various inorganic insulating materials, organic insulating materials, and conductive materials as appropriate. In particular, layer 128 is preferably formed of an insulating material, and is particularly preferably formed of an organic insulating material. As layer 128, for example, an organic insulating material that can be used for the above-mentioned insulating layer 237 can be used.

[0611] Although Fig.27A An example is shown in which the top surface of the layer 128 has a flat portion, but there is no particular limitation on the shape of the layer 128. The top surface of the layer 128 may have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0612] The height of the top surface of layer 128 may be the same as or substantially the same as the height of the top surface of conductive layer 124R, or may be different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

[0613] The end of the conductive layer 126R may also be aligned with the end of the conductive layer 124R, and may also cover the side of the end of the conductive layer 124R. Each end of the conductive layer 124R and the conductive layer 126R preferably has a tapered shape. Specifically, each end of the conductive layer 124R and the conductive layer 126R preferably has a tapered shape with a taper angle less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side of the pixel electrode has an inclined portion. By making the side of the pixel electrode have a tapered shape, the coverage of the EL layer provided along the side of the pixel electrode can be improved.

[0614] Since the conductive layers 124G and 126G and the conductive layers 124B and 126B are the same as the conductive layers 124R and 126R, detailed descriptions thereof will be omitted.

[0615] The top surface and side surfaces of the conductive layer 126R are covered by the layer 133R. Similarly, the top surface and side surfaces of the conductive layer 126G are covered by the layer 133G, and the top surface and side surfaces of the conductive layer 126B are covered by the layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0616] Part of the top surface and side surfaces of the layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is provided on the layers 133R, 133G, 133B, and the insulating layers 125 and 127, and a common electrode 115 is provided on the common layer 114. Both the common layer 114 and the common electrode 115 are continuous films shared by a plurality of light-emitting elements.

[0617] exist Fig.27A In the embodiment, there is no arrangement between the conductive layer 126R and the layer 133R. Fig.24A In other words, the display device 50E is not provided with an insulating layer (also referred to as a partition wall, a dam, a spacer, etc.) that contacts the pixel electrode and covers the top surface end of the pixel electrode. Therefore, the interval between adjacent light-emitting elements can be made very small. Thus, a high-definition or high-resolution display device can be realized. In addition, there is no need for a mask for forming the insulating layer, thereby reducing the manufacturing cost of the display device.

[0618] As described above, layer 133R, layer 133G, and layer 133B all include a light-emitting layer. Layer 133R, layer 133G, and layer 133B preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. In addition, layer 133R, layer 133G, and layer 133B preferably include a light-emitting layer and a carrier blocking layer (hole blocking layer or electron blocking layer) on the light-emitting layer. In addition, layer 133R, layer 133G, and layer 133B may also include a light-emitting layer, a carrier blocking layer on the light-emitting layer, and a carrier transport layer on the carrier blocking layer. The surfaces of layer 133R, layer 133G, and layer 133B are exposed in the manufacturing process of the display device, so by providing one or both of the carrier transport layer and the carrier blocking layer on the light-emitting layer, the light-emitting layer can be prevented from being exposed to the outermost surface and the damage to the light-emitting layer can be reduced. As a result, the reliability of the light-emitting element can be improved.

[0619] The common layer 114 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The light emitting elements 130R, 130G, and 130B share the common layer 114.

[0620] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B via the insulating layer 125.

[0621] By covering the side surfaces of the layers 133R, 133G, and 133B (or even covering a portion of the top surfaces thereof) with at least one of the insulating layer 125 and the insulating layer 127, the common layer 114 (or the common electrode 115) can be prevented from contacting the pixel electrode and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing the light-emitting element from being short-circuited. Thus, the reliability of the light-emitting element can be improved.

[0622] The insulating layer 125 is preferably in contact with the side surfaces of the layers 133R, 133G, and 133B. By adopting a structure in which the insulating layer 125 is in contact with the layers 133R, 133G, and 133B, film peeling of the layers 133R, 133G, and 133B can be prevented, thereby improving the reliability of the light-emitting element.

[0623] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recessed portion of the insulating layer 125. The insulating layer 127 preferably covers at least a part of the side surface of the insulating layer 125.

[0624] By providing the insulating layer 125 and the insulating layer 127, the space between adjacent island-shaped layers can be filled, so that the unevenness of the formed surface of the layer (for example, the carrier injection layer, the common electrode, etc.) provided on the island-shaped layer can be reduced and further flattened. Therefore, the coverage of the carrier injection layer or the common electrode, etc. can be improved.

[0625] The common layer 114 and the common electrode 115 are arranged on the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are arranged, steps are generated due to the area where the pixel electrode and the island EL layer are arranged and the area where the pixel electrode and the island EL layer are not arranged (the area between the light-emitting elements). The display device of one embodiment of the present invention can flatten the step by including the insulating layer 125 and the insulating layer 127, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection caused by disconnection can be suppressed. Alternatively, the resistance increase caused by the local thin filmization of the common electrode 115 due to the step can be suppressed.

[0626] The top surface of the insulating layer 127 preferably has a shape with higher flatness. The top surface of the insulating layer 127 may also have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the top surface of the insulating layer 127 preferably has a convex curved surface shape with high flatness.

[0627] The insulating layer 125 may be an insulating layer containing an inorganic material. As the insulating layer 125, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film may be used. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 may be a single-layer structure or a stacked-layer structure. In particular, the selectivity of aluminum oxide to the EL layer is high in etching, and it has a function of protecting the EL layer in the formation of the insulating layer 127 described later, so it is preferred. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD method for the insulating layer 125, an insulating layer 125 with fewer pinholes and a good function of protecting the EL layer can be formed. In addition, the insulating layer 125 may also have a stacked-layer structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulating layer 125 may have a stacked-layer structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0628] The insulating layer 125 preferably has a function of a blocking insulating layer with respect to at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing the diffusion of at least one of water and oxygen. In addition, the insulating layer 125 preferably has a function of capturing or fixing (also referred to as doping) at least one of water and oxygen.

[0629] When the insulating layer 125 is used as a blocking insulating layer or has an impurity gettering function, it can have a structure that suppresses the entry of impurities (typically, at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. By adopting this structure, a light-emitting element with high reliability can be provided, and a display device with high reliability can be provided.

[0630] The impurity concentration of the insulating layer 125 is preferably low. This can prevent impurities from being mixed into the EL layer from the insulating layer 125 and deteriorating the EL layer. In addition, by reducing the impurity concentration in the insulating layer 125, the barrier property against at least one of water and oxygen can be improved. For example, it is preferable that one of the hydrogen concentration and the carbon concentration in the insulating layer 125 is sufficiently low, and it is preferable that both the hydrogen concentration and the carbon concentration are sufficiently low.

[0631] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the large unevenness of the insulating layer 125 formed between adjacent light emitting elements. In other words, the insulating layer 127 improves the flatness of the surface on which the common electrode 115 is formed.

[0632] As the insulating layer 127, an insulating layer containing an organic material can be used as appropriate. As the organic material, a photosensitive organic resin is preferably used, for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification, etc., acrylic resin does not refer to only polymethacrylate or methacrylic resin, and sometimes refers to acrylic polymers in a broad sense as a whole.

[0633] As the insulating layer 127, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of the above resins can also be used. In addition, as the insulating layer 127, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose or alcohol-soluble polyamide resin can also be used. In addition, as a photosensitive resin, a photoresist can also be used. As a photosensitive organic resin, a positive material or a negative material can be used.

[0634] A material that absorbs visible light may also be used as the insulating layer 127. By absorbing the light emitted from the light-emitting element by the insulating layer 127, it is possible to suppress the leakage of light from the light-emitting element to the adjacent light-emitting element through the insulating layer 127 (stray light). Therefore, the display quality of the display device can be improved. In addition, the display quality can be improved even if a polarizing plate is not used in the display device, so a lightweight and thin display device can be realized.

[0635] As materials that absorb visible light, materials including pigments such as black, materials including dyes, resin materials including light absorption (for example, polyimide, etc.), and resin materials that can be used for color filters (color filter materials) can be cited. In particular, when using a resin material formed by stacking or mixing two or more colors of color filter materials, the effect of shielding visible light can be improved, so it is preferred. In particular, by mixing three or more colors of color filter materials, a black or nearly black resin layer can be achieved.

[0636] <Structural Example 6 of Display Device>

[0637] Fig.27B The display device 50F shown is mainly different from the display device 50E in that a light-emitting element including a layer 133 and a coloring layer (color filter, etc.) are provided in a sub-pixel of each color.

[0638] Fig.27B The structure shown can be combined with Fig.27A The structure shown includes the region of the FPC 172, the peripheral circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display portion 162, the connection portion 140, and the end portion.

[0639] Fig.27B The display device 50F shown includes light emitting elements 130R, 130G, and 130B, a coloring layer 132R that transmits red light, a coloring layer 132G that transmits green light, a coloring layer 132B that transmits blue light, and the like.

[0640] The light emitted by the light emitting element 130R is extracted as red light to the outside of the display device 50F through the coloring layer 132R. Similarly, the light emitted by the light emitting element 130G is extracted as green light to the outside of the display device 50F through the coloring layer 132G. The light emitted by the light emitting element 130B is extracted as blue light to the outside of the display device 50F through the coloring layer 132B.

[0641] The light-emitting elements 130R, 130G, and 130B each include a layer 133. These three layers 133 are formed by the same process and the same material. In addition, these three layers 133 are separated from each other. By providing an island-shaped EL layer in each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. Therefore, unintentional light emission caused by crosstalk can be suppressed, thereby realizing a display device with very high contrast.

[0642] For example, Fig.27B The light emitting elements 130R, 130G, and 130B shown emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0643] Or, for example Fig.27B The light-emitting elements 130R, 130G, and 130B shown emit blue light. In this case, the layer 133 includes one or more light-emitting layers that emit blue light. For the sub-pixel that presents blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, for the sub-pixel that presents red light and the sub-pixel that presents green light, by providing a color conversion layer between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or 130G can be converted into light with a longer wavelength and extracted as red light or green light. In addition, it is preferred that a coloring layer 132R is provided between the color conversion layer on the light-emitting element 130R and the substrate 152, and a coloring layer 132G is provided between the color conversion layer on the light-emitting element 130G and the substrate 152. By extracting the light that transmits the color conversion layer through the coloring layer, the color purity of the light presented by the sub-pixel can be improved by absorbing light other than the desired color light by the coloring layer.

[0644] In addition, the bottom emission display device shown in the display device 50C can also use the structure of the light emitting element 130 shown in the display device 50E and the display device 50F. In this case, the pixel electrode 111 of the light emitting element 130 can use a material with high visible light transmittance, and the common electrode 115 can use a material that reflects visible light.

[0645] <Example of Method for Manufacturing Display Device>

[0646] The following describes a method for manufacturing a device using an MML (Metal Mask Less) structure with reference to FIG28. Here, the process of manufacturing a light-emitting element without a high-definition metal mask is described in detail. FIG28 is a cross-sectional view of three light-emitting elements and a connection portion 140 included in a display portion 162 in each process.

[0647] When manufacturing a light-emitting element, a vacuum process such as evaporation and a solution process such as spin coating and inkjet can be used. As an evaporation method, physical evaporation methods (PVD methods) such as sputtering, ion plating, ion beam evaporation, molecular beam evaporation, vacuum evaporation, and chemical vapor deposition (CVD methods) can be cited. In particular, a functional layer (hole injection layer, hole transport layer, hole blocking layer, light-emitting layer, electron blocking layer, electron transport layer, electron injection layer, charge generation layer, etc.) included in the EL layer can be formed using evaporation (vacuum evaporation), coating (dip coating, dye coating, rod coating, spin coating, spray coating), printing (inkjet, screen printing (porcelain printing), offset printing (lithography), flexographic printing (relief printing), gravure printing or micro-contact printing, etc.) and other methods.

[0648] The island-shaped layer (including the light-emitting layer) manufactured in the manufacturing method of the display device described below is not formed using a high-precision metal mask, but is formed by processing by photolithography after the light-emitting layer is deposited on the entire surface. Therefore, a high-definition display device or a display device with a high aperture ratio that has been difficult to achieve so far can be realized. Furthermore, since the light-emitting layer can be formed separately for each color, a display device with extremely clear, high contrast and high display quality can be realized. In addition, by providing a sacrificial layer on the light-emitting layer, the damage to the light-emitting layer during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0649] For example, when a display device is composed of three light-emitting elements: a light-emitting element emitting blue light, a light-emitting element emitting green light, and a light-emitting element emitting red light, three island-shaped light-emitting layers can be formed by repeating the formation of the light-emitting layer and the photolithography process three times.

[0650] First, pixel electrodes 111R, 111G, 111B and a conductive layer 123 are formed on a substrate 151 provided with transistors 205R, 205G, 205B, etc. (not shown). Fig.28A ).

[0651] When forming the conductive film to be the pixel electrode, for example, a sputtering method or a vacuum evaporation method may be used. By forming a resist mask on the conductive film by a photolithography process and then processing the conductive film, the pixel electrodes 111R, 111G, 111B and the conductive layer 123 can be formed. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0652] Next, a film 133Bf (which will later become a layer 133B) is formed on the pixel electrodes 111R, 111G, and 111B. Fig.28A ). The film 133Bf (latter layer 133B) includes a light-emitting layer that emits blue light.

[0653] This embodiment shows an example in which an island-shaped EL layer is first formed in a light-emitting element that emits blue light, and then an island-shaped EL layer is formed in a light-emitting element that emits light of other colors.

[0654] In the process of forming the island-shaped EL layer, the pixel electrodes in the light-emitting elements of the colors formed second and later may be damaged in the previous process. Therefore, the driving voltage of the light-emitting elements of the colors formed second and later may become high.

[0655] Therefore, when manufacturing a display device according to one embodiment of the present invention, it is preferred to start manufacturing from the island EL layer of the light-emitting element (e.g., the blue light-emitting element) that emits the shortest wavelength of light. For example, it is preferred to manufacture the island EL layer in the order of blue, green, red, or blue, red, green.

[0656] Thus, the state of the interface between the pixel electrode and the EL layer in the blue light-emitting element can be well maintained, thereby suppressing the driving voltage of the blue light-emitting element from becoming higher. In addition, the life of the blue light-emitting element can be extended and the reliability can be improved. Note that compared with the blue light-emitting element, the driving voltage rise of the red and green light-emitting elements is less affected, so the driving voltage can be reduced and the reliability can be improved as a whole display device.

[0657] Note that the order of manufacturing the island-shaped EL layers is not limited to the above order, and for example, the island-shaped EL layers may be manufactured in the order of red, green, and blue.

[0658] like Fig.28AAs shown, the film 133Bf is not formed on the conductive layer 123. For example, the film 133Bf can be deposited only in a desired region using a range mask. By adopting a deposition process using a range mask and a processing process using a resist mask, a light emitting element can be manufactured with a relatively simple process.

[0659] The heat-resistant temperature of the compound contained in the film 133Bf is preferably 100° C. or more and 180° C. or less, more preferably 120° C. or more and 180° C. or less, and further preferably 140° C. or more and 180° C. or less. Thus, the reliability of the light-emitting element can be improved. In addition, the upper limit of the temperature that can be applied in the manufacturing process of the display device can be increased. Therefore, the range of selection of materials and formation methods for the display device can be expanded, thereby achieving an increase in yield and an increase in reliability.

[0660] As the heat-resistant temperature, for example, any of the glass transition temperature, softening point, melting point, thermal decomposition temperature and 5% weight loss temperature may be used, and the lowest temperature among the above temperatures is preferably used.

[0661] The film 133Bf can be formed by, for example, a vapor deposition method, specifically, a vacuum vapor deposition method. Alternatively, the film 133Bf can be formed by a transfer method, a printing method, an inkjet method, or a coating method.

[0662] Next, a sacrificial layer 118B is formed on the film 133Bf and the conductive layer 123 ( Fig.28A ). The sacrificial layer 118B can be formed by forming a resist mask on a film that will later become the sacrificial layer 118B by a photolithography process and then processing the film.

[0663] By providing the sacrificial layer 118B on the film 133Bf, damage to the film 133Bf during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0664] The sacrificial layer 118B is preferably provided in a manner covering each end of the pixel electrodes 111R, 111G, and 111B. Thus, the end of the layer 133B formed in the subsequent process is located outside the end of the pixel electrode 111B. Since the entire top surface of the pixel electrode 111B can be used as a light-emitting area, the aperture ratio of the pixel can be increased. In addition, the end of the layer 133B may be damaged in the process after the layer 133B is formed, so it is preferably located outside the end of the pixel electrode 111B, that is, it is preferably not used as a light-emitting area. Thus, the uneven characteristics of the light-emitting element can be suppressed, and the reliability can be improved.

[0665] By covering the top surface and side surfaces of the pixel electrode 111B with the layer 133B, each process after forming the layer 133B can be performed without exposing the pixel electrode 111B. When the end of the pixel electrode 111B is exposed, corrosion may occur in an etching process, etc. By suppressing the corrosion of the pixel electrode 111B, the yield and characteristics of the light-emitting element can be improved.

[0666] Preferably, the sacrificial layer 118B is further provided at a position overlapping with the conductive layer 123. Thus, the conductive layer 123 can be prevented from being damaged during the manufacturing process of the display device.

[0667] As the sacrificial layer 118B, a film having high resistance to the processing conditions of the film 133Bf is used. Specifically, a film having a large etching selectivity ratio with the film 133Bf is used.

[0668] The sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound included in the film 133Bf. The substrate temperature when forming the sacrificial layer 118B is typically 200°C or less, preferably 150°C or less, more preferably 120°C or less, further preferably 100°C or less, and further preferably 80°C or less.

[0669] When the heat-resistant temperature of the compound contained in the film 133Bf is high, the deposition temperature of the sacrificial layer 118B can be increased, so it is preferred. For example, the substrate temperature when forming the sacrificial layer 118B can also be set to above 100°C, above 120°C, or above 140°C. The higher the deposition temperature, the denser and more barrier-resistant inorganic insulating film can be formed. Therefore, by depositing the sacrificial layer at the above temperature, the damage to the film 133Bf can be further reduced, thereby improving the reliability of the light-emitting element.

[0670] The deposition temperature of other layers (eg, insulating film 125f) formed on the film 133Bf is the same as described above.

[0671] The sacrificial layer 118B may be formed by, for example, sputtering, ALD (including thermal ALD and PEALD), CVD, or vacuum evaporation. Alternatively, the sacrificial layer 118B may be formed by the above-mentioned wet deposition method.

[0672] The sacrificial layer 118B (a layer provided in contact with the film 133Bf when the sacrificial layer 118B has a stacked structure) is preferably formed by a formation method that causes less damage to the film 133Bf. For example, ALD or vacuum evaporation is more preferable than sputtering.

[0673] The sacrificial layer 118B can be processed by wet etching or dry etching. The sacrificial layer 118B is preferably processed by anisotropic etching.

[0674] By using the wet etching method, the damage to the film 133Bf during the processing of the sacrificial layer 118B can be reduced compared to the dry etching method. When the wet etching method is used, for example, it is preferred to use a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of the above. In addition, when the wet etching method is used, a mixed acid solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid can also be used. Note that the solution used for the wet etching process can be alkaline or acidic.

[0675] As the sacrificial layer 118B, for example, one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film can be used.

[0676] As the sacrificial layer 118B, for example, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium and tantalum, or alloy materials containing these metal materials can be used.

[0677] The sacrificial layer 118B can use metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.

[0678] Note that element M (M is one or more of aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used instead of the above-mentioned gallium.

[0679] For example, as a material very suitable for the manufacturing process of semiconductors, semiconductor materials such as silicon or germanium are preferably used. In addition, oxides or nitrides of the above semiconductor materials can be used. In addition, non-metallic materials such as carbon or their compounds can be used. In addition, metals such as titanium, tantalum, tungsten, chromium, aluminum, or alloys containing one or more of them can be used. In addition, oxides of the above metals such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride can be used.

[0680] As the sacrificial layer 118B, various inorganic insulating films that can be used for the protective layer 131 can be used. In particular, the adhesion between the oxide insulating film and the film 133Bf is higher than the adhesion between the nitride insulating film and the film 133Bf, so it is preferred. For example, inorganic insulating materials such as aluminum oxide, hafnium oxide and silicon oxide can be used for the sacrificial layer 118B. As the sacrificial layer 118B, for example, an aluminum oxide film can be formed by the ALD method. By using the ALD method, damage to the substrate (especially the film 133Bf) can be reduced, so it is preferred.

[0681] For example, the sacrificial layer 118B may have a stacked structure of an inorganic insulating film (eg, an aluminum oxide film) formed by ALD and an inorganic film (eg, an In—Ga—Zn oxide film, a silicon film, or a tungsten film) formed by sputtering.

[0682] In addition, the same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 formed later. For example, an aluminum oxide film formed using the ALD method can be used for both the sacrificial layer 118B and the insulating layer 125. Here, the sacrificial layer 118B and the insulating layer 125 can be deposited under the same deposition conditions or different deposition conditions. For example, by depositing the sacrificial layer 118B under the same conditions as the insulating layer 125, the sacrificial layer 118B can be formed as an insulating layer with high barrier properties to at least one of water and oxygen. On the other hand, the sacrificial layer 118B is a layer that is mostly or entirely removed in a subsequent process, so it is preferably easy to process. Therefore, the sacrificial layer 118B is preferably deposited under conditions where the substrate temperature is lower than that of the insulating layer 125 during deposition.

[0683] An organic material may also be used as the sacrificial layer 118B. For example, a material that is soluble in a solvent that is chemically stable to at least the film located at the uppermost portion of the film 133Bf may also be used as the organic material. In particular, a material that is soluble in water or alcohol may be used appropriately. When depositing the above-mentioned material, it is preferred that the material is applied by the above-mentioned wet deposition method in a state where the material is dissolved in a solvent such as water or alcohol, and then a heating treatment is performed to evaporate the solvent. At this time, by performing the heating treatment in a reduced pressure atmosphere, the solvent can be removed at a low temperature and in a short time, so that thermal damage to the film 133Bf can be reduced, which is preferred.

[0684] Alternatively, the sacrificial layer 118B may be made of an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, alcohol-soluble polyamide resin, or fluororesin such as perfluoropolymer.

[0685] For example, the sacrificial layer 118B may have a stacked structure of an organic film (eg, a PVA film) formed by evaporation or the wet deposition method and an inorganic film (eg, a silicon nitride film) formed by sputtering.

[0686] Note that a part of the sacrificial film may remain as a sacrificial layer in the display device of one embodiment of the present invention.

[0687] Next, the sacrificial layer 118B is used as a hard mask processing film 133Bf to form a layer 133B ( Fig.28B ).

[0688] Therefore, if Fig.28B As shown, the stacked structure of the layer 133B and the sacrificial layer 118B remains on the pixel electrode 111B. In addition, the pixel electrode 111R and the pixel electrode 111G are exposed. In addition, the sacrificial layer 118B r...

Claims

1. A semiconductor device comprising: a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer on the first semiconductor layer, a third conductive layer on the second insulating layer, and a first insulating layer sandwiched between the first conductive layer and the second conductive layer, wherein the first insulating layer has a first opening reaching the first conductive layer, The second conductive layer has a second opening, The first opening and the second opening overlap each other when viewed from a plane, The first semiconductor layer contacts the top surface of the first conductive layer and the side surface of the first insulating layer in the first opening. The first semiconductor layer contacts a side surface of the second conductive layer in the second opening, The first semiconductor layer has a region overlapping the third conductive layer via the second insulating layer. Furthermore, the side surface of the first insulating layer in the first opening has a region where an angle formed with the top surface of the first conductive layer is greater than or equal to 10 degrees and less than 55 degrees. 2 . The semiconductor device according to claim 1 , wherein a thickness of the first insulating layer is greater than or equal to 10 nm and less than 3 μm. The semiconductor device according to claim 1 , wherein the first semiconductor layer comprises a metal oxide.

4. A semiconductor device comprising: a first transistor, a second transistor and a first insulating layer, The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer on the first semiconductor layer, and a third conductive layer on the second insulating layer. The second transistor includes a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, the second insulating layer on the second semiconductor layer, and a sixth conductive layer on the second insulating layer, The first insulating layer has a region sandwiched between the first conductive layer and the second conductive layer and a region sandwiched between the fourth conductive layer and the fifth conductive layer. The first insulating layer includes a first opening reaching the first conductive layer and a second opening reaching the fourth conductive layer, The side surface of the first insulating layer in the first opening has a region where the angle formed with the top surface of the first conductive layer is greater than 10 degrees and less than 55 degrees, The side surface of the first insulating layer in the second opening has a region where the angle formed with the top surface of the fourth conductive layer is greater than or equal to 55 degrees and less than or equal to 90 degrees, The second conductive layer has a third opening, The first opening and the third opening overlap each other when viewed from a plane, The fifth conductive layer has a fourth opening, The second opening and the fourth opening overlap each other when viewed from a plane, The first semiconductor layer contacts the top surface of the first conductive layer and the side surface of the first insulating layer in the first opening. The first semiconductor layer contacts the side surface of the second conductive layer in the third opening, The first semiconductor layer overlaps with the third conductive layer via the second insulating layer. The second semiconductor layer contacts the top surface of the fourth conductive layer and the side surface of the first insulating layer in the second opening. The second semiconductor layer contacts the side surface of the fifth conductive layer in the fourth opening. Furthermore, the second semiconductor layer overlaps the sixth conductive layer via the second insulating layer.

5. The semiconductor device according to claim 4, The second insulating layer includes a first region covering the side surface of the first insulating layer in the first opening through the first semiconductor layer, a second region covering the top surface of the second conductive layer through the first semiconductor layer, a third region covering the side surface of the first insulating layer in the second opening through the second semiconductor layer, and a fourth region covering the top surface of the fifth conductive layer through the second semiconductor layer. The thickness of the first region is greater than 0.85 times and less than 1.2 times the thickness of the second region, Furthermore, the thickness of the third region is not less than 0.4 times and not more than 0.85 times the thickness of the fourth region.

6. The semiconductor device according to claim 5, wherein the thickness of the second region is greater than or equal to 10 nm and less than or equal to 200 nm, And the thickness of the fourth region is greater than or equal to 10 nm and less than or equal to 200 nm.

7. The semiconductor device according to claim 4, The second insulating layer includes a first region covering the side surface of the first insulating layer in the first opening through the first semiconductor layer, a second region covering the top surface of the first conductive layer through the first semiconductor layer, a third region covering the side surface of the first insulating layer in the second opening through the second semiconductor layer, and a fourth region covering the top surface of the fourth conductive layer through the second semiconductor layer. The thickness of the first region is greater than 0.85 times and less than 1.2 times the thickness of the second region, Furthermore, the thickness of the third region is greater than or equal to 0.4 times and less than or equal to 0.85 times the thickness of the fourth region.

8. The semiconductor device according to claim 7, wherein the thickness of the second region is greater than or equal to 10 nm and less than or equal to 200 nm, And the thickness of the fourth region is greater than or equal to 10 nm and less than or equal to 200 nm.

9. The semiconductor device according to claim 4, wherein in the first semiconductor layer, a thickness of a region of the first opening in contact with a side surface of the first insulating layer is greater than 0.85 times and less than 1.2 times a thickness of a region in contact with a top surface of the second conductive layer, Furthermore, in the second semiconductor layer, a thickness of a region of the second opening that contacts a side surface of the first insulating layer is greater than or equal to 0.4 times and less than or equal to 0.85 times a thickness of a region of the second opening that contacts a top surface of the fifth conductive layer.

10. The semiconductor device according to claim 9, wherein a thickness of a region of the first semiconductor layer in contact with a top surface of the second conductive layer is greater than or equal to 1 nm and less than or equal to 200 nm, Furthermore, a thickness of a region of the second semiconductor layer that contacts a top surface of the fifth conductive layer is greater than or equal to 1 nm and less than or equal to 200 nm.

11. The semiconductor device according to claim 4, wherein in the first semiconductor layer, a thickness of a region in the first opening that contacts a side surface of the first insulating layer is greater than 0.85 times and less than 1.2 times a thickness of a region in the first opening that contacts a top surface of the first conductive layer, In the second semiconductor layer, a thickness of a region of the second opening in contact with a side surface of the first insulating layer is not less than 0.4 times and not more than 0.85 times a thickness of a region of the second opening in contact with a top surface of the fourth conductive layer.

12. The semiconductor device according to claim 11, wherein a thickness of a region of the first semiconductor layer in contact with a top surface of the first conductive layer is greater than or equal to 1 nm and less than or equal to 200 nm, Furthermore, a thickness of a region of the second semiconductor layer that contacts the top surface of the fourth conductive layer is greater than or equal to 1 nm and less than or equal to 200 nm.

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