Method for testing concentration and mobility of longitudinally distributed carriers of semiconductor material
By adding the voltage source and calculating the depletion zone width in the Vanderbilt Fahall test system, the problem of low accuracy and efficiency when testing the longitudinal distribution carrier concentration and mobility of semiconductor materials in the prior art is solved, and high-precision and high-efficiency testing is achieved, reducing costs and environmental pollution.
Patent Information
- Application Number
- CN202510025526.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-22
- Filing Date
- 2025-01-08
- Publication Date
- 2025-04-22
AI Technical Summary
When testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials, the prior art uses wet corrosion technology and Vanderbilt Fahall testing technology, which has problems such as inaccurate corrosion rate and uneven corrosion depth, resulting in poor test accuracy and low efficiency.
By adding a voltage source to the original Vanderbilt Fahall test system, and calculating the depletion zone width under different reverse bias voltages through the Schottky junction reverse bias depletion zone calculation formula, a series of reverse bias voltage values of different depletion zone widths are designed, and the Vanderbilt Fahall test is performed to obtain the carrier concentration and mobility values.
The accuracy and efficiency of testing the longitudinal distribution carrier concentration and mobility of semiconductor materials is improved, which simplifies the sample preparation process, reduces costs, reduces environmental pollution, and improves the test accuracy to nm level resolution.
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Figure CN119861112A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor material testing, in particular to a method for testing the longitudinal distribution carrier concentration and mobility of semiconductor materials. Background Art
[0002] Semiconductor materials are electronic materials that have semiconductor properties and conductivity between conductors and insulators, and can be used to make semiconductor devices and integrated circuits. Semiconductor materials are usually crystals, and the atoms that make up the materials are arranged periodically in space. The energy levels of a single atom are expanded into energy bands in semiconductor materials, including valence bands and conduction bands. There are many ways to classify semiconductor materials. For example, based on the band gap, which is the energy difference between the valence band and the conduction band, there are wide-bandgap and narrow-bandgap semiconductors. Based on the relative positions of the maximum and minimum electron energy in the energy band, there are direct-bandgap and indirect-bandgap semiconductors.
[0003] At present, wet etching technology and Van der Pauw Hall test technology are generally used to test the carrier concentration and mobility of the longitudinal distribution of semiconductor materials. Traditional wet etching technology and Van der Pauw Hall test technology are destructive methods, which will result in inaccurate corrosion rate and uneven corrosion depth, and it is impossible to perform in-situ corrosion on the test machine. This will lead to poor accuracy and low test efficiency in testing the carrier concentration and mobility of the longitudinal distribution of semiconductor materials. Summary of the invention
[0004] The object of the present invention is to provide a method for testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials to solve the problems raised in the above background technology.
[0005] To achieve the above object, the present invention provides the following technical solutions:
[0006] A method for testing the longitudinal distribution of carrier concentration and mobility of a semiconductor material comprises the following steps:
[0007] S1: Prepare a square sample from the wafer to be tested;
[0008] S2: Prepare four contact electrodes at the four corners of the sample;
[0009] S3: Fix the sample prepared in S2 on the Hall test plate;
[0010] S4: Add a voltage source capable of outputting voltage to the original Vanderbilt Hall test system;
[0011] S5: short-circuit the output negative terminal of the added voltage source and the output negative terminal of the current source of the original Vanderbilt Hall test system;
[0012] S6: adding an electrode to the test fixture in the original Vanderbilt Hall test system, wherein the electrode is connected to the positive output terminal of the voltage source;
[0013] S7: cutting out an electrode plate, and connecting the electrode plate to the electrode added to the test fixture in S6 through a wire;
[0014] S8: placing the electrode plate in S7 onto the sample to be tested;
[0015] S9: Set the voltage source in S4 to no output, perform the Van der Pauw Hall test under the original conditions, and obtain the carrier concentration value of the material;
[0016] S10: according to the carrier concentration value in S9, the depletion region width under different reverse bias voltages is calculated by using the Schottky junction reverse bias depletion region calculation formula, the reverse bias voltage corresponding to different depletion region widths is calculated according to the Schottky junction reverse bias depletion region calculation formula, and a series of reverse bias voltage values with different depletion region widths are designed;
[0017] S11: according to the reverse bias voltage value calculated in S10, the voltage output of the voltage source in S4 is set in turn according to the reverse bias voltage value calculated, and a Van der Pauw Hall test is performed to obtain carrier concentration values in turn;
[0018] S12: The different carrier concentration values obtained in S11 are matched one by one with the reverse bias voltages of different depletion region widths calculated in S10 to obtain the carrier concentration and mobility values of the longitudinal distribution of the sample.
[0019] As a further solution of the present invention: the sample is prepared by mechanical or laser scribing.
[0020] As a further solution of the present invention: the side length of the sample is 5mm-10mm.
[0021] As a further solution of the present invention: the contact electrode is a circular ohmic contact electrode with a diameter of 0.5 mm-1 mm.
[0022] As a further solution of the present invention: the contact electrode is a square ohmic contact electrode with a side length of 0.5 mm-1 mm.
[0023] As a further solution of the present invention: the electrode plate is a cube with a side length of 8 mm and a thickness of 1 mm.
[0024] As a further solution of the present invention: the electrode plate is made of gold.
[0025] As a further solution of the present invention: placing the electrode plate in S7 on the sample to be tested includes:
[0026] The electrode plate in S7 is placed on the sample to be tested by crimping.
[0027] As a further solution of the present invention: the electrode plate and the four contact electrodes are separated from each other and have no contact.
[0028] As a further solution of the present invention: the calculation formula of the reverse bias depletion region of the Schottky junction is:
[0029]
[0030] Among them, X n is the depletion region width, V bi is the built-in potential, N d is the net donor concentration in the N region, ε s is the dielectric constant, V R is the reverse bias voltage.
[0031] Compared with the prior art, the present invention has the following beneficial effects:
[0032] 1. Simplified steps: No need to prepare samples using conventional semiconductor device process methods; traditional wet etching methods require multiple steps such as photolithography, development, etching, and metal evaporation, while the method of the present invention does not require the above steps;
[0033] 2. Convenient processing and low cost: it can be completed by manual operation; the traditional wet etching method requires multiple photolithography machines, etching pools, step meters, evaporation tables and other special equipment, but the method of the present invention does not require the above equipment, which greatly saves costs;
[0034] 3. Improved production efficiency: The traditional wet layer-by-layer etching method has a long test cycle for a single sample; the traditional wet layer-by-layer etching method requires a series of operating steps such as preparing etching solution, calibrating etching rate, timing etching, calibrating thickness, etc. Generally, a single etching operation takes 1-2 hours. If it is necessary to test the carrier concentration and mobility longitudinal distribution of dozens of different positions, the total time for wet etching may reach 1-2 weeks; the technology of the present invention can omit the above operating steps, which greatly improves efficiency;
[0035] 4. Improved test reliability: No need for etching, no need to control the etching rate and etching time; the traditional wet layer-by-layer etching method is a destructive method. If the etching steps are wrong, it will greatly affect the test results. The present invention uses a high-precision voltage source to control the width of the depletion region, which is non-destructive to the sample and can easily repeat various test conditions, thereby improving the test reliability;
[0036] 5. Reduced environmental pollution: In the present invention, no wet etching operation is required, no etching operation is required, and the use of chemicals is avoided, thereby avoiding environmental pollution;
[0037] 6. Improve test accuracy: The width of the depletion region is controlled by reverse voltage, and the depletion region width control can achieve nm-level resolution. It is difficult to accurately control the wet etching rate to nm-level resolution. In the present invention, a high-precision voltage source is used to achieve nm-level resolution. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 Schematic diagram of the structure of S1 in the method for testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials.
[0039] Figure 2 Schematic diagram of the structure of S2 in the method for testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials.
[0040] Figure 3 A schematic diagram of the structure of S3 in the method for testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials.
[0041] Figure 4 A schematic diagram of the structure of S5 in the method for testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials.
[0042] Figure 5 Schematic diagram of the structure of S6 in the method for testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials.
[0043] Figure 6 Schematic diagram of the structure of S8 in the method for testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials. DETAILED DESCRIPTION
[0044] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.
[0045] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
[0046] In addition, in order to better illustrate the present application, numerous specific details are provided in the specific embodiments below. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, and elements well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.
[0047] Embodiment 1
[0048] A method for testing the longitudinal distribution of carrier concentration and mobility of a semiconductor material comprises the following steps:
[0049] S1: Prepare a square sample with a side length of 5mm-10mm from the wafer to be tested by mechanical or laser scribing; refer to Figure 1 ;
[0050] S2: Prepare four circular ohmic contact electrodes with a diameter of 0.5 mm to 1 mm or four square ohmic contact electrodes with a side length of 0.5 mm to 1 mm at the four corners of the sample; Figure 2 ;
[0051] S3: Fix the sample prepared in S2 on the Hall test board, refer to Figure 3 ;
[0052] S4: Add a voltage source capable of outputting voltage to the original Vanderbilt Hall test system;
[0053] S5: short-circuit the negative output terminal of the added voltage source and the negative output terminal of the current source of the original Vanderbilt Hall test system; Figure 4 ;
[0054] S6: Add an electrode to the test fixture in the original Vanderbilt Hall test system, and connect the electrode to the positive output terminal of the voltage source; refer to Figure 5 ;
[0055] S7: Cut out a square gold electrode plate with a side length of 8 mm and a thickness of 1 mm, and connect the electrode plate to the electrode added to the test fixture in S6 through a wire;
[0056] S8: Place the square electrode plate in S7 onto the sample to be tested by crimping, and avoid the electrode plate contacting the four contact electrodes prepared in S2 on the sample; Figure 6 ;
[0057] S9: Set the voltage source in S4 to no output, perform the Van der Pauw Hall test under the original conditions, and obtain the resistivity, mobility and carrier concentration values of the material; refer to Table 1;
[0058] Resistivity Mobility Carrier concentration 6.94E-0.3 1500 6.00E+17
[0059] Table 1
[0060] The resistivity, mobility, and carrier concentration values in Table 1 are the test results given after passing the Van der Pauw Hall test.
[0061] S10: according to the carrier concentration value in S9, the depletion region width under different reverse bias voltages is calculated by using the Schottky junction reverse bias depletion region calculation formula, the reverse bias voltage corresponding to different depletion region widths is calculated according to the Schottky junction reverse bias depletion region calculation formula, and a series of reverse bias voltage values with different depletion region widths are designed;
[0062] The formula for calculating the reverse bias depletion region of the Schottky junction is:
[0063]
[0064] Among them, X n is the depletion region width, V bi is the built-in potential, N d is the net donor concentration in the N region, ε s is the dielectric constant, V R is the reverse bias voltage. Refer to Table 2;
[0065]
[0066]
[0067] Table 2
[0068] S11: according to the reverse bias voltage value calculated in S10, the voltage output of the voltage source in S4 is set in turn according to the reverse bias voltage value calculated, and a Van der Pauw Hall test is performed to obtain carrier concentration values in turn;
[0069] S12: By making a one-to-one correspondence between the different carrier concentration values obtained in S11 and the reverse bias voltages of different depletion region widths calculated in S10, the carrier concentration and mobility values of the longitudinal distribution of this sample can be obtained; refer to Table 3.
[0070] Voltage Depletion region width Resistivity Mobility Carrier concentration 0 0 6.94E-03 1500 6.00E+17 0.1 1nm 7.32E+14 1550 5.50E+00 0.3 2nm 7.80E-03 1600 5.00E+17 0.6 3nm 8.41E-03 1650 4.50E+17 0.9 4nm 9.18E-03 1700 4.00E+17
[0071] Table 3
[0072] The present invention has a simplified structure and does not require sample preparation using conventional semiconductor device process methods. It is easy to process and can be completed by manual operation, thereby improving production efficiency. The test cycle of a single sample using the traditional wet layer-by-layer etching method can reach about one week, and the test reliability rate is improved. For a single etching, there is no need to strictly control the etching rate and etching time, and environmental pollution is reduced. A single etching greatly reduces the amount of chemicals used, thereby improving test accuracy. The depletion region width is controlled by reverse voltage, and the depletion region width control can achieve nm level resolution.
[0073] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive in all respects, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention.
[0074] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A method for testing the longitudinal distribution of carrier concentration and mobility of semiconductor materials, characterized in that: The following steps are involved: S1: Prepare a square sample from the wafer to be tested; S2: Prepare four contact electrodes at the four corners of the sample; S3: Fix the sample prepared in S2 on the Hall test plate; S4: Add a voltage source capable of outputting voltage to the original Vanderbilt Hall test system; S5: short-circuit the output negative terminal of the added voltage source and the output negative terminal of the current source of the original Vanderbilt Hall test system; S6: adding an electrode to the test fixture in the original Vanderbilt Hall test system, wherein the electrode is connected to the positive output terminal of the voltage source; S7: cutting out an electrode plate, and connecting the electrode plate to the electrode added to the test fixture in S6 through a wire; S8: placing the electrode plate in S7 onto the sample to be tested; S9: Set the voltage source in S4 to no output, perform the Van der Pauw Hall test under the original conditions, and obtain the carrier concentration value of the material; S10: according to the carrier concentration value in S9, the depletion region width under different reverse bias voltages is calculated by using the Schottky junction reverse bias depletion region calculation formula, the reverse bias voltage corresponding to different depletion region widths is calculated according to the Schottky junction reverse bias depletion region calculation formula, and a series of reverse bias voltage values with different depletion region widths are designed; S11: according to the reverse bias voltage value calculated in S10, the voltage output of the voltage source in S4 is set in turn according to the reverse bias voltage value calculated, and a Van der Pauw Hall test is performed to obtain carrier concentration values in turn; S12: The different carrier concentration values obtained in S11 are matched one by one with the reverse bias voltages of different depletion region widths calculated in S10 to obtain the carrier concentration and mobility values of the longitudinal distribution of the sample.
2. The method according to claim 1, characterized in that The sample is prepared by mechanical or laser scribing.
3. The method according to claim 1, characterized in that The side length of the sample is 5mm-10mm.
4. The method according to claim 1, characterized in that: The contact electrode is a circular ohmic contact electrode with a diameter of 0.5 mm-1 mm.
5. The method according to claim 1, characterized in that The contact electrode is a square ohmic contact electrode with a side length of 0.5 mm-1 mm.
6. The method according to claim 1, characterized in that The electrode plate is a cube with a side length of 8 mm and a thickness of 1 mm.
7. The method according to claim 1, characterized in that The electrode plate is made of gold.
8. The method according to claim 1, characterized in that Placing the electrode plate in S7 on the sample to be tested includes: The electrode plate in S7 is placed on the sample to be tested by crimping.
9. The method according to claim 1, characterized in that: The electrode plate and the four contact electrodes are separated from each other and have no contact.
10. The method according to claim 1, characterized in that The calculation formula for the reverse bias depletion region of the Schottky junction is: Among them, X n is the depletion region width, V bi is the built-in potential, N d is the net donor concentration in the N region, ε s is the dielectric constant, V R is the reverse bias voltage.