Power vector analyzer

Abstract

A power vector analyzer for analyzing power from a device under test (DUT) includes: one or more channels for measuring a reference voltage signal from a power line connected to the DUT; one or more channels for measuring a reference current signal from the power line; a user interface comprising a display and one or more controls; and a quadrature synchronization detector (QSD) for each phase of the measured apparent power, the QSD configured to use a reference voltage signal from the one or more channels and a reference current signal from the one or more channels to determine an apparent power for each phase of power measured by the DUT, and displaying the apparent power for each phase on the display.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS The present disclosure is a non-provisional application of U.S. Provisional Application No. 63 / 592,060, filed on October 20, 2023, and entitled “ELECTRIC MOTOR VECTOR ANALYZER,” and claims the benefit of the U.S. Provisional Application, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a power vector analyzer, and more particularly to a power vector analyzer using a synchronous complex detector that uses a complex zero vector to calibrate to a reference operating point of a motor. Background Art

[0003] The global electric vehicle (EV) motor market is valued at $8.5 billion in 2022 and is forecasted to be worth around $65.95 billion by 2032, expanding at a CAGR of 21% from 2023 to 2032 according to Precedence Research. Therefore, there is a need to facilitate this growth through improved technologies.

[0004] The electric vehicle (EV) market is growing rapidly as governments work to phase out gasoline-powered vehicles and replace them with electric vehicles. Each EV typically has one or two three-phase electric motors, which can be about 500HP combined. For example, a Tesla motor operates at 200kW with variable three-phase pulse width modulated sine wave power supplied by a DC to AC inverter. The frequency of the inverter can be varied in the range of 20Hz to 300Hz. The motor drive voltage is variable, about 750V pp , and the current can be about 27A pp .

[0005] The ability to analyze power signals (such as those in electric motors) to determine the phase and magnitude of the power signal relative to a reference signal is useful. U.S. Patent 6,525,522, "System for Determining the Phase and Magnitude of an Incident Signal Relative to a Cyclical Reference Signal," which is incorporated herein by reference in its entirety, describes an example of a system having this capability.

[0006] There are examples of motor analysis tools in the market. One such example of prior art for motor analysis is the Fluke Model 438-2 High Quality Motor Analyzer. Some examples of three-phase power analyzers that can display power on a vector graph include the Fluke 437II Power High Quality and Energy Analyzer, the Hioki PW6001 Power Analyzer, and the Yokogawa WT3000E Precision Power Analyzer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An embodiment of a user interface on a power vector analyzer (PVA) displaying static power for three-phase power is shown.

[0008] Figure 2 An embodiment of a user interface on the PVA during nulling of static power is shown.

[0009] Figure 3 An embodiment of a user interface on a power vector analyzer displaying zeroed static power is shown.

[0010] Figure 4 An embodiment of a user interface on a power vector analyzer displaying measured power transients relative to zeroed quiescent power is shown.

[0011] Figure 5 An embodiment of a display showing measured power transients including limit circles relative to zeroed quiescent power is shown.

[0012] Figure 6 An embodiment of a user interface on a power vector analyzer showing different possible detector configurations is shown.

[0013] Figure 7 An embodiment of a power vector analyzer with a single-phase motor having a load and a quadrature synchronous detector (QSD) for one phase of power is shown.

[0014] Figure 8 A representation of the power vector relationship is shown.

[0015] Fig. 9 An example of a block diagram using three QSDs for three-phase power is shown.

[0016] Fig.10 An embodiment of a QSD generating a zero vector is shown.

[0017] Fig.11 A more focused flow diagram of the QSD is shown.

[0018] Fig.12 A block diagram of the rotation block is shown.

[0019] Fig.13 An embodiment of a scaling block diagram is shown.

[0020] Fig.14 An embodiment of a power vector analyzer architecture is shown. DETAILED DESCRIPTION

[0021] Embodiments herein relate to a power vector analyzer (PVA) for analyzing power signals under load, such as in a motor or even from a power grid. The PVA of an embodiment can provide additional capabilities to an existing motor or power analyzer. The embodiments herein provide an improved user interface and transparent zero vector calculations. The zero vector determination used in the embodiments provides a complex power measurement result, which the PVA can display as a trace of real-time changes in the complex load impedance of a motor or other power consuming system, represented as a power vector. The ability to analyze the starting characteristics of the power signal and the behavior of a power consuming entity, such as a motor or large equipment as an example, is valuable.

[0022] The PVA of an embodiment may display a static power signal prior to any operation of a device under test, such as a motor or other power device. Figure 1 A user interface 10 is shown with controls 12 on the left and a display 14 on the right. Points such as 16 represent "reference" apparent power signals for each of the three phases on a polar grid, with each phase being 120° out of phase with the other two phases. Controls 12 allow the user to set the detector configuration, start and stop the nulling process, clear previously determined zeroed quiescent powers, and make selections regarding the graph. The term "reference apparent powers" applies to the apparent powers displayed before the quiescent powers are removed to distinguish them from the apparent powers measured after the nulling process.

[0023] Figure 2 An embodiment of a user interface during the zero value calculation process discussed in detail below is shown. The zeroing process essentially removes static power from the apparent power measurement, allowing for more accurate representation and measurement of transient power fluctuations. Lines such as 18 between each point such as 16 and the center of the graph 20 represent the process of determining the zero vector that the system adds to the reference apparent power to remove static power from future measurements. Figure 3 The resulting display is shown in which all three points have moved to the center 20, indicating that the static power has been zeroed and the apparent power appears to be zero for all three phases.

[0024] Figure 4 The transient apparent power fluctuations about the zero center are shown, where transients are shown for each phase of the power, such as 22. One aspect of the embodiment allows the user to set a limit mask, which is determined by Figure 4 and 5 denoted by circle 24 shown in . The limit mask sets limits on the apparent power measurement results regarding how far "off" or above zero center a transient may become before causing a reaction in the PVA. In one embodiment, when the power line is connected to a powered device (such as a motor under load), when the apparent power transient signal exceeds a limit mask (such as 28), this may cause the device under test (DUT) to fail the test. In other embodiments, the limit mask may indicate conditions on the power line that require closer monitoring or the performance of some action. The user interface presents a message such as 26 "Transient Detected".

[0025] As mentioned above, the PVA can operate on three-phase power, or it can operate on one-phase power. Figure 6 Four different variations in the configuration of user interface controls 30 for controlling the detectors for sending the measurement results of the power signal to the PVA are shown. The leftmost shows a detector configuration 32 for one phase of power, where one detector is for voltage (1V) and one detector is for current (1I), so the setting is 1V1I. Each detector will be connected to one channel on the PVA. The second from the left 34 shows a setting of two voltage detectors (2V) and two current detectors (2I) for one phase of power, but there are two conductive wires as in 220V power. The second from the right 36 shows three-phase power (3P), with two voltage detectors (2V) and two current detectors (2I). The last panel at 38 shows the detector controls set to three-phase power, where they are in a "Δ (delta)" configuration with three voltage detectors and three current detectors. The last setting not shown as selected here includes a configuration for three-phase power in a "Y (wye)" configuration with three voltage detectors and three current detectors.

[0026] Figure 7 A diagram of a motor 40 connected to a load 42 and to a power 44 is shown. In this embodiment, the PVA includes a "zero-valued" quadrature synchronous detector (QSD) at 46. How the QSD of an embodiment determines the zero vector to zero the static power will be discussed in further detail below. The QSD outputs real power P and reactive power Q. Figure 8 It shows the relationship between P, Q and Figure 1-5 The relationship between the apparent power S shown on the user interface in .

[0027] With this configuration, a method for testing a motor may follow this process. The user connects one or more voltage probes such as 48 and one or more current probes such as 49 to the power line. The user then selects the previously Figure 1-3 Click the "Null" button shown in to start the nulling process.

[0028] The zeroing process can occur using one of two alternatives. In one embodiment, the user connects a "golden" reference device (such as a motor) to the PVA, meaning a device that meets all specifications and has its responses documented. The user will then press a "zero" button for each phase being measured. The user interface can also include a master "zero" to complete all three phases simultaneously. Zeroing takes very little time and moves the phase traces discussed above to the same position as the phase traces discussed above. Figure 2 and 3 The center of the graphical display is shown in . All further displays of the complex power are relative to this reference.

[0029] Since the PVA of the embodiments can operate in both one-phase power and three-phase power, this discussion refers to these options as "measured phase" or "each phase measured", where the measured phase includes one phase for one-phase power or each of the three phases for three-phase power.

[0030] In another embodiment, the user sets the DUT device (such as a motor) to a reference load value, frequency, and voltage. The PVA uses these to generate a zero vector and zero the static power. All further displays of complex power are relative to this reference. Other embodiments may use a combination, such as a golden motor combined with the DUT.

[0031] Discussion herein will refer to the voltage and current signals used by the QSD to zero the quiescent power as the “reference voltage” and “reference current.” Once the zeroing process has been completed and the PVA is monitoring the power signal(s), discussion will continue to refer to the monitored voltage and current as the reference voltage and reference current for simplicity.

[0032] Once the zeroing process has been completed, the PVA can test different loads on the DUT, which means that it will be tested at various loads, resulting in different voltage and frequency settings. For the best implementation, the channels of the PVA connected to (one or more) voltage and current signals will use analog-to-digital converters (ADCs). For the ideal implementation, all A / D samples will be streamed to the display. However, some test and measurement instruments on which the PVA can be implemented may not have a sampling rate high enough to support streaming. The instrument will operate with a long enough record length so that only small gaps in the processing stream do not go to the display.

[0033] One aspect of the embodiment is to allow the user to set a limit mask (such as previously in Figure 5As discussed above, the user can define limits beyond which the PVA will flag any transient apparent power fluctuations that exceed the limit mask. The user can use the limit mask to set thresholds, such as the number of times a transient in a phase exceeds the limit mask, or the length of time a transient exceeds the limit mask as a pass / fail trigger, or a level for notification. Return to Figure 5 , the display posts a notification that a transient has been detected 26. To aid in the setting and monitoring of limit masks, the PVA may have a rotation knob. This allows the user to rotate the grid and data to a 3-phase view or manually adjust to optimize the data layout for each phase leg of the motor. This allows for easy drawing of masks or viewing. It also allows the data from all three legs to be displayed with the correct global phase relative to each other.

[0034] During operation in the test and analysis modes, the PVA can perform a double-view power measurement and display the readings. Any glitches or deviation transients will be captured on the display and presented to the limit test mask. This provides the advantage of continuous monitoring and debugging of problems with the DUT.

[0035] The discussion now moves to Figure 7 4 shows a QSD with a zero value for a single-phase power device under load, such as a motor with a single-phase power 44. The QSD 46 with a zero value receives input from a high voltage detector 48 as a REF signal and receives input from a current detector 49 as an I signal. The QSD outputs active power P and reactive power Q for determining apparent power. Figure 8 The relationship between the active power in Watts, the reactive power in VAR (volt-amperes reactive) and the apparent power S in VA (volt-amperes) is shown.

[0036] Fig. 9 A configuration for a three-phase power device under load is shown. Each phase 44A-44C of power has a corresponding QSD 46A-46C. The (one or more) QSDs measure complex power. Each QSD has a high voltage detector 48A-C and a current detector 49A-C.

[0037] Fig.10 Shown is a detailed depiction of one QSD 46. This will be replicated for each of the phases measured by PVA as discussed above. Fig.10The layout is shown, and the discussion here focuses on the zeroing process. The QSD receives a voltage signal, also referred to as a reference voltage, at the top, and a current signal, also referred to as a reference current, at the bottom. The voltage signal undergoes demodulation and downsampling at 50, and the current signal undergoes demodulation and downsampling at 52. The application of the filter causes transients at the beginning and end of the acquired waveform, so the demodulated and downsampled voltage signal is trimmed at 54, and the current signal is trimmed at 56 to remove transients. The reference voltage signal is represented by the cosine of the reference voltage signal. The Hilbert filter 58 uses the cosine of the voltage signal and rotates or shifts it by 90 degrees in phase. This changes the phase of the voltage signal, which is shifted by 90 degrees for each frequency component at "V90", here referred to as a shifted voltage signal. The cosine of the voltage signal Vr goes to the mixer 60, where it will be mixed with the cosine of the zero angle θ from the amplifier 62. The zero angle θ has an initial value between -π and π. The zero angle and zero gain come from the expander scanning module 64. The sine of the zero angle 66 is mixed at the mixer 68 with the shifted voltage signal.

[0038] The outputs of mixers 60 and 68 are summed at 70 to produce Vq. Vq then goes to mixer 72 and is mixed with the inverse of the zero gain from inverter 74 to become a zero vector 97. The zero vector is added to the demodulated and downsampled current signal at summing node 76. The result of this summation is then mixed with the shifted voltage signal at mixer 78 and with the cosine of the voltage signal at mixer 80. The outputs of mixers 78 and 80 are low pass filtered at 82 and 84, respectively. The low pass filter is based on frequency f and is expanded by multiplying by 2 at 86 and 88 to produce Q reactive power and P active power. The mean of Q is returned to the zero value expander scanning block 64 at 90 and the mean of P at 92, and the process is iterated until the values ​​of P and Q are equal to 0. This results in an apparent power display as shown Figure 3 centered as shown in . The gain value and phase value that bring those values ​​to zero is the final zero vector. Adding the zero vector to the incoming voltage and current signals cancels those out to remove static power. The zero marker at 94 determines when the zeroing process occurs. If the user presses the "zero" button on the user interface, the zeroing process begins. When the zeroing process has reached the zero value of Q and P, the zero marker resets back to 0.

[0039] Fig.10 The process shown in is repeated for the other phases of power as needed, so that the three phases of power are zeroed simultaneously. The above process occurs because the user selects the "Zero" button on the user interface, which sets the zero mark to 1 or turns on. After the process is completed, the zero mark is reset to 0. The QSD continues to perform the zeroing process unless it is turned off. The apparent power measurement after the zeroing process is completed does not include the static power that has been removed by the zeroing process.

[0040] A menu option allows the user to turn off the nulling operation at any time in order to observe the actual total power. Switch 96 may allow control over whether the nulling process occurs. Fig.11 A more focused version of the QSD is shown for making those measurements when the nulling process is off (meaning switch 96 is open). It should be noted that the process is as in Fig.10 but is simplified to make it easier to understand the double vision in power measurement without the nulling process. Fig.10 , Fig.11 An incoming power signal is shown with a reference voltage signal component of the voltage across the load in volts RMS (root mean square) and a reference current in amperes RMS. The figure labels the phase angle as φ. The term ω is the rate of change of the phase of the waveform and is equal to 2πf, where f is frequency and t is time. The ω term has a range between 20 and 2000.

[0041] The process obtains a representation of the reference voltage signal V including the cosine of (ωt) before applying the Hilbert filter at 58 at 77. Discussions herein will refer to this representation as the cosine voltage function. Similarly, the cosine of (ωt+φ) is used as a representation of the reference current signal A at 79, referred to herein as the cosine current function, where the cosine current function is shifted in phase relative to the reference voltage. The cosine current function and the cosine voltage function are multiplied at 80 to produce PP, the active power discussed below. The cosine voltage signal is shifted 90 degrees by the Hilbert filter, resulting in the voltage sine function Vsin(ωt). The voltage sine function is multiplied by the cosine current function at 78 to produce signal QQ, the reactive power also discussed below. These two signals are low pass filtered and then expanded by a factor of 2, as described with respect to Fig.10 The scaling factor of 2 is explained below to produce reactive power as VA sin(φ) and active power as VA cos(φ). These are then used to find the apparent power of the power line, which is used for display.

[0042] The signals PP and QQ are determined as follows: QQ=A·cos(ωt+φ).V.sin(ωt)PP=A.cos(ωt+φ).V.cos(ωt) Rearranging the terms and applying the trigonometric identity cos(a+b)=cos(a)cos(b)–sin(a)sin(b) to both QQ and PP yields: QQ=VA.cos(ωt+φ)cos(φ)sin(ωt)–VA, sin(ωt)sin(φ)sin(ωt) PP=VA.cos(ωt)cos(ωt)cos(φ)–VA.sin(φ)sin(ωt)cos(ωt) Applying the trigonometric identities where cos(a)sin(a)=sin(2a) / 2, sin(a)sin(a)=cos(2a) / 2–1 / 2, and cos(a)cos(a)=cos(2a) / 2+1 / 2 and then rearranging the terms yields: QQ=VA / 2.sin(2ωt)cos(φ)+VA / 2·sin(φ)–VA / 2.cos(2ωt)sin(φ) PP=VA / 2.cos(2ωt)cos(φ)+VA / 2.cos(φ)–VA / 2.sin(2ωt)sin(φ).

[0043] A low pass filter is then applied to QQ and PP to remove the higher frequency terms, leaving QQ = VA / 2.sin(φ) and PP = VA / 2.cos(φ). Applying the scaling factor of 2 shown in the figure yields Q = VAsin(φ) and P = VAcos(φ). These power measurements are then used to find the apparent power S of the power line at that point in time.

[0044] Fig.12 An embodiment of a rotation block 98 is shown. The rotation block is concerned with rotating the complex output of the QSD in a normalized XY plane, where P is defined with respect to X-axis position and Q is defined with respect to Y-axis position. The normal P and Q outputs of the QSD on each of the three legs of a 3-phase motor will appear on a single polar grid plot. Each individual leg will have a standard rotation of 0 of the polar grid view. This will lose the global phase difference between each leg of the motor. Fig.12 , the cosine of the phase of the power signals P and Q is multiplied with the P signal at 100 and then summed with the sine of the phase angle 102 at summing node 104. Similarly, the cosine of the phase angle is multiplied with the Q signal at 106 and then summed with the sine of the phase angle 108 at summing node 110.

[0045] In one embodiment, the first phase of the motor can be displayed on the display with a 0 degree rotation. The second phase can be displayed with a 120 degree rotation and the third phase can be displayed with a 240 degree rotation. Figure 1The right image in is used as an example, where each point is offset by 120 degrees from each other. In an alternative embodiment, additional global phase measurements between the three voltages can be made and used to set the rotation block phase angle. Another useful display embodiment can be: display all three phases overlaid with 0 degrees rotation. Direct visual comparison of the power of all three motor feet can be made in the overlay view. In addition, this will potentially allow only one limit mask to be created for all three feet. When creating the limit mask, it can be useful to rotate the polar coordinate grid to an angle that makes it easier to draw the limit mask. It may be optimal that once the limit mask is drawn, it will rotate with the display.

[0046] Fig.13 is an embodiment of an apparent power block 114 for calculating apparent power and power factor angle φ. The purpose of the apparent power block 114 is to output P in Watts, Q in V Ar, S in VA, and φ in degrees.

[0047] A possible advantage of doing this from the output of the QSD rather than direct measurements on the voltage and current waveforms is improved noise reduction and measurement resolution due to the averaging effect of the QSD. A second advantage may be that the measurement is tracked in time position in the acquired data stream since it changes based on load, frequency, and voltage. The measurements may be labeled with time and the markers on the XY display with the polar grid may be tracked along with the cursors on the YT view of the three input voltage waveforms and the three input current waveforms.

[0048] Fig.14 An embodiment of a block diagram of a PVA configured with a DUT motor 120 after the system has been zeroed with a golden reference motor is shown. Alternatively, the system may be zeroed with a reference frequency, voltage, and load settings using the DUT motor. In this embodiment, the only hardware required for the architecture is three voltage probes, three current probes, and an instrument such as an oscilloscope or digitizer 130. Also, the user provides a variable load 122 and the DUT motor 120. An additional aspect of the present invention is a software application 124 that may be run on an instrument 130, such as an oscilloscope or digitizer system. One or more processors on the instrument 130 may be configured to execute code that causes the one or more processors to run the software application 124. The QSD discussed above may be implemented in a processor or in a logic circuit.

[0049] The architecture includes three main QSD processing paths, one for each leg of the three-phase power device. Note that a single-phase motor can be analyzed by enabling only one leg of the signal processing path. The discussion here uses the first QSD path for discussion with the understanding that the discussion applies to each leg. The current probe 128 is connected to one channel of the instrument and the high voltage probe 126 is connected to another channel of the instrument. Each channel has one or more analog-to-digital converters (ADCs), such as 132 and 134.

[0050] As mentioned above, depending on the capabilities of the instrument, samples from the ADC may be continuously streamed or used to form long records (LR), such as 136 and 138. Although these are named LR here, they may also be continuously streamed. These represent a continuous stream of samples into the signal processing path, with all output samples going to an infinite persistence display. Persistence may also be set to decay. In the case where the instrument 130 does not have a high enough streaming sample rate to support the highest frequency to be sampled in the motor, this continuous stream, sometimes referred to as a rolling mode block, is optional. This will include distortion harmonics. If the rolling mode sample rate is not high enough, then the rolling mode block is not used, and a relatively long record length waveform will be used, making the dead time between acquisitions relatively small, so that a large percentage of all samples reach the display.

[0051] The previously discussed QSD 46 operates on voltage and current signals in sample form. Depending on the setting of the zero mark, the QSD can find the zeroed static power or make a complex power measurement. The rotation block 98 and the apparent power block 114 are applied to the signal. The user then turns limit testing on or off at 140 and can draw a limit mask at 142 as selected. All results are then displayed, either as a single display 144 or as a multi-layer display showing data from all three legs at 146.

[0052] In operation, the user will connect the probe to the instrument and power device, such as a motor. The user will then set the instrument acquisition to capture all six channels with appropriate gain settings. The user will then start the PVA software application and assign the signal to the instrument channel. First, the instrument must perform the zeroing process. The user will set the desired frequency, reference load and voltage. If the zeroing process uses a golden reference motor, once the zeroing is achieved, the user will need to switch the probe to the DUT power device. The zeroing feature can also be used for situations such as monitoring three-phase power on the power grid. The zeroing feature can be used to zero out the nominal static power so that the display on the PVA polar coordinate grid will only show deviations away from the nominal power. This will be useful for capturing power transients such as lightning strikes, or load switching changes, or other types of transients that may occur. At this point, the user will continuously observe complex power data, measured power vectors P, Q and S, and transient behavior with real-time load changes as the motor condition changes. This allows the user to set up a mask for pass / fail testing or other triggered events.

[0053] The user interface may include play / pause / stop playback controls with fast forward, the entire time record may be visually analyzed in short periods of time, and all samples over the entire interval may be viewed in one view on the display giving insights not seen with previous power analyzers.

[0054] It should be noted that embodiments include the sum of multiple elements. The combination of these elements creates new and very useful PVAs. Some of these architectural elements of embodiments of the present invention may include an inverter 132, such as Fig.14 This drives a power device that is part of a DUT or lab setup for testing. It is configured to deliver three-phase pulse width modulated sine wave voltage and current. The frequency can be varied within a range and the voltage can be varied to achieve optimal operation of the motor for torque and power.

[0055] As part of the testing of the power device, the user will employ a variable load. The customer test automation software 124 will control the load settings. The power device is coupled to the shaft of the variable load. The customer provides customer test automation software for testing the power device and controlling the PVA settings during the desired process.

[0056] In this way, an embodiment provides a PVA for analyzing high-power electrical equipment (such as one-phase and three-phase motors). The PVA provides real-time continuous complex power curves for all three motor phases. It can provide curves representing the apparent power, reactive power, and active power for each motor phase. The PVA also has a unique zeroing feature similar to calibrating a 1-port VNA calibrated relative to a reference power setting. The reference power setting can come from a reference motor or a DUT set to a reference voltage, load, and frequency, and then a zero value calibration is completed. Once zeroed, the PVA can continuously monitor and capture all samples over time to an infinite persistent display. It can create power graphs over the entire range of load, frequency, and voltage. It also captures glitches and other weird behaviors. Limit tests can mark glitches and transients. Using an instrument platform for the PVA means that other measurement waveform analysis tools of the instrument can also be used during the test of the motor, thereby providing additional advantages to the user.

[0057] Aspects of the present disclosure may be operated on specially created hardware, on firmware, digital signal processors, or on a specially programmed general-purpose computer including a processor that operates according to programmed instructions. The term controller or processor as used herein is intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and dedicated hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions executed by one or more computers (including monitoring modules) or other devices, such as one or more program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types when executed by processors in computers or other devices. Computer-executable instructions may be stored on non-transient computer-readable media, such as hard disks, optical disks, removable storage media, solid-state memory, random access memory (RAM), etc. As will be appreciated by those skilled in the art, the functionality of program modules may be combined or distributed as desired in various aspects. In addition, functionality may be embodied in whole or in part in firmware or hardware equivalents (such as integrated circuits, FPGAs, etc.). Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are contemplated within the scope of the computer-executable instructions and computer-usable data described herein.

[0058] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by one or more non-transient computer-readable media or stored on one or more non-transient computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as computer program products. As discussed herein, computer-readable media means any medium accessible by a computing device. As an example and not limitation, computer-readable media may include computer storage media and communication media.

[0059] Computer storage media means any medium that can be used to store computer-readable information. As an example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD), or other optical disk storage, cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media excludes the signal itself and the signal transmission in transient form.

[0060] Communication media refers to any medium that can be used for communication of computer-readable information. By way of example and not limitation, communication media can include coaxial cables, fiber optic cables, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic or other types of signals.

[0061] Example Illustrative examples of the disclosed technology are provided below. Embodiments of the technology may include one or more and any combination of the examples described below.

[0062] Example 1 is a power vector analyzer for analyzing power from a device under test (DUT), comprising: one or more channels for measuring a reference voltage signal from a power line connected to the DUT; one or more channels for measuring a reference current signal from the power line; a user interface comprising a display and one or more controls; and a quadrature synchronous detector (QSD) for each phase of apparent power being measured, the QSD being configured to use the reference voltage signal from the one or more channels and the reference current signal from the one or more channels to determine the apparent power for each phase of power measured by the DUT, and to display the apparent power for each phase on the display.

[0063] Example 2 is the power vector analyzer of Example 1, further comprising: one or more processors configured to execute code causing the one or more processors to perform the following operations: receiving a signal from a user through the one or more controls on the user interface indicating that the user wants to start a zeroing process; sending a signal to the QSD to generate a zero vector; applying the zero vector to the reference voltage and the reference current to remove static power; and displaying an apparent power signal for a test voltage and a test current relative to the zeroed static power for each phase of the power.

[0064] Example 3 is the power vector analyzer of Example 2, wherein the one or more processors are further configured to: display the reference apparent power signal as the reference apparent power signal for each phase measured moves to 0 when the zero vector is generated for the QSD for each phase.

[0065] Example 4 is the power vector analyzer of Example 3, wherein the code causing the one or more processors to display the test power signal comprises code for displaying a reference power signal for each phase overlaid on a display.

[0066] Example 5 is the power vector analyzer of any one of Examples 2 to 4, wherein the reference voltage signal and the reference current signal for the zeroing process are generated by a DUT operating at a reference load value, a reference frequency, and a reference voltage.

[0067] Example 6 is the power vector analyzer of any one of Examples 2 to 5, wherein the reference voltage signal and the reference current signal for the zeroing process are generated by a reference motor for generating zeroed static power.

[0068] Example 7 is the power vector analyzer of any of Examples 1 to 6, wherein three phases of power are measured and the QSD for each phase of power includes three QSDs, and the apparent power display displays the apparent power for each of the three phases of power.

[0069] Example 8 is the power vector analyzer of any of Examples 1 to 7, wherein the reference voltage signal from the one or more channels and the reference current signal from the one or more channels are static operating powers on a DUT power line.

[0070] Example 9 is the power vector analyzer of any of Examples 1 to 8, wherein the one or more controls include a control that allows the user to move the apparent power signal for each phase being measured on the display as desired by the user.

[0071] Example 10 is the power vector analyzer of any one of Examples 1 to 9, wherein the one or more controls include a control allowing the user to define a limit mask on the display, the limit mask indicating an area of ​​the apparent power signal that is within a pass limit.

[0072] Example 11 is the power vector analyzer of Example 10, wherein the one or more processors are further configured to: pass the DUT when the apparent power measurement result does not exceed the limit mask; and fail the DUT when the apparent power measurement result exceeds the limit mask.

[0073] Example 12 is a power vector analyzer of any one of Examples 1 to 11, wherein the QSD for each phase of power uses the reference voltage signal and the reference current signal to generate the apparent power by the following operations: multiplying a reference voltage signal represented by a cosine voltage function with a reference current signal represented by a cosine current function, the cosine current function having a phase shift relative to the reference voltage to produce a result, and filtering the result to obtain a real power value; shifting the cosine voltage function by 90 degrees to produce a shifted voltage function as a sinusoidal voltage function; multiplying the sinusoidal voltage function with the cosine current function and filtering the result to produce a reactive power signal; and using the reactive power signal and the active power signal to generate the apparent power.

[0074] Example 13 is a method of measuring one or more power signals, comprising: measuring a reference voltage signal from a power line connected to a device under test; measuring a reference current signal from the power line; using a quadrature synchronous detector (QSD) for each phase of the power being measured to obtain the reference voltage signal and the reference current signal to generate an apparent power for each phase of the power measured by the DUT; and displaying the apparent power relative to a zeroed static power for each phase of the apparent power being measured.

[0075] Example 14 is the method of Example 13, further comprising: receiving a signal from a user via one or more controls on the user interface indicating that the user wants to start a zeroing process; sending a signal to the QSD to generate a zero vector; applying the zero vector to the reference voltage signal and the reference current signal to produce a zeroed power static; and displaying an apparent power signal relative to the zeroed power static for each phase of the power.

[0076] Example 15 is the method of Example 14, further comprising: displaying a reference apparent power for each phase being measured as the QSD generates the zero vector and reference voltage and reference current signals move to zero.

[0077] Example 16 is the method of Example 14, wherein the reference voltage signal and the reference current signal are generated by a DUT operating at a reference load value, a reference frequency, and a reference voltage.

[0078] Example 17 is the method of Example 14, wherein the reference voltage signal and the reference current signal are generated by a reference DUT for producing zeroed quiescent power.

[0079] Example 18 is the method of any of Examples 13 to 17, wherein one or three phases of power or one phase of power is measured.

[0080] Example 19 is the method of Example 17, wherein three phases of apparent power are measured, and displaying the apparent power signal comprises displaying the apparent power signal for each phase overlaid on a display.

[0081] Example 20 is the method of any one of Examples 13 to 19, further comprising: allowing the user to move the apparent power signal for each phase being measured on the display as desired by the user.

[0082] Example 21 is the method of any one of Examples 13 to 20, further comprising: allowing the user to define a limit mask on the display, the limit mask indicating an area of ​​the apparent power signal that is within a pass limit.

[0083] Example 22 is a method of any one of Examples 13 to 21, wherein the reference voltage signal and the reference current signal are used for the QSD of each phase of the power to generate the apparent power by: multiplying a reference voltage signal represented by a cosine voltage function with a reference current signal represented by a cosine current function, the cosine current function having a phase shift relative to the reference voltage to produce a result, and filtering the result to obtain a real power value; shifting the cosine voltage function by 90 degrees to produce a shifted voltage function as a sinusoidal voltage function; multiplying the sinusoidal voltage function with the cosine current function and filtering the result to produce a reactive power signal; and using the reactive power signal and the active power signal to generate the apparent power.

[0084] In addition, the written description mentions specific features. It should be understood that the disclosure in this specification includes all possible combinations of those specific features. Where a specific feature is disclosed in the context of a particular aspect or example, the feature may also be used in the context of other aspects and examples as much as possible.

[0085] Furthermore, when the present application refers to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0086] All features disclosed in the specification including claims, abstract and drawings, and all steps in any disclosed method or process may be combined in any combination except combinations in which at least some of such features and / or steps are mutually exclusive. Each feature disclosed in the specification including claims, abstract and drawings may be replaced by an alternative feature serving the same, equivalent or similar purpose, unless expressly stated otherwise.

[0087] Although specific examples of the present invention have been shown and described for purposes of illustration, it should be understood that various modifications can be made without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be limited, except by the appended claims.

Claims

1. A power vector analyzer for analyzing power from a device under test (DUT), comprising: one or more channels for measuring a reference voltage signal from a power line connected to the DUT; one or more channels for measuring a reference current signal from the power line; a user interface, including a display and one or more controls; as well as a quadrature synchronous detector (QSD) for each phase of apparent power being measured, the QSD being configured to use a reference voltage signal from the one or more channels and a reference current signal from the one or more channels to determine an apparent power for each phase of power measured by the DUT, and to display the apparent power for each phase on the display.

2. The power vector analyzer of claim 1, further comprising: One or more processors configured to execute code that causes the one or more processors to perform the following operations: receiving, via the one or more controls on the user interface, a signal from a user indicating that the user wants to begin a zeroing process; sending a signal to the QSD to generate a zero vector; applying the zero vector to the reference voltage and the reference current to remove static power; as well as The apparent power signals for the test voltage and test current are displayed relative to the zeroed quiescent power for each phase of power.

3. A power vector analyzer as described in claim 2, wherein the one or more processors are further configured to: display the reference apparent power signal as the reference apparent power signal for each phase being measured moves to 0 when the zero vector is generated for the QSD of each phase.

4. The power vector analyzer of claim 3, wherein the code causing the one or more processors to display the test power signal comprises code that displays a reference power signal for each phase overlaid on a display.

5. The power vector analyzer of claim 2, wherein a reference voltage signal and a reference current signal for the zeroing process are generated by a DUT operating at a reference load value, a reference frequency, and a reference voltage.

6. The power vector analyzer of claim 2, wherein a reference voltage signal and a reference current signal for the zeroing process are generated by a reference motor for generating zeroed static power.

7. The power vector analyzer of claim 1, wherein three phases of power are measured and the QSD for each phase of power comprises three QSDs, and the apparent power display displays the apparent power for each of the three phases of power.

8. The power vector analyzer of claim 1, wherein the reference voltage signal from the one or more channels and the reference current signal from the one or more channels are static operating powers on a DUT power line.

9. The power vector analyzer of claim 1, wherein the one or more controls include a control that allows the user to move the apparent power signal for each phase being measured on the display as desired by the user.

10. The power vector analyzer of claim 1, wherein the one or more controls include a control that allows the user to define a limit mask on the display, the limit mask indicating a region of the apparent power signal that is within a pass limit.

11. The power vector analyzer of claim 10, wherein the one or more processors are further configured to: pass the DUT when the apparent power measurement result does not exceed the limit mask; and fail the DUT when the apparent power measurement result exceeds the limit mask.

12. The power vector analyzer of claim 1 , wherein the QSD for each phase of power uses the reference voltage signal and the reference current signal to generate the apparent power by: multiplying a reference voltage signal represented by a cosine voltage function and a reference current signal represented by a cosine current function having a phase shift relative to the reference voltage to produce a result, and filtering the result to obtain a real power value; shifting the cosine voltage function by 90 degrees to produce a shifted voltage function as a sine voltage function; multiplying the sinusoidal voltage function by the cosine current function and filtering the result to generate a reactive power signal; as well as The reactive power signal and the active power signal are used to generate the apparent power.

13. A method of measuring one or more power signals, comprising: measuring a reference voltage signal from a power line connected to the device under test; measuring a reference current signal from the power line; using a quadrature synchronous detector (QSD) for each phase of the power being measured to obtain the reference voltage signal and the reference current signal to generate an apparent power for each phase of the power measured by the DUT; as well as The apparent power is displayed relative to the zeroed quiescent power for each phase of the measured apparent power.

14. The method of claim 13, further comprising: receiving a signal from a user via one or more controls on the user interface indicating that the user wants to begin a zeroing process; sending a signal to the QSD to generate a zero vector; applying the zero vector to the reference voltage signal and the reference current signal to produce a zeroed power static; as well as The apparent power signal is displayed relative to the zeroed power static for each phase of power.

15. The method of claim 14, further comprising: As the QSD generates the zero vector and the reference voltage and reference current signals move to zero, the reference apparent power for each phase being measured is displayed.

16. The method of claim 14, wherein the reference voltage signal and the reference current signal are generated by a DUT operating at a reference load value, a reference frequency, and a reference voltage.

17. The method of claim 14, wherein the reference voltage signal and the reference current signal are generated by a reference DUT for producing zeroed quiescent power.

18. The method of claim 13, wherein one or three phases of power or one phase of power is measured.

19. The method of claim 17, wherein three phases of apparent power are measured and displaying the apparent power signal comprises displaying the apparent power signal for each phase overlaid on a display.

20. The method of claim 13, further comprising: The user is allowed to move the apparent power signal for each phase being measured on the display as the user desires.

21. The method of claim 13, further comprising: The user is allowed to define a limit mask on the display, the limit mask indicating areas of the apparent power signal that are within passing limits.

22. The method of claim 13, wherein the QSD for each phase of power uses the reference voltage signal and the reference current signal to generate the apparent power by: multiplying a reference voltage signal represented by a cosine voltage function and a reference current signal represented by a cosine current function having a phase shift relative to the reference voltage to produce a result, and filtering the result to obtain a real power value; shifting the cosine voltage function by 90 degrees to produce a shifted voltage function as a sine voltage function; multiplying the sinusoidal voltage function by the cosine current function and filtering the result to generate a reactive power signal; as well as The reactive power signal and the active power signal are used to generate the apparent power.

Images