Test control method and device, electronic equipment and storage medium

Abstract

The invention relates to the field of testing, in particular to a test control method and device, electronic equipment and a storage medium. After the test operation instruction is received, the upper computer can respond quickly, the test client is started to accurately capture the comprehensive test task covering the lower computer and the hardware module, tedious manual deployment is not needed, and the starting efficiency is greatly improved. The lower computer and the hardware module are synchronously tested, the low-efficiency limitation of traditional successive testing is broken through, and a large number of samples can be covered within a short time. Moreover, the automatic testing process greatly reduces the human input, reduces the risk of human errors, and also reduces the material loss. And finally, a report is quickly generated based on test results of the lower computer and the hardware module, so that a powerful basis is provided for product quality evaluation, and the urgent requirements on stable, quick, efficient and reliable test quality when large-batch products are offline are comprehensively met.

Description

Technical Field

[0001] The present invention relates to the field of testing, and in particular to a test control method, device, electronic equipment and storage medium. Background Art

[0002] In today's technological product manufacturing industry, product testing plays a core role in ensuring quality, but the traditional testing model is full of problems. Many companies have long adopted manual testing, where operators conduct various functional tests on products one by one. This method is extremely inefficient, the number of products tested daily is limited, and the test volume is seriously insufficient. A large number of products cannot be fully tested, product stability is not guaranteed, and there are many safety hazards. In order to expand the scale of testing, some companies choose to invest a lot of manpower, but they don't want to fall into a new dilemma. Human-machine collaboration is chaotic, material loss is aggravated, and labor costs are soaring. The overall testing efficiency has not been significantly improved, but instead it has led to high input and low output. Summary of the invention

[0003] In view of this, the embodiments of the present invention provide a test control method, device, electronic device and storage medium to solve the problems of low efficiency, insufficient test level, high resource consumption and inability to meet the urgent demand for test quality when large quantities of products are put into production in traditional testing methods.

[0004] In a first aspect, an embodiment of the present invention provides a test control method, the method comprising:

[0005] Receiving a test running instruction for a test client, wherein the test client is deployed on a host computer, and the host computer is connected to a slave computer and a hardware module respectively;

[0006] In response to the test running instruction, the test client is run, and a test task is obtained, wherein the test task includes a first test item for the lower computer and a second test item for the hardware module;

[0007] Testing the lower computer according to the first test item to obtain a first test result, and testing the hardware module according to the second test item to obtain a second test result;

[0008] A test report is generated based on the first test result and the second test result.

[0009] Further, the testing the lower computer according to the first test item to obtain a first test result includes:

[0010] Sending a first test instruction to the lower computer based on the first test item, wherein the lower computer is used to perform a test according to the first test instruction to obtain first test data;

[0011] Obtain first test data obtained by testing the lower computer, and compare the first test data with a preset data range to obtain the first test result, wherein if the first test data falls within the preset data range, the first test result is that the lower computer is normal, or, if the first test data does not fall within the preset data range, the first test result is that the lower computer is abnormal.

[0012] Further, testing the hardware module according to the second test item to obtain a second test result includes:

[0013] generating signal configuration information based on the second test item;

[0014] Generate an excitation signal according to the configuration information through a digital input / digital output board;

[0015] Sending an excitation signal to the hardware module through the digital input / digital output board, wherein after the hardware module receives the excitation signal, the internal circuit of the hardware module processes the excitation signal according to the functional logic to obtain second test data, and feeds the second test data back to the host computer through the test loop;

[0016] Obtain second test data fed back by the hardware module, and analyze whether the second test data meets the test conditions corresponding to the second test item, to obtain the second test result, wherein, if the second test data does not meet the test conditions corresponding to the second test item, then the second test result is that the function corresponding to the second test item of the hardware module is abnormal; or, if the second test data meets the test conditions corresponding to the second test item, then the second test result is that the function corresponding to the second test item of the hardware module is normal.

[0017] Further, the generating signal configuration information based on the second test item includes:

[0018] Obtaining a test function corresponding to the second test item, and determining a signal level type and a signal frequency corresponding to the test function;

[0019] Query parameter configuration information of the hardware module, and determine the signal amplitude and signal duration based on the parameter configuration information;

[0020] The signal configuration information is generated based on the signal level type, the signal frequency, the signal amplitude, and the signal duration.

[0021] Furthermore, the method further comprises:

[0022] Acquire first historical test data of the slave computer under different working conditions and second historical test data of the hardware module under different working conditions;

[0023] Analyzing a first correlation between abnormal data in the first historical test data and different operating conditions, and analyzing a second correlation between abnormal data in the second historical test data and different operating conditions;

[0024] An abnormality analysis model is constructed based on the first association relationship and the second association relationship.

[0025] Furthermore, the method further comprises:

[0026] When the first test result is that the lower computer is abnormal, and / or the second test result is that the function corresponding to the daily test item of the hardware module is abnormal, obtaining first test data obtained by testing the lower computer according to the first test item, and / or obtaining second test data obtained by testing the hardware module according to the second test item;

[0027] The first test data and / or the second test data are input into the abnormality analysis model to obtain the abnormality cause of the lower computer and / or the abnormality cause of the hardware module.

[0028] Furthermore, the method further comprises:

[0029] Diagnose the abnormal cause of the lower computer and / or the abnormal cause of the hardware module, and obtain repair suggestion information corresponding to the abnormal cause of the lower computer and / or the abnormal cause of the hardware module;

[0030] Repair the lower computer and / or the hardware module according to the repair suggestion information.

[0031] In a second aspect, an embodiment of the present invention provides a test control device, the device comprising:

[0032] A receiving module, used for receiving a test running instruction for a test client, wherein the test client is deployed on a host computer, and the host computer is connected to a slave computer and a hardware module respectively;

[0033] A response module, used to respond to the test running instruction, run the test client, and obtain a test task, wherein the test task includes a first test item for the lower computer and a second test item for the hardware module;

[0034] A test module, configured to test the lower computer according to the first test item to obtain a first test result, and to test the hardware module according to the second test item to obtain a second test result;

[0035] A generating module is used to generate a test report based on the first test result and the second test result.

[0036] In a third aspect, an embodiment of the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0037] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the method of the first aspect or any corresponding embodiment thereof.

[0038] After this application receives the test run instruction, the upper computer can respond quickly and start the test client to accurately capture the comprehensive test tasks covering the lower computer and hardware modules, without the need for tedious manual deployment, which greatly improves the startup efficiency. The simultaneous testing of the lower computer and the hardware module breaks the inefficient limitations of traditional sequential testing and can cover a large number of samples in a short period of time. Furthermore, the automated testing process greatly reduces manpower investment, reduces the risk of human error, and reduces material loss. Finally, the report quickly generated based on the test results of the lower computer and hardware module provides a strong basis for product quality evaluation, and fully meets the urgent needs for stable, fast, efficient and reliable test quality when large quantities of products are offline. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 is a flow chart of a test control method according to some embodiments of the present invention;

[0041] Figure 2 is a schematic diagram of a testing process according to some embodiments of the present invention;

[0042] Figure 3 is a structural block diagram of a test control device according to an embodiment of the present invention;

[0043] Figure 4 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0045] According to an embodiment of the present invention, a test control method, device, electronic device and storage medium are provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0046] In this embodiment, a test control method is provided. Figure 1 is a flow chart of a test control method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0047] Step S101, receiving a test running instruction for a test client, wherein the test client is deployed on a host computer, and the host computer is connected to a slave computer and a hardware module respectively.

[0048] In the embodiment of the present application, the host computer, as the control center of the entire test system, is always in a state of monitoring the network port or a specific communication channel, waiting for the test operation instruction sent from the external test control terminal (such as the operating computer of the test engineer, the automated test scheduling system, etc.). The instruction is encapsulated according to the predefined communication protocol, and contains key information such as the instruction type (start test, pause test, terminate test, etc.), the test item number, and the product model identification.

[0049] When the communication module of the host computer receives the data, it first verifies the integrity and legality of the data, and ensures that the received data has not been damaged or tampered with during the transmission process by verifying the checksum and data length. If the data is correct, the instruction content is parsed according to the communication protocol, and it is identified as a start test instruction for the test client, and the relevant information is passed to the test task scheduling module of the host computer to prepare to start the subsequent process.

[0050] Step S102, responding to the test running instruction, running the test client, and obtaining a test task, wherein the test task includes a first test item for the lower computer and a second test item for the hardware module.

[0051] In the embodiment of the present application, the test task scheduling module of the host computer immediately activates the test client program deployed locally on the host computer after receiving the startup command. During the startup of the test client, a series of basic configuration files will be automatically loaded, which contain parameter settings for communicating with the lower computer and hardware modules (such as serial port baud rate, IP address, port number, etc.), test data storage path, test report template format and other information to ensure that the client can interact with peripheral devices normally and record the test process.

[0052] At the same time, the test client quickly retrieves and matches the corresponding test task based on the test task library pre-stored in the host computer and the product model and test item number carried in the instruction received this time. For example, if the instruction specifies to test a new model of electronic products, the test client will find a complete test plan for the model in the task library, and extract the first test item for the lower computer (which may involve lower computer software function testing, communication protocol testing, etc.) and the second test item for the hardware module (such as output stability testing of the internal high-voltage power supply, signal driving capability testing of multi-channel DI / DO boards, etc.), so as to make full preparations for the next step of test execution.

[0053] Step S103, testing the lower computer according to the first test item to obtain a first test result, and testing the hardware module according to the second test item to obtain a second test result.

[0054] In the embodiment of the present application, testing the lower computer according to the first test item to obtain the first test result includes the following steps A1-A2:

[0055] Step A1: sending a first test instruction to a lower computer based on a first test item, wherein the lower computer is used to perform a test according to the first test instruction to obtain first test data.

[0056] Specifically, first, the host computer constructs the first test instruction according to the specific content specified in the first test item through a communication interface (such as a serial port, Ethernet port, etc.) that is pre-configured and compatible with the lower computer. This instruction will clearly contain key information such as the operation requirements and parameter settings that need to be executed by the lower computer. For example, if the first test item is to detect the accuracy of a certain algorithm module of the lower computer in processing specific input data, the test instruction will contain the specific data value to be input, the trigger condition for the algorithm to start, and other contents. After constructing the instruction, the host computer encapsulates the instruction according to the established communication protocol format, and then sends it to the lower computer accurately through the communication link. The communication receiving module built into the lower computer monitors the link in real time. Once the instruction is received, it will pass it to its own microcontroller. The microcontroller then starts the corresponding functional module according to the requirements in the instruction to start the test-related operations such as calculation and processing, and collects the first test data such as calculation results, intermediate state parameters, and execution time during the operation.

[0057] Step A2, obtain the first test data obtained by testing the lower computer, and compare the first test data with the preset data range to obtain a first test result, wherein, if the first test data falls within the preset data range, the first test result is that the lower computer is normal, or, if the first test data does not fall within the preset data range, the first test result is that the lower computer is abnormal.

[0058] The upper computer initiates a data acquisition request to the lower computer through the same communication link at a certain time interval or according to a specific signal fed back by the lower computer. After receiving the request, the lower computer packages the first test data collected during the test process in accordance with the communication data format agreed upon by both parties, and then transmits it back to the upper computer through the communication interface. After receiving these data, the upper computer extracts the key test indicator data, and then searches for the preset data range corresponding to the first test item. For example, for the algorithm processing accuracy detection mentioned above, the preset data range is the result interval correctly output by the algorithm and the reasonable execution time range. The extracted first test data is compared with the preset data range one by one. If the key indicator values ​​in the first test data all fall within the corresponding preset data range, then the first test result is determined to be normal for the lower computer; otherwise, if some or all of the key indicator values ​​exceed the preset data range, the first test result is determined to be abnormal for the lower computer, thereby completing the result determination of this test item of the lower computer.

[0059] In the embodiment of the present application, testing the hardware module according to the second test item to obtain the second test result includes the following steps B1-B4:

[0060] Step B1: Generate signal configuration information based on the second test item.

[0061] Specifically, generating signal configuration information based on the second test item includes: obtaining the test function corresponding to the second test item, and determining the signal level type and signal frequency corresponding to the test function; querying the parameter configuration information of the hardware module, and determining the signal amplitude and signal duration based on the parameter configuration information; generating signal configuration information based on the signal level type, signal frequency, signal amplitude and signal duration.

[0062] Specifically, the host computer stores a complete list of test tasks. When focusing on the second test item, it will extract from the corresponding test description document or database record which function of the hardware module the test is to test, such as the signal amplification function of a circuit in the hardware module, or its filtering function for a specific frequency signal, etc. This step clarifies the starting point and goal of the subsequent generation of signal configuration information, and provides a basic basis for determining specific signal parameters.

[0063] According to the test function obtained, if the test function is to verify whether the hardware module can respond correctly to the high-level trigger signal, such as detecting whether a digital circuit can accurately turn on the corresponding functional module when receiving a high level (such as +5V), then the signal level type is determined to be a high level; if it is to test the response to a low-level signal (such as 0V), then the signal level type is a low level; and if it involves testing the processing function of pulse signals, such as detecting the counting accuracy of a counter circuit for a certain frequency pulse signal, it is necessary to determine the specific signal frequency based on the design requirements of the circuit and past similar test experience, which may be different frequency values ​​such as 100 pulses per second and 500 pulses per second, so as to meet the processing capability detection requirements of the hardware module to be tested for the corresponding frequency signal in the actual application scenario.

[0064] The host computer will access the database or configuration file that stores the detailed parameters of the hardware module, and search for the specific parameters of the hardware module related to the current second test item. For the signal amplitude, for example, if a certain input port in the hardware module clearly marks that the acceptable voltage amplitude range is 3V-5V, then in order to test the performance of the port within the normal working range, this range will be used to determine the appropriate signal amplitude, and the middle value of 4V may be selected; for the signal duration, it will be determined based on the time required for the internal circuit of the hardware module to complete a complete functional operation or reach a stable state. For example, it takes about 10 milliseconds for a circuit to receive an input signal and output a stable result, then the signal duration may be set to be greater than or equal to 10 milliseconds to ensure that the hardware module has enough time to process the input signal and give corresponding feedback, so as to ensure the effectiveness and accuracy of the test.

[0065] Integrate the previously determined signal parameters in a predetermined format. For example, it may be represented by a specific data structure, with the signal level type indicated at the beginning (using codes to represent high level, low level, or specific values ​​to represent level voltage values), and then fill in the signal frequency (specific value in Hertz), signal amplitude (precise voltage value), and signal duration (specific duration in seconds or milliseconds) and other parameters in sequence, forming a complete signal configuration information that can be accurately identified and parsed by subsequent digital input / digital output boards and other related devices, so that they can generate and output stimulus signals that meet the requirements based on these configuration information for testing hardware modules.

[0066] Step B2: Generate an excitation signal according to the configuration information through the digital input / digital output board.

[0067] Specifically, the host computer sends the generated signal configuration information to the digital input / digital output board through a communication link (such as a serial port, USB, etc.). The digital input / digital output board has a corresponding control circuit inside. After receiving the configuration information, the microprocessor in its control circuit will parse the information. Then, according to the requirements of the analyzed signal type, amplitude, frequency, and duration, the signal generation circuit module in the control board is adjusted accordingly. For example, if a high-amplitude pulse signal is required to be output, the output voltage will be increased by adjusting related components such as the digital-to-analog converter; if the frequency is to be changed, the parameters of the clock circuit will be adjusted to accurately generate the corresponding excitation signal according to the configuration information.

[0068] Step B3, sending an excitation signal to the hardware module through the digital input / digital output board, wherein after the hardware module receives the excitation signal, the internal circuit of the hardware module processes the excitation signal according to the functional logic to obtain the second test data, and feeds back the second test data to the host computer through the test loop.

[0069] Specifically, after the digital input / digital output board generates an excitation signal, the excitation signal is sent to the hardware module by using the electrical connection line established between its output port and the hardware module. After the hardware module receives the excitation signal, its internal circuit will start to process the signal according to its pre-set functional logic. For example, for a signal amplification circuit module, it will amplify the input excitation signal according to its own amplification factor and other parameters. During this processing, the hardware module will collect key data such as output voltage, current, signal waveform, etc. as the second test data through internal sensors, monitoring points, etc. Then, the hardware module will send these second test data back to the host computer in accordance with the agreed communication protocol and data format through the pre-built test loop between the host computer (which can be a special data feedback line, or it can be a communication link transferred by means of the digital input / digital output board, etc.), to ensure that the host computer can accurately receive them.

[0070] Step B4, obtaining the second test data fed back by the hardware module, and analyzing whether the second test data meets the test conditions corresponding to the second test item, to obtain a second test result, wherein, if the second test data does not meet the test conditions corresponding to the second test item, the second test result is that the function corresponding to the second test item of the hardware module is abnormal; or, if the second test data meets the test conditions corresponding to the second test item, the second test result is that the function corresponding to the second test item of the hardware module is normal.

[0071] Specifically, the host computer continuously monitors the second test data fed back from the hardware module through the corresponding communication interface. Once the data is received, the data will be parsed and extracted first to obtain the key test index data. Then, the host computer searches for the test conditions set in advance for the second test item. These test conditions clearly specify the range, logical relationship and other requirements that the corresponding test indicators should meet when the hardware module works normally. For example, for the signal output function test of a certain hardware module, the test conditions may stipulate that the output voltage should be stable within a certain interval, the distortion of the signal waveform should be lower than a certain percentage, etc. The key indicators in the extracted second test data are compared and analyzed one by one with these test conditions. If it is found that there are key indicators that do not meet the corresponding test conditions, such as the output voltage exceeds the specified interval or the signal waveform distortion is too large, then the second test result is determined to be the function of the second test item of the hardware module. Abnormal; conversely, if all key indicators meet the corresponding test conditions, the second test result is determined to be the function of the second test item of the hardware module. Normal, thereby completing the judgment of the functional status of this test item of the hardware module.

[0072] Step S104: Generate a test report based on the first test result and the second test result.

[0073] In the embodiments of the present application, Figure 2 As shown, ensure that the host computer is correctly connected to the slave computer and the hardware module. The test client has been deployed on the host computer. Open the test software and enter the test interface as shown in the figure. In the table on the left side of the interface, for different analog inputs (such as AII (12V), AII (24V), etc.), check and set the standard value, offset, standard value allowable deviation, measured value and other parameters. For example, for AII (12V), assume that the standard value is set to 12V, the offset is 0V, and the standard value allowable deviation is ±0.5V.

[0074] Click the "Start Test" button in the lower left corner of the interface. After receiving the test run command, the test client will perform the test according to the preset test task. The test task includes the first test item for the lower computer and the second test item for the hardware module. In this interface, the first test item may involve the test of analog input, and the second test item may involve various functional tests in the list on the right (such as DO detection, AI detection, LED detection, etc.).

[0075] For the test of the lower machine:

[0076] The test client will read the actual value of analog inputs such as AII (12V) and compare it with the preset standard value. For example, if the measured value of AII (12V) is 11.8V, since 11.8V is within the allowable deviation range of 12V±0.5V, the first test result of AII (12V) is passed.

[0077] For testing of hardware modules:

[0078] The test client will execute each test listed on the right in turn. For example, when performing DO detection, the test client will send instructions to check whether the status of the digital output port is correct; when performing AI detection, it will check whether the analog input port functions normally. Assuming that in the DO detection, the status of all digital output ports is consistent with expectations, the second test result of the DO detection is passed.

[0079] After the test is completed, the test client generates a test report based on the first test result and the second test result. On the interface, the test result (such as pass or fail) may be displayed next to the corresponding test item, or after the test report is generated, a specific button can be used to view the detailed test report. For example, the test report will list the measured value of AII (12V) as 11.8V, the test result as pass, and the result of DO detection as pass.

[0080] According to the test report, analyze whether there are any problems with the product. If all test items pass, the product can enter the next production stage or be prepared for shipment. If a test item fails, for example, it is found that the output voltage of a power supply exceeds the allowable deviation range during the voltage test, it is necessary to further investigate whether it is a problem with the lower computer or the hardware module, and repair it according to the problem.

[0081] The test results will be recorded for subsequent tracking and statistics of product quality. For products that fail the test, the problems will be fed back to the relevant technicians for repair and improvement.

[0082] After this application receives the test run instruction, the upper computer can respond quickly and start the test client to accurately capture the comprehensive test tasks covering the lower computer and hardware modules, without the need for tedious manual deployment, which greatly improves the startup efficiency. The simultaneous testing of the lower computer and the hardware module breaks the inefficient limitations of traditional sequential testing and can cover a large number of samples in a short period of time. Furthermore, the automated testing process greatly reduces manpower investment, reduces the risk of human error, and reduces material loss. Finally, the report quickly generated based on the test results of the lower computer and hardware module provides a strong basis for product quality evaluation, and fully meets the urgent needs for stable, fast, efficient and reliable test quality when large quantities of products are offline.

[0083] In an embodiment of the present application, the method further includes:

[0084] Step C1, obtaining first historical test data of the lower computer under different working conditions and second historical test data of the hardware module under different working conditions.

[0085] Specifically, the host computer first connects to the database or data warehouse that stores the test data. These storage locations classify and save the test data of each lower computer in the past according to certain rules. The host computer screens the lower computer test data according to the pre-set search conditions, such as the time range (past year, past six months, etc.), product model, lower computer software version number and other information to determine which batches of lower computer test data to obtain.

[0086] Then, for each screened test record, further extract the data under different working conditions. The working condition information can be comprehensively judged from the environmental parameters recorded during the test (such as the temperature, humidity, electromagnetic interference intensity, etc. at the time) and the operating status parameters of the lower computer itself (such as being in standby, running at full load, executing specific tasks, etc.). For example, the test data on processor usage, memory usage, communication delay, etc. collected when the temperature is 25℃-30℃ and the lower computer is in full load operation state are classified as the first historical test data under this working condition, and the corresponding relevant data under different working conditions are extracted in turn to form a complete first historical test data set.

[0087] Similarly, the host computer accesses the corresponding data storage location and first determines the batch of related hardware module test data to be obtained according to similar screening rules (time range, hardware module model, etc.).

[0088] Next, analyze the working conditions of the hardware module during each test, and judge different working conditions through the recorded information such as external power supply voltage, input signal type and frequency, load connection status, etc. For example, under the working condition where the input signal is a pulse signal of a certain frequency and the external load is a high resistance value, collect the test data such as the output voltage, current, signal distortion of the hardware module as the second historical test data under this working condition, sort out the hardware module test data corresponding to different working conditions, and summarize them to obtain the second historical test data set.

[0089] Step C2, analyzing a first correlation relationship between abnormal data in the first historical test data and different operating conditions, and analyzing a second correlation relationship between abnormal data in the second historical test data and different operating conditions.

[0090] Specifically, the host computer first uses data cleaning and preprocessing algorithms to process the first historical test data, remove obviously erroneous data (such as data formats that do not meet specifications, values ​​that exceed a reasonable physical range, etc.), and ensure data quality.

[0091] Then, by setting reasonable thresholds or using some statistical anomaly detection methods (such as the 3-times standard deviation principle, etc.), the abnormal data is identified. For example, when the processor usage of the lower computer is continuously higher than the maximum usage threshold set during normal operation under a certain working condition, these data points are determined to be abnormal data. Then, these abnormal data are correlated with the corresponding working condition information for analysis. For example, under the working conditions of high temperature and high humidity and the lower computer performing complex tasks, the number and proportion of abnormal increases in processor usage are counted, and the frequency, regularity and other characteristics of abnormal data under such working conditions are analyzed to determine the first correlation between the abnormal data and the working condition. Such analysis is performed on different working conditions to sort out a comprehensive correlation.

[0092] Similarly, the second historical test data is first cleaned and preprocessed to ensure the accuracy and availability of the data. Use appropriate anomaly detection methods (such as judging signal anomalies based on the mutation point of the wavelet transform detection signal, etc., for the signal-related data of the hardware module) to identify abnormal data. For example, the output voltage of the hardware module fluctuates greatly and deviates from the normal range, which is marked as abnormal data. Then match these abnormal data with the corresponding working conditions for analysis, observe the performance of various types of abnormal data in the hardware module under different input signal types, different external loads and other working conditions, and count the probability and trend of different abnormal situations under each working condition, so as to determine the second correlation between the abnormal data and each working condition, and fully grasp the distribution law and correlation characteristics of abnormal data of the hardware module under different working conditions.

[0093] Step C3: constructing an abnormality analysis model based on the first association relationship and the second association relationship.

[0094] Specifically, the host computer selects an appropriate modeling method to construct an abnormal analysis model based on the first correlation relationship and the second correlation relationship obtained in the previous analysis. If the correlation relationship presents a more complex nonlinear feature, a neural network model (such as a multi-layer perceptron, etc.) may be selected; if the model is more expected to have better interpretability, a decision tree or random forest model would be a more appropriate choice.

[0095] The operating condition characteristics in the first association relationship (such as temperature, humidity, lower computer operating status, etc.) and the corresponding abnormal data characteristics (such as abnormal processor usage value, abnormal communication delay value, etc.) are used as input, and whether an abnormality occurs (indicated by 0 or 1, 0 indicates normal, and 1 indicates abnormal) is used as output to perform model training on the data of the lower computer part; at the same time, the operating condition characteristics in the second association relationship (such as input signal parameters, external load conditions, etc.) and the abnormal data characteristics of the hardware module (such as abnormal output voltage fluctuation value, abnormal signal distortion value, etc.) are used as input, and whether an abnormality occurs is used as output to perform model training on the data of the hardware module part.

[0096] During the training process, by adjusting the model's hyperparameters (such as the number of layers and nodes of the neural network, the depth of the decision tree, etc.) and using a portion of historical data as a validation set, the model's performance indicators such as accuracy and recall rate are evaluated and optimized, and training is continuously iterated until the model can more accurately predict whether the lower computer and hardware modules will have abnormal conditions based on the input working condition information, thereby constructing a complete abnormality analysis model for subsequent early prediction and analysis of abnormal conditions of the lower computer and hardware modules under different working conditions.

[0097] In an embodiment of the present application, the method also includes: when the first test result is an abnormality of the lower computer, and / or the second test result is a functional abnormality corresponding to the daily test item of the hardware module, obtaining first test data obtained by testing the lower computer according to the first test item, and / or obtaining second test data obtained by testing the hardware module according to the second test item; inputting the first test data and / or the second test data into the abnormality analysis model to obtain the abnormal cause of the lower computer and / or the abnormal cause of the hardware module.

[0098] The upper computer first confirms which first test item of the lower computer has the abnormal result, and then initiates a data acquisition request to the lower computer again based on the communication link and data acquisition mechanism previously established with the lower computer. This request will explicitly require the lower computer to provide all relevant first test data recorded during the execution of the first test item. For example, if the first test item is to detect the transmission stability of a communication module of the lower computer, the data requested to be acquired includes detailed information such as the content of the sent data, the content of the received data, the packet loss during the transmission process, and the transmission delay.

[0099] After receiving the request, the lower computer will extract the corresponding data from its own storage unit (such as a cache area or a dedicated data recording module), package it according to the communication protocol format agreed upon by both parties, and then transmit the first test data back to the upper computer through the communication interface (such as a serial port, Ethernet port, etc.) to ensure that the upper computer can receive it accurately and completely.

[0100] The host computer also first determines which function corresponding to the second test item has a problem, and then sends a data acquisition instruction to the hardware module through the communication link between the hardware module and related test equipment (such as digital input / digital output board, etc., if involved). The instruction will instruct the hardware module to feedback the second test data collected when executing the second test item. These data cover the excitation signal parameters received by the hardware module (such as input voltage amplitude, frequency, etc.), the real-time voltage and current conditions of each key node of the internal circuit, and the final output signal status, etc., which depends on the functional characteristics and test requirements of the hardware module itself.

[0101] The hardware module sends the corresponding second test data to the host computer through a test loop (which may be a data line directly connected to the host computer or a communication link transferred by an intermediate device) in accordance with the instruction requirements in accordance with the established data format, so as to facilitate subsequent analysis and processing by the host computer.

[0102] After receiving the first test data from the lower computer, the upper computer will preprocess the data, such as unifying the data format, removing invalid data, etc., to ensure that the data meets the requirements of the abnormal analysis model input. Then, the processed first test data is filled into the corresponding input variable positions one by one according to the input order and format specified by the model, for example, the key indicator data such as the packet loss rate and transmission delay of the communication module are filled into the corresponding input parameter positions in the model.

[0103] The abnormal analysis model calculates and infers the first test data input based on its internal trained logic and parameters (the correlation between working conditions and abnormal conditions built through a large amount of historical data training), and analyzes the possible causes of abnormality in the lower computer. For example, the model determines from the data that the communication protocol of the lower computer is misconfigured, resulting in transmission stability problems under specific working conditions, or that the lower computer processor has insufficient resource allocation when processing the communication task, and finally outputs the corresponding abnormal cause analysis results.

[0104] The host computer performs similar data preprocessing on the acquired second test data to ensure that the data quality and format meet the model requirements. The preprocessed second test data is accurately input into the abnormal analysis model, such as inputting the amplitude and frequency of the excitation signal of the hardware module and the voltage value of its internal key nodes into the corresponding input parameter position of the model. The abnormal analysis model analyzes and judges these data based on its own operation rules and the learned abnormal association rules of the hardware module to obtain the cause of the abnormality of the hardware module. For example, the model may determine that the performance of a certain capacitor element in the hardware module has deteriorated, resulting in a deterioration in the filtering effect of the input signal, thereby affecting its overall functional output, or because the amplitude of the input signal exceeds the normal working range of the hardware module, causing the internal circuit to have an abnormal working state, etc., and output the abnormal causes of these hardware modules to the host computer as the final analysis results, so that subsequent maintenance personnel can conduct targeted investigations and repairs based on these causes.

[0105] In an embodiment of the present application, the method also includes: diagnosing the abnormal cause of the lower computer and / or the abnormal cause of the hardware module, obtaining repair suggestion information corresponding to the abnormal cause of the lower computer and / or the abnormal cause of the hardware module; and repairing the lower computer and / or the hardware module according to the repair suggestion information.

[0106] Specifically, for the lower computer: after obtaining the abnormal cause of the lower computer, the diagnosis module in the upper computer will first classify and process it according to the cause type. For example, if the abnormal cause is at the software level, such as a logical error in a certain control program of the lower computer, the diagnosis module will call the built-in code analysis tool to perform static analysis on the relevant program code to check whether there are problems in the code structure, variable assignment, logical judgment and other links, and at the same time, combined with the functional requirements document corresponding to the program, determine what the correct logical direction should be.

[0107] If it is found that the condition setting of a conditional judgment statement in the code is unreasonable, resulting in the execution of the wrong branch under specific working conditions, thereby causing an exception, then the repair suggestion information may be to modify the specific condition value of this conditional judgment statement to make it conform to the expected functional logic.

[0108] If the abnormal reason is hardware-related, such as a hardware failure of a communication interface of the lower computer, the diagnostic module will query the hardware schematic diagram of the lower computer and the maintenance record knowledge base of similar failures in the past. From the schematic diagram, the circuit components, connection relationships and other information involved in the communication interface are determined, and then the solutions to similar communication failures in the maintenance records are referred to. For example, if the probability of interface chip damage is high, the repair suggestion information may be to replace the corresponding model of interface chip, and give specific replacement operation steps, including how to disassemble and weld, and safety precautions such as anti-static.

[0109] For hardware modules: After the cause of the hardware module abnormality is identified, the diagnostic module will also conduct targeted analysis. If the cause of the abnormality is that the performance of a capacitor component inside the hardware module has deteriorated, resulting in abnormal filtering function, the diagnostic module will first look up the detailed circuit design documents of the hardware module to determine the specific role of the capacitor in the entire circuit, its specifications and parameters, and its location.

[0110] Then, referring to the component selection manual and past hardware maintenance experience, repair suggestion information is generated. For example, it is recommended to use high-quality capacitors of the same specifications and models for replacement, and the key parameter requirements such as the capacitor's withstand voltage value and capacitance value are explained in detail. The key points for replacing capacitors are also attached, such as how to safely remove the old capacitors, the correct method of welding new capacitors, and the circuit detection steps after welding, etc., to ensure that the replacement operation can be completed accurately and the normal function of the hardware module is restored.

[0111] If the cause of the abnormality is an overall design defect of the hardware module, for example, the bandwidth design of a signal processing module is too narrow and cannot meet the signal frequency range requirements of the actual application scenario, the diagnostic module will give specific suggestions for modifying the circuit design and adjusting related component parameters (such as replacing inductors, resistors and other components to change the bandwidth of the circuit) based on professional circuit design theory and optimization cases of similar functional modules in the industry. At the same time, it will provide corresponding circuit simulation verification methods to help the subsequent hardware improvement work proceed smoothly.

[0112] If the repair suggestion information involves software-level modifications, such as updating program code, the developer will follow the suggestion and use the corresponding programming tool (such as a specific integrated development environment) to open the corresponding software project of the lower computer, locate the code location that needs to be modified, and edit the code according to the suggested modification content, such as changing the value of the conditional judgment statement, adding code comments to enhance code readability, etc. After the code modification is completed, operations such as compilation and linking will be performed to generate a new executable program file, and then the new program file will be safely transferred and burned to the storage unit of the lower computer through the program download channel between the upper computer and the lower computer, and then the lower computer will be restarted to observe its running status and verify whether the anomaly has been repaired.

[0113] If it involves hardware repair, the maintenance personnel will prepare the corresponding tools (such as screwdrivers, soldering irons, etc.) and replacement hardware components (such as interface chips, etc.) according to the repair suggestion information, and first power off the lower computer according to the recommended steps, open the device casing, carefully disassemble the faulty hardware components, and then accurately weld the new components to the corresponding positions. After welding, check the solder joints and test the circuit connectivity to ensure that the hardware connection is normal. Reassemble the lower computer, power it on, and check whether the previous abnormal situation has been eliminated, so as to complete the repair of the lower computer hardware failure.

[0114] When the repair suggestion information is to replace components, the maintenance personnel will prepare suitable replacement components according to the component specifications, models and other requirements mentioned in the suggestion. Then, use professional tools (such as heat guns, tweezers, etc. for surface mount components) and follow the recommended operating steps to power off the hardware module, remove the old components, and carefully install the new components to the corresponding positions, ensuring that the welding is firm and the pins are connected correctly. After that, use a multimeter or other testing tools to test the electrical performance of the circuit where the new component is located, such as measuring parameters such as voltage and resistance. After confirming that the circuit is normal, power on the hardware module again to observe whether its function has returned to normal and determine whether the abnormality has been repaired successfully.

[0115] If the repair suggestion is to improve the circuit design of the hardware module, the hardware engineer will redraw the circuit schematic according to the suggestion, adjust the parameters of related components, and use circuit simulation software to perform performance simulation verification on the improved circuit to ensure that it can meet the functional requirements. Then, a new hardware prototype is made according to the new schematic, and after replacing the original hardware module with the new prototype, an actual functional test is performed to check whether the previous abnormal phenomenon no longer occurs, thereby completing the repair work of the hardware module based on the design improvement.

[0116] In this embodiment, a test control device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0117] This embodiment provides a test control device, such as Figure 3 As shown, including:

[0118] The receiving module 301 is used to receive a test running instruction for a test client, wherein the test client is deployed on a host computer, and the host computer is connected to the slave computer and the hardware module respectively;

[0119] A response module 302 is used to respond to the test running instruction, run the test client, and obtain a test task, wherein the test task includes a first test item for the lower computer and a second test item for the hardware module;

[0120] The testing module 303 is used to test the lower computer according to the first test item to obtain a first test result, and to test the hardware module according to the second test item to obtain a second test result;

[0121] The generating module 304 is configured to generate a test report based on the first test result and the second test result.

[0122] In an embodiment of the present application, the test module 303 is used to send a first test instruction to a lower computer based on a first test item, wherein the lower computer is used to perform a test according to the first test instruction to obtain first test data; obtain the first test data obtained by testing the lower computer, and compare the first test data with a preset data range to obtain a first test result, wherein if the first test data falls within the preset data range, the first test result is that the lower computer is normal, or, if the first test data does not fall within the preset data range, the first test result is that the lower computer is abnormal.

[0123] In an embodiment of the present application, the test module 303 is used to generate signal configuration information based on the second test item; generate an excitation signal according to the configuration information through a digital input / digital output board; send the excitation signal to the hardware module through the digital input / digital output board, wherein, after the hardware module receives the excitation signal, the internal circuit of the hardware module processes the excitation signal according to the functional logic to obtain second test data, and feeds back the second test data to the host computer through the test loop; obtain the second test data fed back by the hardware module, and analyze whether the second test data meets the test conditions corresponding to the second test item to obtain a second test result, wherein, if the second test data does not meet the test conditions corresponding to the second test item, the second test result is that the function corresponding to the second test item of the hardware module is abnormal; or, if the second test data meets the test conditions corresponding to the second test item, the second test result is that the function corresponding to the second test item of the hardware module is normal.

[0124] In an embodiment of the present application, the test module 303 is used to obtain the test function corresponding to the second test item, and determine the signal level type and signal frequency corresponding to the test function; query the parameter configuration information of the hardware module, and determine the signal amplitude and signal duration based on the parameter configuration information; generate signal configuration information based on the signal level type, signal frequency, signal amplitude and signal duration.

[0125] In an embodiment of the present application, the device also includes: a construction module for obtaining first historical test data of the lower computer under different working conditions and second historical test data of the hardware module under different working conditions; analyzing the first correlation relationship between the abnormal data in the first historical test data and the different working conditions, and analyzing the second correlation relationship between the abnormal data in the second historical test data and the different working conditions; and constructing an abnormal analysis model based on the first correlation relationship and the second correlation relationship.

[0126] In an embodiment of the present application, the device also includes: a processing module, which is used to obtain first test data obtained by testing the lower computer according to the first test item and / or obtain second test data obtained by testing the hardware module according to the second test item when the first test result is an abnormality of the lower computer and / or the second test result is a functional abnormality corresponding to the daily test item of the hardware module; input the first test data and / or the second test data into the abnormality analysis model to obtain the abnormal cause of the lower computer and / or the abnormal cause of the hardware module.

[0127] In an embodiment of the present application, the device also includes: a diagnostic module, which is used to diagnose the abnormal cause of the lower computer and / or the abnormal cause of the hardware module, and obtain repair suggestion information corresponding to the abnormal cause of the lower computer and / or the abnormal cause of the hardware module; repair the lower computer and / or the hardware module according to the repair suggestion information.

[0128] See also Figure 4 , Figure 4 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 4 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 4 A processor 10 is taken as an example.

[0129] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0130] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0131] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of a computer device based on the presentation of a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0132] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0133] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0134] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0135] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A test control method, characterized in that: The method comprises: Receiving a test running instruction for a test client, wherein the test client is deployed on a host computer, and the host computer is connected to a slave computer and a hardware module respectively; In response to the test running instruction, the test client is run, and a test task is obtained, wherein the test task includes a first test item for the lower computer and a second test item for the hardware module; Testing the lower computer according to the first test item to obtain a first test result, and testing the hardware module according to the second test item to obtain a second test result; A test report is generated based on the first test result and the second test result.

2. The method according to claim 1, characterized in that The step of testing the lower computer according to the first test item to obtain a first test result includes: Sending a first test instruction to the lower computer based on the first test item, wherein the lower computer is used to perform a test according to the first test instruction to obtain first test data; Obtain first test data obtained by testing the lower computer, and compare the first test data with a preset data range to obtain the first test result, wherein if the first test data falls within the preset data range, the first test result is that the lower computer is normal, or, if the first test data does not fall within the preset data range, the first test result is that the lower computer is abnormal.

3. The method according to claim 1, characterized in that The step of testing the hardware module according to the second test item to obtain a second test result includes: generating signal configuration information based on the second test item; Generate an excitation signal according to the configuration information through a digital input / digital output board; Sending an excitation signal to the hardware module through the digital input / digital output board, wherein after the hardware module receives the excitation signal, the internal circuit of the hardware module processes the excitation signal according to the functional logic to obtain second test data, and feeds the second test data back to the host computer through the test loop; Obtain second test data fed back by the hardware module, and analyze whether the second test data meets the test conditions corresponding to the second test item, to obtain the second test result, wherein, if the second test data does not meet the test conditions corresponding to the second test item, then the second test result is that the function corresponding to the second test item of the hardware module is abnormal; or, if the second test data meets the test conditions corresponding to the second test item, then the second test result is that the function corresponding to the second test item of the hardware module is normal.

4. The method according to claim 3, characterized in that The generating signal configuration information based on the second test item includes: Obtaining a test function corresponding to the second test item, and determining a signal level type and a signal frequency corresponding to the test function; Query parameter configuration information of the hardware module, and determine the signal amplitude and signal duration based on the parameter configuration information; The signal configuration information is generated based on the signal level type, the signal frequency, the signal amplitude, and the signal duration.

5. The method according to claim 1, characterized in that The method further comprises: Acquire first historical test data of the slave computer under different working conditions and second historical test data of the hardware module under different working conditions; Analyzing a first correlation between abnormal data in the first historical test data and different operating conditions, and analyzing a second correlation between abnormal data in the second historical test data and different operating conditions; An abnormality analysis model is constructed based on the first association relationship and the second association relationship.

6. The method according to claim 5, characterized in that The method further comprises: When the first test result is that the lower computer is abnormal, and / or the second test result is that the function corresponding to the daily test item of the hardware module is abnormal, obtaining first test data obtained by testing the lower computer according to the first test item, and / or obtaining second test data obtained by testing the hardware module according to the second test item; The first test data and / or the second test data are input into the abnormality analysis model to obtain the abnormality cause of the lower computer and / or the abnormality cause of the hardware module.

7. The method according to claim 6, characterized in that The method further comprises: Diagnose the abnormal cause of the lower computer and / or the abnormal cause of the hardware module, and obtain repair suggestion information corresponding to the abnormal cause of the lower computer and / or the abnormal cause of the hardware module; Repair the lower computer and / or the hardware module according to the repair suggestion information.

8. A test control device, characterized in that: The device comprises: A receiving module, used for receiving a test running instruction for a test client, wherein the test client is deployed on a host computer, and the host computer is connected to a slave computer and a hardware module respectively; A response module, used to respond to the test running instruction, run the test client, and obtain a test task, wherein the test task includes a first test item for the lower computer and a second test item for the hardware module; A test module, configured to test the lower computer according to the first test item to obtain a first test result, and to test the hardware module according to the second test item to obtain a second test result; A generating module is used to generate a test report based on the first test result and the second test result.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 7.

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