Vector instruction processing method and device, electronic equipment and storage medium

Abstract

The invention provides a vector instruction processing method and device, electronic equipment and a storage medium, and relates to the technical field of data processing.The method comprises the steps that a null item is distributed for a vector instruction in an instruction sequencing queue, the vector instruction is split into vector instruction internal operation corresponding to each data element in the vector instruction, and the vector instruction internal operation corresponds to each data element in the vector instruction; performing register renaming on the internal operation of each vector instruction, respectively distributing an empty item for the internal operation of each vector instruction in the vector instruction sequencing queue, executing the internal operation of each vector instruction out of order, writing the internal operation of each vector instruction back to an item corresponding to the internal operation of each vector instruction in the vector instruction sequencing queue, and writing the internal operation of each vector instruction back to the item corresponding to the internal operation of each vector instruction in the vector instruction sequencing queue. And writing the vector instruction back to an item corresponding to the vector instruction in the instruction sequencing queue. The invention provides a vector instruction processing method and device, electronic equipment and a storage medium, which can more reasonably utilize computing resources of a processor so as to reduce the computing resources of the processor required to be occupied by vector instruction processing.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a vector instruction processing method, device, electronic equipment and storage medium. Background Art

[0002] With the rapid development of artificial intelligence and big data technologies, users have put forward higher and higher requirements on the performance of artificial intelligence algorithms and data analysis applications, and therefore the requirements on computer processing capabilities are also getting higher and higher. Vector processing technology has become a hot technology that is of common concern to academia and industry because it can process multiple data with one instruction, provide data-level parallelism, and thus greatly improve data processing efficiency.

[0003] The bit width of a vector instruction indicates the total width of data that can be processed by a single vector instruction at one time. The bit width of a vector instruction is relatively large, usually up to 128 bits, 256 bits, or 512 bits. The high parallelism and complexity of vector instruction processing result in more processor computing resources being required for vector instruction processing, which has a significant impact on the processor's main frequency, chip area, and power consumption.

[0004] Therefore, how to reduce the processor computing resources required for vector instruction processing, thereby improving the performance stability of the processor and reducing the operating cost and manufacturing cost of the processor, is a technical problem that needs to be urgently solved in this field. Summary of the invention

[0005] The present invention provides a vector instruction processing method, device, electronic device and storage medium, which are used to solve the defects of the prior art in that the high parallelism and complexity of vector instruction processing result in a large number of processor computing resources required for vector instruction processing, which has a significant impact on the processor's main frequency, chip area, power consumption and other performance, and reduces the processor computing resources required for vector instruction processing, thereby improving the performance stability of the processor and reducing the operating cost and manufacturing cost of the processor.

[0006] The present invention provides a vector instruction processing method, comprising the following steps.

[0007] When a vector instruction enters a vector instruction emission queue, a blank item is allocated to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue; the vector instruction is split into vector instruction internal operations corresponding to each data element in the vector instruction, registers are renamed for the vector instruction internal operations corresponding to each data element, and a blank item is allocated to each vector instruction internal operation corresponding to the data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue; the vector instruction internal operations corresponding to each data element are executed in disorder; after the vector instruction internal operation corresponding to each data element is written back to the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue, the vector instruction is written back to the item corresponding to the vector instruction in the instruction sequencing queue.

[0008] According to a vector instruction processing method provided by the present invention, the out-of-order execution of the vector instruction internal operations corresponding to each of the data elements includes: adding the vector instruction internal operations corresponding to each of the data elements to a vector instruction internal operation emission queue, and the vector instruction internal operation emission queue, when determining that the source operands of the vector instruction internal operations corresponding to each of the data elements are ready, uses an out-of-order emission mechanism to emit the vector instruction internal operations corresponding to each of the data elements, so that the vector instruction internal operations corresponding to each of the data elements can read the vector register stack and obtain the value of the source operand of the vector instruction internal operations corresponding to each of the data elements; based on the operation type of the vector instruction internal operations corresponding to each of the data elements, respectively assigning the vector instruction internal operations corresponding to each of the data elements to different execution units, so that the different execution units can execute the vector instruction internal operations corresponding to each of the data elements based on the value of the source operand of the vector instruction internal operations corresponding to each of the data elements.

[0009] According to a vector instruction processing method provided by the present invention, the vector instruction is split into vector instruction internal operations corresponding to each data element in the vector instruction, including: based on the configuration information of the vector control and status register of the vector instruction and the vector instruction operation code of the vector instruction, the vector instruction is split into vector instruction internal operations corresponding to each data element.

[0010] According to a vector instruction processing method provided by the present invention, after writing the vector instruction back to the item corresponding to the vector instruction in the instruction sequencing queue, the method further comprises: submitting the vector instruction in sequence through the instruction sequencing queue; The instruction sequencing queue is notified to release the item corresponding to the vector instruction in the instruction sequencing queue, and the vector instruction sequencing queue is notified to release the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue.

[0011] According to a vector instruction processing method provided by the present invention, the method also includes: when a scalar instruction enters a scalar instruction emission queue, an empty item is allocated to the scalar instruction in the instruction sequencing queue as the item corresponding to the scalar instruction in the instruction sequencing queue; the scalar instruction is added to the scalar instruction emission queue, and the scalar instruction emission queue emits the scalar instruction when it is determined that the source operand of the scalar instruction is ready, so that the scalar instruction reads a scalar register stack and obtains the value of the source operand of the scalar instruction; the scalar instruction is allocated to an execution unit, so that the execution unit executes the scalar instruction based on the value of the source operand of the scalar instruction; and the scalar instruction is written back to the item corresponding to the scalar instruction in the instruction sequencing queue.

[0012] According to a vector instruction processing method provided by the present invention, the method also includes: in the event that a prediction execution error occurs in the processor, based on the vector instruction sequencing queue and / or the instruction sequencing queue, obtaining the sequential relationship between the erroneous instruction in which the prediction execution error occurs and other instructions; based on the sequential relationship between the erroneous instruction and other instructions, restoring the state information of the processor to the state information before executing the erroneous instruction, the state information of the processor including the register renaming relationship.

[0013] According to a vector instruction processing method provided by the present invention, after allocating an empty item for the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue, the method further includes: determining the identification information of the item corresponding to the vector instruction in the instruction sequencing queue as the sequence identification information of the vector instruction; before writing the vector instruction back to the item corresponding to the vector instruction in the instruction sequencing queue, the method further includes: determining the item corresponding to the vector instruction in the instruction sequencing queue based on the sequence identification information of the vector instruction.

[0014] According to a vector instruction processing method provided by the present invention, after allocating an empty item to each vector instruction internal operation corresponding to the data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue, the method further includes: determining the identification information of the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue as the sequence identification of the vector instruction internal operation corresponding to each data element; before writing the vector instruction internal operation corresponding to each data element back to the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue, the method further includes: determining the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue based on the sequence identification of the vector instruction internal operation corresponding to each data element.

[0015] The present invention also provides a vector instruction processing device, comprising the following modules.

[0016] The first sequencing module is used for allocating an empty item for the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue when the vector instruction enters the vector instruction issuing queue.

[0017] The second sequencing module is used to split the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction, rename the registers of the vector instruction internal operations corresponding to each data element, and allocate an empty item to each vector instruction internal operation corresponding to the data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue.

[0018] The operation execution module is used to execute the vector instruction internal operation corresponding to each of the data elements out of order.

[0019] The instruction write-back module is used to write the vector instruction internal operation corresponding to each of the data elements back to the item corresponding to the vector instruction internal operation corresponding to each of the data elements in the vector instruction sequencing queue, and then write the vector instruction back to the item corresponding to the vector instruction in the instruction sequencing queue.

[0020] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, any of the above-mentioned vector instruction processing methods is implemented.

[0021] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the vector instruction processing method described above is implemented.

[0022] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned vector instruction processing methods.

[0023] The vector instruction processing method, device, electronic device and storage medium provided by the present invention allocate an empty item to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue when the vector instruction enters the vector instruction emission queue, and then split the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction, rename the registers of the vector instruction internal operations corresponding to each data element, allocate an empty item to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue, and after the vector instruction internal operations corresponding to each data element are executed out of order, each data element is After the internal operation of the vector instruction corresponding to the element is written back to the item corresponding to the internal operation of the vector instruction corresponding to each data element in the vector instruction sequencing queue, the vector instruction is written back to the item corresponding to the vector instruction in the instruction sequencing queue. Based on the above-mentioned multi-level sequencing queue, the out-of-order execution and sequential submission of the internal operation of the vector instruction corresponding to each data element in the vector instruction can be realized, and the computing resources of the processor can be more reasonably utilized, thereby reducing the computing resources of the processor required for vector instruction processing, improving the performance stability of the processor, reducing the operating cost and manufacturing cost of the processor, and improving the execution efficiency of the internal operation of the vector instruction corresponding to each data element in the vector instruction, thereby improving the processing efficiency and throughput of the vector instruction, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 It is a field distribution diagram of the vector type in the related art.

[0026] Figure 2 This is one of the flow charts of the vector instruction processing method provided by the present invention.

[0027] Figure 3This is the second flow chart of the vector instruction processing method provided by the present invention.

[0028] Figure 4 It is a structural schematic diagram of the vector instruction processing device provided by the present invention.

[0029] Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] In the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are usually a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, in the description of the present application, "and / or" represents at least one of the connected objects, and the character " / " generally represents that the front and back associated objects are in an "or" relationship.

[0033] It should be noted that RISC-V (Reduced Instruction Set Computing-Five, the fifth generation of reduced instruction set) is currently a widely used open source reduced instruction set. The vector extension instruction set specification of the RISC-V instruction set, riscv-v-spec (RISC-V Vector Extension, RVV), is an important extension of the RISC-V architecture, which aims to improve the parallel processing performance of the processor. RVV can support vector operations of various bit widths and allow dynamic adjustment of vector length to flexibly adapt to different application requirements.

[0034] The RISC-V vector instruction set RVV contains a vector control and status register (CSR) and a vector register. The vector CSR is used to store configuration information, including vector length and operation bit width, and the vector register is used to store vectorized operation data.

[0035] RVV specifies that 32 vector registers (denoted as v0-v31, all with a bit width of VLEN) and 7 non-privileged CSRs (vstart, vxsat, vxrm, vcsr, vl, vtype, and vlenb, all with a bit width of XLEN) are extended on the basis of the basic spec (Specification). Among them, VLEN refers to the length of a vector register (Vector Length, VLEN); XLEN refers to the length of a vector control and status register.

[0036] In the configuration information stored in the vector CSR, vtype (vector type) is used to indicate the default type of the vector register content. The vector type also determines the arrangement of elements in each vector register and how to group multiple vector registers. Figure 1 This is a field distribution diagram of the vector type in the related technology. The fields included in the vector type are as follows: Figure 1 shown.

[0037] It should be noted that Figure 1 The vlmul[2:0] in the _DML_PAGE_STRING indicates vector register grouping. Multiple vector registers can be grouped together so that a single vector instruction can operate on multiple vector registers.

[0038] LMUL points to the number of logical lanes in the vector register (Lane Multiplication Factor). vlmul represents a signed number. The value of LMUL can be a fractional number in addition to an integer, which reduces the number of bits used in a single vector register. LMUL=2 vlmul[2:0]. Fractional grouping is mainly used for mixed width instruction operations. Therefore, the value of LMUL can be 1 / 8, 1 / 4, 1 / 2, 1, 2, 4, 8. The corresponding relationship between LMUL and vlmul is shown in Table 1: Table 1 Correspondence between LMUL and vlmul

[0039] vsew[2:0] indicates the width of each element in the vector register. The vector register is considered to be divided into VLEN / SEW standard width elements. SEW refers to the standard width of a single data element (Select Element Width, SEW).

[0040] The corresponding relationship between SEW and vsew is shown in Table 2: Table 2 Correspondence between SEW and vsew

[0041] Figure 1 In the , reserved means that the field is reserved, that is, it is not used in the current version of the instruction set. Reserved fields are usually used for future expansion or compatibility considerations; vma (vector mask agnostic) means vector mask agnostic; vta (vector tail agnostic) means vector tail agnostic; vill is set to indicate that an illegal vtype value is set.

[0042] A vector instruction usually includes multiple data elements, and the data elements in the vector instruction are the basic units of vector instruction processing. When the processor processes a vector instruction, the processor can perform arithmetic operations, logical operations or other operations on each data element in the vector instruction at the same time.

[0043] The number of data elements in a vector instruction is determined by the vector control and status register and the type of the vector instruction. The number of data elements in a vector instruction = VLEN × LMUL / SEW. For example, when the length of the vector source register corresponding to the vector instruction is 256 bits, the number of logical channels of the above vector source register is 8, and the standard width of the data elements in the above vector source register is 16 bits, the number of data elements in the above vector instruction is 128.

[0044] When the processor processes vector instructions, it needs to complete a large number of computing tasks in a short period of time. The high parallelism and complexity of vector instruction processing result in more processor computing resources being required for vector instruction processing, which has a significant impact on the processor's main frequency, chip area, power consumption and other performance.

[0045] For example, in order to support the parallel calculation of multiple data elements in vector instructions, multiple execution units in the processor are required to perform parallel calculations. However, when multiple execution units perform parallel calculations, the dynamic power consumption of the processor increases sharply. For another example, after a vector instruction is executed, if the results of multiple data elements in the vector instruction need to be written back to different vector registers, a multi-port and wide-bit-width register stack is required to support parallel writing. A multi-port and wide-bit-width register stack needs to be configured with more transistors, thereby occupying more chip area, increasing static power consumption and chip manufacturing costs. In addition, writing the results of multiple data elements back to different vector registers will also cause a surge in the dynamic power consumption of the processor. For example, the bit width of vector instructions is relatively large, which means that the data path in the processor that supports vector instructions requires wider connections (such as ALU or bus, etc.), which takes up more chip area. In addition, the wiring design of wide data paths is difficult, which can easily lead to the extension of data transmission paths and increased wiring complexity, which in turn leads to data transmission delays. The processor's main frequency is limited by the data transmission delay, and in actual operation, the processor may need to reduce the frequency to ensure operational stability.

[0046] Therefore, how to reduce the processor computing resources required for vector instruction processing, thereby improving the performance stability of the processor and reducing the operating cost and manufacturing cost of the processor, is a technical problem that needs to be urgently solved in this field.

[0047] In this regard, the present invention provides a vector instruction processing method. The vector instruction processing method provided by the present invention splits a vector instruction into multiple vector instruction internal operations inside a processor, and through a multi-level sequence queue, it can be realized that the multiple vector instruction internal operations split from the vector instruction can be executed in disorder and efficiently, and the vector instruction and the scalar instruction can also be executed in disorder and efficiently, thereby realizing the disorder execution and sequential submission of the vector instruction and the scalar instruction, and achieving the goals of high performance, high main frequency, low power consumption and low cost of the processor.

[0048] Combine the following Figure 2-Figure 3 The vector instruction processing method provided by the present invention is described.

[0049] Figure 2 FIG. 1 is one of the flow charts of the vector instruction processing method provided by the present invention. Figure 2 As shown, the method includes the following steps: Step 201: when a vector instruction enters a vector instruction issuing queue, an empty item is allocated to the vector instruction in the instruction sequencing queue as an item corresponding to the vector instruction in the instruction sequencing queue.

[0050] It should be noted that the execution subject of the embodiment of the present invention is a vector instruction processing device, and the vector instruction processing device may be a processor. When executing the vector instruction processing method provided by the present invention, the above processor may process the vector instruction.

[0051] It should be noted that, before the vector instruction in the embodiment of the present invention enters the vector instruction issue queue, register renaming has been completed in the main pipeline.

[0052] It should be noted that the instruction ordering queue in the embodiment of the present invention is shared by vector instructions and scalar instructions. The above instruction ordering queue can ensure that instructions can be submitted in the original order when they are executed out of order.

[0053] Figure 3 FIG. 2 is a flow chart of the vector instruction processing method provided by the present invention. Figure 3 As shown, the vector instruction enters the vector instruction issue queue after completing register renaming in the mainstream pipeline.

[0054] When a vector instruction enters a vector instruction issuance queue, an empty item may be allocated to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue, and the identification information of the item corresponding to the vector instruction in the instruction sequencing queue may be determined as the sequence identification information of the vector instruction.

[0055] It should be noted that, in the embodiment of the present invention, an empty item may be allocated to the above-mentioned vector instruction in the instruction sequencing queue according to the arrangement order of the empty items in the instruction sequencing queue, as the item corresponding to the above-mentioned vector instruction in the instruction sequencing queue.

[0056] Step 202: split the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction, rename the registers for the vector instruction internal operations corresponding to each data element, and allocate an empty item to each vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue.

[0057] Specifically, in the embodiment of the present invention, based on each data element in the vector instruction, the vector instruction may be split into vector instruction internal operations corresponding to each data element in the vector instruction.

[0058] As an optional embodiment, the vector instruction is split into vector instruction internal operations corresponding to each data element in the vector instruction, including: based on the configuration information of the vector control and status register of the vector instruction and the vector instruction opcode of the vector instruction, the vector instruction is split into vector instruction internal operations corresponding to each data element.

[0059] It should be noted that the vector instruction opcode of the vector instruction is used to identify the vector operation type of the vector instruction, such as load (ie, fetching data) and store (ie, storing data), as well as the data elements in the vector instruction.

[0060] It should be noted that the RISC-V vector extension introduces a series of vector control and status registers to configure the execution environment of vector instructions, manage the status information of vector processing, and provide fine control over vector operations. The above-mentioned vector control and status registers usually include a vector length register (VLEN), a vector type register (VTYPE), a vector start register (VSTART), etc. The above-mentioned vector control and status registers jointly determine the behavior and performance of vector instructions. Therefore, the configuration information of the vector control and status registers of vector instructions can be used to indicate the vector length and type, the starting position of the vector operation, the execution environment of the vector operation, and exception and interrupt handling.

[0061] Based on the configuration information of the vector control and status register of the vector instruction and the vector instruction operation code of the vector instruction, the above vector instruction can be split into vector instruction internal operations corresponding to each data element in the above vector instruction.

[0062] After splitting the above-mentioned vector instruction into vector instruction internal operations corresponding to each data element in the above-mentioned vector instruction, the registers of the vector instruction internal operations corresponding to each data element in the above-mentioned vector instruction can be renamed, and corresponding physical registers can be found for the source register and destination register of the vector instruction internal operations corresponding to each data element in the above-mentioned vector instruction, and the destination register of the vector instruction internal operations corresponding to each data element in the above-mentioned vector instruction can be mapped to an idle physical register.

[0063] After register renaming of the vector instruction internal operation corresponding to each data element in the above-mentioned vector instruction, an empty item can be allocated to the vector instruction internal operation corresponding to each data element in the above-mentioned vector instruction in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operation corresponding to each data element in the above-mentioned vector instruction in the vector instruction sequencing queue, and the identification information of the item corresponding to the vector instruction internal operation corresponding to each data element in the above-mentioned vector instruction in the vector instruction sequencing queue is determined as the sequence identification information of the vector instruction internal operation corresponding to each data element in the above-mentioned vector instruction.

[0064] It should be noted that the vector instruction sequencing queue in the embodiment of the present invention is dedicated to vector instructions. The above vector instruction sequencing queue can ensure that the vector instructions can be submitted in the original order when they are executed out of order.

[0065] It should be noted that, in an embodiment of the present invention, according to the arrangement order of the empty items in the vector instruction sequencing queue, an empty item can be allocated in the vector instruction sequencing queue for the vector instruction internal operation corresponding to each data element in the above-mentioned vector instruction, as the item corresponding to the vector instruction internal operation corresponding to each data element in the above-mentioned vector instruction in the vector instruction sequencing queue.

[0066] Step 203: Execute the internal operations of the vector instructions corresponding to each data element out of order.

[0067] Specifically, after determining the item corresponding to the vector instruction internal operation corresponding to each data element in the above vector instruction in the vector instruction sequencing queue, the vector instruction internal operation corresponding to each data element in the above vector instruction can be executed in disorder to obtain the result data of the vector instruction internal operation corresponding to each data element in the above vector instruction.

[0068] As an optional embodiment, the vector instruction internal operation corresponding to each data element is executed out of order, including: adding the vector instruction internal operation corresponding to each data element to the vector instruction internal operation emission queue, and the vector instruction internal operation emission queue uses an out of order emission mechanism to emit the vector instruction internal operation corresponding to each data element when it is determined that the source operands of the vector instruction internal operation corresponding to each data element are ready, so that the vector instruction internal operation corresponding to each data element reads the vector register stack and obtains the value of the source operand of the vector instruction internal operation corresponding to each data element.

[0069] Based on the operation type of the vector instruction internal operation corresponding to each data element, the vector instruction internal operation corresponding to each data element is respectively allocated to different execution units, so that the different execution units can execute the vector instruction internal operation corresponding to each data element based on the value of the source operand of the vector instruction internal operation corresponding to each data element.

[0070] Step 204: After writing the vector instruction internal operation corresponding to each data element back to the entry corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue, write the vector instruction back to the entry corresponding to the vector instruction in the instruction sequencing queue.

[0071] Specifically, after executing the vector instruction internal operation corresponding to each data element, the vector instruction internal operation corresponding to each data element in the above vector instruction can be written back to the item corresponding to the vector instruction internal operation corresponding to each data element in the above vector instruction in the vector instruction sequencing queue based on the sequence identification information of the vector instruction internal operation corresponding to each data element in the above vector instruction.

[0072] When it is determined that the vector instruction internal operation corresponding to each data element has been written back to the item corresponding to the vector instruction internal operation corresponding to each data element in the above vector instruction in the vector instruction sequencing queue, the vector instruction can be written back to the item corresponding to the vector instruction in the instruction sequencing queue based on the sequence identification information of the above vector instruction.

[0073] As an optional embodiment, after writing the vector instruction back to the item corresponding to the vector instruction in the instruction sequencing queue, the method further includes: submitting the vector instruction in sequence through the instruction sequencing queue.

[0074] Notify the instruction sequencing queue to release the item corresponding to the vector instruction in the instruction sequencing queue.

[0075] As an optional embodiment, after writing the vector instruction back to the entry corresponding to the vector instruction in the instruction sequencing queue, the method further includes: notifying the vector instruction sequencing queue to release the entry corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue.

[0076] It is understandable that any vector instruction internal operation in the vector instruction occupies an entry in the vector instruction sequencing queue after register renaming and before the vector instruction is submitted. After the vector instruction performs register renaming in the main pipeline, it occupies an entry in the instruction sequencing queue until the above vector instruction is submitted.

[0077] In the embodiment of the present invention, when a vector instruction enters a vector instruction emission queue, an empty item is allocated to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue, and then the vector instruction is split into vector instruction internal operations corresponding to each data element in the vector instruction, and the registers of the vector instruction internal operations corresponding to each data element are renamed, and an empty item is allocated to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue, and after the vector instruction internal operations corresponding to each data element are executed out of order, the vector instruction internal operations corresponding to each data element are renamed. After the operation is written back to the item corresponding to the internal operation of the vector instruction corresponding to each data element in the vector instruction sequencing queue, the vector instruction is written back to the item corresponding to the vector instruction in the instruction sequencing queue. Based on the above-mentioned multi-level sequencing queue, the out-of-order execution and sequential submission of the internal operation of the vector instruction corresponding to each data element in the vector instruction can be realized, and the computing resources of the processor can be more reasonably utilized, thereby reducing the computing resources of the processor required for vector instruction processing, improving the performance stability of the processor, reducing the operating cost and manufacturing cost of the processor, and improving the execution efficiency of the internal operation of the vector instruction corresponding to each data element in the vector instruction, thereby improving the processing efficiency and throughput of the vector instruction, and has broad application prospects.

[0078] As an optional embodiment, the method further includes: when the scalar instruction enters the scalar instruction issue queue, allocating an empty item for the scalar instruction in the instruction sequencing queue as the item corresponding to the scalar instruction in the instruction sequencing queue.

[0079] It should be noted that, before the scalar instruction in the embodiment of the present invention enters the scalar instruction issue queue, register renaming has been completed in the main pipeline.

[0080] When a scalar instruction enters a scalar instruction issuance queue, an empty item may be allocated to the scalar instruction in the instruction sequencing queue as the item corresponding to the scalar instruction in the instruction sequencing queue, and the identification information of the item corresponding to the scalar instruction in the instruction sequencing queue may be determined as the sequence identification information of the scalar instruction.

[0081] It should be noted that, in the embodiment of the present invention, an empty item may be allocated to the scalar instruction in the instruction sequencing queue according to the arrangement order of the empty items in the instruction sequencing queue, as the item corresponding to the scalar instruction in the instruction sequencing queue.

[0082] The scalar instruction is added to the scalar instruction issuance queue, and the scalar instruction issuance queue issues the scalar instruction when determining that the source operand of the scalar instruction is ready, so that the scalar instruction reads the scalar register stack to obtain the value of the source operand of the scalar instruction.

[0083] The scalar instruction is dispatched to the execution unit for the execution unit to execute the scalar instruction based on the value of the source operand of the scalar instruction.

[0084] Write the scalar instruction back to the entry corresponding to the scalar instruction in the instruction sequencing queue.

[0085] In the embodiment of the present invention, the order between all instructions is maintained by the instruction sequencing queue, including the order between vector instructions and vector instructions, between vector instructions and scalar instructions, and between scalar instructions and scalar instructions. The vector instruction sequencing queue maintains the order between the internal operations of the vector instructions corresponding to multiple data elements in the vector instructions, ensuring that all the internal operations of multiple vector instructions obtained by splitting a vector instruction are written back, which can more reasonably utilize the computing resources of the processor. The order of the two types of instructions is uniformly maintained by the instruction sequencing queue, which can better avoid execution conflicts or data inconsistencies. Under the premise of ensuring program correctness, the parallelism of instruction execution can be maximized. By separating the order management of scalar instructions and vector instructions, the hardware design is simplified and the scalability and maintainability of the processor are improved.

[0086] As an optional embodiment, the method further includes: when a prediction execution error occurs in the processor, based on the vector instruction sequencing queue and / or the instruction sequencing queue, obtaining a sequence relationship between the erroneous instruction that has the prediction execution error and other instructions.

[0087] Based on the sequential relationship between the erroneous instruction and other instructions, the state information of the processor is restored to the state information before the erroneous instruction is executed, the state information of the processor includes the register renaming relationship, and the processor is the execution subject of the method.

[0088] It should be noted that in order to improve performance, processors in related technologies usually use prediction mechanisms such as branch prediction, memory address prediction, and value prediction when processing instructions. The above prediction mechanisms allow the processor to execute subsequent instructions in advance when the result is not yet determined, thereby making full use of pipeline and hardware resources. Among them, branch prediction can predict the direction (jump or not) of branch instructions (such as conditional jumps); memory address prediction can predict the memory address or data dependency accessed by memory access instructions (such as Load / Store). Value prediction can predict the result value of certain instructions (such as Load instructions).

[0089] A processor mispredicts execution, which means that when the processor is processing a certain instruction, the processor's prediction is inconsistent with the actual result, causing the processor to execute the wrong instruction or use the wrong data. Common mispredicts execution errors include branch prediction errors, memory access instruction related prediction errors, and memory access instruction value prediction errors. Among them, a branch prediction error means that the processor predicts the wrong direction of a branch instruction, resulting in the execution of the wrong instruction path. A memory access instruction related prediction error means that the processor predicts the address or data correlation of a memory access instruction (such as Load / Store) incorrectly, resulting in data conflicts or errors. A memory access instruction value prediction error means that the processor predicts the result value of a memory access instruction (such as a Load instruction) incorrectly, resulting in the use of incorrect data in subsequent instructions.

[0090] In an embodiment of the present invention, when a prediction execution error occurs in the processor, the sequence relationship between the erroneous instruction that occurs the prediction execution error and other instructions can be obtained based on the sequence relationship between the internal operations of the vector instructions corresponding to the data elements in the vector instructions maintained by the vector instruction sequencing queue, and / or the sequence relationship between the instructions maintained by the instruction sequencing queue, and then based on the above sequence relationship, the state information of the processor can be restored to the state information before the execution of the erroneous instruction.

[0091] Optionally, the state information of the processor in the embodiment of the present invention may also include a program counter.

[0092] The embodiments of the present invention can ensure the accuracy of processor state recovery by restoring the processor state in a vector instruction sequencing queue and / or an instruction sequencing queue when a predicted execution error occurs in the processor, better predict the impact of the execution error on the subsequent instruction execution, reduce the pause time of the pipeline, thereby improving the overall execution efficiency of the processor, and enhance the fault tolerance of the processor when handling predicted execution errors, thereby ensuring the continuous and stable operation of the processor.

[0093] Figure 4 Schematic diagram of the structure of the vector instruction processing device provided by the present invention. Figure 4 The vector instruction processing device provided by the present invention is described. The vector instruction processing device described below and the vector instruction processing method provided by the present invention described above can be referred to each other. Figure 4 As shown, the device includes: a first sequencing module 401 , a second sequencing module 402 , an operation execution module 403 and an instruction write-back module 404 .

[0094] The first sequencing module 401 is used to allocate an empty item in the instruction sequencing queue for the vector instruction when the vector instruction enters the vector instruction issuing queue, as the item corresponding to the vector instruction in the instruction sequencing queue.

[0095] The second sequencing module 402 is used to split the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction, rename the registers of the vector instruction internal operations corresponding to each data element, and allocate an empty item to each vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue.

[0096] The operation execution module 403 is used to execute the internal operations of the vector instructions corresponding to each data element out of order.

[0097] The instruction write-back module 404 is used to write the vector instruction internal operation corresponding to each data element back to the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue, and then write the vector instruction back to the item corresponding to the vector instruction in the instruction sequencing queue.

[0098] Specifically, the first sequencing module 401 , the second sequencing module 402 , the operation execution module 403 and the instruction write-back module 404 are electrically connected.

[0099] The vector instruction processing device in the embodiment of the present invention allocates an empty item to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue when the vector instruction enters the vector instruction emission queue, and then splits the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction, renames the registers for the vector instruction internal operations corresponding to each data element, allocates an empty item to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue, and after executing the vector instruction internal operations corresponding to each data element in a disorderly manner, the vector instruction internal operations corresponding to each data element are renamed. After the internal operation of the vector instruction is written back to the item corresponding to the internal operation of the vector instruction corresponding to each data element in the vector instruction sequencing queue, the vector instruction is written back to the item corresponding to the vector instruction in the instruction sequencing queue. Based on the above-mentioned multi-level sequencing queue, the out-of-order execution and sequential submission of the internal operation of the vector instruction corresponding to each data element in the vector instruction can be realized, and the computing resources of the processor can be more reasonably utilized, thereby reducing the computing resources of the processor required for vector instruction processing, improving the performance stability of the processor, reducing the operating cost and manufacturing cost of the processor, and improving the execution efficiency of the internal operation of the vector instruction corresponding to each data element in the vector instruction, thereby improving the processing efficiency and throughput of the vector instruction, and has broad application prospects.

[0100] Figure 5 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 5As shown, the electronic device may include: a processor (processor) 510, a communication interface (Communications Interface) 520, a memory (memory) 530 and a communication bus 540, wherein the processor 510, the communication interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 can call the logic instructions in the memory 530 to execute the vector instruction processing method, which includes: when the vector instruction enters the vector instruction emission queue, a blank item is allocated to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue; the vector instruction is split into vector instruction internal operations corresponding to each data element in the vector instruction, registers are renamed for the vector instruction internal operations corresponding to each data element, and a blank item is allocated to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue; the vector instruction internal operations corresponding to each data element are executed out of order; after the vector instruction internal operations corresponding to each data element are written back to the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue, the vector instruction is written back to the item corresponding to the vector instruction in the instruction sequencing queue.

[0101] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0102] Optionally, the electronic device in the embodiment of the present invention may be a processor.

[0103] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the vector instruction processing method provided by the above methods, which method includes: when a vector instruction enters a vector instruction emission queue, a blank item is allocated to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue; the vector instruction is split into vector instruction internal operations corresponding to each data element in the vector instruction, registers are renamed for the vector instruction internal operations corresponding to each data element, and a blank item is allocated to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue; the vector instruction internal operations corresponding to each data element are executed out of order; after the vector instruction internal operations corresponding to each data element are written back to the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue, the vector instruction is written back to the item corresponding to the vector instruction in the instruction sequencing queue.

[0104] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the vector instruction processing method provided by the above methods is implemented, the method comprising: when a vector instruction enters a vector instruction emission queue, a blank item is allocated to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue; the vector instruction is split into vector instruction internal operations corresponding to each data element in the vector instruction, registers are renamed for the vector instruction internal operations corresponding to each data element, a blank item is allocated to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue as the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue; the vector instruction internal operations corresponding to each data element are executed out of order; after the vector instruction internal operations corresponding to each data element are written back to the item corresponding to the vector instruction internal operations corresponding to each data element in the vector instruction sequencing queue, the vector instruction is written back to the item corresponding to the vector instruction in the instruction sequencing queue.

[0105] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0106] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vector instruction processing method, characterized in that: include: In the case where a vector instruction enters the vector instruction issue queue, an empty item is allocated to the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue; Splitting the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction, performing register renaming on the vector instruction internal operations corresponding to each data element, and respectively allocating an empty item to each vector instruction internal operation corresponding to the data element in the vector instruction sequencing queue as an item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue; Execute the vector instruction internal operations corresponding to each of the data elements out of order; After writing the vector instruction internal operation corresponding to each of the data elements back to the entry corresponding to the vector instruction internal operation corresponding to each of the data elements in the vector instruction sequencing queue, the vector instruction is written back to the entry corresponding to the vector instruction in the instruction sequencing queue.

2. The vector instruction processing method according to claim 1, characterized in that: The out-of-order execution of the vector instruction internal operations corresponding to the data elements includes: Adding the vector instruction internal operation corresponding to each of the data elements into a vector instruction internal operation emission queue, and the vector instruction internal operation emission queue, when determining that the source operands of the vector instruction internal operation corresponding to each of the data elements are ready, uses a disorderly emission mechanism to emit the vector instruction internal operation corresponding to each of the data elements, so that the vector instruction internal operation corresponding to each of the data elements reads a vector register stack and obtains the value of the source operand of the vector instruction internal operation corresponding to each of the data elements; Based on the operation type of the vector instruction internal operation corresponding to each of the data elements, the vector instruction internal operation corresponding to each of the data elements is respectively allocated to different execution units, so that the different execution units can execute the vector instruction internal operation corresponding to each of the data elements based on the value of the source operand of the vector instruction internal operation corresponding to each of the data elements.

3. The vector instruction processing method according to claim 1, characterized in that: The step of splitting the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction includes: Based on the configuration information of the vector control and status register of the vector instruction and the vector instruction operation code of the vector instruction, the vector instruction is split into vector instruction internal operations corresponding to each of the data elements.

4. The vector instruction processing method according to claim 1, characterized in that: After writing the vector instruction back to the item corresponding to the vector instruction in the instruction sequencing queue, the method further includes: Submitting the vector instructions in order through the instruction sequencing queue; The instruction sequencing queue is notified to release the item corresponding to the vector instruction in the instruction sequencing queue, and the vector instruction sequencing queue is notified to release the item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue.

5. The vector instruction processing method according to any one of claims 1 to 4, characterized in that: The method further comprises: In the case where a scalar instruction enters the scalar instruction issue queue, allocating an empty entry for the scalar instruction in the instruction sequencing queue as the entry corresponding to the scalar instruction in the instruction sequencing queue; The scalar instruction is added to a scalar instruction issuance queue, and the scalar instruction issuance queue, when determining that a source operand of the scalar instruction is ready, issues the scalar instruction, so that the scalar instruction reads a scalar register file to obtain a value of the source operand of the scalar instruction; Dispatching the scalar instruction to an execution unit so that the execution unit executes the scalar instruction based on a value of a source operand of the scalar instruction; The scalar instruction is written back to the entry corresponding to the scalar instruction in the instruction sequencing queue.

6. The vector instruction processing method according to claim 5, characterized in that: The method further comprises: When a prediction execution error occurs in the processor, obtaining a sequence relationship between an erroneous instruction having the prediction execution error and other instructions based on the vector instruction sequencing queue and / or the instruction sequencing queue; Based on the sequential relationship between the erroneous instruction and other instructions, the state information of the processor is restored to the state information before the erroneous instruction is executed, the state information of the processor includes a register renaming relationship, and the processor is the execution subject of the method.

7. The vector instruction processing method according to claim 1, characterized in that: After allocating an empty entry for the vector instruction in the instruction sequencing queue as the entry corresponding to the vector instruction in the instruction sequencing queue, the method further comprises: Determine the identification information of the item corresponding to the vector instruction in the instruction sequencing queue as the sequence identification information of the vector instruction; Before writing the vector instruction back to the item corresponding to the vector instruction in the instruction sequencing queue, the method further includes: Based on the sequence identification information of the vector instruction, an item corresponding to the vector instruction is determined in the instruction sequencing queue.

8. The vector instruction processing method according to claim 1, characterized in that: After allocating an empty item in the vector instruction sequencing queue for each vector instruction internal operation corresponding to the data element as an item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue, the method further comprises: Determine the identification information of the item corresponding to the vector instruction internal operation corresponding to each of the data elements in the vector instruction sequencing queue as the sequence identification of the vector instruction internal operation corresponding to each of the data elements; Before writing the vector instruction internal operation corresponding to each of the data elements back to the entry corresponding to the vector instruction internal operation corresponding to each of the data elements in the vector instruction sequencing queue, the method further includes: Based on the sequence identifier of the vector instruction internal operation corresponding to each of the data elements, an item corresponding to the vector instruction internal operation corresponding to each of the data elements is determined in the vector instruction sequencing queue.

9. A vector instruction processing device, characterized in that: include: A first sequencing module is used for allocating an empty item for the vector instruction in the instruction sequencing queue as the item corresponding to the vector instruction in the instruction sequencing queue when the vector instruction enters the vector instruction issuance queue; A second sequencing module is used to split the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction, perform register renaming on the vector instruction internal operations corresponding to each data element, and allocate an empty item to each vector instruction internal operation corresponding to the data element in the vector instruction sequencing queue as an item corresponding to the vector instruction internal operation corresponding to each data element in the vector instruction sequencing queue; An operation execution module, used for executing the internal operations of the vector instructions corresponding to each of the data elements out of order; The instruction write-back module is used to write the vector instruction internal operation corresponding to each of the data elements back to the item corresponding to the vector instruction internal operation corresponding to each of the data elements in the vector instruction sequencing queue, and then write the vector instruction back to the item corresponding to the vector instruction in the instruction sequencing queue.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the vector instruction processing method according to any one of claims 1 to 8 is implemented.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the vector instruction processing method according to any one of claims 1 to 8 is implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the vector instruction processing method according to any one of claims 1 to 8 is implemented.

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