Instruction processing method and processor

Abstract

The embodiment of the invention provides an instruction processing method and a processor, and the method comprises the steps: obtaining a to-be-executed instruction, and determining a conflict type of the to-be-executed instruction; distributing a physical register for the to-be-executed instruction based on the conflict type; determining a dependency conflict condition and a resource conflict condition of the to-be-executed instruction, and determining an execution sequence of the to-be-executed instruction based on the dependency conflict condition and the resource conflict condition; determining a target execution unit based on the execution sequence, and sending the instruction to be executed to the target execution unit; and controlling the target execution unit to execute the to-be-executed instruction, and writing the to-be-executed instruction into the physical register when the to-be-executed instruction is executed, so that efficient out-of-order execution is realized through refined conflict detection, resource allocation and instruction scheduling, and the performance of the RISC-V processor can be remarkably improved. And the adaptability to complex applications is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of instruction processing, and in particular to an instruction processing method and a processor. Background Art

[0002] With the development of computer architecture, the improvement of processor performance depends not only on the increase of main frequency, but also on the development of instruction-level parallelism. Modern high-performance processors generally use out-of-order execution technology to improve the execution efficiency of instruction pipelines through dynamic scheduling. Out-of-order execution is a hardware-level optimization technology that allows the processor to dynamically adjust the execution order of instructions based on the availability of data and resources, rather than strictly following the order of instructions in the program code.

[0003] In recent years, RISC-V, as an emerging open instruction set architecture, has gained wide attention for its modularity, scalability and simplicity. In the field of high-performance computing, the flexibility of the RISC-V instruction set architecture provides new requirements for the design of multi-unit out-of-order execution scheduling modules. The multi-unit out-of-order execution scheduling module is a core component of modern out-of-order execution processors. Its task is to coordinate resource allocation and scheduling between multiple instructions to achieve efficient parallel execution. Especially in the RISC-V architecture, the efficiency of out-of-order execution still needs to be further improved in order to support the extended instruction set. Summary of the invention

[0004] The embodiments of the present invention provide an instruction processing method, device, electronic device and computer-readable storage medium to overcome the above problems or at least partially solve the above problems.

[0005] An embodiment of the present invention discloses an instruction processing method, comprising: Obtaining instructions to be executed, and determining conflict types of the instructions to be executed; Allocating a physical register to the instruction to be executed based on the conflict type; Determining dependency conflicts and resource conflicts of the instructions to be executed, and determining an execution order of the instructions to be executed based on the dependency conflicts and resource conflicts; Determine a target execution unit based on the execution order, and send the to-be-executed instruction to the target execution unit; The target execution unit is controlled to execute the instruction to be executed, and when the instruction to be executed is completed, the instruction to be executed is written into the physical register.

[0006] Optionally, the instructions to be executed include at least a first instruction, a second instruction and a third instruction, the first instruction, the second instruction and the third instruction are arranged in sequence, and the step of allocating physical registers to the instructions to be executed based on the conflict type includes: When it is determined that the logical register to which the first instruction has executed a write operation, the logical register to which the second instruction is about to execute a read operation, and the logical register to which the third instruction is about to execute a write operation are the same first logical register, determining a first target physical register; Constructing a first mapping relationship between the first logical register and a first target physical register; Adding a first mapping relationship between the first logical register and the first target physical register to a preset renaming mapping table; the first mapping relationship is used to control the second instruction to perform a read operation on the first target physical register by reading the first mapping relationship in the renaming mapping table when performing a read operation; determining a second target physical register; the first target physical register and the second target physical register are independent of each other; A second mapping relationship between the first logical register and the second target physical register is constructed; the second mapping relationship is used to control the third instruction to perform a write operation to the second target physical register when performing a write operation.

[0007] Optionally, the step of allocating a physical register to the instruction to be executed based on the conflict type includes: When it is determined that the write operations of different instructions to be executed correspond to the same second logical register, an independent and unique physical register is allocated to each of the instructions to be executed.

[0008] Optionally, the step of allocating an independent and unique physical register to each of the instructions to be executed includes: determining an independent and unique physical register as a third target physical register; Constructing a third mapping relationship between the second logical register and a third target physical register; The third mapping relationship is stored in a preset renaming mapping table.

[0009] Optionally, the step of determining the dependency conflict situation and the resource conflict situation of the instructions to be executed, and determining the execution order of the instructions to be executed based on the dependency conflict situation and the resource conflict situation includes: Checking, through the data dependency queue, whether there is an executing instruction that has not yet been completed; the executing instruction and the to-be-executed instruction use the same physical register; Check whether the target execution unit is available; When it is determined that there is no executing instruction that has not yet been executed and the target execution unit is available, the to-be-executed instruction is added to a to-be-executed queue.

[0010] Optionally, the step of determining a target execution unit based on the execution order and sending the to-be-executed instruction to the target execution unit includes: When it is determined that the processor type is a multi-issue processor, and the multi-issue processor simultaneously dispatches multiple instructions to be executed, and there is a special instruction among the multiple instructions to be executed, the special instruction is sent to the target execution unit; the special instruction is a predicted jump instruction or an exception instruction.

[0011] Optionally, before the step of determining a target execution unit based on the execution order and sending the to-be-executed instruction to the target execution unit, the method further includes: A physical register index of the physical register is saved to a data dependency queue.

[0012] Optionally, the step of controlling the target execution unit to execute the instruction to be executed includes: When it is determined that a prediction error or abnormal state occurs during the execution of the instruction to be executed, a flush error request is initiated, and whether there is a potential abnormal signal; When it is determined that there is a potential exception signal, a recovery operation is performed on the reorder cache of the register renaming module, and / or the renaming mapping table, and / or the data dependency queue of the dispatch scheduling module, and / or the target execution unit.

[0013] Optionally, when the instruction to be executed is completed, the step of writing the instruction to be executed into the physical register includes: When it is determined that no prediction error or abnormal state occurs during the execution of the instruction to be executed and the execution of the instruction to be executed is completed, the instruction to be executed and the execution result of the instruction to be executed are written into the physical register based on the execution order according to the physical register index of the physical register; When it is determined that the physical register sends the instruction to be executed and the execution result to the logical register corresponding to the instruction to be executed, the physical register is marked as an idle state.

[0014] The embodiment of the present invention further discloses a processor, wherein the processor is configured with a multi-unit out-of-order execution scheduling module, wherein the multi-unit out-of-order execution scheduling module is used to obtain instructions to be executed, and the multi-unit out-of-order execution scheduling module includes a register renaming module, a dispatch scheduling module, an execution control module, and an instruction delivery module; The register renaming module, and / or the dispatch scheduling module, and / or the execution control module, and / or the instruction delivery module are used to enable the processor to execute the method described in the embodiment of the present invention when the multi-unit out-of-order execution scheduling module obtains the instruction to be executed.

[0015] The embodiments of the present invention include the following advantages: The embodiment of the present invention obtains instructions to be executed and determines the conflict type of the instructions to be executed; allocates physical registers to the instructions to be executed based on the conflict type; determines the dependency conflict situation and resource conflict situation of the instructions to be executed, and determines the execution order of the instructions to be executed based on the dependency conflict situation and the resource conflict situation; determines the target execution unit based on the execution order, and sends the instructions to be executed to the target execution unit; controls the target execution unit to execute the instructions to be executed, and writes the instructions to be executed to the physical register when the instructions to be executed are completed. This realizes efficient out-of-order execution through refined conflict detection, resource allocation and instruction scheduling, can significantly improve the performance of the RISC-V processor, and enhance its adaptability to complex applications.

[0016] Improve instruction-level parallelism: By determining the conflict type, dependency conflict, and resource conflict of instructions and dynamically adjusting the execution order of instructions, out-of-order execution is achieved, making full use of the parallel computing resources inside the processor. Compared with traditional sequential execution, out-of-order execution can significantly improve the efficiency of the instruction pipeline, especially when processing programs with complex data dependencies.

[0017] Optimize resource allocation: physical registers are allocated based on conflict types, effectively avoiding register resource competition and improving register utilization. The execution order is determined based on dependency conflicts and resource conflicts, which can reasonably allocate execution units and avoid resource waste.

[0018] Reduce pipeline stalls: By detecting and resolving data dependency conflicts and resource conflicts in advance, the possibility of pipeline stalls is reduced. Out-of-order execution allows the processor to continue executing other unrelated instructions when encountering data dependency or resource conflicts, thereby improving pipeline throughput.

[0019] Enhance the adaptability of the RISC-V architecture: This technical solution is applicable to the RISC-V architecture and can meet its characteristics of modularity, scalability and simplicity. For the RISC-V extended instruction set, this solution can effectively improve the efficiency of out-of-order execution and meet the needs of high-performance computing.

[0020] Improve processor performance: Through the above optimization measures, the technical solution described in this paragraph can significantly improve the overall performance of the processor, including execution speed and throughput. By judging exceptions and conflicts, the performance loss caused by exceptions and conflicts is reduced as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flowchart of a method for processing instructions provided in an embodiment of the present invention; Figure 2 is a flowchart of an instruction processing method provided in an embodiment of the present invention; Figure 3 It is a structural block diagram of a processor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] In order to enable those skilled in the art to better understand the embodiments of the present invention, some technical terms involved in the embodiments of the present invention are explained below.

[0024] 1. Instruction Level Parallelism (ILP) is one of the important technologies used in modern computer architecture to improve processor performance. The core idea of ​​ILP is to improve the throughput of the processor by executing multiple independent instructions at the same time.

[0025] 2. Out-of-Order Execution (OoOE) is a hardware optimization technology used to improve processor performance. Its core idea is to break the sequential execution restrictions of instructions in the program and dynamically adjust the execution order of instructions according to the availability of the instruction operands and the idleness of execution resources, thereby maximizing instruction-level parallelism.

[0026] 3. Extended instruction set (such as M extension, A extension, F extension): In the RISC-V architecture, the extended instruction set refers to the functional modules added on the basis of the basic integer instruction set to meet the needs of specific computing scenarios. These extended instruction sets provide RISC-V with high flexibility and scalability through modular design. M extension is integer multiplication and division extension, A extension is atomic extension, and F extension is floating point extension.

[0027] 4. Logical registers (ARF): Logical registers, also known as architectural register files (ARF), are a set of registers in the processor instruction set architecture (ISA) that are directly visible to the program. The number and function of logical registers are defined by the instruction set architecture, for example, there are 32 general-purpose logical registers (x0 to x31) in the RISC-V architecture. These registers store program variables or intermediate calculation results and are visible to the compiler and programmer.

[0028] 5. Physical registers (PRF): Physical registers are a set of registers actually implemented by the processor hardware, and their number is usually much larger than that of logical registers. Physical registers exist to support register renaming, thereby solving the resource conflict problem caused by the limited number of logical registers.

[0029] 6. Instruction Set Architecture (ISA) is one of the core concepts of computer architecture. It defines the interface between computer hardware and software and is the basis for the processor to execute programs. ISA is a set of instructions that specify the types of operations that the processor can perform and how to operate, including data operations, memory access, and control flow.

[0030] The instruction set architecture is the interface between computer hardware and software that defines the set of instructions that the CPU can execute.

[0031] Simply put, the ISA determines how the CPU understands and executes commands issued by the software.

[0032] RISC-V is an open standard instruction set architecture.

[0033] Features of RISC-V: Open source: The core feature of RISC-V is its open source nature, which means that anyone can freely use, modify and extend the RISC-V instruction set.

[0034] This is in stark contrast to traditional closed ISAs such as x86 and ARM.

[0035] Modularity: RISC-V adopts a modular design, allowing developers to choose different instruction set extensions according to their needs, thereby flexibly adapting to various application scenarios.

[0036] Scalability: RISC-V's instruction set can be expanded as needed to meet evolving technology needs.

[0037] Reduced Instruction Set Computing (RISC): RISC-V follows the design principle of Reduced Instruction Set Computing (RISC), which means that it uses a simplified set of instructions, thereby improving the efficiency and performance of the central processing unit CPU.

[0038] The relationship between RISC-V and CPU: The design of the CPU must follow a specific ISA.

[0039] Therefore, RISC-V is a blueprint for CPU design, and chip manufacturers can design and manufacture CPUs based on the RISC-V instruction set.

[0040] The open source nature of RISC-V allows anyone to design their own CPU based on RISC-V, thus promoting the innovation and development of CPU design.

[0041] RISC-V is an open, modular and extensible instruction set architecture that provides new possibilities for CPU design. Due to its open source nature, RISC-V is becoming an important force in the CPU field.

[0042] In practical applications, with the continuous evolution of computer architecture, the improvement of processor performance no longer relies solely on the simple superposition of main frequency, but increasingly relies on the deep mining of instruction-level parallelism. Modern high-performance processors generally use out-of-order execution technology to optimize the execution efficiency of the instruction pipeline through a dynamic scheduling mechanism. As a key hardware optimization technology, out-of-order execution allows the processor to flexibly adjust the execution order of instructions based on the real-time availability of data and resources, breaking through the inherent order restrictions of program code. This move can make better use of processor resources, such as execution units, register files, and memory bandwidth, effectively alleviate data dependencies and pipeline congestion, and thus significantly improve the throughput and overall performance of the processor.

[0043] In recent years, RISC-V, as an emerging open instruction set architecture, has won wide attention in the industry with its modularity, scalability and simplicity. Especially in the field of high-performance computing, the flexibility of the RISC-V instruction set architecture has brought unprecedented opportunities and challenges to the design of multi-unit out-of-order execution scheduling modules. As a core component of modern out-of-order execution processors, the multi-unit out-of-order execution scheduling module is responsible for coordinating the resource allocation and scheduling of multiple instructions, aiming to achieve efficient parallel execution. Especially under the RISC-V architecture, in order to support rich instruction set extensions such as M extension, A extension, and F extension, the scheduling module must have the ability to efficiently manage multiple types of execution units such as integer arithmetic units, floating-point arithmetic units, and memory access units.

[0044] However, there are still many technical challenges in implementing an efficient multi-unit out-of-order execution scheduling module under the RISC-V architecture: Complexity of dynamic scheduling: In modern processors, the data dependencies between instructions are intricate, involving multiple data dependency conflicts such as write-after-write (WAW), read-after-write (WAR), and read-after-write (RAW). The dynamic scheduling mechanism needs to parse these complex dependencies in real time, but traditional scheduling modules often have difficulty completing this task efficiently, resulting in pipeline blockage and reduced scheduling efficiency.

[0045] Compatibility and scalability bottlenecks: The RISC-V architecture is known for its excellent modularity and scalability. It supports a variety of instruction set extensions and places higher demands on the adaptability of the scheduling module. However, the existing scheduling logic mostly relies on specific processor architectures or hardware configurations, and requires targeted redesign under new scenarios or functional requirements. This design model that lacks flexibility and versatility not only prolongs the development cycle and increases costs, but also limits the application potential of the scheduling module in a variety of scenarios.

[0046] Performance loss in special cases: Branch prediction failures, interruptions, exceptions and other events will cause the instruction execution flow to be interrupted, causing the pipeline to be cleared or refreshed. The scheduling module needs to quickly locate the erroneous instructions, clear invalid instructions, and ensure that other independent instructions are not affected. However, when dealing with these special cases, existing designs often suffer from large performance losses and excessive hardware resource usage, making it difficult to achieve an ideal balance between complexity and efficiency.

[0047] Reference Figure 1 , shows a flowchart of a method for processing an instruction provided in an embodiment of the present invention, which may specifically include the following steps: Step 101, obtaining instructions to be executed, and determining the conflict type of the instructions to be executed; An embodiment of the present invention can be applied to a processor, which is configured with a multi-unit out-of-order execution scheduling module, which is used to obtain one or more instructions to be executed, and the multi-unit out-of-order execution scheduling module includes a register renaming module, a dispatch scheduling module, an execution control module and an instruction delivery module.

[0048] Microarchitecture refers to the specific implementation method inside the processor, including data paths, control logic, storage structure, etc.; the register renaming module, dispatch scheduling module, execution control module and instruction delivery module are part of the processor microarchitecture and represent different logical functions inside the processor.

[0049] Specifically, the functions of each module are as follows.

[0050] Register renaming module: Responsible for mapping logical registers to physical registers and eliminating register dependencies.

[0051] The register renaming module may include hardware structures such as a physical register file, a reorder buffer, and a renaming mapping table.

[0052] Dispatch scheduling module: Responsible for the scheduling and dispatching of instructions, and resolving data dependencies and resource conflicts.

[0053] The dispatch scheduling module may include hardware logic such as data dependency queues and dependency judgment modules.

[0054] Execution Control Module: Responsible for handling exceptions and interrupts to ensure the correctness of instruction execution.

[0055] The execution control module may include hardware logic such as an anomaly detection module and a recovery detection module.

[0056] Instruction delivery module: Responsible for the submission and writing back of instructions to ensure that instructions are completed in program order.

[0057] The instruction delivery module may include hardware logic such as an instruction write-back module and an instruction delivery module.

[0058] Although the modules are divided according to the execution logic, in the hardware implementation, they correspond to specific circuits and hardware structures. Each module is a real logical functional unit in the processor hardware microarchitecture. They are implemented through hardware circuits and are responsible for performing specific tasks to improve the performance and efficiency of the processor. They are an integral part of the physical implementation of the processor.

[0059] The instructions to be executed may be arithmetic logic operation instructions, for example: Addition instructions (ADD), subtraction instructions (SUB), logical operation instructions (AND, OR, XOR); these instructions are executed in the arithmetic logic unit (ALU).

[0060] 2. Memory access instructions, such as: Load instructions (LOAD) and storage instructions (STORE) are executed in the memory access unit.

[0061] 3. Branch instructions, such as: Conditional branch instructions (BEQ, BNE, BLT, BGT), unconditional jump instructions (JMP), these instructions are predicted in the branch prediction unit and calculated in the execution unit.

[0062] 4. Floating point operation instructions, such as: Floating-point addition instruction (FADD), floating-point multiplication instruction (FMUL), these instructions are executed in the floating-point unit (FPU).

[0063] 5. Other instructions, such as: Shift instruction (SHIFT). Compare instruction (CMP).

[0064] Step 102, allocating a physical register for the instruction to be executed based on the conflict type; The embodiment of the present invention can allocate physical registers to the instructions to be executed based on the conflict type through a register renaming module.

[0065] In the specific implementation, physical registers are allocated to instructions to be executed according to different conflict types, which can improve instruction-level parallelism. At the same time, more physical register resources are provided for subsequent instructions to avoid pipeline blocking caused by insufficient number of logical registers.

[0066] Exemplarily, the conflict types may include, but are not limited to, WAW conflicts (write-after-write conflicts) and WAR conflicts (write-after-read conflicts). For different conflict types in WAW and WAR, different methods may be used to establish a mapping of logical destination registers to physical registers, so as to allocate physical registers to instructions to be executed, so that instructions to be executed can be allocated to more available register resources, reducing restrictions on register allocation, thereby improving the flexibility of instruction scheduling.

[0067] Step 103, determining the dependency conflict situation and resource conflict situation of the instructions to be executed, and determining the execution order of the instructions to be executed based on the dependency conflict situation and the resource conflict situation; The embodiment of the present invention may adopt a dispatch scheduling module to determine the dependency conflict situation and resource conflict situation of the instructions to be executed, and determine the execution order of the instructions to be executed based on the dependency conflict situation and the resource conflict situation.

[0068] The purpose of determining dependency conflicts is to resolve RAW conflicts (read-after-write conflicts). In the specific implementation, the dispatch scheduling module queries the data dependency queue (OITF) to check whether there are ongoing instructions that have not yet completed execution, and the third target physical register of the ongoing instruction is the same as the number of physical registers allocated for the instruction to be executed. If there are ongoing instructions, it means that the current instruction to be executed depends on the result of the previous instruction, and there is a RAW data dependency conflict.

[0069] Execution units may include: Arithmetic Logic Unit (ALU): Performs basic arithmetic and logic operations like addition, subtraction, AND, OR, etc.

[0070] Floating-point unit (FPU): performs floating-point operations such as floating-point addition, multiplication, and division.

[0071] Memory access unit (Load / Store Unit): responsible for reading (Load) and writing (Store) memory data.

[0072] Branch Prediction Unit: predicts the execution direction of branch instructions to improve pipeline efficiency.

[0073] The purpose of resource conflict is to resolve structural conflicts. In the specific implementation, the dispatch scheduling module checks whether the execution unit requested by the current instruction to be executed is available. If all relevant execution units are busy and cannot provide execution resources for the current instruction to be executed, a structural conflict is detected.

[0074] Step 104, determining a target execution unit based on the execution order, and sending the to-be-executed instruction to the target execution unit; Exemplarily, the instructions to be executed may be dispatched in the following manner.

[0075] If the instruction has no data dependency conflict and resource conflict and is not a special instruction, the dispatch scheduling module will dispatch the to-be-executed instruction to the to-be-executed queue based on the timestamp corresponding to the instruction.

[0076] If there are multiple instructions to be executed that can be dispatched at the same time, the dispatch scheduling module will decide which instructions to dispatch based on the idle state of the execution unit and the priority of each instruction to be executed.

[0077] The embodiment of the present invention realizes dynamic scheduling of instructions by detecting data dependency and resource conflict, and effectively ensures correct dispatch and execution of instructions to be executed.

[0078] Step 105: Control the target execution unit to execute the instruction to be executed, and write the instruction to be executed into the physical register when the instruction to be executed is completed.

[0079] The execution unit is the hardware module in the processor that actually executes instruction operations. It is responsible for performing various operations, such as arithmetic operations (addition, subtraction, etc.), logical operations (AND, OR, etc.), floating-point operations, memory access, etc. Different types of execution units are responsible for executing different types of instructions.

[0080] The physical register PRF is a register that actually exists in the processor and is used to store the intermediate and final results of instruction execution. Unlike logical registers, the number of physical registers is usually much larger than that of logical registers to support register renaming and out-of-order execution.

[0081] When the instruction to be executed successfully completes the execution phase in the execution unit and no exception occurs, it will enter the write-back phase. In the write-back phase, the instruction delivery module can write the executed instruction and the execution result of the instruction into the physical register according to its execution result and the physical register index.

[0082] The embodiment of the present invention obtains instructions to be executed and determines the conflict type of the instructions to be executed; allocates physical registers to the instructions to be executed based on the conflict type; determines the dependency conflict situation and resource conflict situation of the instructions to be executed, and determines the execution order of the instructions to be executed based on the dependency conflict situation and the resource conflict situation; determines the target execution unit based on the execution order, and sends the instructions to be executed to the target execution unit; controls the target execution unit to execute the instructions to be executed, and writes the instructions to be executed to the physical register when the instructions to be executed are completed. This realizes efficient out-of-order execution through refined conflict detection, resource allocation and instruction scheduling, can significantly improve the performance of the RISC-V processor, and enhance its adaptability to complex applications.

[0083] Improve instruction-level parallelism: By determining the conflict type, dependency conflict, and resource conflict of instructions and dynamically adjusting the execution order of instructions, out-of-order execution is achieved, making full use of the parallel computing resources inside the processor. Compared with traditional sequential execution, out-of-order execution can significantly improve the efficiency of the instruction pipeline, especially when processing programs with complex data dependencies.

[0084] Optimize resource allocation: physical registers are allocated based on conflict types, effectively avoiding register resource competition and improving register utilization. The execution order is determined based on dependency conflicts and resource conflicts, which can reasonably allocate execution units and avoid resource waste.

[0085] Reduce pipeline stalls: By detecting and resolving data dependency conflicts and resource conflicts in advance, the possibility of pipeline stalls is reduced. Out-of-order execution allows the processor to continue executing other unrelated instructions when encountering data dependency or resource conflicts, thereby improving pipeline throughput.

[0086] Enhance the adaptability of the RISC-V architecture: This technical solution is applicable to the RISC-V architecture and can meet its characteristics of modularity, scalability and simplicity. For the RISC-V extended instruction set, this solution can effectively improve the efficiency of out-of-order execution and meet the needs of high-performance computing.

[0087] Improve processor performance: Through the above optimization measures, the technical solution described in this paragraph can significantly improve the overall performance of the processor, including execution speed and throughput. By judging exceptions and conflicts, the performance loss caused by exceptions and conflicts is reduced as much as possible.

[0088] Based on the above embodiment, a variant embodiment of the above embodiment is proposed. It should be noted that in order to make the description concise, only the differences from the above embodiment are described in the variant embodiment.

[0089] The instructions to be executed include at least a first instruction, a second instruction and a third instruction, the first instruction, the second instruction and the third instruction are arranged in sequence, and the step of allocating physical registers to the instructions to be executed based on the conflict type includes: When it is determined that the logical register to which the first instruction has executed a write operation, the logical register to which the second instruction is about to execute a read operation, and the logical register to which the third instruction is about to execute a write operation are the same first logical register, determining a first target physical register; Constructing a first mapping relationship between the first logical register and a first target physical register; Adding a first mapping relationship between the first logical register and the first target physical register to a preset renaming mapping table; the first mapping relationship is used to control the second instruction to perform a read operation on the first target physical register by reading the first mapping relationship in the renaming mapping table when performing a read operation; determining a second target physical register; the first target physical register and the second target physical register are independent of each other; A second mapping relationship between the first logical register and the second target physical register is constructed; the second mapping relationship is used to control the third instruction to perform a write operation to the second target physical register when performing a write operation.

[0090] The core of WAR conflict (read-after-write conflict): WAR conflict occurs between "read" operation and "write" operation. If the "write" operation occurs before the "read" operation is completed, and they operate the same logical register, then the "read" operation will read the wrong value.

[0091] For example, when one instruction reads a logical register and another instruction subsequently writes to the same logical register, an incorrect value may be read if the write completes before the read.

[0092] In the embodiment of the present invention, during the register renaming stage, when reading an operand, the physical register corresponding to the logical register can be searched through the RAT. When writing an operand, a new physical register is allocated. In this way, even if the write operation is completed before the read operation, the read operation can still read the correct value because they operate on different physical registers.

[0093] For example, There are three instructions to be executed: First instruction: LOAD R2, [address] (load data from memory to logical register R2) Second instruction: ADD R3, R2, R4 (add logical registers R2 and R4 and write the result to R3) The third instruction: STORE R2, [address2] (store the value of logical register R2 into memory) The execution order of the first instruction, the second instruction, and the third instruction is 1, 2, and 3. Although the first instruction, the second instruction, and the third instruction have a fixed execution order, the write operation of the third instruction may be completed before the read operation of the second instruction.

[0094] step: First instruction (LOAD R2, [address]): 1.1. In the register renaming stage, a new first target physical register P10 is allocated to the first logical register R2.

[0095] 1.2. Update the rename mapping table (RAT): record the first mapping relationship of the first logical register R2 -> P10.

[0096] 1.3. The first instruction actually writes to physical register P10.

[0097] Second instruction (ADD R3, R2, R4): 2.1. In the register renaming stage, the physical register corresponding to the first logical register R2 is searched through the renaming mapping table RAT.

[0098] 2.2. The physical register corresponding to the first logical register R2 is obtained from the renaming mapping table RAT as the first target physical register P10.

[0099] 2.3. The second instruction actually reads the value of the first target physical register P10.

[0100] The third instruction (STORE R2, [address2]): 3.1. In the register renaming stage, a new second target physical register P12 is allocated to the first logical register R2.

[0101] 3.2. Update RAT: record the second mapping relationship of the first logical register R2->second target physical register P12 (overwriting the previous R2->P10).

[0102] 3.3. The third instruction actually writes into physical register P12.

[0103] Result analysis: Even if the write operation of the third instruction is completed before the read operation of the second instruction, the second instruction still reads the value of the first target physical register P10, that is, the correct value written by the first instruction.

[0104] The embodiment of the present invention eliminates WAR conflicts by allocating a new physical register for each write and using RAT to search for the physical register corresponding to the read operand.

[0105] In an optional embodiment of the present invention, the step of allocating a physical register to the instruction to be executed based on the conflict type includes: When it is determined that the write operations of different instructions to be executed correspond to the same second logical register, an independent and unique physical register is allocated to each of the instructions to be executed.

[0106] Logical registers are registers that programmers use when writing assembly code. They are part of the instruction set architecture (ISA) definition and there are a limited number of them. For example, in RISC-V, logical registers can be x0, x1, x2, ..., x31.

[0107] WAW conflict (write-after-write conflict) refers to when two instructions write to the same logical register one after another, if the latter instruction is completed first, the previous write will be overwritten, resulting in an error.

[0108] In the embodiment of the present invention, the destination logical register of each instruction is mapped to a new and unique physical register in the register renaming stage. Even if two instructions write to the same logical register, they actually write to different physical registers. In this way, the writing of the latter instruction will not affect the writing of the former instruction, thereby eliminating the WAW conflict.

[0109] For example, Instruction 1: ADD R1, R2, R3 (add R2 and R3 and write the result to the second logical register R1) In the rename phase, a new physical register is allocated, for example, physical register P5, and assigned to R1.

[0110] RAT Update: R1 -> P5 Instruction 1 actually writes to P5.

[0111] Instruction 2: SUB R1, R4, R5 (subtract R4 and R5 and write the result to the second logical register R1) In the renaming stage, a new physical register is allocated again, for example, physical register P8, and assigned to R1.

[0112] RAT update: R1 -> P8 (previous R1 -> P5 is overwritten) Instruction 2 actually writes to P8.

[0113] result: Even if instruction 2 is completed first, it writes to physical register P8 and will not affect physical register P5 written by instruction 1.

[0114] When instruction 1 finally commits, the correct result is read from P5.

[0115] In the above manner, WAW conflicts are eliminated.

[0116] In an optional embodiment of the present invention, the step of allocating an independent and unique physical register to each of the instructions to be executed includes: determining an independent and unique physical register as a third target physical register; Constructing a third mapping relationship between the second logical register and a third target physical register; The third mapping relationship is stored in a preset renaming mapping table.

[0117] In a specific implementation, the register renaming module can select an available physical register Pdest from the free list of the physical register stack and determine it as the third target physical register, which is independent and unique; after determining the third target physical register, a third mapping relationship between the third target physical register Pdest and the second logical register Dest of the instruction to be executed can be constructed to assign the third target physical register Pdest to the second logical register Dest of the instruction to be executed; then, the third mapping relationship between Dest and Pdest is written into the renaming mapping table RAT so that the corresponding physical register Pdest can be quickly located when the subsequent instruction accesses Dest. Specifically, the renaming mapping table RAT is usually composed of registers or static random access memory (SRAM), whose address index corresponds to the logical register, and the stored data content is the physical register number. Taking 32 logical registers and 128 physical registers as an example, the RAT consists of 32 table entries, which can be addressed by a 5-bit index, and each table entry stores a 7-bit physical register index.

[0118] The embodiment of the present invention ensures that each write instruction uses a different physical register by obtaining a new physical register Pdest from the free list. Even if multiple instructions write to the same logical register Dest, they actually write to different physical registers, thereby avoiding write-after-write (WAW) conflicts.

[0119] The mapping relationship between the logical register Dest and the physical register Pdest is written into the RAT, which provides a basis for subsequent instructions to find the physical register. Subsequent instructions can quickly locate the physical register Pdest corresponding to the destination logical register Dest through the RAT, thereby realizing register renaming.

[0120] By dynamically allocating and releasing physical registers, the utilization of the physical register stack is improved. When an instruction is submitted, the physical registers it uses will be released back to the free list for use by subsequent instructions.

[0121] Using a memory array composed of registers or static random access memory (SRAM) to implement RAT simplifies hardware design. The mapping of logical registers to physical registers can be quickly achieved through address index and data content.

[0122] By renaming registers and mapping logical registers to more physical registers, WAW and WAR conflicts can be effectively resolved. In this way, data correctness can be guaranteed even if the execution order of instructions is disrupted.

[0123] In an optional embodiment of the present invention, the step of determining the dependency conflict situation and the resource conflict situation of the instructions to be executed, and determining the execution order of the instructions to be executed based on the dependency conflict situation and the resource conflict situation includes: Checking, through the data dependency queue, whether there is an executing instruction that has not yet been completed; the executing instruction and the to-be-executed instruction use the same physical register; Check whether the target execution unit is available; When it is determined that there is no executing instruction that has not yet been executed and the target execution unit is available, the to-be-executed instruction is added to a to-be-executed queue.

[0124] In the specific implementation, the dispatch scheduling module queries the data dependency queue (OITF) to check whether there are any in-flight instructions that have not yet been completed, and the physical register of the in-flight instruction is the same as the physical register of the current instruction to be executed. If it is determined that there are in-flight instructions that have not yet been completed, there is a RAW data dependency conflict.

[0125] Detect dependency conflicts: A RAW conflict (read-after-write conflict) means that an instruction (instruction B) needs to read the value of a register or memory address, and another instruction (instruction A) has previously written a new value to the register or memory address. If the read operation of instruction B is executed before the write operation of instruction A is completed, a RAW conflict will occur.

[0126] Data dependency: Instruction B needs to use the result produced by instruction A in order to execute correctly.

[0127] Write Back: After instruction A completes execution, the result is written to the physical register.

[0128] Detecting structural conflicts: The target execution unit may be the execution unit currently requested by the instruction to be executed, and the dispatch scheduling module checks whether the execution unit currently requested by the instruction to be executed is available. If all relevant execution units are busy and cannot provide execution resources for the current instruction, a structural conflict is detected.

[0129] If there are no data dependency conflicts or structural conflicts, the pending instructions may be dispatched to the pending queue.

[0130] Optionally, if a RAW conflict is detected, the dispatch scheduling module will suspend the dispatch of the current instruction to be executed until the dependent instructions are written back to ensure the correctness of the data dependency.

[0131] For example, When a RAW conflict is detected, the dispatch scheduling module detects that the data that instruction B needs to read is the result of instruction A writing, which means that instruction B must wait for instruction A to complete writing before it can read the correct data. In order to prevent instruction B from reading incorrect data, the dispatch scheduling module suspends the dispatch of instruction B. At this time, instruction B is blocked until instruction A completes writing.

[0132] Waiting for instruction A to complete the write-back, that is, after instruction A is executed, its result is written into the physical register. This write operation is called "write-back". Only when instruction A completes the write-back can instruction B read the correct data. By waiting for instruction A to complete the write-back, the dispatch scheduling module ensures that the data read by instruction B is correct, thereby ensuring the correctness of data dependency.

[0133] Optionally, if a structural conflict is detected, the dispatch scheduling module pulls down the dispatch enable signal to suspend the dispatch of the current instruction until sufficient execution resources are available.

[0134] Exemplarily, the dispatch scheduling module detects that the execution unit (such as ALU) required for the current instruction to be executed is busy and cannot process the instruction immediately, which means that if the instruction is dispatched immediately, it will cause resource conflicts and the instruction cannot be executed correctly.

[0135] In order to avoid resource conflicts, the dispatch scheduling module can set the dispatch enable signal to a low level, which will prevent the current instruction to be executed from being dispatched to the execution unit, causing it to be suspended in the waiting queue. This is because the dispatch enable signal is pulled low, the current instruction is suspended from being dispatched and cannot enter the execution unit.

[0136] The dispatch scheduling module can continuously monitor the availability status of the execution units.

[0137] Once the required execution unit is idle and has enough resources to process the pending instruction, the dispatch scheduling module will set the dispatch enable signal to a high level. At this point, the suspended pending instruction can be dispatched to the target execution unit and continue to be executed.

[0138] In an optional embodiment of the present invention, the step of determining a target execution unit based on the execution order and sending the to-be-executed instruction to the target execution unit includes: When it is determined that the processor type is a multi-issue processor, and the multi-issue processor simultaneously dispatches multiple instructions to be executed, and there is a special instruction among the multiple instructions to be executed, the special instruction is sent to the target execution unit; the special instruction is a predicted jump instruction or an exception instruction.

[0139] Features of multi-issue processor: Parallel execution: Multi-issue processors can execute multiple instructions simultaneously, thereby improving instruction-level parallelism (ILP), which means that the processor can complete more work in one clock cycle, improving the processor's throughput.

[0140] Superscalar processor: A multi-issue processor is usually a superscalar processor. A superscalar processor achieves instruction-level parallelism by issuing multiple instructions in the same clock cycle.

[0141] The significance of a multi-issue processor dispatching multiple instructions to be executed at the same time: Improved performance: By dispatching multiple instructions simultaneously, multi-issue processors can more fully utilize the resources of the execution units, thereby improving processor performance.

[0142] Increased throughput: Multi-issue processors can complete more instructions per unit time, thereby increasing the processor throughput.

[0143] In a specific implementation, for a multi-issue processor, if multiple instructions to be executed are dispatched at the same time and there are predicted jump instructions or instructions that may cause exceptions, only the special instruction is dispatched, and the dispatch of other instructions in the same cycle is suspended for one clock cycle.

[0144] Predicted jump instructions may include the following instructions: Conditional branch instructions: These instructions decide whether to jump to another instruction address based on a certain condition (for example, the result of a comparison between two registers). Since the result of the condition is usually unknown before the instruction is executed, the processor uses branch prediction techniques to guess whether the jump will occur. If the prediction is wrong, the processor needs to undo the instructions that have been executed and jump to the correct instruction address.

[0145] Unconditional jump instructions: These instructions always jump to another instruction address. Although unconditional jump instructions themselves do not cause misprediction, they may interact with other prediction mechanisms (e.g., return address prediction) in some cases.

[0146] Indirect jump instruction: The target address is provided by a register or memory. Due to the uncertainty of the target address, the indirect jump instruction is more difficult to predict.

[0147] Exception instructions refer to instructions that may cause exceptions, including the following instructions: Division instructions: Division by zero causes an arithmetic exception.

[0148] Memory access instructions (load / store): Accessing an invalid memory address (for example, out-of-bounds access or accessing unmapped memory) causes a memory access exception.

[0149] Privileged instructions: These instructions can only be executed in privileged mode. Executing a privileged instruction in non-privileged mode results in a privileged instruction exception.

[0150] System call instructions: These instructions are used to request operating system services. Incorrect system call parameters or invalid system call numbers will cause system call exceptions.

[0151] Floating-point operation instructions: Floating-point operations may cause exceptions such as overflow, underflow, and division by zero.

[0152] By limiting the execution of subsequent instructions, only a few instructions need to be revoked or processed when a prediction error or exception occurs, thus simplifying the complexity of exception handling. By dispatching special instructions first, errors can be detected as early as possible and flushing or exception handling can be initiated as soon as possible, thus reducing performance loss. By suspending the dispatch of other instructions, irrelevant instructions are avoided from being executed after the erroneous instruction, ensuring the correctness of instruction execution.

[0153] In an embodiment of the present invention, when it is determined that the processor type is a multi-issue processor, and the multi-issue processor simultaneously dispatches multiple instructions to be executed, and there is a special instruction among the multiple instructions to be executed, the special instruction is sent to the target execution unit; and the special instruction is a predicted jump instruction or an exception instruction, the following beneficial effects can be achieved.

[0154] Reduced performance penalty: Since exception handling is less complex, the processor can resume normal execution more quickly, resulting in less performance penalty.

[0155] Reduced hardware overhead: Since fewer instructions need to be retired or processed, the processor can simplify the hardware design, thereby reducing hardware overhead.

[0156] Improve system reliability: By ensuring the correctness of instruction execution, the reliability of the system is improved.

[0157] In an optional embodiment of the present invention, before the step of determining the target execution unit based on the execution order and sending the to-be-executed instruction to the target execution unit, the method further includes: A physical register index of the physical register is saved to a data dependency queue.

[0158] The embodiment of the present invention may save the physical register index (Pdest) of the instruction into the data dependency queue (OITF) to implement the update of the dependency queue OITF.

[0159] Physical register index (Pdest): During the register renaming phase, the target logical register of each instruction is mapped to a unique physical register. Pdest is the index of this physical register and is used to locate the register in the physical register file.

[0160] Data Dependency Queue (OITF): The OITF is a hardware structure used to track instructions being executed. It records the target physical register indexes of these instructions in order to detect data dependencies.

[0161] The purpose of saving Pdest is to detect RAW dependency. When a new instruction (instruction B) needs to read a register, the dispatch scheduling module will check OITF. If there is an instruction (instruction A) in OITF, and its Pdest is the same as the source physical register index of instruction B, then it means that instruction B depends on the result of instruction A. In this way, the dispatch scheduling module can detect RAW dependency and suspend the dispatch of instruction B until instruction A is written back.

[0162] Tracking instruction status: OITF is also used to track the execution status of instructions. When the instruction is written back, the corresponding entry in OITF can be cleared, that is, the physical register index of the physical register can be cleared.

[0163] By saving Pdest in OITF, the dispatch scheduling module can effectively detect RAW dependencies and track the execution status of instructions, which helps to ensure the correct execution of instructions and improve the performance of the processor.

[0164] In an optional embodiment of the present invention, the step of controlling the target execution unit to execute the instruction to be executed includes: When it is determined that a prediction error or abnormal state occurs during the execution of the instruction to be executed, a flush error request is initiated, and whether there is a potential abnormal signal; When it is determined that there is a potential exception signal, a recovery operation is performed on the reorder cache of the register renaming module, the renaming mapping table, the data dependency queue of the dispatch scheduling module, and the target execution unit.

[0165] In the execution phase of the embodiment of the present invention, the exception judgment module continuously monitors the instructions, and once a prediction error or exception is detected, the exception handling process is immediately started. The exception detection is completed within the first clock cycle of the execution cycle, and a flush request is quickly issued in the second cycle. At the same time, the detection and recovery unit synchronously evaluates whether there is a potential exception signal, that is, whether there is a new instruction that has just entered the execution phase from the dispatch phase. If the flush request and the potential exception signal appear at the same time, it indicates that the relevant execution unit and its control logic need to be restored. Specifically, the reorder buffer (ROB), rename mapping table (RAT), data dependency queue (OITF) and the current execution unit will all be included in the recovery scope.

[0166] Specifically, it can be executed as follows: Step 1: During the execution phase, the exception judgment module can continuously monitor the execution status of the instructions to be executed. The monitoring content includes prediction errors (such as branch prediction errors) and abnormal conditions (such as division by zero errors and memory access errors).

[0167] The purpose is to promptly detect errors in the instruction execution process and prevent the propagation of erroneous results, so as to improve the reliability and correctness of instruction execution and reduce the performance loss caused by errors.

[0168] Step 2: The exception judgment module detects the exception in the first clock cycle of the execution phase.

[0169] The purpose is to detect errors as early as possible and buy time for subsequent exception handling, so as to shorten the delay of error detection and improve the response speed of exception handling.

[0170] Step 3: Initiate a flush error request. In the second clock cycle of the execution phase, the abnormality judgment module immediately initiates a flush error request.

[0171] The purpose is to notify other modules in the pipeline that the erroneous instruction and its subsequent instructions need to be revoked to prevent the erroneous results from being written to registers or memory, thereby preventing the propagation of erroneous results, ensuring data consistency, and reducing performance losses caused by errors.

[0172] Step 4: While initiating the flush error request, the detection recovery unit determines whether there is a potential abnormal signal. If it is determined that there is a potential abnormal signal, it means that the instruction to be executed enters the first cycle of the execution stage from the dispatch stage.

[0173] The purpose is to determine the scope of modules that need to be restored and avoid unnecessary recovery operations, so as to accurately control the recovery scope, reduce the cost of recovery operations, and improve the efficiency of recovery operations.

[0174] Step 5: If there is an error request and a potential abnormal signal, the detection recovery unit controls the recovery operation. The modules that need to be recovered include the reorder buffer ROB of the register renaming module, the renaming mapping table RAT, the data dependency queue OITF of the dispatch scheduling module, and the current execution unit.

[0175] The purpose is to restore the pipeline to the correct state so that subsequent instructions can be executed correctly, thereby ensuring the stability and reliability of the system and reducing performance losses caused by exceptions.

[0176] The embodiment of the present invention is an abnormality detection and processing flow in the execution phase. By detecting abnormalities as early as possible, initiating flushing error requests and accurately controlling the recovery range, the technical solution can effectively reduce the performance loss caused by abnormalities and improve the reliability of the system.

[0177] In an optional embodiment of the present invention, when the instruction to be executed is completed, the step of writing the instruction to be executed into the physical register includes: When it is determined that no prediction error or abnormal state occurs during the execution of the instruction to be executed and the execution of the instruction to be executed is completed, the instruction to be executed and the execution result of the instruction to be executed are written into the physical register based on the execution order according to the physical register index of the physical register; When it is determined that the physical register sends the instruction to be executed and the execution result to the logical register corresponding to the instruction to be executed, the physical register is marked as an idle state.

[0178] Exemplarily, the instructions to be executed may be written into the physical register in the following manner.

[0179] 1. Check the command completion status: 1.1 Check whether the instruction completed successfully during the execution phase.

[0180] 1.2 Check whether there are any exceptions during the execution of the instruction.

[0181] Purpose: To ensure that only instructions that have been completed successfully and without exception can enter the write-back phase, and to ensure that the data written into the physical register is valid and correct.

[0182] 2. Write back to the physical register: 2.1 According to the execution result of the instruction and the physical register index (Pdest), write the data to the corresponding physical register.

[0183] Purpose: Store the execution result of the instruction in the physical register for use by subsequent instructions to ensure that the execution result of the instruction is correctly saved.

[0184] 3. Clear data dependencies in OITF: 3.1 Clear the entry corresponding to the instruction in OITF (data dependency queue), that is, the physical register index of the physical register, prompting subsequent instructions to use the data in the current physical register for calculation. At the same time, it can release the resources in OITF to track the data dependencies of other instructions, ensure that subsequent instructions can correctly read the data in the physical register, and improve the utilization of OITF.

[0185] 4. Mark the physical register as free: 4.1 Mark the relevant physical registers as “free”.

[0186] 4.2 Return the free physical registers to the physical register pool.

[0187] Purpose: Release physical register resources for use by subsequent instructions and improve the utilization of physical register resources.

[0188] 5. Update the status of RAT and ROB: 5.1 Update the status of the RAT (Rename Map Table) to reflect the changes in the mapping relationship between logical registers and physical registers.

[0189] 5.2 Update the status of the ROB (reorder buffer) to reflect the completion and submission of instructions.

[0190] Purpose: To ensure that subsequent instructions can correctly perform register mapping and data delivery, and to ensure the continuity and correctness of the instruction stream.

[0191] The embodiment of the present invention ensures the correctness and consistency of instruction execution results and the correctness of program logic through write-back and commit operations, improves the utilization rate of physical register resources, ensures the continuity of instruction streams, and provides correct input for subsequent instructions.

[0192] In order to enable those skilled in the art to better understand the embodiments of the present invention, a complete example is used below to illustrate the embodiments of the present invention.

[0193] refer to Figure 2 , Figure 2 It is a flowchart of an instruction processing method provided in an embodiment of the present invention.

[0194] The example explains in detail how an instruction, after going through the instruction fetch and decode stages, passes through the multi-unit out-of-order execution scheduling module to complete the register renaming, dispatch, execution, and write-back delivery stages in sequence: S1: Register renaming stage: The instruction first searches for the corresponding physical register index PRS1 / PRS2 in the renaming mapping table RAT according to the source operand logical register index RS1 / RS2 obtained by decoding. Then, the instruction obtains a physical register Pdest from the free list of the physical register stack as the physical register of its destination logical register Dest. Finally, the instruction writes the mapping relationship between Dest and Pdest into RAT so that the corresponding physical register can be found when subsequent instructions access Dest. RAT is implemented using a register or SRAM array, with the logical register index as the address and the physical register index as the data. For example, for 32 logical registers and 128 physical registers, the SRAM contains 32 table entries, which are addressed by a 5-bit index, and each table entry stores a 7-bit physical register index.

[0195] S2: Dispatch phase: The dispatch scheduling module queries the data dependency queue OITF to check whether there are instructions that have not yet completed execution and whose target physical register is the same as the physical register of the source operand of the current instruction. If so, a RAW data dependency conflict occurs, and the module suspends the dispatch of the current instruction until the dependent instruction is written back. The module also checks whether the execution unit requested by the current instruction is ready; if all related units are busy, a structural conflict occurs, and the module pulls down the dispatch enable signal until resources are available. For multi-issue processors, to ensure that prediction errors or exceptions only affect the first cycle of the execution stage, if multiple instructions are dispatched at the same time and include predicted jump or exception instructions, only the instruction is dispatched, and the dispatch of other instructions is suspended for one cycle. When there is no conflict, the module dispatches the instruction to the queue to be executed and records the target physical register index Pdest in OITF to maintain data correctness. If multiple instructions need to be dispatched at the same time, the module will select according to the idle state and priority of the execution unit. After the instruction is successfully dispatched and written back, the corresponding table entry of OITF will be cleared.

[0196] S3: Execution phase: The instruction shakes hands with the execution unit according to the type, and is dispatched to the ALU, FPU or memory access unit, etc. according to the unit's idle status. The instruction is executed in the selected unit, and arithmetic operations, memory access or jump calculations are performed according to the function. During the execution phase, the exception judgment module continuously monitors the instruction, and once a prediction error or exception is found, exception handling is initiated. Exception detection is completed in the first clock cycle of the execution cycle, and a flush request is issued in the second cycle. At the same time, the detection and recovery unit evaluates whether there is a potential exception signal. If the flush request and the potential exception signal appear at the same time, the ROB, RAT, OITF and the current execution unit need to be restored. After the instruction is executed, it is marked as "completed" and its result is passed to the write-back module to be written to the physical register file PRF and updated to the target register in the delivery phase.

[0197] S4: Write-back delivery phase The write-back phase can only be entered when the instruction is successfully completed without exception in the execution phase. The instruction writes data to the physical register according to the execution result and the physical register index, and clears the data dependency in the OITF. In the delivery phase, the instruction results are delivered from the physical register to the logical register in program order to ensure execution order consistency. The delivery process depends on the mapping relationship (RAT) between the physical register and the logical register and the instruction order (ROB) before the program is out-of-order. After the instruction results are delivered and updated to the logical register, the relevant physical register will be marked as "free" and returned to the physical register pool to release resources. After the write-back delivery phase is completed, the system synchronously updates the status of each module, such as RAT and ROB, to ensure the correct mapping and delivery of subsequent instructions. The completion of this phase ensures the continuity of the instruction stream and prepares for the execution of the next instruction.

[0198] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0199] Reference Figure 3 , Figure 3 It is a structural block diagram of a processor provided in an embodiment of the present invention.

[0200] The embodiment of the present invention further discloses a processor, wherein the processor is configured with a multi-unit out-of-order execution scheduling module, wherein the multi-unit out-of-order execution scheduling module is used to obtain instructions to be executed, and the multi-unit out-of-order execution scheduling module includes a register renaming module, a dispatch scheduling module, an execution control module, and an instruction delivery module; The register renaming module, and / or the dispatch scheduling module, and / or the execution control module, and / or the instruction delivery module are used to enable the processor to execute the method described in the embodiment of the present invention when the multi-unit out-of-order execution scheduling module obtains the instruction to be executed.

[0201] In a specific implementation, an embodiment of the present invention proposes a processor, which includes an instruction fetch and decoding module for fetching instructions, and a multi-unit out-of-order execution scheduling module based on the RISC-V architecture, aiming to improve the efficiency and flexibility of high-performance processors.

[0202] The multi-unit out-of-order execution scheduling module significantly optimizes data dependency conflicts and achieves efficient out-of-order execution through refined register renaming, dispatch scheduling and instruction delivery mechanisms. At the same time, the multi-unit out-of-order execution scheduling module adopts a regular and configurable data interaction port design and a valid-ready handshake mechanism to enhance its compatibility and scalability, and supports customized access to execution units with different functions and numbers. In addition, the independently designed flush control logic can efficiently handle special situations such as branch prediction failures and interrupt exceptions, effectively reducing performance losses and area overhead.

[0203] The structure of the multi-unit out-of-order execution scheduling module: The multi-unit out-of-order execution scheduling module contains the following core components: Register renaming module 301: responsible for the register renaming stage of instructions, consisting of physical registers (PRF), reorder buffer (ROB), rename mapping table (RAT) and control path. By mapping limited logical registers (ARF) to more physical registers (PRF), this module effectively reduces WAW and WAR data conflicts, reduces pipeline blocking, and improves processor performance.

[0204] Physical Register File (PRF): Stores the intermediate results of instruction execution until the instruction is completed and committed to the Logical Register File (ARF) in program order.

[0205] Reorder Buffer (ROB): Ensures that the results of instructions in out-of-order execution are submitted in program order, solving data dependency problems between instructions.

[0206] Rename Map Table (RAT): stores the mapping relationship between logical registers and physical registers, and provides the physical register index corresponding to the logical register.

[0207] Dispatch scheduling module 302: responsible for the instruction dispatch stage, including the data dependency queue (OITF), dependency judgment module (Depend) and control path. This module detects potential RAW data conflicts and structural conflicts by identifying instruction categories and physical register indexes, and controls instruction dispatch.

[0208] Data dependency queue (OITF): tracks the physical register operands of instructions that are being executed but not yet written back, and detects RAW data dependency conflicts.

[0209] Dependency determination module (Depend): identifies potential pipeline conflict risks, controls instruction dispatch, and handles special instruction dispatch in multi-issue processors.

[0210] Execution control module 303: The execution control module includes an abnormality judgment module and an execution control module, which is responsible for handling abnormal situations in the execution phase, including an abnormality judgment module and a recovery detection module. This module can detect abnormalities in the early cycle and reduce recovery costs.

[0211] Exception judgment module: detects predicted jump instructions and abnormal instructions, and quickly initiates flush error requests during the execution phase.

[0212] Recovery detection module: When an exception occurs, it detects the execution units and control logic that need to be recovered.

[0213] Instruction delivery module 304: responsible for the write-back and delivery phases of instructions, including an instruction write-back module and an instruction delivery module. This module ensures that the instruction result is correctly written into the physical register and delivered to the logical register in program order.

[0214] Instruction write-back module: writes the calculation results of the execution unit back to the physical register file (PRF) and updates the data dependencies.

[0215] Instruction delivery module: delivers the data in the physical register to the logical register file (ARF) in program order to complete instruction submission.

[0216] The workflow of the multi-unit out-of-order execution scheduling module is as follows: Instruction acquisition: The scheduling module receives instruction information from the RISC-V processor after the instruction fetch and decoding stages.

[0217] Register renaming stage: The scheduling module renames registers based on the source operand and destination register of the instruction.

[0218] Dispatch phase: The dispatch module determines data dependency conflicts and dispatches instructions when conditions permit.

[0219] Execution stage: Instructions are dispatched to the corresponding execution units for execution, during which the execution control module handles special situations such as prediction errors and interrupt exceptions.

[0220] Write-back delivery phase: The calculation result of the instruction is written back to the physical register and updated to the logical register in the order of instruction fetch to complete the instruction delivery.

[0221] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

[0222] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0223] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0224] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0225] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0226] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0227] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical disks.

[0228] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A command processing method, characterized in that: include: Obtaining instructions to be executed, and determining conflict types of the instructions to be executed; Allocating a physical register to the instruction to be executed based on the conflict type; Determining dependency conflicts and resource conflicts of the instructions to be executed, and determining an execution order of the instructions to be executed based on the dependency conflicts and the resource conflicts; Determine a target execution unit based on the execution order, and send the to-be-executed instruction to the target execution unit; The target execution unit is controlled to execute the instruction to be executed, and when the instruction to be executed is completed, the instruction to be executed is written into the physical register.

2. The method according to claim 1, characterized in that The instructions to be executed include at least a first instruction, a second instruction and a third instruction, the first instruction, the second instruction and the third instruction are arranged in sequence, and the step of allocating physical registers to the instructions to be executed based on the conflict type includes: When it is determined that the logical register to which the first instruction has executed a write operation, the logical register to which the second instruction is about to execute a read operation, and the logical register to which the third instruction is about to execute a write operation are the same first logical register, determining a first target physical register; Constructing a first mapping relationship between the first logical register and a first target physical register; Adding a first mapping relationship between the first logical register and the first target physical register to a preset renaming mapping table; the first mapping relationship is used to control the second instruction to perform a read operation on the first target physical register by reading the first mapping relationship in the renaming mapping table when performing a read operation; determining a second target physical register; the first target physical register and the second target physical register are independent of each other; A second mapping relationship between the first logical register and the second target physical register is constructed; the second mapping relationship is used to control the third instruction to perform a write operation to the second target physical register when performing a write operation.

3. The method according to claim 1, characterized in that The step of allocating physical registers for the instructions to be executed based on the conflict type comprises: When it is determined that the write operations of different instructions to be executed correspond to the same second logical register, an independent and unique physical register is allocated to each of the instructions to be executed.

4. The method according to claim 3, characterized in that The step of allocating an independent and unique physical register to each of the instructions to be executed comprises: determining an independent and unique physical register as a third target physical register; Constructing a third mapping relationship between the second logical register and a third target physical register; The third mapping relationship is stored in a preset renaming mapping table.

5. The method according to claim 1, characterized in that The step of determining the dependency conflict situation and the resource conflict situation of the instructions to be executed, and determining the execution order of the instructions to be executed based on the dependency conflict situation and the resource conflict situation comprises: Checking, through the data dependency queue, whether there is an executing instruction that has not yet been completed; the executing instruction and the to-be-executed instruction use the same physical register; Check whether the target execution unit is available; When it is determined that there is no executing instruction that has not yet been executed and the target execution unit is available, the to-be-executed instruction is added to a to-be-executed queue.

6. The method according to claim 5, characterized in that The step of determining a target execution unit based on the execution order and sending the to-be-executed instruction to the target execution unit comprises: When it is determined that the processor type is a multi-issue processor, and the multi-issue processor simultaneously dispatches multiple instructions to be executed, and there is a special instruction among the multiple instructions to be executed, the special instruction is sent to the target execution unit; the special instruction is a predicted jump instruction or an exception instruction.

7. The method according to claim 5, characterized in that Before the step of determining the target execution unit based on the execution order and sending the to-be-executed instruction to the target execution unit, the method further includes: A physical register index of the physical register is saved to a data dependency queue.

8. The method according to claim 6, characterized in that The step of controlling the target execution unit to execute the instruction to be executed comprises: When it is determined that a prediction error or abnormal state occurs during the execution of the instruction to be executed, a flush error request is initiated, and whether there is a potential abnormal signal; When it is determined that there is a potential exception signal, a recovery operation is performed on the reorder cache of the register renaming module, and / or the renaming mapping table, and / or the data dependency queue of the dispatch scheduling module, and / or the target execution unit.

9. The method according to claim 8, characterized in that When the instruction to be executed is completed, the step of writing the instruction to be executed into the physical register comprises: When it is determined that no prediction error or abnormal state occurs during the execution of the instruction to be executed and the execution of the instruction to be executed is completed, the instruction to be executed and the execution result of the instruction to be executed are written into the physical register based on the execution order according to the physical register index of the physical register; When it is determined that the physical register sends the instruction to be executed and the execution result to the logical register corresponding to the instruction to be executed, the physical register is marked as an idle state.

10. A processor, characterized in that: The processor is configured with a multi-unit out-of-order execution scheduling module, which is used to obtain instructions to be executed, and the multi-unit out-of-order execution scheduling module includes a register renaming module, a dispatch scheduling module, an execution control module and an instruction delivery module; The register renaming module, and / or the dispatch scheduling module, and / or the execution control module, and / or the instruction delivery module are used to implement the method described in any one of claims 1-9 when the multi-unit out-of-order execution scheduling module obtains the instruction to be executed.

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