Invalid instruction generation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an invalid instruction generation method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that a first instruction coding format is selected from an instruction coding format set corresponding to a preset instruction set architecture; generating a first random code of which the coding length is equal to the total length of the fixed bit segment of the first instruction coding format; and under the condition that the first random code is inconsistent with each preset fixed code corresponding to the first instruction coding format, generating an invalid instruction corresponding to the preset instruction set architecture based on the first random code. According to the technical scheme, the invalid instruction which does not conform to the instruction coding format corresponding to the preset instruction set architecture can be directly generated in a random generation mode, and the efficiency of generating the invalid instruction of the preset instruction set architecture can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and in particular to an invalid instruction generation method, device, electronic device and storage medium. Background Art

[0002] At present, with the continuous development of computer technology, the design of the central processing unit (CPU) is becoming more and more complex. Usually, an instruction generator is used to randomly generate some instructions to test the CPU. These instructions include valid instructions that comply with the instruction set architecture of the CPU, and invalid instructions that do not comply with the definition of the instruction set architecture of the CPU.

[0003] In the related art, valid instructions that meet a certain instruction type are usually generated according to the definition requirements of the instruction set architecture, and then these valid instructions are modified to generate invalid instructions that are different from the valid instructions. However, the efficiency of generating invalid instructions in the above manner is poor. Summary of the invention

[0004] The embodiments of the present invention provide an invalid instruction generation method, device, electronic device and storage medium, which can improve the efficiency of generating invalid instructions.

[0005] In order to solve the above problem, an embodiment of the present invention discloses a method for generating an invalid instruction, the method comprising: Selecting a first instruction encoding format from a set of instruction encoding formats corresponding to a preset instruction set architecture; Generate a first random code having a code length equal to a total length of a fixed bit segment of the first instruction encoding format; When the first random code is inconsistent with all preset fixed codes corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code; wherein the invalid instruction is used to test the central processing unit.

[0006] Optionally, the generating, based on the first random code, an invalid instruction corresponding to the preset instruction set architecture includes: Generate a pending instruction corresponding to the first instruction encoding format based on the first random code; When the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture, the pending instruction is determined as an invalid instruction corresponding to the preset instruction set architecture; wherein the other instruction encoding formats represent instruction encoding formats in the preset instruction set architecture other than the first instruction encoding format.

[0007] Optionally, the method further includes: Based on the fixed bit segment range information corresponding to other instruction encoding formats in the instruction encoding format set, extracting each first fixed bit segment code corresponding to the other instruction encoding formats from the pending instruction; Based on the bit segment sequence corresponding to each first fixed bit segment code, concatenate each first fixed bit segment code to obtain a code to be compared; When the code to be compared is inconsistent with each preset fixed code corresponding to the other instruction encoding formats, it is determined that the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture.

[0008] Optionally, the generating, based on the first random code, a pending instruction corresponding to the first instruction encoding format includes: Generate a second random code corresponding to the variable bit segment of the first instruction encoding format; The first random code and the second random code are concatenated to obtain a pending instruction corresponding to the first instruction encoding format.

[0009] Optionally, the concatenating the first random code and the second random code to obtain a pending instruction corresponding to the first instruction encoding format includes: Based on the fixed bit segment range information of the first instruction encoding format, the first random code is divided to obtain second fixed bit segment codes corresponding to the fixed bit segments of the first instruction encoding format; Based on the bit segment order corresponding to the second random code and each second fixed bit segment code, the second random code and each second fixed bit segment code are concatenated to obtain a pending instruction corresponding to the first instruction encoding format.

[0010] Optionally, after generating the invalid instruction corresponding to the preset instruction set architecture based on the first random code, the method further includes: Determine the first random code corresponding to the invalid instruction as a preset fixed code corresponding to the first instruction encoding format; The step of selecting the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture is re-executed to continue generating the next invalid instruction, thereby obtaining an invalid instruction sequence including multiple invalid instructions.

[0011] Optionally, the method further includes: Obtaining fixed bit segment range information corresponding to the first instruction encoding format; Determine the fixed bit segment lengths corresponding to the fixed bit segments of the first instruction encoding format based on the fixed bit segment range information; The total length of the fixed bit segments is determined based on the fixed bit segment lengths respectively corresponding to the fixed bit segments.

[0012] On the other hand, an embodiment of the present invention discloses an invalid instruction generating device, the device comprising: A selection module, configured to select a first instruction encoding format from a set of instruction encoding formats corresponding to a preset instruction set architecture; A generating module, used for generating a first random code having a code length equal to a total length of a fixed bit segment of the first instruction coding format; An instruction module is used to generate an invalid instruction corresponding to the preset instruction set architecture based on the first random code when the first random code is inconsistent with each preset fixed code corresponding to the first instruction code format; wherein the invalid instruction is used to test the central processing unit.

[0013] Optionally, the instruction module includes: A pending instruction submodule, used for generating a pending instruction corresponding to the first instruction encoding format based on the first random code; An invalid instruction submodule is used to determine the pending instruction as an invalid instruction corresponding to the preset instruction set architecture when the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture; wherein the other instruction encoding formats represent instruction encoding formats in the preset instruction set architecture other than the first instruction encoding format.

[0014] Optionally, the device further comprises: A first fixed bit segment coding module, configured to extract first fixed bit segment codes corresponding to other instruction coding formats in the instruction coding format set from the pending instruction based on fixed bit segment range information corresponding to other instruction coding formats in the instruction coding format set; A code module to be compared, used for splicing the first fixed bit segment codes based on the bit segment sequence corresponding to the first fixed bit segment codes to obtain the code to be compared; The determination module is used to determine that the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture when the code to be compared is inconsistent with each preset fixed code corresponding to the other instruction encoding formats.

[0015] Optionally, the pending instruction submodule includes: A random encoding unit, used for generating a second random code corresponding to the variable bit segment of the first instruction encoding format; The pending instruction generating unit is used to concatenate the first random code and the second random code to obtain a pending instruction corresponding to the first instruction encoding format.

[0016] Optionally, the pending instruction generating unit includes: a segmentation subunit, configured to segment the first random code based on the fixed bit segment range information of the first instruction encoding format, to obtain second fixed bit segment codes corresponding to the fixed bit segments of the first instruction encoding format; The pending instruction splicing subunit is used to splice the second random code and each second fixed bit segment code based on the bit segment sequence corresponding to the second random code and each second fixed bit segment code to obtain the pending instruction corresponding to the first instruction coding format.

[0017] Optionally, the device further comprises: A preset fixed coding module, used for determining the first random code corresponding to the invalid instruction as a preset fixed code corresponding to the first instruction coding format; The invalid instruction sequence module is used to re-execute the step of selecting the first instruction encoding format from the instruction encoding format set corresponding to the preset instruction set architecture, and continue to generate the next invalid instruction, thereby obtaining an invalid instruction sequence including multiple invalid instructions.

[0018] Optionally, the device further comprises: A fixed bit segment range information module, used to obtain fixed bit segment range information corresponding to the first instruction encoding format; A fixed bit segment length module, used to determine the fixed bit segment lengths corresponding to each fixed bit segment of the first instruction encoding format based on the fixed bit segment range information; The fixed bit segment total length module is used to determine the fixed bit segment total length based on the fixed bit segment lengths corresponding to each fixed bit segment.

[0019] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0020] The embodiment of the present invention further discloses a computer-readable storage medium on which instructions are stored. When executed by one or more processors, the processors execute the method as described above.

[0021] The embodiments of the present invention include the following advantages: in the invalid instruction generation method provided in the embodiments of the present invention, a first instruction encoding format is selected from the instruction encoding format set corresponding to the preset instruction set architecture; a first random code is generated whose encoding length is equal to the total length of the fixed bit segment of the first instruction encoding format; when the first random code is inconsistent with each preset fixed code corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code. Invalid instructions that do not conform to the instruction encoding format corresponding to the preset instruction architecture can be directly generated by random generation, which helps to improve the efficiency of generating invalid instructions of the preset instruction set architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0023] Figure 1 is a flow chart of the steps of an invalid instruction generation method provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of an invalid instruction generation process provided by an embodiment of the present invention; Figure 3 is a block diagram of an invalid instruction generating device provided by an embodiment of the present invention; Figure 4 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Reference Figure 1 , shows a flow chart of the steps of an invalid instruction generation method provided by an embodiment of the present invention, such as Figure 1 As shown, the method may specifically include the following steps: Step 101: Select a first instruction encoding format from a set of instruction encoding formats corresponding to a preset instruction set architecture.

[0026] During the design and verification of the central processing unit (CPU), test instructions are usually generated for testing, and the CPU core to be tested is actually tested or simulated using the test instructions. The test environment may include a hardware environment and a simulation environment, that is, the CPU core to be tested may be a physical core or a simulated core. The above test instructions may refer to instructions generated by certain rules or randomly generated instructions.

[0027] When testing the CPU core, it is necessary not only to test whether the CPU core can correctly respond to the correct valid instructions with clear definitions, but also to test whether the CPU core's response process to invalid instructions can proceed smoothly according to the design requirements, that is, it is necessary to test whether the response generated by the CPU core when receiving invalid instructions meets the design requirements. These responses may include but are not limited to abnormal jumps, abnormal triggering conditions, whether the abnormal trigger type is accurate, interrupt logic, etc., in order to judge the security, robustness, stability and other characteristics of the CPU core. Among them, invalid instructions can represent instructions that do not conform to the instruction encoding specifications of the instruction set architecture of the CPU core to be tested. Invalid instructions can also be called undefined instructions, illegal instructions, illegal instructions, error instructions, abnormal instructions, etc., which are not specifically limited in the embodiments of the present invention.

[0028] In an embodiment of the present invention, in order to generate an invalid instruction, a first instruction encoding format can be selected from a set of instruction encoding formats corresponding to a preset instruction set architecture. The preset instruction set architecture represents the instruction set architecture of the CPU core to be tested, such as RISC-V, ARM, X86, etc.; the set of instruction encoding formats can include all instruction encoding formats corresponding to the preset instruction set architecture, and the instruction encoding format is used to define the structure of binary instructions that the processor can recognize and execute, that is, to specify the binary representation of valid instructions. Specifically, the instruction encoding format can define which bit segments are included in the instruction binary encoding in the corresponding instruction set architecture, and the meaning of each bit segment.

[0029] For example, an instruction encoding format A may be as shown in Table 1 below: Table 1

[0030] Among them, the instruction encoding format A is 12 bits long and contains 4 bit segments. The binary bits with the bit sequence from 0 to 3 are bit segment 1, the binary bits with the bit sequence from 4 to 5 are bit segment 2, and so on.

[0031] In an embodiment of the present invention, an instruction encoding format set including all instruction encoding formats corresponding to a preset instruction set architecture may be pre-established, and when an invalid instruction of the preset instruction set architecture needs to be generated, an instruction encoding format is selected from the corresponding instruction encoding format set as the first instruction encoding format. The above selection method may include but is not limited to random selection, sequential selection, selection according to rules, etc., and the embodiment of the present invention does not specifically limit this.

[0032] Step 102: Generate a first random code whose code length is equal to the total length of the fixed bit segment of the first instruction encoding format.

[0033] In an embodiment of the present invention, after selecting and obtaining the first instruction encoding format, the total length of the fixed bit segment corresponding to the first instruction encoding format can be determined. Among them, the total length of the fixed bit segment represents the sum of the lengths of all fixed bit segments defined in the corresponding first instruction encoding format, and the fixed bit segment represents the bit segment with predefined specific content in the instruction binary encoding. The fixed bit segment may include but is not limited to the bit segment used to define the instruction opcode, the bit segment used to define the instruction function, and so on. In other words, the specific content of the fixed bit segment can determine the instruction type of the instruction, and the fixed bit segment corresponding to each instruction type has a clear content. Exemplarily, if a certain instruction encoding format includes a fixed bit segment 1 and a fixed bit segment 2, the fixed bit segment 1 content preset by the instruction type ADD is 0010, and the fixed bit segment 2 content is 0001. If in the binary encoding of an instruction C, the fixed bit segment 1 is 0010 and the fixed bit segment 2 is 0001, then the instruction C is identified as an ADD instruction.

[0034] In one embodiment, each instruction encoding format in the instruction encoding format set may correspond to a fixed bit segment total length, and each instruction encoding format may be recorded in the instruction encoding format set in the form of a format identifier, so that after selecting the first instruction encoding format from the instruction encoding format set, the corresponding fixed bit segment total length may be queried through the corresponding format identifier to obtain the fixed bit segment total length corresponding to the first instruction encoding format, and then a random code with a code length equal to the fixed bit segment total length is generated as the first random code. The random code generated above is in binary form, that is, each bit of the random code is 0 or 1.

[0035] In another embodiment, the instruction encoding format in the instruction encoding format set may include specific format information. After selecting the first instruction encoding format from the instruction encoding format set, the format information of the first instruction encoding format may be analyzed to determine the length of each fixed bit segment and sum them to obtain the total length of the fixed bit segment, and then generate a random code with a code length equal to the total length of the fixed bit segment as the first random code.

[0036] In an embodiment of the present invention, the above-mentioned first random code can be generated by a random number generator. In one embodiment, the base number (binary) and the first random number digit (total length of the fixed bit segment) can be input into the random number generator, so that the random number generator outputs the first random code with a code length equal to the total length of the fixed bit segment at one time. In another embodiment, the base number (binary) and the second random number digit (a factor of the total length of the fixed bit segment) can be input into the random number generator, so that the random number generator outputs a plurality of random numbers with a length equal to the factor, and these random numbers are spliced ​​to obtain the first random code with a code length equal to the total length of the fixed bit segment. The embodiment of the present invention does not specifically limit the method of generating the first random code.

[0037] Step 103: When the first random code is inconsistent with any preset fixed code corresponding to the first instruction encoding format, generate an invalid instruction corresponding to the preset instruction set architecture based on the first random code; wherein the invalid instruction is used to test the central processing unit.

[0038] In the embodiment of the present invention, after obtaining the first random code, the first random code can be compared with all preset fixed codes corresponding to the first instruction coding format. If the first random code is different from all preset fixed codes corresponding to the first instruction coding format, it means that the first random code does not match any instruction type defined in the first instruction coding format, and an invalid instruction corresponding to the preset instruction set architecture can be generated according to the first random code. Among them, a preset fixed code corresponding to the instruction coding format represents: the code obtained by splicing the contents of all fixed bit segments corresponding to an instruction type defined in the instruction coding format.

[0039] For example, if the bit segment 1 and bit segment 3 in the instruction encoding format shown in Table 1 are fixed bit segments, there are two instruction types defined under the instruction encoding format: instruction type C1 and instruction type C2, wherein the content of bit segment 1 defined by instruction type C1 is 0000 and the content of bit segment 3 is 101; the content of bit segment 1 defined by instruction type C2 is 1010 and the content of bit segment 3 is 010. Then the preset fixed code corresponding to instruction type C1 defined in the instruction encoding format can be 1010000 (obtained by concatenating the content of bit segment 1 and the content of bit segment 3 corresponding to instruction C1), and the preset fixed code corresponding to instruction type C2 can be 1010010. Among them, the method of splicing the contents of each bit segment may include the high-order bit segment first and the low-order bit segment second, or the low-order bit segment first and the high-order bit segment second. For example, if the splicing method of the high-order bit segment first and the low-order bit segment second is adopted, the preset fixed code corresponding to the instruction type C2 is 1010010. If the splicing method of the low-order bit segment first and the high-order bit segment second is adopted, the preset fixed code corresponding to the instruction type C1 is 0010101. In the embodiment of the present invention, all processes of splicing bit segments may adopt the method of the high-order bit segment first and the low-order bit segment second. The preset fixed code of the instruction encoding format obtained by splicing in this way can be represented by the following set CAT_SET1: CAT_SET1 = {1010000,1010010}.

[0040] Specifically, if the first random code is inconsistent with all preset fixed codes corresponding to the corresponding first instruction coding format, the first random code can be expanded according to the instruction coding format corresponding to the first random code, expanded to the instruction bit number defined by the corresponding instruction coding format, and an invalid instruction is obtained, and the position of the code corresponding to each fixed bit segment in the first random code in the invalid instruction is kept to conform to the definition of the instruction coding format. That is, the first random code is filled to obtain the instruction binary code of the corresponding invalid instruction.

[0041] In one implementation, the binary bits filled in the invalid instruction may be preset bits (e.g., 1 bits or 0 bits), that is, the binary bits filled in the invalid instruction may all be 1 bits or all be 0 bits. In another implementation, the binary bits filled in the invalid instruction may also be random binary bits, which is not specifically limited in the embodiment of the present invention.

[0042] Continuing with the above example, if the first random code is "1110110", the corresponding first instruction encoding format is shown in Table 1. The first random code "1110110" can be compared with each element of the above set CAT_SET1. Since the first random code "1110110" is inconsistent with each element, an invalid instruction can be further generated based on the first random code "1110110". Since the high bit "111" in the first random code corresponds to bit segment 3, and the low bit "0110" in the first random code corresponds to bit segment 1, the two preset bits (0 bits) corresponding to bit segment 2 can be inserted between "111" and "0110", and the three preset bits (0 bits) corresponding to bit segment 4 can be inserted on the left side of "111", and the corresponding invalid instruction "000111000110" is obtained.

[0043] In the embodiment of the present invention, after determining an invalid instruction, step 101 can be re-executed, and a first instruction encoding format can be selected from the instruction encoding format set corresponding to the preset instruction set architecture, and invalid instructions corresponding to the first instruction encoding format can be continuously generated. Thus, a large number of invalid instructions can be obtained for testing the corresponding CPU core. In addition, the obtained multiple invalid instructions can be combined into an invalid instruction stream, so as to implement a large number of invalid instruction tests on the CPU core at one time, thereby improving the test efficiency.

[0044] In summary, in an invalid instruction generation method provided by an embodiment of the present invention, a first instruction encoding format is selected from a set of instruction encoding formats corresponding to a preset instruction set architecture; a first random code is generated whose encoding length is equal to the total length of the fixed bit segment of the first instruction encoding format; when the first random code is inconsistent with each preset fixed code corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code. Invalid instructions that do not conform to the instruction encoding format corresponding to the preset instruction architecture can be directly generated by random generation, which helps to improve the efficiency of generating invalid instructions for the preset instruction set architecture.

[0045] Optionally, in some embodiments, the step of generating a first random code having a code length equal to the total length of the fixed bit segment of the first instruction encoding format may be specifically implemented by the following process: In an embodiment of the present invention, when generating the first random code, the preset fixed code set consisting of all preset fixed codes corresponding to the first instruction code format can be used to determine the random constraint when generating the first random code, that is, the random constraint can include: the generated random code does not belong to any code in the preset fixed code set. Thus, through the above random constraint, a first random code that is inconsistent with all preset fixed codes corresponding to the first instruction code format can be directly generated, so there is no need to actually match the first random code with all preset fixed codes corresponding to the first instruction code format. The first random code obtained in this generation mode can be directly determined to be inconsistent with all preset fixed codes corresponding to the first instruction code format, and the step of generating an invalid instruction corresponding to the preset instruction set architecture according to the first random code is directly executed, which helps to improve the generation efficiency of invalid instructions. It should be noted that the above random constraint can also include base constraint, length constraint, value range constraint, etc., which are not specifically limited in the embodiment of the present invention.

[0046] Optionally, in some embodiments, the step of generating an invalid instruction corresponding to the preset instruction set architecture based on the first random code may specifically include: Step 1031: Generate a pending instruction corresponding to the first instruction encoding format based on the first random code.

[0047] In an embodiment of the present invention, since the instruction encoding format set corresponding to the preset instruction set architecture may include multiple instruction encoding formats, when the instruction encoding format set includes multiple instruction encoding formats, the invalid instruction finally generated needs to be an invalid instruction for all instruction encoding formats in the instruction encoding format set before it can be determined to be an invalid instruction corresponding to the preset instruction set architecture. Therefore, in an embodiment of the present invention, when the instruction encoding format set includes multiple instruction encoding formats, a pending instruction corresponding to the preset instruction set architecture is first generated based on the first random code. Among them, the pending instruction represents an instruction whose fixed bit segment does not match the preset fixed code defined by the first instruction encoding format.

[0048] It should be noted that the method of generating the above pending instructions may be the same as the method of generating the invalid instructions in the above step 103, which will not be described in detail in the embodiment of the present invention.

[0049] Optionally, in some embodiments, the step of generating a pending instruction corresponding to the first instruction encoding format based on the first random code may specifically include: Step A1, generating a second random code corresponding to the variable bit segment of the first instruction encoding format.

[0050] In the embodiment of the present invention, a variable bit segment may also be defined in the instruction encoding format, and the variable bit segment represents a bit segment composed of bits used to record variable information such as a logical register number and an immediate value in the instruction. Generally speaking, a bit segment other than a fixed bit segment is a variable bit segment.

[0051] In an embodiment of the present invention, since the instruction encoding format not only defines a fixed bit segment but also defines a variable bit segment, in order to be able to generate a pending instruction consisting of a fixed bit segment and a variable bit segment, a second random code corresponding to the corresponding variable bit segment can also be generated for the corresponding first instruction encoding format.

[0052] Specifically, the first instruction encoding format may define the bit segment length and bit segment position of each variable bit segment, and the second random code corresponding to each variable bit segment may be generated based on the bit segment length of the variable bit segment. Exemplarily, in the instruction encoding format shown in Table 1, if bit segment 2 and bit segment 4 are variable bit segments, a 2-bit second random code 1 (for example, 10) and a 3-bit second random code 2 (for example, 001) may be generated for bit segment 2 and bit segment 4, respectively.

[0053] Step A2: concatenate the first random code and the second random code to obtain a pending instruction corresponding to the first instruction encoding format.

[0054] In the embodiment of the present invention, the first random code and the second random code can be spliced ​​to obtain a complete pending instruction corresponding to the first instruction encoding format. During the splicing process, the codes corresponding to the fixed bit segments in the first random code and the codes corresponding to the variable bit segments in the second random code can be combined according to the bit segment sequence defined in the corresponding first instruction encoding format, thereby obtaining a pending instruction that satisfies the first instruction encoding format.

[0055] The second random code corresponding to the variable bit segment of the first instruction encoding format is generated; the first random code and the second random code are concatenated to obtain the pending instruction corresponding to the first instruction encoding format. The codes of the fixed bit segment and the variable bit segment in the pending instruction can be obtained based on the random code, thereby generating a pending instruction with high randomness under a preset instruction set architecture, improving the unpredictability of the pending instruction, and thus helping to improve the effectiveness of testing the CPU core based on invalid instructions determined by the pending instruction.

[0056] Optionally, the step of concatenating the first random code and the second random code to obtain a pending instruction corresponding to the first instruction encoding format may specifically include: Step A21, based on the fixed bit segment range information of the first instruction encoding format, divide the first random code to obtain second fixed bit segment codes corresponding to each fixed bit segment of the first instruction encoding format.

[0057] In an embodiment of the present invention, the instruction encoding format may include fixed bit segment range information, and the fixed bit segment range information is used to indicate the binary bit range of each fixed bit segment in the instruction encoding format in the corresponding instruction binary encoding. Exemplarily, taking the instruction encoding format described in Table 1 above as an example, the fixed bit segment range information may include: the 0th to 3rd bit sequence belongs to the fixed bit segment, and the 6th to 8th bit sequence belongs to the fixed bit segment.

[0058] In an embodiment of the present invention, the bit segment length of each fixed bit segment can be determined based on the fixed bit segment range information of the first instruction encoding format, and then the first random code can be divided according to the bit segment length of each fixed bit segment to obtain the second fixed bit segment code corresponding to each fixed bit segment of the first instruction encoding format.

[0059] Exemplarily, if the first random code is 1110110, the corresponding first instruction encoding format is shown in Table 1, and its fixed bit segment range information may include: bits 0 to 3 belong to a fixed bit segment, and bits 6 to 8 belong to a fixed bit segment. According to the fixed bit segment range information, the bit segment lengths of each fixed bit segment can be determined as follows: the bit segment length of bit segment 1 is 4, and the bit segment length of bit segment 3 is 3. According to the above bit segment lengths, the first random code 1110110 is segmented to obtain the second fixed bit segment codes 111 and 0110.

[0060] Step A22, based on the bit segment order corresponding to the second random code and each second fixed bit segment code, splice the second random code and each second fixed bit segment code to obtain the pending instruction corresponding to the first instruction encoding format.

[0061] In the embodiment of the present invention, the second random code and each second fixed bit segment code may be concatenated based on the bit segment sequence corresponding to the second random code and each second fixed bit segment code to obtain a pending instruction corresponding to the first instruction encoding format.

[0062] Specifically, since each second random code corresponds to a corresponding variable bit segment, and each second fixed bit segment code corresponds to a corresponding fixed bit segment, the bit segment order of each variable bit segment and fixed bit segment is defined in the corresponding first instruction encoding format, therefore, the corresponding second random code and the second fixed bit segment code can be directly spliced ​​according to the bit segment order defined in the first instruction encoding format to obtain the pending instruction. It should be noted that the above-mentioned bit segment order can be determined by calculating the position / range information of each bit segment, or can be directly predefined, and the embodiment of the present invention does not make specific limitations.

[0063] In the embodiment of the present invention, the first random code can be segmented based on the fixed bit segment range information of the first instruction encoding format to obtain the second fixed bit segment codes corresponding to each fixed bit segment of the first instruction encoding format; based on the bit segment sequence corresponding to the second random code and each second fixed bit segment code, the second random code and each second fixed bit segment code are spliced ​​to obtain the pending instruction corresponding to the first instruction encoding format. The code of each fixed bit segment and variable bit segment can be determined, and these codes can be accurately spliced ​​based on the defined bit segment sequence to obtain the corresponding pending instruction, which helps to improve the stability and accuracy of the pending instruction generation process.

[0064] Step 1032: When the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture, determine the pending instruction as an invalid instruction corresponding to the preset instruction set architecture; wherein the other instruction encoding formats represent instruction encoding formats in the preset instruction set architecture other than the first instruction encoding format.

[0065] In an embodiment of the present invention, it is possible to determine whether a pending instruction matches other instruction encoding formats in a preset instruction set architecture. If the pending instruction does not match any other instruction encoding formats in the preset instruction set architecture, the pending instruction can be determined as an invalid instruction corresponding to the preset instruction set architecture; if the pending instruction matches at least one other instruction encoding format in the preset instruction set architecture, it means that the pending instruction is legal for at least one instruction encoding format and cannot be used as an invalid instruction of the preset instruction set architecture. Among them, other instruction encoding formats can represent other instruction encoding formats except the first instruction encoding format among all instruction encoding formats corresponding to the preset instruction set architecture.

[0066] In an embodiment of the present invention, if the pending instruction matches at least one other instruction encoding format in the preset instruction set architecture, the pending instruction can be discarded and a first random code having a coding length equal to the total length of the fixed bit segment of the first instruction encoding format can be regenerated, that is, a new first random code is generated, and then the above step 1031 is re-executed based on the new first random code to generate a new pending instruction to continue judging until a pending instruction that does not match other instruction encoding formats corresponding to the preset instruction set architecture is obtained, and the pending instruction is regarded as an invalid instruction of the preset instruction set architecture.

[0067] By generating a pending instruction corresponding to a preset instruction set architecture based on the first random code; when the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture, the pending instruction is used as an invalid instruction corresponding to the preset instruction set architecture. The generated invalid instruction can be made undefined for all instruction encoding formats of the preset instruction set architecture, which helps to improve the accuracy of the generated invalid instruction.

[0068] Optionally, in some embodiments, whether the pending instruction matches the encoding format of other instructions can be determined by the following steps: Step B1, based on the fixed bit segment range information corresponding to other instruction encoding formats in the instruction encoding format set, extract each first fixed bit segment code corresponding to the other instruction encoding formats from the pending instruction.

[0069] In an embodiment of the present invention, for each other instruction encoding format in the instruction encoding format set, the fixed bit segment range information corresponding to the other instruction encoding format can be obtained, and based on the fixed bit segment range information, the first fixed bit segment code corresponding to each fixed bit segment of the corresponding other instruction encoding format is extracted from the pending instruction. The first fixed bit segment code represents the fixed bit segment code corresponding to the fixed bit segment defined by the other instruction encoding format in the pending instruction.

[0070] For example, if the preset instruction set architecture includes two instruction encoding formats, in a certain generation process, the first instruction encoding format selected is as shown in Table 1 above, then the other instruction encoding format can be used as the other instruction encoding format, and the other instruction encoding format can be as shown in Table 2 below: Table 2

[0071] Among them, in other instruction encoding formats shown in Table 2, bit segments 1, bit segments 3 and bit segments 5 are fixed bit segments, and bit segments 2 and bit segments 4 are variable bit segments. Correspondingly, the fixed bit segment range information can be: bit 0 to bit 2 (bit segment 1), bit 5 to bit 7 (bit segment 3), bit 10 to bit 11 (bit segment 5).

[0072] If the generated pending instruction is "000111000110", based on the fixed bit segment range information of the above-mentioned other instruction encoding formats, the 0th to 2nd bits, the 5th to 7th bits, and the 10th to 11th bits of the pending instruction can be extracted to obtain the first fixed bit segment codes "110", "110" and "00" respectively.

[0073] Step B2, based on the bit segment sequence corresponding to each first fixed bit segment code, splice each first fixed bit segment code to obtain the code to be compared.

[0074] In the embodiment of the present invention, in order to improve the comparison efficiency, each first fixed bit segment code can be spliced ​​according to the corresponding bit segment sequence to obtain the code to be compared. The bit segment sequence corresponding to the first fixed bit segment code can be determined based on the fixed bit segment range information of each first fixed bit segment code.

[0075] Continuing with the above example, if the first fixed bit segment codes include "110", "110" and "00", the code to be compared can be concatenated into "00110110" according to the bit segment sequence corresponding to each first fixed bit segment code.

[0076] Step B3, when the code to be compared is inconsistent with each preset fixed code corresponding to the other instruction encoding formats, it is determined that the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture.

[0077] In the embodiment of the present invention, for each other instruction encoding format, all preset fixed codes corresponding to the other instruction encoding format can be obtained, and the codes to be compared corresponding to the other instruction encoding format are compared one by one with the preset fixed codes corresponding to them. If the code to be compared is inconsistent with all its preset fixed codes, it can be determined that the pending instruction corresponding to the code to be compared does not match the other instruction encoding format. Among them, the preset fixed code corresponding to the other instruction encoding format can be composed of the contents of all fixed bit segments corresponding to the instruction type defined by one other instruction encoding format.

[0078] Exemplarily, if another instruction encoding format is as shown in Table 2 above, it is assumed that the other instruction encoding format defines three instruction types: instruction type C3, instruction type C4, and instruction type C5. Since the other instruction encoding format has three fixed bit segments: bit segment 1, bit segment 3, and bit segment 5, it is assumed that the bit segment 5 encoding (content) of instruction type C3 is 00, bit segment 3 is 101, and bit segment 1 is 100; the bit segment 5 encoding of instruction type C4 is 11, bit segment 3 is 001, and bit segment 1 is 010; the bit segment 5 encoding of instruction type C5 is 10, bit segment 3 is 000, and bit segment 1 is 111. Then the preset fixed encoding corresponding to the other instruction encoding format may include "00101100" composed of the contents of the fixed bit segments of instruction type C3, "11001010" composed of the contents of the fixed bit segments of instruction type C4, and "10000111" composed of the contents of the fixed bit segments of instruction type C5. In the embodiment of the present invention, all processes of splicing bit segments can adopt the method of high-order bit segments first and low-order bit segments later. The preset fixed code of the other instruction encoding format obtained by splicing in this way can be represented by the following set CAT_SET2: CAT_SET2 = {00101100,11001010,10000111}.

[0079] When the code to be compared is "00110110", the code to be compared "00110110" can be compared with each element of the above-mentioned set CAT_SET2. Since "00110110" is inconsistent with each element, it can be determined that the code to be compared "00110110" is inconsistent with all preset fixed codes corresponding to the other instruction encoding formats. When it is determined that the code to be compared "00110110" is inconsistent with all preset fixed codes corresponding to other instruction encoding formats, it can be determined that the pending instruction corresponding to the code to be compared does not match other instruction encoding formats corresponding to the preset instruction set architecture.

[0080] In an embodiment of the present invention, based on the fixed bit segment range information corresponding to other instruction encoding formats in the instruction encoding format set, the first fixed bit segment code corresponding to other instruction encoding formats can be extracted from the pending instruction; based on the bit segment sequence corresponding to each first fixed bit segment code, the first fixed bit segment code is spliced ​​to obtain the code to be compared; when the code to be compared is inconsistent with all preset fixed codes corresponding to other instruction encoding formats, it is determined that the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture. The matching relationship between the pending instruction and all instruction types defined under the other instruction encoding formats can be accurately determined, thereby helping to improve the accuracy of determining whether the pending instruction matches other instruction encoding formats.

[0081] Optionally, in some embodiments, after the step of generating an invalid instruction corresponding to the preset instruction set architecture based on the first random code, the following steps may be specifically performed: Step C1, determining the first random code corresponding to the invalid instruction as a preset fixed code corresponding to the first instruction encoding format.

[0082] In the embodiment of the present invention, after an invalid instruction is generated, the first random code corresponding to the invalid instruction can be used as a preset fixed code corresponding to the corresponding first instruction encoding format and added to the preset fixed code set corresponding to the first instruction encoding format, so as to continue to generate subsequent invalid instructions.

[0083] Step C2, re-execute the step of selecting the first instruction encoding format from the instruction encoding format set corresponding to the preset instruction set architecture, and continue to generate the next invalid instruction, thereby obtaining an invalid instruction sequence including multiple invalid instructions.

[0084] In an embodiment of the present invention, after the first random code corresponding to the generated invalid instruction is used as a preset fixed code corresponding to the first instruction encoding format, the next invalid instruction can be generated, that is, the next first instruction encoding format is reselected from the instruction encoding format set corresponding to the preset instruction set architecture, and the next invalid instruction is determined according to the next first instruction encoding format. Since the first random code in each invalid instruction generated previously is used as a preset fixed code of the corresponding instruction encoding format, when the next invalid instruction is determined according to the next first instruction encoding format, if the generated first random code is the same as any first random code generated previously, the first random code generated this time will match the corresponding preset fixed code, so the invalid instruction will not be generated based on the first random code, and the first random code can be regenerated, which can effectively avoid the generation of invalid instructions with repeated actual content in the fixed bit segment. This helps to improve the diversity of the generated invalid instructions.

[0085] In an embodiment of the present invention, the generated multiple invalid instructions can be combined into an invalid instruction sequence, and each invalid instruction in the invalid instruction sequence has different fixed bit segment content, so that not only the efficiency of testing the CPU core can be improved through the invalid instruction sequence, but also because the invalid instruction sequence has a high invalid instruction diversity, the probability of discovering CPU core problems when testing the CPU core through the invalid instruction sequence can be increased, thereby improving the test accuracy.

[0086] Optionally, in some embodiments, the total length of the fixed bit segment of the first instruction encoding format may be determined by the following steps: Step D1, obtaining fixed bit segment range information corresponding to the first instruction encoding format.

[0087] In the embodiment of the present invention, different instruction set architectures and different instruction encoding formats usually have different total lengths of fixed bit segments. Therefore, in order to improve the adaptability of the present solution to different instruction set architectures, the total length of the fixed bit segment corresponding to the first instruction encoding format can be automatically determined according to the fixed bit segment range information corresponding to the first instruction encoding format, thereby improving the applicability of the solution to different instruction set architectures and different instruction encoding formats.

[0088] Specifically, the fixed bit segment range information corresponding to the first instruction encoding format may be obtained. The fixed bit segment range information may be recorded in a table form, a key-value pair form, etc., which is not specifically limited in the embodiment of the present invention.

[0089] Step D2, determining the fixed bit segment lengths corresponding to each fixed bit segment of the first instruction encoding format based on the fixed bit segment range information.

[0090] In an embodiment of the present invention, the fixed bit segment lengths corresponding to the fixed bit segments of the first instruction encoding format can be determined based on the fixed bit segment range information corresponding to the first instruction encoding format. Exemplarily, if the first instruction encoding format is as shown in Table 2 above, since the first instruction encoding format has three fixed bit segments: bit segment 1, bit segment 3, and bit segment 5, the fixed bit segment range information of the first instruction encoding format can be: bit 0 to bit 2 (bit segment 1), bit 5 to bit 7 (bit segment 3), bit 10 to bit 11 (bit segment 5), then it can be determined that the fixed bit segment length corresponding to fixed bit segment 1 is 3, the fixed bit segment length corresponding to fixed bit segment 3 is 2, and the fixed bit segment length corresponding to fixed bit segment 5 is 2.

[0091] Specifically, since the fixed bit segment range information can include the starting bit sequence and ending bit sequence of each fixed bit segment, the fixed bit segment length of the corresponding fixed bit segment can be obtained by calculating the difference between the starting bit sequence and the ending bit sequence of each fixed bit segment in the fixed bit segment range information, adding 1 to the difference.

[0092] Step D3, determining the total length of the fixed bit segments based on the fixed bit segment lengths corresponding to the fixed bit segments.

[0093] After determining the fixed bit segment lengths corresponding to the fixed bit segments of the first instruction encoding format, the fixed bit segment lengths corresponding to the fixed bit segments may be accumulated to obtain the total fixed tail length of the first instruction encoding format.

[0094] In the embodiment of the present invention, the fixed bit segment range information corresponding to the first instruction encoding format can be obtained; the fixed bit segment lengths corresponding to each fixed bit segment of the first instruction encoding format are determined based on the fixed bit segment range information; and the total length of the fixed bit segment is determined based on the fixed bit segment lengths corresponding to each fixed bit segment. Therefore, the corresponding total length of the fixed bit segment is calculated through the fixed bit segment range information of the first instruction encoding format, which helps to improve the adaptability of the present solution to different instruction set architectures and different instruction encoding formats, and improve the overall scope of use of the solution.

[0095] Reference Figure 2 , Figure 2 FIG. 4 shows a schematic diagram of an invalid instruction generation process provided by an embodiment of the present invention. Figure 2As shown. First, according to the preset instruction set architecture, a preset fixed code set corresponding to each instruction encoding format in the preset instruction set architecture can be constructed. When it is necessary to generate an invalid instruction corresponding to the preset instruction set architecture, first randomly select a first instruction encoding format from all instruction encoding formats of the preset instruction set architecture, and construct a random constraint condition according to the corresponding preset fixed code set; then generate a first random code according to the random constraint condition; then randomly generate a second random code corresponding to the variable bit segment of the first instruction encoding format; then splice the first random code and the second random code to obtain a pending instruction; it can be determined whether the pending instruction matches other instruction encoding formats corresponding to the preset instruction set architecture. If the judgment result is a match, the pending instruction is discarded, and the first instruction encoding format is randomly selected from all instruction encoding formats of the preset instruction set architecture again. If the judgment result is a mismatch, the pending instruction is determined as an invalid instruction.

[0096] Reference Figure 3 , shows a block diagram of an invalid instruction generating device provided by an embodiment of the present invention, such as Figure 3 As shown, the device may specifically include: A selection module 301 is used to select a first instruction encoding format from a set of instruction encoding formats corresponding to a preset instruction set architecture; A generating module 302, configured to generate a first random code having a code length equal to a total length of a fixed bit segment of the first instruction code format; The instruction module 303 is used to generate an invalid instruction corresponding to the preset instruction set architecture based on the first random code when the first random code is inconsistent with the preset fixed codes corresponding to the first instruction coding format; wherein the invalid instruction is used to test the central processing unit.

[0097] Optionally, the instruction module includes: A pending instruction submodule, used for generating a pending instruction corresponding to the first instruction encoding format based on the first random code; An invalid instruction submodule is used to determine the pending instruction as an invalid instruction corresponding to the preset instruction set architecture when the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture; wherein the other instruction encoding formats represent instruction encoding formats in the preset instruction set architecture other than the first instruction encoding format.

[0098] Optionally, the device further comprises: A first fixed bit segment coding module, configured to extract first fixed bit segment codes corresponding to other instruction coding formats in the instruction coding format set from the pending instruction based on fixed bit segment range information corresponding to other instruction coding formats in the instruction coding format set; A code module to be compared, used for splicing the first fixed bit segment codes based on the bit segment sequence corresponding to the first fixed bit segment codes to obtain the code to be compared; The determination module is used to determine that the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture when the code to be compared is inconsistent with each preset fixed code corresponding to the other instruction encoding formats.

[0099] Optionally, the pending instruction submodule includes: A random encoding unit, used for generating a second random code corresponding to the variable bit segment of the first instruction encoding format; The pending instruction generating unit is used to concatenate the first random code and the second random code to obtain a pending instruction corresponding to the first instruction encoding format.

[0100] Optionally, the pending instruction generating unit includes: a segmentation subunit, configured to segment the first random code based on the fixed bit segment range information of the first instruction encoding format, to obtain second fixed bit segment codes corresponding to the fixed bit segments of the first instruction encoding format; The pending instruction splicing subunit is used to splice the second random code and each second fixed bit segment code based on the bit segment sequence corresponding to the second random code and each second fixed bit segment code to obtain the pending instruction corresponding to the first instruction coding format.

[0101] Optionally, the device further comprises: A preset fixed coding module, used for determining the first random code corresponding to the invalid instruction as a preset fixed code corresponding to the first instruction coding format; The invalid instruction sequence module is used to re-execute the step of selecting the first instruction encoding format from the instruction encoding format set corresponding to the preset instruction set architecture, and continue to generate the next invalid instruction, thereby obtaining an invalid instruction sequence including multiple invalid instructions.

[0102] Optionally, the device further comprises: A fixed bit segment range information module, used to obtain fixed bit segment range information corresponding to the first instruction encoding format; A fixed bit segment length module, used to determine the fixed bit segment lengths corresponding to each fixed bit segment of the first instruction encoding format based on the fixed bit segment range information; The fixed bit segment total length module is used to determine the fixed bit segment total length based on the fixed bit segment lengths corresponding to each fixed bit segment.

[0103] In summary, in the invalid instruction generation device provided by the embodiment of the present invention, a first instruction encoding format is selected from the set of instruction encoding formats corresponding to the preset instruction set architecture; a first random code is generated whose encoding length is equal to the total length of the fixed bit segment of the first instruction encoding format; when the first random code is inconsistent with each preset fixed code corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code. Invalid instructions that do not conform to the instruction encoding format corresponding to the preset instruction architecture can be directly generated by random generation, which helps to improve the efficiency of generating invalid instructions for the preset instruction set architecture.

[0104] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the invalid instruction generation method of the above embodiment. The executable instructions can form a program.

[0105] An embodiment of the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the invalid instruction generation method of the aforementioned embodiment.

[0106] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0107] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. It should be noted that all actions of acquiring signals, information or data in the present invention are carried out under the premise of complying with the corresponding data protection laws and policies of the country of residence and with the authorization given by the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0108] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0109] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0110] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0111] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0112] The above is a detailed introduction to an invalid instruction generation method, an invalid instruction generation device, an electronic device and a storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a general technician in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for generating an invalid instruction, characterized in that: The method comprises: Selecting a first instruction encoding format from a set of instruction encoding formats corresponding to a preset instruction set architecture; Generate a first random code having a code length equal to a total length of a fixed bit segment of the first instruction encoding format; When the first random code is inconsistent with all preset fixed codes corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code; wherein the invalid instruction is used to test the central processing unit.

2. The invalid instruction generation method according to claim 1, characterized in that: The generating the invalid instruction corresponding to the preset instruction set architecture based on the first random code includes: Generate a pending instruction corresponding to the first instruction encoding format based on the first random code; When the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture, the pending instruction is determined as an invalid instruction corresponding to the preset instruction set architecture; wherein the other instruction encoding formats represent instruction encoding formats in the preset instruction set architecture other than the first instruction encoding format.

3. The invalid instruction generation method according to claim 2, characterized in that: The method further comprises: Based on the fixed bit segment range information corresponding to other instruction encoding formats in the instruction encoding format set, extracting each first fixed bit segment code corresponding to the other instruction encoding formats from the pending instruction; Based on the bit segment sequence corresponding to each first fixed bit segment code, concatenate each first fixed bit segment code to obtain a code to be compared; When the code to be compared is inconsistent with any preset fixed code corresponding to the other instruction encoding formats, it is determined that the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture.

4. The invalid instruction generation method according to claim 1, characterized in that: The generating, based on the first random code, a pending instruction corresponding to the first instruction encoding format includes: Generate a second random code corresponding to the variable bit segment of the first instruction encoding format; The first random code and the second random code are concatenated to obtain a pending instruction corresponding to the first instruction encoding format.

5. The invalid instruction generation method according to claim 4, characterized in that: The step of concatenating the first random code and the second random code to obtain a pending instruction corresponding to the first instruction encoding format includes: Based on the fixed bit segment range information of the first instruction encoding format, the first random code is divided to obtain second fixed bit segment codes corresponding to the fixed bit segments of the first instruction encoding format; Based on the bit segment order corresponding to the second random code and each second fixed bit segment code, the second random code and each second fixed bit segment code are concatenated to obtain a pending instruction corresponding to the first instruction encoding format.

6. The invalid instruction generation method according to claim 1, characterized in that: After generating the invalid instruction corresponding to the preset instruction set architecture based on the first random code, the method further includes: Determine the first random code corresponding to the invalid instruction as a preset fixed code corresponding to the first instruction encoding format; The step of selecting the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture is re-executed to continue generating the next invalid instruction, thereby obtaining an invalid instruction sequence including multiple invalid instructions.

7. The invalid instruction generation method according to claim 1, characterized in that: The method further comprises: Obtaining fixed bit segment range information corresponding to the first instruction encoding format; Determine the fixed bit segment lengths corresponding to the fixed bit segments of the first instruction encoding format based on the fixed bit segment range information; The total length of the fixed bit segments is determined based on the fixed bit segment lengths respectively corresponding to the fixed bit segments.

8. An invalid instruction generating device, characterized in that: The device comprises: A selection module, configured to select a first instruction encoding format from a set of instruction encoding formats corresponding to a preset instruction set architecture; A generating module, used for generating a first random code having a code length equal to a total length of a fixed bit segment of the first instruction coding format; An instruction module is used to generate an invalid instruction corresponding to the preset instruction set architecture based on the first random code when the first random code is inconsistent with each preset fixed code corresponding to the first instruction coding format; wherein the invalid instruction is used to test the central processing unit.

9. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the invalid instruction generation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Instructions are stored thereon, and when executed by one or more processors, the processors are caused to execute the invalid instruction generation method according to any one of claims 1 to 7.

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