Method and apparatus for error detection during data modification in a memory subsystem

Abstract

The invention relates to a method and apparatus for error detection during data modification in a memory subsystem. A request to store first data is received. And receiving the first data and first error check data. The first error check data may be a cyclic redundancy check (CRC) operation based on the first data. Second data is generated by removing a portion of the first data. Second error check data of the second data is generated by using the first error check data and the removed portion of the first data.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 202010661878.5, application date July 10, 2020, and invention name “Method and device for error detection during data modification in a memory subsystem”. Technical Field

[0003] Embodiments of the present invention generally relate to memory subsystems, and more particularly, to generating error checking data for error detection during data modification in a memory subsystem. Background Art

[0004] The memory subsystem may be a storage device, a memory module, and a mixture of storage devices and memory modules. The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0005] In one aspect, the present invention relates to a system comprising: a memory component; a processing device operably coupled to the memory component to: receive a request to store first data; receive the first data and first error checking data, the first error checking data being based on a cyclic redundancy check (CRC) operation of the first data; generate second data by removing a portion of the first data; and generate second error checking data for the second data by using the first error checking data and the removed portion of the first data.

[0006] In another aspect, the present invention relates to a method comprising: receiving a request to store first data; receiving the first data and first error checking data, wherein the first error checking data is based on a cyclic redundancy check (CRC) operation of the first data; generating second data by removing a portion of the first data; and generating, by a processing device, second error checking data for the second data by using the first error checking data and the removed portion of the first data.

[0007] In a further aspect, the present invention relates to a method comprising: receiving a request to store first data; receiving the first data and first error checking data, the first error checking data being based on a cyclic redundancy check (CRC) operation of the first data; generating second data by combining the first data with a data pattern; and generating, by a processing device, second error checking data for the second data by using a combination of the first error checking data and another data pattern having a size based on the data pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention will be more fully understood from the detailed description given below and from the drawings of various embodiments of the invention. However, the drawings should not be understood as limiting the invention to specific embodiments, but are only for explanation and understanding.

[0009] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the invention is described.

[0010] Figure 2A is a flow chart of an example method of detecting whether errors have been introduced during data truncation according to some embodiments of the invention.

[0011] Figure 2B is a flow chart of an example method of detecting whether errors have been introduced during data expansion according to some embodiments of the invention.

[0012] Figure 3A is a flow chart of an example method of detecting whether errors have been introduced when appending a data pattern to data according to some embodiments of the invention.

[0013] Figure 3B is a flow chart of an example method of detecting whether errors have been introduced when removing a data pattern from data according to some embodiments of the invention.

[0014] Figure 4 is a flow chart of an example method of generating error checking data according to some embodiments of the present invention.

[0015] Figure 5 is a flow chart of another example method of generating error checking data according to some embodiments of the present invention.

[0016] Figure 6 is a block diagram of an example computer system in which embodiments of the present invention may operate. DETAILED DESCRIPTION

[0017] Aspects of the present invention relate to generating error checking data for error detection during data modification in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (also referred to below as a "memory device"). The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0018] The memory subsystem may receive a message or data with a cyclic redundancy check (CRC) code appended thereto from a host system to store the data and the CRC code to one or more memory components. Later, the memory subsystem may modify the original data in various ways, such as truncating the original data and / or appending metadata to the original data. Subsequently, the memory subsystem may store the modified data together with the original CRC code (e.g., the CRC code received from the host system).

[0019] Later, the host system may request the memory subsystem to access data and CRC code. In response, the memory subsystem may retrieve the modified data and obtain the original data from the modified data. Then, the memory subsystem may provide the requested data to the host system together with the original CRC code. Therefore, the host system may use the original CRC code and the retrieved data to verify whether the retrieved data is damaged or contains an error. For example, the host system may generate a new CRC code from the retrieved data, and may compare the new CRC code with the original CRC code. If the two CRC codes match, the host system may determine that the retrieved data is valid (e.g., the same as the original data requested to be stored). On the other hand, if the two CRC codes do not match, the host system may determine that the retrieved data is damaged. In some cases, the memory subsystem (rather than the host system) may use the new CRC code and the original CRC code to verify the integrity of the original data.

[0020] Conventionally, the memory subsystem stores the original CRC code together with the data modified by truncation and / or appending metadata to the data in order to verify the retrieved data (i.e., the data changed back from the modified data). Because the memory subsystem should store the original CRC code of the host system when requesting to retrieve the data, the memory subsystem cannot verify whether errors have been introduced and / or the location of the introduced errors when the data is modified. For example, errors may be introduced during modification (e.g., encryption, appending metadata to the original data from the host system) or reversing the modification (or canceling the modification) (e.g., decryption, truncation). In order to verify this error, the memory subsystem needs a CRC code corresponding to the modified data so that the memory subsystem can compare the corresponding CRC code with the new CRC code generated based on the modified data. If the two CRC codes are the same, the memory subsystem can determine that no errors were introduced during the modification. However, if the memory subsystem replaces the original CRC code with the CRC code of the modified data, the retrieved data may not be verified. Thus, conventional memory subsystems cannot identify whether errors are introduced and / or the location of the introduced errors when storing and retrieving data from the host system.

[0021] Aspects of the present invention address the above and other shortcomings by generating error checking data (e.g., CRC code) at each modification performed on data received from a host system during storage and / or retrieval of data. According to aspects of the present invention, in order to store data received from a host system by removing a portion of the data (e.g., removing unused metadata), a memory subsystem generates error checking data using the error checking data of the data received from the host system and the removed portion of the data received from the host system. In order to retrieve data, the memory subsystem generates error checking data by updating the error checking data corresponding to the modified data with the removed portion of the data received from the host system. According to other aspects of the present invention, in order to store data received from a host system by appending a data pattern of metadata describing system information associated with the stored data (e.g., data address, time stamp), the memory subsystem generates error checking data using a combination of the error checking data of the data received from the host system and another data pattern of a size based on the appended data pattern. In order to retrieve data, the memory subsystem generates error checking data by updating the error checking data corresponding to the modified data with a data pattern used to generate the error checking data corresponding to the modified data.

[0022] Advantages of the present invention include, but are not limited to, ensuring the integrity of data during storage and retrieval by detecting when and / or if errors are introduced during storage and retrieval of data and performing corrective actions (e.g., repeating the modification and / or reversing the modification) upon detection. Thus, the reliability of the memory subsystem can be improved.

[0023] Figure 1 An example computing environment 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the invention. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such things.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0026] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing device including a memory and a processing device. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0027] The memory devices may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Examples of non-volatile memory devices (e.g., memory devices 130) include negative AND (NAND) type flash memory. Each of the memory devices 130 may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of memory cells. Each of the memory cells may store one or more data bits used by the host system 120. In addition, the memory cells of the memory devices 130 may be grouped into memory pages or memory blocks, which may refer to a unit of a memory component for storing data.

[0029] Although non-volatile memory components (e.g., NAND-type flash memory) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), magnetic random access memory (MRAM), negative-OR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point non-volatile memory cell arrays. Cross-point non-volatile memory arrays may perform bit storage based on body resistance changes in conjunction with a stacked cross-gate data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, in which non-volatile memory cells are programmed without prior erasure of the non-volatile memory cells.

[0030] The memory subsystem controller 115 may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present invention, the memory subsystem 110 may not include the memory subsystem controller 115, and may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0033] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system that communicates with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130 .

[0036] The memory subsystem 110 includes an error detection component 113, which can be used to generate error checking data or codes. In some embodiments, the memory subsystem controller 115 includes at least a portion of the error detection component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the error detection component 113 is part of the host system 110, an application, or an operating system.

[0037] The error detection component 113 may receive a request to store data. The error detection component 113 may receive data and corresponding error checking data. The error detection component 113 may generate another data by removing a portion of the data. The error detection component 113 may also generate error checking data corresponding to the modified data by using the received error checking data and the removed portion of the received data. Further details about the operation of the error detection component 113 are described below.

[0038] Figure 2A 2 is a flow chart of an example method 200 for detecting whether an error has been introduced during data truncation according to some embodiments of the present invention. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The error detection component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0039] In operation 210, the processing device receives a message or data (e.g., M) from the host system 120. In some embodiments, the data may include N binary data bits, such as M0, M1, etc. The processing device may receive the data as part of a write request to store data from the host system 120. In some embodiments, the processing device may receive the data and error checking data for the data together in a data packet. The data packet may have error checking data attached to the data. In this case, the processing device may extract the data and error checking data from the data packet. The error checking data may include R binary data bits, such as C0, C1, etc. The error checking data (e.g., CRC) may be generated by applying a cyclic redundancy check (CRC) operation to the data M. In some embodiments, any error checking data generated from the CRC operation will have R binary data bits.

[0040] Furthermore, in operation 210, the processing device truncates the data M to generate truncated data M'. In some embodiments, the resulting truncated data M' may have a binary number having N-1-K number of bits. That is, the processing device may remove the first K data bits M from the data M. T The processing device then stores the truncated data on the memory component 112. This truncation process will reduce the data size required to store the data in response to a write operation from the host system 120. When the host system 120 later requests access to the data M, the processing device processes the data M' to transfer the data M back to the host system 120, as will be described below with respect to Figure 2B In addition, in operation 210, the processing device may generate metadata indicating the type of modification performed on the original data M. The processing device may associate the modified data M' with the original data M for retrieval using the metadata.

[0041] After truncating the data M, at operation 215, the processing device performs the operation of processing the removed portion M. T Applying a CRC operation to generate the removed portion M T Error check data CRC T Then, at operation 218, the processing device uses the removed portion M T Error check data CRC T Update the error checking data CRC of the original data M. For example, the processing device may combine the removed portion M T Error check data CRC T and the error checking data CRC of the original data M. In some embodiments, the processing device may calculate two error checking data CRC and CRC T Specifically, the processing device may perform a calculation on the two error checking data CRC and CRC TAn exclusive OR (XOR) logic function is applied. As a result of the update, the processing device generates incremental error checking data CRC*. As used herein, incremental error checking data refers to error checking data (e.g., a CRC code calculated from a CRC operation) used to incrementally update error checking data corresponding to the original data to arrive at error checking data corresponding to data changed from the original data. Thus, the processing device can use CRC* as incremental error checking data for calculating error checking data (e.g., CRC') for the truncated data M', as will be described below with respect to operations 220 and 225.

[0042] In operation 220, the processing device modifies the incremental error checking data CRC* by appending a data pattern. For example, the processing device may append a series of identical or any binary digits (e.g., values ​​of '0' or '1') as a data pattern to the incremental error checking data CRC*. The data pattern may have a data size, which includes the data size R of the error checking data CRC of the original data M or any other CRC (because all error checking data have the same data size R) and the removed portion M. T In some embodiments, the processing device may use the mathematical formula '2 R -1-K' calculates the data size of the data pattern. That is, the processing device may generate a data pattern having '2 R -1-K' number of 0's data pattern. Then, the processing device may append the data pattern to the incremental error checking data CRC*. The processing device may append the data pattern to the front end (ie, the beginning) or the end of the incremental error checking data CRC*.

[0043] At operation 225, the processing device generates error checking data CRC' of the truncated data M' by performing a CRC operation on the modified incremental error checking data CRC*. Thus, by incrementally updating the error checking data CRC of the original data M, the processing device may generate error checking data CRC' of the modified data M'. Subsequently, the processing device may use CRC' to detect whether there are any errors introduced during truncation, as will be described below with respect to operations 230 and 240. Such errors may be caused by noise or other such impairments when storing data and / or retrieving stored data, such as alpha particles emitted by packaging materials of the memory subsystem 110, which may cause a data value or data bit stored in a memory cell to switch from a '0' value to a '1' value (or vice versa).

[0044] In operation 230, the processing device applies a CRC operation to the truncated data M'. Next, in operation 240, the processing device detects whether an error has been introduced during the truncation of operation 210 based on the two error checking data CRC' and CRC". If the two error checking data have the same value, the processing device may determine that the truncated data M' is valid. Otherwise, if the two error checking data do not match, the processing device may determine that the truncated data M' is invalid due to the error introduced during the truncation of operation 210. Thus, by updating the error checking data (e.g., CRC) of the original data M using the incremental error checking data (e.g., CRC*), the processing device may generate error checking data (e.g., CRC') corresponding to the truncated data M' for detecting any errors introduced during the modification of operation 210.

[0045] In response to determining that the truncated data M' is valid, the processing device may store the truncated data M' along with its corresponding error checking data CRC' in the memory component 112. In this case where CRC" matches CRC', the processing device may store CRC" instead of CRC'. In further embodiments, the processing device may modify the received data (e.g., M) multiple times. In this case, the processing device may perform method 200 each time a modification is performed in order to ensure the integrity of the modified data and perform any corrective actions accordingly.

[0046] Figure 2B 2 is a flow chart of an example method 250 for detecting whether an error has been introduced during data expansion according to some embodiments of the present invention. The method 250 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 250 is performed by Figure 1 The error detection component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0047] At operation 260, the processing device receives the truncated data M'. In some embodiments, the processing device may retrieve the truncated data M' stored in the memory component 112 from the method 200. For example, the truncated data M' may include 'N-1-K' binary data bits, such as M K 、M K+1 …M N-1In some embodiments, the processing device may access the stored data M' in response to a retrieval request from the host system 120. The request may be associated with a write Figure 2A That is, the host system 120 may send a read operation to the processing device to retrieve the data M that was transmitted to the processing device for storage. The host system 120 may be unaware of the truncation performed on M. Therefore, in response to the retrieval request from the host system 120, the processing device may reverse or undo (i.e., expand) the modifications associated with the stored data M'. In order to determine how to reverse the modification or undo the modification, the processing device may identify the type of modification performed on the original data M from the metadata associated with the modified data M'.

[0048] The processing device may then determine an operation to convert the truncated data M' back to the original data M. For example, if Figure 2A If the original data M has been truncated to M', the processing device may expand the truncated data M' to obtain the original data M. Therefore, the expanded data M will have a larger number of bits than the truncated data M'. For example, the expanded data M has N bits, while the truncated data has 'N-1-K' bits. During expansion, the processing device may determine the portion M that has been removed from the original data M during truncation. T In other words, the processing device may determine the portion M of the original data M that needs to be restored in order to obtain the portion M of the original data M from the truncated data M′. T Once the modified data M' is changed back to the original data M, the processing device provides the original data M to the host system 120 in response to the read operation (unless an error is detected during the expansion process, as will be described below with respect to operation 285).

[0049] At operation 265, the processing device combines part M T The processing device may retrieve the CRC' associated with the truncated data M' stored in the memory component 112. In order to combine the portion M T With the error checking data CRC', the processing device can convert part M T to the error checking data CRC' or vice versa. In some embodiments, the processing device may T Prefix to the front end of the error checking data CRC'. In other embodiments, the processing device may T Appended to the end of the error checking data CRC'.

[0050] In operation 270, the processing device performs a CRC operation on the combined or updated error checking data CRC'. Thus, the processing device has incrementally updated the error checking data (e.g., CRC') of the truncated data M' to generate the error checking data CRC of the extended data M. The processing device may provide the error checking data CRC of the extended data M to the host system 120 in response to the retrieval request.

[0051] In operation 280, the processing device applies a CRC operation to the extended data M and generates error checking data (e.g., CRC**). In operation 285, in order to detect whether an error is introduced during the extension of operation 260 or whether the extended data M contains an error, the processing device determines whether the error checking data CRC** of the extended data M matches the error checking data CRC** obtained by using a portion of M. T The error check data CRC determined by updating the error check data CRC' of the truncated data M'. If the two error check data CRC and CRC** match, the processing device can verify that the extended data M does not contain errors. In this case, Figure 2B The extended data M in should be the same as that from Figure 2A On the other hand, if the processing device determines that the two error check data do not match, the processing device may notify the host system 120 that retrieval of the requested data has failed and / or return to operation 260. In a further embodiment, if multiple modifications have been applied to the original data M received from the host system 120, the processing device may perform method 250 multiple times.

[0052] Figure 3A 1 is a flow chart of an example method 300 for detecting whether an error has been introduced during the appending of a data pattern to data according to some embodiments of the present invention. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The error detection component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] In operation 310, the processing device receives a message or data (e.g., M) from the host system 120. In some embodiments, the data may include N binary data bits, such as M0, M1, etc. The processing device may receive the data from the host system 120 as part of a write request to store data. In some embodiments, the processing device may receive the data and error checking data for the data together in a data packet. The data packet may have error checking data attached to the data. In this case, the processing device may extract the data and error checking data from the data packet. The error checking data may include R binary data bits, such as C0, C1, etc. The error checking data (e.g., CRC) may be generated by applying a CRC operation to the data M. In some embodiments, any error checking data generated from the CRC operation will have R binary data bits.

[0054] In addition, in operation 310, the processing device generates modified data M' by appending a data pattern (e.g., P zeros) to the data M. In some embodiments, the processing device may generate a data pattern having a series of identical binary digits (e.g., values ​​of '1' or '0'). In other embodiments, the processing device may generate metadata describing system information in binary digits as the data pattern. This data pattern may include system information, such as a data address of the generated data (e.g., M') to be stored, a timestamp associated with the generated data M', and / or a flag representing any other system information. After generating the data pattern having a data size P, the processing device may append the data pattern to the front end (i.e., the beginning) or end of the data M. For some embodiments, this modification process will record any system information required by the memory subsystem 110 when managing write or read operations to the memory component 112. When the host system 120 later requests access to the data M, the processing device separates or removes the data pattern from the modified data M' to transmit the data M back to the host system 120, as will be described below with respect to Figure 3B Description. In addition, in operation 310, the processing device may generate another metadata indicating the type of modification performed on the original data M (e.g., appending a data pattern). The metadata of the type of modification may further include the content of the data pattern (e.g., a series of binary digits), the data size of the data pattern (e.g., P), and the position to which the data pattern will be appended (e.g., the front or the end). The processing device may associate the modified data M' with the original data M for retrieval using the metadata.

[0055] In operation 315, the processing device converts another data pattern (eg, '2 R-1-P'0'0) is appended to the error checking data CRC of the original data M. The processing device may receive the CRC from a data packet having the original data M with the CRC appended thereto. In an alternative embodiment, the processing device may generate the CRC from a CRC operation of the original data M. In some embodiments, this data pattern may be different from the data pattern of operation 310. Although this data pattern may also be a series of identical (or any) binary digits, the data size of this data pattern is based on the data size of the error checking data CRC of the original data M (e.g., R) and the data size of the data pattern of operation 310 associated with modifying the original data M (e.g., P). For example, the processing device may use the mathematical formula '2 R -1-P' to calculate the data size of the data pattern. After determining the data pattern, the processing device may append the data pattern to the front end (ie, the beginning) or the end of the error checking data CRC of the original data M.

[0056] In operation 320, the processing device generates error checking data CRC' of the modified data M' by performing a CRC operation on the error checking data CRC updated with the data pattern. Thus, by incrementally updating the error checking data CRC of the original data M, the processing device can generate error checking data CRC' of the modified data M'. Subsequently, the processing device can use CRC' to detect whether there are any errors introduced during the append operation, as will be described below with respect to operations 325 and 340.

[0057] In operation 325, the processing device applies a CRC operation to the modified data M' having the appended data pattern. Next, in operation 340, the processing device detects whether an error has been introduced during the modification of operation 310 based on the two error checking data CRC' and CRC". If the two error checking data have the same value, the processing device may determine that the modified data M' is valid. Otherwise, if the two error checking data do not match, the processing device may determine that the modified data M' is invalid due to the error introduced during the appending operation of operation 310. Thus, by using the data pattern (e.g., '2 R -1-P'0) updates the error checking data (eg, CRC) of the original data M, the processing device may generate error checking data (eg, CRC') corresponding to the modified data M' for detecting any errors introduced during the modification in operation 310.

[0058] In response to determining that the modified data M' is valid, the processing device may store the modified data M' along with its corresponding error checking data CRC' in the memory component 112. In this case where CRC" matches CRC', the processing device may store CRC" instead of CRC'. In further embodiments, the processing device may modify the received data (e.g., M) multiple times. In this case, the processing device may perform method 300 each time a modification is performed in order to ensure the integrity of the modified data and perform any corrective actions accordingly.

[0059] Figure 3B 3 is a flow chart of an example method 350 for detecting whether an error has been introduced during removal of a data pattern from data according to some embodiments of the present invention. The method 350 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 350 is performed by Figure 1 The error detection component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0060] At operation 360, the processing device receives modified data M'. For example, the modified data M' may have 'K+P' bits including P data pattern bits prepended to the front of the original data M having K binary data bits. In some embodiments, the processing device may retrieve the modified data M' stored in the memory component 112 from the method 300. In some embodiments, the processing device may access the stored data M' in response to a retrieval request from the host system 120. The request may be associated with a write request. Figure 3A That is, the host system 120 may send a read operation to the processing device to retrieve the data M that was transmitted to the processing device for storage. The host system 120 may be unaware of the modifications performed on M. Therefore, in response to the retrieval request from the host system 120, the processing device may reverse or undo (i.e., remove the appended data pattern P zeros) the modifications associated with the stored data M'. In order to determine how to reverse the modification or undo the modification, the processing device may identify the type of modification performed on the original data M (e.g., the appended data pattern) from metadata associated with the modified data M'. The processing device may further determine from the metadata the content of the data pattern (e.g., a series of binary digits), the data size of the data pattern, and the location to which the data pattern will be appended (e.g., the front end or the end).

[0061] Then, the processing device may determine an operation to transform the modified data M' back to the original data M. For example, if a data pattern having a data size P is appended to the data from Figure 3A If the modified data M' is at the front end of the original data M of the modified data, the processing device may remove the data pattern from the retrieved data M' or truncate the retrieved data M' to obtain the original data M. Therefore, the truncated data M will have a smaller number of bits than the retrieved data M' with the appended data pattern. For example, the truncated data M has K bits, while the retrieved data M' has 'K+P' bits. Once the modified data M' is changed back to the original data M, the processing device provides the original data M to the host system 120 in response to the read operation (unless an error is detected during the removal process, as will be described below with respect to operation 385).

[0062] In operation 365, the processing device appends another data pattern to the error checking data (e.g., CRC') corresponding to the retrieved data M'. The processing device may determine the data pattern to be appended from the series of binary digits. The data pattern may include the same or any binary digits. In addition, the processing device may determine the size of the data pattern based on the size (e.g., R) of the error checking data (e.g., CRC') of the retrieved data M' and the size (e.g., P) of the data pattern (e.g., P zeros) removed from the retrieved data M'. For example, the processing device may use the same mathematical formula '2' as used in operation 315. R -1-P' to calculate the size of the data pattern to be appended. The processing device may retrieve the CRC' associated with the retrieved data M' stored in the memory component 112. In some embodiments, the processing device may R The data pattern of -1-P' is prepended to the front end of the error checking data CRC'. In other embodiments, the processing device may append the data pattern to the end of the error checking data CRC'.

[0063] At operation 370, the processing device performs a CRC operation on the modified or updated error checking data CRC'. Thus, the processing device has incrementally updated the error checking data (e.g., CRC') of the data M' with the appended data pattern (P zeros) to generate error checking data of the truncated data M. The processing device may provide the error checking data CRC' of the truncated data M to the host system 120 in response to the retrieval request.

[0064] In operation 380, the processing device applies a CRC operation or generates error checking data (e.g., CRC**) to the truncated data M. In operation 385, in order to detect whether an error is introduced during the removal operation of operation 360 or whether the truncated data M contains an error, the processing device determines whether the error checking data CRC** of the truncated data M matches the CRC** of the truncated data M appended with the data size '2 R -1-P' data pattern and the error check data CRC determined by the error check data CRC' of the data M'. If the two error check data CRC and CRC** match, the processing device can verify that the truncated data M does not contain errors. In this case, Figure 3B The truncated data M in should be the same as the data from Figure 3A On the other hand, if the processing device determines that the two error check data do not match, the processing device may notify the host system 120 that retrieval of the requested data has failed or return to operation 360. In a further embodiment, if multiple modifications have been applied to the original data M received from the host system 120, the processing device may perform method 350 multiple times.

[0065] Figure 4 4 is a flow chart of an example method 400 of generating error checking data according to some embodiments of the present invention. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The error detection component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0066] In operation 410, a processing device receives storage data (e.g., Figure 2A For example, the processing device may receive a request to store data M as provided by the host system 120. In other embodiments, the processing device may receive the request from the memory subsystem 110.

[0067] In operation 420, the processing device receives data (eg, M) and error checking data (eg, Figure 2A420). In some embodiments, the processing device may receive data with a request. The processing device may receive data from the host system 120 or the memory subsystem 110. The data may be in the form of binary digits. In further embodiments, after receiving the data, the processing device may create a copy of the received data to perform corrective actions if an error is detected with respect to operation 430, as will be described below. In some embodiments, the error checking data may be a cyclic redundancy check code generated by applying a CRC operation to the received data. In addition, the error checking data may be appended to the received data. In this case, the processing device may read the error checking data (e.g., CRC) from a data packet containing the data (e.g., M) and the corresponding error checking data (e.g., CRC). In some embodiments, the processing device may receive the error checking data from the host system 120 or the memory subsystem 110. The error checking data may be in the form of binary digits. In some other embodiments, the processing device may perform a CRC operation on the received data to generate error checking data for operation 420.

[0068] In operation 430, the processing device removes a portion (eg, Figure 2A M T ) to generate another data (for example, Figure 2A In some embodiments, the processing device may remove the leading portion (eg, M) of the data (eg, M). T ). In other embodiments, the processing device may remove the back of the data or remove any other part from the data. For example, the processing device may truncate M and generate M', which is a truncated M having a smaller number of bits than the number of bits of M. In some embodiments, the processing device may identify the type of modification (e.g., truncation and / or extension) and store the type of modification along with M', e.g., using metadata.

[0069] In operation 440, the processing device detects the received data (eg, M) by using the error checking data (eg, CRC) of the received data (eg, M) and the removed portion (eg, M) of the received data (eg, M). T ) to generate error check data (eg, Figure 2A For example, to generate error checking data for the data (e.g., M), the processing device may update the error checking data (e.g., CRC) received in operation 420. The processing device may combine the error checking data (e.g., CRC) with the removed portion of the data (e.g., M). T ) CRC operation generates error check data (e.g., CRC TIn some embodiments, the processing device may combine the received error checking data (e.g., CRC) with the error checking data (e.g., CRC) generated from the removed portion using the difference between the two data. T ). The processing device may determine the difference using an XOR logic function. The error checking data generated based on the removed portion may be in the form of binary data. As a result of the combination, the processing device generates incremental error checking data (e.g., Figure 2A Incremental error checking data may be in the form of binary data. Incremental error checking data as used herein refers to error checking data for incrementally updating original data to arrive at error checking data for modified data to verify error checking data (calculated from CRC operation) of modified data resulting from data modification from original data to modified data. Thus, the processing device incrementally updates the received error checking data (e.g., CRC) to the incremental error checking data (e.g., CRC*), and then updates to the error checking data (e.g., CRC') of the modified data (e.g., M'), as described in the following description.

[0070] After the update, the processing device may perform a check based on the updated error check data (eg, CRC*) and the removed portion (eg, M T ) to generate error checking data (e.g., CRC') of the modified data (e.g., M'). In some embodiments, the data pattern may correspond to a series of identical binary digits. In addition, the processing device may use the removed portion of the received data (e.g., M) to generate error checking data (e.g., CRC') of the modified data (e.g., M'). T ) and the size of the received error checking data (e.g., CRC). For example, the processing device may determine the size of the data pattern by calculating the data size (e.g., Figure 2A R in the power minus the removed portion M T The data size (for example, Figure 2A K) and the value '1' to calculate the size of the data pattern, such as Figure 2A 220 (i.e., R -1-K). Once the processing device determines the size of the data pattern, the processing device may generate a series of '1's or '0's having the determined size. Then, the processing device may modify the updated error checking data or the incremental error checking data (e.g., CRC*) by appending the data pattern. In some embodiments, the processing device may append the data pattern to the front end of the updated error checking data (e.g., CRC*). The processing device may apply a CRC operation to the combination of the updated error checking data and the data pattern to generate error checking data (e.g., CRC') of the modified data (e.g., M').

[0071] In further embodiments, the processing device may determine whether the data (e.g., M') contains an error. The error may be caused by any impairment that induces the state of a memory cell in the memory component 112 to flip to an opposite state (e.g., from a '1' value to a '0' value, and vice versa). In some embodiments, the processing device may determine whether the data (e.g., M') contains an error by comparing error checking data (e.g., CRC') generated for the modified data (e.g., M') with error checking data (e.g., CRC') determined by applying a CRC operation to the modified data (e.g., M'). Figure 2A 4”) to detect whether an error was introduced during the removal operation of operation 430. When comparing the two CRCs, the processing device may determine whether the values ​​represented by the binary digits of each CRC are the same. In some embodiments, if the two error checking data match, the processing device determines that no error was introduced or that the data modified by the removal operation (e.g., M′) does not contain an error. In this case, the processing device may store the modified data (e.g., M′) together with the error checking data (e.g., CRC′) generated in operation 430 on the memory component according to the request received in operation 410. When storing the modified data (e.g., M′), the processing device may use the error checking data (e.g., CRC′) generated in operation 430 to store the modified data (e.g., M′). The modified data (e.g., M') is associated with the received original data (e.g., M). The processing device may use an identifier or metadata for the association. In this way, when the processing device receives a request to retrieve M from the host system 120, the processing device may access M' based on the association. On the other hand, if the two error check data do not match, the processing device may determine that the data modified by the removal operation is damaged. In some embodiments, the processing device may perform a corrective action by repeating operation 420 on a copy of the received original data (i.e., regenerating the data with the removed portion). In addition, the processing device may notify the host system 120 of a failure to store the requested data.

[0072] Later, the processing device may receive a request from the host system 120 to retrieve data (e.g., M) that has been requested to be stored on the memory component. In response, the processing device may retrieve the stored data (e.g., Figure 2B M' in) and modify the stored data back to the original data (e.g., Figure 2B For example, the processing device may determine how to restore the original data (e.g., M) by referring to metadata associated with the retrieved data (e.g., M'). The metadata may include the type of truncation and / or extension applicable to the corresponding data. Accordingly, the processing device may extend the retrieved data (e.g., M') by appending a data pattern of an appropriate size to restore from truncation. Thus, the processing device may include or add the removed portion (e.g., M') according to information from the metadata. Figure 2B M T) to modify the retrieved data (e.g., M'). In some embodiments, the processing device may determine the removed portion (e.g., M) by comparing the retrieved data (e.g., M') with the expanded data (e.g., M). T ).

[0073] In addition, in some further embodiments, the processing device may update the error checking data (eg, Figure 2B ') in order to generate error checking data corresponding to the modified data (eg, M), that is, the restored original data (eg, Figure 2B CRC' can be stored with M' by appending it to M'. In some embodiments, both the retrieved data and the error checking data can be in the form of binary data. To update the error checking data (e.g., CRC'), the processing device can combine the retrieved error checking data (e.g., CRC') with the removed portion (e.g., M'). T For example, the processing device may remove the removed portion (eg, M T ) is added or inserted into the retrieved error checking data (eg, CRC'). Then, the processing device may update the error checking data (eg, CRC') by applying a CRC operation to the combination.

[0074] After updating the error checking data (eg, CRC′), the processing device may compare the updated error checking data (eg, CRC) with the error checking data (eg, CRC′) generated from the CRC operation of the modified data (eg, M). Figure 2B 430). In response to determining that the two error check data match each other, the processing device may provide the restored original data (e.g., M) to the host system 120 according to the retrieval request. On the other hand, if the two error check data do not match, the processing device may determine that the modified data (e.g., M) contains an error. In this case, the processing device may perform operation 430 again. In addition, the processing device may notify the host system 120 of an error or failure in retrieving the requested data.

[0075] Figure 5 is a flow chart of another example method 500 of generating error checking data according to some embodiments of the present invention. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1The error detection component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0076] In operation 510, a processing device receives storage data (e.g., Figure 3A For example, the processing device may receive a request to store data M provided by the host system 120. In other embodiments, the processing device may receive the request from the memory subsystem 110.

[0077] In operation 520, the processing device receives data (eg, M) and error checking data (eg, Figure 3A 520). In some embodiments, the processing device may receive data with a request. The processing device may receive data from the host system 120 or the memory subsystem 110. The data may be in the form of binary digits. In further embodiments, after receiving the data, the processing device may create a copy of the received data to perform corrective actions if an error is detected with respect to operation 530, as will be described below. In some embodiments, the error checking data may be a cyclic redundancy check code generated by applying a CRC operation to the received data. In addition, the error checking data may be appended to the received data. In this case, the processing device may read the error checking data (e.g., CRC) from a data packet containing the data (e.g., M) and the corresponding error checking data (e.g., CRC). In some embodiments, the processing device may receive the error checking data from the host system 120 or the memory subsystem 110. The error checking data may be in the form of binary digits. In some other embodiments, the processing device may perform a CRC operation on the received data to generate error checking data for operation 520.

[0078] In operation 530, the processing device combines the data (eg, M) with the data pattern (eg, Figure 3A P 0s in it) to generate another data (for example, Figure 3AIn some embodiments, the processing device may generate a data pattern corresponding to metadata describing system information (e.g., a data address of the generated data (e.g., M') to be stored, a timestamp associated with the generated data (e.g., M'), and / or a flag representing any other system information). The data pattern may be in the form of binary data. In other embodiments, the processing device may generate a series of identical binary digits as the data pattern. Then, the processing device may append the data pattern to the received data. In some embodiments, the processing device may prepend the data pattern to the front end of the received data. In some embodiments, the processing device may append the data pattern to the end of the received data. In addition, the processing device may identify the type of modification (e.g., an additional data pattern) and (e.g.) store the type of modification together with M' using metadata. In some embodiments, the metadata of the type of modification may further include the content of the data pattern (e.g., a series of binary digits), the data size of the data pattern, and the position (e.g., the front end or the end) to which the data pattern will be appended.

[0079] In operation 540, the processing device generates error checking data (e.g., CRC) of another data (e.g., M') by using the error checking data (e.g., CRC) of the received data (e.g., M) in combination with another data pattern having a size based on the data pattern used to generate the other data (e.g., M'). Figure 3A In some embodiments, the processing device may generate another data pattern corresponding to a series of identical binary digits (e.g., values ​​of '0' or '1'). In other embodiments, the data pattern may have any series of binary digits. The processing device may determine the size of this data pattern based on the size (e.g., P) of the data pattern (e.g., P 0s) used to generate another data (e.g., M') and the size (e.g., R) of the error checking data (e.g., CRC) of the data (e.g., M). For example, if Figure 3A As described in operations 310 and 315 of FIG. 1 , the data pattern for updating the error check data (eg, CRC) of the received data (eg, M) may have a value of '2 R Once the data pattern is determined, the processing device may combine the error checking data (eg, CRC) of the received data (eg, M) with the data pattern. For example, the processing device may combine the error checking data (eg, CRC) of the received data (eg, M) with the data pattern. R-1-P' is appended to the error checking data (e.g., CRC) of the received data (e.g., M). In some embodiments, the processing device may prepend the data pattern to the front end of the error checking data (e.g., CRC). In other embodiments, the processing device may append the data pattern to the end of the error checking data (e.g., CRC). Subsequently, the processing device generates the error checking data (e.g., CRC') of the modified data (e.g., M') by applying a CRC operation to the combination. Thus, similar to operation 440, the processing device may incrementally update the error checking data (e.g., CRC) of the original data (e.g., M) received by appending the data pattern, thereby generating the error checking data (e.g., CRC') of the modified data (e.g., M').

[0080] In further embodiments, the processing device may determine whether the data (e.g., M') contains an error. In some embodiments, the processing device may determine whether the data (e.g., M') contains an error by comparing error checking data (e.g., CRC') generated for the modified data (e.g., M') with error checking data (e.g., CRC') determined by applying a CRC operation to the modified data (e.g., M'). Figure 3A ”) to detect whether errors were introduced during the additional operation of operation 530. Figure 4 In a further embodiment described, if the two error checking data match, the processing device determines that no error is introduced or the data modified by the append operation (e.g., M') does not contain an error. In this case, the processing device may store the modified data (e.g., M') together with the error checking data (e.g., CRC') generated in operation 520 on the memory component according to the request received in operation 510. When storing the modified data (e.g., M'), the processing device may associate the modified data (e.g., M') with the received original data (e.g., M). The processing device may use an identifier or metadata for association. On the other hand, if the two error checking data do not match, the processing device may determine that the data modified by the append operation is invalid. In some embodiments, the processing device may perform a corrective action by repeating operation 530 (i.e., regenerating data with an appended data pattern) on a copy of the received original data. In addition, the processing device may notify the host system 120 of the failure to store the requested data.

[0081] Subsequently, the processing device may receive a request from the host system 120 to retrieve data (e.g., M) requested to be stored on the memory component. In response, the processing device may retrieve the stored data (e.g., Figure 3B M' in) and modify the stored data back to the original data (e.g., Figure 3BFor example, the processing device may determine how to restore the original data (e.g., M) by referring to metadata associated with the retrieved data (e.g., M'). The metadata may describe that a particular data pattern is appended to the received data. In some embodiments, the metadata may further specify the content of the appended data pattern, the data size of the appended data pattern, and the location (e.g., the front or the end) to which the data pattern is appended. Accordingly, the processing device may perform a processing operation by removing the data pattern (e.g., the front or the end) based on the metadata. Figure 3B P 0s in ) to modify the retrieved data (e.g., M').

[0082] In addition, in some further embodiments, the processing device may update the error checking data (eg, Figure 3B ') in order to generate error checking data corresponding to the modified data (eg, M), that is, the restored original data (eg, Figure 3B CRC' can be stored with M' by appending it to M'. In some embodiments, both the retrieved data and the error checking data can be in the form of binary data. The processing device can update the retrieved error checking data (e.g., CRC') based on another data pattern. In some embodiments, this data pattern can be the same data pattern used to generate the retrieved error checking data (e.g., CRC') in operation 540. For example, the data pattern can be '2 R -1-P' 0s. Accordingly, the processing device may append the data pattern to the retrieved error checking data (e.g., CRC"). In some embodiments, the processing device may prepend the data pattern to the front end of the retrieved error checking data (e.g., CRC'). In other embodiments, the processing device may append the data pattern to the end of the retrieved error checking data (e.g., CRC'). Then, the processing device may compare the retrieved error checking data (e.g., CRC') with a pair having, for example, '2 R -1-P' 0 data pattern combination applies CRC operation, thereby generating updated error checking data (eg, Figure 3B The updated error checking data may be in the form of binary data.

[0083] After updating the error checking data (eg, CRC′), the processing device may compare the updated error checking data (eg, CRC) with the error checking data (eg, CRC′) generated from the CRC operation of the modified data (eg, M). Figure 3B530). In response to determining that the two error check data match each other, the processing device may provide the restored original data (e.g., M) to the host system 120 according to the retrieval request. On the other hand, if the two error check data do not match, the processing device may determine that the modified data (e.g., M) contains an error. In this case, the processing device may perform operation 530 again. In addition, the processing device may notify the host system 120 of an error or failure in retrieving the requested data.

[0084] Figure 6 An example machine illustrating a computer system 600 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 A host system 120 including a memory subsystem (e.g., Figure 1 110), coupled to the memory subsystem or utilizing the memory subsystem or operable to perform operations of the controller (e.g., executing an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-client network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0085] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0086] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618 that communicate with each other via a bus 630.

[0087] The processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate over a network 620.

[0088] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0089] In one embodiment, instructions 626 include implementing a command corresponding to an error detection component (e.g., Figure 1 The machine-readable storage medium 624 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions executed by a machine and causing the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" should accordingly be understood to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0090] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily due to common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0091] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0092] The present invention also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0093] The algorithms and displays presented herein do not inherently relate to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures for various of these systems will appear as set forth in the description below. In addition, the present invention is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present invention described herein.

[0094] The present invention may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0095] In the foregoing specification, embodiments of the invention have been described with reference to specific example embodiments of the invention. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the invention as set forth in the following claims. The specification and drawings should accordingly be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory system, comprising: Memory components; a processing device operatively coupled to the memory component to: receiving a request to store first data; Receiving the first data and first error checking data, where the first error checking data is based on a cyclic redundancy check (CRC) operation on the first data; generating second data by removing a portion of the first data; updating the first error-checking data based on the removed portion of the first data to obtain updated first error-checking data; and Second error-checking data for the second data is generated based on the updated first error-checking data and a data pattern having a size based on the portion of the first data that was removed.

2. The memory system according to claim 1, wherein in order to update the first error checking data, the processing device: The first error checking data is combined with error checking data resulting from the CRC operation of the portion of the first data that was removed.

3. The memory system according to claim 1 , wherein in order to generate the second error checking data, the processing device: obtaining modified first error-checking data by appending the data pattern to the beginning of the updated first error-checking data; and The second error-checking data is generated by applying the CRC operation to the modified first error-checking data.

4. The memory system of claim 1, wherein: The data pattern corresponds to a series of identical binary digits; and The size of the data pattern is determined using a size of the portion of the first data that is removed and a size of the first error-checking data.

5. The memory system of claim 1 , wherein the processing device further: determining whether the second data contains an error by comparing the second error check data with error check data generated from the CRC operation of the second data; responsive to determining that the second error checking data matches the error checking data generated from the CRC operation of the second data, storing the second data together with the second error checking data; and In response to determining that the second error checking data does not match the error checking data generated from the CRC operation of the second data, the second data is regenerated.

6. The memory system of claim 1, wherein the processing device further: In response to receiving a request from a host system to retrieve the first data: obtaining combined data by combining the removed portion of the first data with the second data, updating the second error-checking data based on the removed portion of the first data to obtain updated second error-checking data, determining whether the combined data contains an error by comparing the updated second error checking data with error checking data generated from the CRC operation of the combined data, and In response to determining that the updated second error-checking data matches the error-checking data generated from the CRC operation of the combined data, providing the combined data to the host system.

7. The memory system according to claim 6, wherein in order to update the second error checking data, the processing device: combining the second error-checking data with the removed portion of the first data to obtain a combination; and The second error checking data is updated by applying the CRC operation to the combination.

8. A method of operating a memory, comprising: Receiving, by the processing device, a request to store first data; The processing device receives the first data and first error checking data, wherein the first error checking data is based on a cyclic redundancy check (CRC) operation on the first data; generating second data by the processing device by removing a portion of the first data; updating, by the processing device, the first error-checking data based on the removed portion of the first data to obtain updated first error-checking data; and Second error-checking data for the second data is generated, by the processing device, based on the updated first error-checking data and a data pattern having a size based on the portion of the first data that was removed.

9. The method of claim 8, wherein updating the first error checking data comprises: The first error checking data is combined with error checking data resulting from the CRC operation of the portion of the first data that was removed.

10. The method according to claim 8, wherein generating the second error checking data comprises: obtaining modified first error-checking data by appending the data pattern to the beginning of the updated first error-checking data; and The second error-checking data is generated by applying the CRC operation to the modified first error-checking data.

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