Chip system with trimming parameter dynamic monitoring function

Abstract

The invention relates to a chip system with a dynamic trimming parameter monitoring function, which is internally provided with an SPI (Serial Peripheral Interface) communication module and a clock module, and completes the writing of trimming parameters and verification results into an internal storage module of a chip according to a clock signal CLK provided by the clock module in the power-on process of a chip factory calibration mode and a user mode. And loading the trimming parameter and the verification result to a register block for working, for the working process of a user mode, the correctness of the trimming parameters loaded in the register group is periodically checked according to an external communication clock signal SCLK of the SPI communication module, and the reloading of the trimming parameters is triggered for errors, so that the chip is recovered to a normal working state, the performance reduction caused by the loss of the trimming parameters is avoided, and the reliability of the chip is improved. And moreover, the influence on the normal use of the chip during the repeated invalid loading period is solved, and the internal power consumption of the chip is effectively controlled while the normal working performance of the chip is ensured.

Description

Technical Field

[0001] The invention relates to a chip system with a function of dynamically monitoring adjustment parameters, belonging to the technical field of chip design. Background Art

[0002] With the development and progress of science and technology, high-performance analog or digital chips are playing an increasingly important role. And as chip performance improves, process deviations in manufacturing have an increasingly greater impact on the key indicators of the chip, so it is necessary to use trimming parameters to adjust the circuit after the chip is produced. Under the existing technology, the chip usually writes trimming parameters to the memory device in the chip at the factory stage. When the user uses the chip, the trimming parameters are automatically loaded from the memory device to the register once when it is powered on and act on the target circuit, thereby improving the performance of the chip under application.

[0003] In the prior art, there are usually two types of chips that need to load tuning parameters. One type is a chip that only loads tuning parameters once when powered on. If the power supply fluctuates during the operation of the tuning parameters loaded into the register, the tuning parameters in the register will be lost, resulting in permanent degradation of chip performance until the chip is powered on again next time. The other type is a chip that periodically and repeatedly loads tuning parameters. In the event of occasional loss of tuning parameters, the tuning parameters can be restored by periodically reloading the tuning parameters. However, during the repeated loading period, the chip needs to stop working and consumes a lot of power to read the tuning parameters from the memory, which will affect the normal use and working performance of the chip. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a chip system with a dynamic monitoring function of adjustment parameters. Based on the external communication clock signal SCLK of the SPI communication module, the correctness of the adjustment parameters loaded in the register group is periodically checked, and the loading of the adjustment parameters is triggered, thereby ensuring the normal working performance of the chip and effectively controlling the internal power consumption of the chip.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions: the present invention designs a chip system with a function of dynamically monitoring adjustment parameters, including a target function simulation module, an SPI communication module with a built-in user mode verification module, and a control module with a built-in register group, wherein the control module interacts and communicates with the SPI communication module and the target function simulation module respectively; the chip is connected to the working circuit based on the SPI communication module being connected to an external host and the target function simulation module being connected to an external circuit;

[0006] In the user mode working process in which the chip is powered on and the register group is loaded with adjustment parameters to control the target function simulation module to work, the user mode verification module performs verification operations on the adjustment parameters loaded in the register group according to the preset cycle length, based on the communication clock signal SCLK provided by the external host of the SPI communication module, to obtain verification results, and compares and verifies the verification results.

[0007] As a preferred technical solution of the present invention: it also includes a clock module, a storage module, and a calibration mode check module built into the control module, wherein the control module communicates with the storage module, the clock module communicates with the control module and the storage module respectively, and the clock module synchronously provides a clock signal CLK to the control module and the storage module;

[0008] In the chip factory calibration mode, the SPI communication module receives the adjustment parameters configured by the host and forwards them to the control module; according to the clock signal CLK synchronously provided by the clock module to the control module and the storage module, the control module calls the calibration mode verification module to perform a verification operation on the adjustment parameters to obtain the verification result, and the control module writes the adjustment parameters and the verification result into the storage module;

[0009] When the chip is connected to the working circuit and performs the user mode power-on process, the control module retrieves the adjustment parameters and verification results from the storage module to the register group based on the clock signal CLK synchronously provided by the clock module to the control module and the storage module, and the register group loads the adjustment parameters to control the target function simulation module to work.

[0010] As a preferred technical solution of the present invention: in the user mode working process, after power-on and reading the data in the memory, the clock module is disabled, and the user mode verification module periodically performs a verification operation on the adjustment parameters loaded in the register group according to the communication clock signal SCLK provided by the external host of the SPI communication module to obtain a verification result, and compares and verifies whether the verification result is consistent with the verification result obtained by the verification operation in the chip factory calibration mode. If so, it is determined that the adjustment parameters loaded in the register group are correct; otherwise, it is determined that the adjustment parameters loaded in the register group are wrong.

[0011] As a preferred technical solution of the present invention: the calibration mode verification module in the chip factory calibration mode performs the same verification operation on the adjustment parameters as the user mode verification module in the user mode working process, and both use the target verification circuit to obtain the verification result;

[0012] The target verification circuit includes a first XOR logic gate module, a second XOR logic gate module, a third XOR logic gate module, and registers D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, and D15 which are connected in series in sequence in a manner that an output Q end of an adjacent front register is connected to an input D end of an adjacent rear register;

[0013] In the factory calibration mode of the chip, the clock CLK ends of each register in the target verification circuit are simultaneously connected to the clock signal CLK provided by the clock module; in the user mode working process, the clock CLK ends of each register in the target verification circuit are simultaneously connected to the communication clock signal SCLK provided by the SPI communication module external host; the input D end of register D0 is connected to the output end of the first XOR logic gate module, and one of the input ends of the first XOR logic gate module constitutes the input end of the target verification circuit, which is used to receive the bit data to be verified; the output Q end of register D1 and the input D end of register D2 are connected in series with the second XOR logic gate module, and the output Q end of register D14 and the input D end of register D15 are connected in series with the third XOR logic gate module. The input end of the target verification circuit is simultaneously connected to the input end of the second XOR logic gate module and the input end of the third XOR logic gate module, and the output Q end of register D15 constitutes the output end of the target verification circuit, which is used to output the result bit data corresponding to the bit data to be verified, and the output Q end of register D15 is simultaneously connected to the input end of the first XOR logic gate module, the input end of the second XOR logic gate module, and the input end of the third XOR logic gate module.

[0014] As a preferred technical solution of the present invention: the calibration mode verification module and the user mode verification module are respectively based on the verification operation performed by the target verification circuit, and according to the clock signal connected, the bit data to be verified in the adjustment parameter is sequentially transmitted to the input end of the target verification circuit in sequence, and after being processed by the target verification circuit, the result bit data corresponding to each bit data to be verified is sequentially outputted from the output end of the target verification circuit, and the result bit data are sequentially combined to form the verification result of the adjustment parameter;

[0015] Alternatively, based on the verification operation of the target verification circuit corresponding to a preset number of iterations, the data groups to be verified of each continuous preset bit length in the adjustment parameter are transmitted sequentially to the input end of the target verification circuit according to the corresponding clock signal. After being processed by the target verification circuit, the target verification circuit outputs the result data groups corresponding to each data group to be verified in sequence, and the result data groups are sequentially combined to form the verification result of the adjustment parameter.

[0016] As a preferred technical solution of the present invention: based on the SPI communication module externally connected to the host, the SPI communication module receives the communication clock signal SCLK, SPI communication chip select signal CSB, SPI communication data input signal SDI, and SPI communication data output signal SDO provided by the host.

[0017] As a preferred technical solution of the present invention, the user mode power-on process to the user mode working process performs the following steps:

[0018] Step A. IDLE state, when the chip is connected to the working circuit and performs the user mode power-on process, according to the clock signal CLK synchronously provided by the clock module to the control module and the storage module, the control module retrieves the adjustment parameters and the verification results from the storage module to the register group, which are used to initialize the values ​​of each register in the register group, and then enters step B;

[0019] Step B. START state, the clock module is disabled, and the user mode check module starts timing according to the communication clock signal SCLK provided by the external host of the SPI communication module, and obtains the starting address of the adjustment parameter in the register group, and then enters step C;

[0020] Step C. WAIT state, with the timing of the user mode verification module, the user mode verification module determines whether the timing reaches the verification period, if yes, it goes to step D; otherwise, it continues to time;

[0021] Step D. CHECK state: according to the communication clock signal SCLK provided by the host external to the SPI communication module, the user mode check module checks one byte of data according to one communication clock signal SCLK, starting from the starting address of the adjustment parameter in the register group, and sequentially performs a check operation on each byte of data in the adjustment parameter, thereby obtaining a check result under the corresponding check operation of the adjustment parameter, and then proceeds to step E;

[0022] Step E. STOP state, the user mode verification module compares and verifies whether the verification result obtained in step D is consistent with the verification result obtained by the verification operation in the chip factory calibration mode, and updates the flag bit of whether the verification is successful or not, and then returns to step B.

[0023] As a preferred technical solution of the present invention: if it is determined that the trimming parameters loaded in the register group are wrong, the user mode verification module generates a trimming parameter error signal for reading by the host externally connected to the SPI communication module. After the host reads the trimming parameter error signal, the host sends a reset instruction to the chip or executes the instruction of the user mode power-on process.

[0024] The chip system with dynamic monitoring function of adjustment parameters described in the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0025] The present invention designs a chip system with a dynamic monitoring function of adjustment parameters, with a built-in SPI communication module and a clock module. For the chip factory calibration mode and the user mode power-on process, the adjustment parameters and the verification results are written into the chip internal storage module according to the clock signal CLK provided by the clock module, and the adjustment parameters and the verification results are loaded into the register group for operation; for the user mode operation process, the correctness of the adjustment parameters loaded in the register group is periodically verified according to the external communication clock signal SCLK of the SPI communication module, and for errors, the adjustment parameters are reloaded, so that the chip is restored to a normal working state, which not only avoids the performance degradation caused by the loss of the adjustment parameters, but also solves the influence on the normal use of the chip during repeated invalid loading, ensures the normal working performance of the chip, and effectively controls the consumption of power consumption inside the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a module schematic diagram of a chip system with a dynamic monitoring function of adjustment parameters designed by the present invention;

[0027] Figure 2 It is a schematic diagram of the relative relationship between the clocks corresponding to the calibration mode and the user mode respectively under the design and application of the present invention;

[0028] Figure 3 It is a schematic diagram of the process flow of the chip factory calibration mode in the design of the present invention;

[0029] Figure 4 It is a schematic diagram of the data structure written into the storage module in the chip factory calibration mode under the design and application of the present invention;

[0030] Figure 5 It is a schematic diagram of a target verification circuit in the design of the present invention;

[0031] Figure 6 It is a schematic diagram of an embodiment of a simulation waveform in a calibration mode under the design and application of the present invention;

[0032] Figure 7 It is a flow chart of the process from the user mode power-on process to the user mode working process in the design of the present invention;

[0033] Figure 8 It is a schematic diagram of the state change from the user mode power-on process to the user mode working process in the design of the present invention;

[0034] Fig. 9 It is a schematic diagram of an embodiment of comparing correct simulation waveforms in user mode under the design and application of the present invention;

[0035] Fig.10 It is a schematic diagram of an embodiment of comparing error simulation waveforms in user mode under the design and application of the present invention. DETAILED DESCRIPTION

[0036] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0037] The present invention is designed to provide a chip system with a function of dynamically monitoring adjustment parameters. In practical applications, Figure 1 As shown, the specific design includes a clock module, a storage module, a target function simulation module, an SPI communication module with a built-in user mode verification module, and a control module with a built-in register group and a calibration mode verification module, wherein the control module interacts and communicates with the SPI communication module, the target function simulation module, and the storage module respectively, and the clock module communicates with the control module and the storage module respectively; based on the SPI communication module, an external host is connected, and the target function simulation module is connected to an external circuit to realize the connection of the chip to the working circuit, wherein, based on the SPI communication module, an external host is connected, and the SPI communication module receives the communication clock signal SCLK, the SPI communication chip select signal CSB, the SPI communication data input signal SDI, and the SPI communication data output signal SDO provided by the host. In actual applications, the SPI communication module communicates with the host, receives host instructions to realize internal control or return data required by the host.

[0038] In actual application, the chip is divided into the chip factory calibration mode, the user mode power-on process, and the user mode working process in sequence, such as Figure 2 As shown, the calibration mode corresponds to the chip factory calibration mode, and the user mode corresponds to the user mode power-on process and the user mode working process. In actual applications, in the chip factory calibration mode, Figure 3 As shown, the SPI communication module receives the N-byte adjustment parameters configured by the host and forwards them to the control module; according to the clock signal CLK synchronously provided by the clock module to the control module and the storage module, the control module calls the calibration mode verification module to perform a verification operation on the adjustment parameters to obtain an M-byte verification result, such as Figure 4 As shown, the control module writes the adjustment parameters and the verification results into the storage module.

[0039] like Figure 7As shown, when the chip is connected to the working circuit and performs the user mode power-on process, according to the clock signal CLK synchronously provided by the clock module to the control module and the storage module, the control module retrieves the adjustment parameters and the verification results from the storage module to the register group, and the register group loads the adjustment parameters to control the target function simulation module to work. The target function simulation module is a module that performs related analog functions, realizes analog signal input ANAIN and analog signal output ANAOUT, and in practical applications, it is any type of analog module such as an operational amplifier, a reference, a digital-to-analog converter or an analog-to-digital converter.

[0040] like Figure 7 As shown, in the user mode working process in which the chip is powered on and the register group is loaded with adjustment parameters to control the target function simulation module to work, the communication clock signal SCLK provided by the external host of the SPI communication module is switched, and the user mode verification module performs a verification operation on the adjustment parameters loaded in the register group according to a preset cycle length to obtain a verification result, and compares and verifies the verification result.

[0041] In the specific practical application of the user mode working process, after power-on and reading the data in the memory, the clock module is disabled to save power consumption. According to the communication clock signal SCLK provided by the host external to the SPI communication module, the user mode verification module performs a verification operation on the adjustment parameters loaded in the register group according to the preset cycle length to obtain a verification result, and compares and verifies whether the verification result is consistent with the verification result obtained by the verification operation in the chip factory calibration mode. If so, it is determined that the adjustment parameters loaded in the register group are correct; otherwise, it is determined that the adjustment parameters loaded in the register group are wrong, which may mean that the adjustment parameters in the register of the chip are lost during use. The user mode verification module generates an adjustment parameter error signal for the host external to the SPI communication module to read. After the host reads the adjustment parameter error signal, the host sends a reset instruction to the chip or executes the instruction of the user mode power-on process, so that the chip reloads the adjustment parameters and the verification results in the memory into the register group, and then waits for the set time for the next verification.

[0042] In practical applications of the above design, the calibration mode verification module in the chip factory calibration mode performs the same verification operation on the adjustment parameters as the user mode verification module in the user mode working process, and both use the target verification circuit to obtain the verification results.

[0043] In specific design, such as Figure 5As shown, the target verification circuit includes a first XOR logic gate module, a second XOR logic gate module, a third XOR logic gate module, and registers D0, register D1, register D2, register D3, register D4, register D5, register D6, register D7, register D8, register D9, register D10, register D11, register D12, register D13, register D14, and register D15 which are connected in series in sequence in a manner that the output Q ends of adjacent front registers are connected to the input D ends of adjacent rear registers.

[0044] In actual application, in the chip factory calibration mode, the clock CLK end of each register in the target verification circuit is simultaneously connected to the clock signal CLK provided by the clock module; in the user mode working process, the clock CLK end of each register in the target verification circuit is simultaneously connected to the communication clock signal SCLK provided by the SPI communication module external host; the input D end of register D0 is connected to the output end of the first XOR logic gate module, and one of the input ends of the first XOR logic gate module constitutes the input end of the target verification circuit for receiving the bit data to be verified; the output Q end of register D1 is connected to the input end of register D2 A second XOR logic gate module is connected in series between the input D terminals, a third XOR logic gate module is connected in series between the output Q terminal of register D14 and the input D terminal of register D15, the input terminal of the target verification circuit is simultaneously connected to the input terminal of the second XOR logic gate module and the input terminal of the third XOR logic gate module, the output Q terminal of register D15 constitutes the output terminal of the target verification circuit, which is used to output the result bit data corresponding to the bit data to be verified, and the output Q terminal of register D15 is simultaneously connected to the input terminal of the first XOR logic gate module, the input terminal of the second XOR logic gate module, and the input terminal of the third XOR logic gate module.

[0045] In the actual verification application of the above-mentioned designed target verification circuit, the calibration mode verification module and the user mode verification module respectively transmit the bit data to be verified in the adjustment parameters to the input end of the target verification circuit in sequence according to the clock signal connected in the verification operation performed based on the target verification circuit. After being processed by the target verification circuit, the target verification circuit outputs the result bit data corresponding to each bit data to be verified in sequence, and combines them in sequence to form the verification result of the adjustment parameters.

[0046] Alternatively, based on the verification operation of the target verification circuit corresponding to a preset number of iterations, the data groups to be verified of each continuous preset bit length in the adjustment parameter are transmitted sequentially to the input end of the target verification circuit according to the corresponding clock signal. After being processed by the target verification circuit, the target verification circuit outputs the result data groups corresponding to each data group to be verified in sequence, and the result data groups are sequentially combined to form the verification result of the adjustment parameter.

[0047] In order to improve the verification efficiency, according to the working characteristics of the verification core circuit, 8 serial 1-bit data can be input into the target verification circuit, and the logic change achieved is equivalent to the logic change achieved by 1 parallel 8-bit data input. The equivalent verification circuit core function satisfies the following formula:

[0048] d[0]=^q[15:8]^(^din[7:0])

[0049] d[1]=^q[15:9]^(^din[7:1])

[0050] d[2]=^q[9:8]^(^din[1:0])

[0051] d[3]=^q[10:9]^(^din[2:1])

[0052] d[4]=^q[11:10]^(^din[3:2])

[0053] d[5]=^q[12:11]^(^din[4:3])

[0054] d[6]=^q[13:12]^(^din[5:4])

[0055] d[7]=^q[14:13]^(^din[6:5])

[0056] d[8]=q[0]^(^q[15:14])^(^din[7:6])

[0057] d[9]=q[1]^q

[15] ^din[7]

[0058] d

[10] =q[2]

[0059] d

[11] =q[3]

[0060] d

[12] =q[4]

[0061] d

[13] =q[5]

[0062] d

[14] =q[6]

[0063] d

[15] =^q[15:7]^(^din[7:0])

[0064] Among them, din[7:0] is the 8-bit data of parallel input, d[15:0] is the current input of 16 registers, and q[15:0] is the output of 16 registers in the previous cycle. Each rising edge of the clock will drive the parallel 8-bit data to be verified until all data are verified, and the verification result is output from q[15:0].

[0065] The chip system with the function of dynamically monitoring the adjustment parameters designed by the present invention is applied in practice, from the user mode power-on process to the user mode working process, such as Figure 7 and Figure 8 As shown, the specific design executes the following steps A to E.

[0066] Step A. IDLE state, when the chip is connected to the working circuit and performs the user mode power-on process, based on the clock signal CLK synchronously provided by the clock module to the control module and the storage module, the control module retrieves the adjustment parameters and verification results from the storage module to the register group, which are used to initialize the values ​​of each register in the register group, and then enters step B.

[0067] Step B. START state, the clock module is disabled, and the user mode check module starts timing according to the communication clock signal SCLK provided by the external host of the SPI communication module, and simultaneously obtains the starting address of the adjustment parameters in the register group, and then enters step C.

[0068] Step C. WAIT state, with the timing of the user mode verification module, the user mode verification module determines whether the timing reaches the verification period, if yes, enters step D; otherwise, continues timing.

[0069] Step D. CHECK state, according to the communication clock signal SCLK provided by the external host of the SPI communication module, the user mode verification module verifies one byte of data according to one communication clock signal SCLK, starting from the starting address of the trimming parameter in the register group, and sequentially verifies each byte of data in the trimming parameter, thereby obtaining the verification result under the corresponding verification operation of the trimming parameter, and then enters step E. Here, 8 bits of data are verified for each communication clock, and when the clock of one communication cycle cannot complete all the verifications, verification is performed through multiple communication cycles until the verification of the trimming parameters in all registers is completed to obtain the verification result in user mode.

[0070] Step E. STOP state, the user mode verification module compares and verifies whether the verification result obtained in step D is consistent with the verification result obtained by the verification operation in the chip factory calibration mode, and updates the flag bit of whether the verification is successful or not, and then returns to step B.

[0071] The simulation results of actual application are as follows Figure 6 , Fig. 9 , Fig.10 As shown, among which, Figure 6 The simulation waveform embodiment in the calibration mode is shown as follows, where clk is the clock driving the check, check_cnt is the number of input clocks, check_din is 8-bit input data, and check_result is the final check result, and the final result is 16'ha847; Fig. 9 ,as well as Fig.10 (a) and (b) shown in the figure respectively show a schematic diagram of a correct simulation waveform embodiment, a schematic diagram of an incorrect simulation waveform embodiment, and a schematic diagram of an incorrect simulation waveform embodiment in the user mode, where SCLK is the clock for driving verification, check_user_cnt is the number of input clocks, check_user_din is 8-bit input data, check_uer_result is the final verification result, and check_err is the verification error signal.

[0072] Fig. 9 This is the waveform when the comparison is successful. The verification result in user mode is also 16'ha847, so no comparison error signal is generated. Fig.10 (a) and (b) are waveforms when a comparison error occurs. The verification result in user mode is 16'h5113, which is different from the verification result in calibration mode. The comparison error signal will become a high level after the communication ends.

[0073] The chip system with the function of dynamic monitoring of adjustment parameters designed by the present invention has a built-in SPI communication module and a clock module. For the chip factory calibration mode and the user mode power-on process, the adjustment parameters and the verification results are written into the chip internal storage module according to the clock signal CLK provided by the clock module, and the adjustment parameters and the verification results are loaded into the register group for operation; for the user mode operation process, the correctness of the adjustment parameters loaded in the register group is periodically verified according to the external communication clock signal SCLK of the SPI communication module, and for errors, the reloading of the adjustment parameters is triggered to restore the chip to a normal working state, which not only avoids the performance degradation caused by the loss of the adjustment parameters, but also solves the influence on the normal use of the chip during repeated invalid loading, ensures the normal working performance of the chip, and effectively controls the consumption of power consumption inside the chip.

[0074] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A chip system with a function of dynamically monitoring adjustment parameters, characterized in that: It includes a target function simulation module, an SPI communication module with a built-in user mode verification module, and a control module with a built-in register group, wherein the control module interacts and communicates with the SPI communication module and the target function simulation module respectively; the chip is connected to the working circuit by connecting the SPI communication module to an external host and the target function simulation module to an external circuit; In the user mode working process in which the chip is powered on and the register group is loaded with adjustment parameters to control the target function simulation module to work, the user mode verification module performs verification operations on the adjustment parameters loaded in the register group according to the preset cycle length, based on the communication clock signal SCLK provided by the external host of the SPI communication module, to obtain verification results, and compares and verifies the verification results.

2. The chip system with dynamic monitoring function of adjustment parameters according to claim 1, characterized in that: It also includes a clock module, a storage module, and a calibration mode check module built into the control module, wherein the control module communicates with the storage module, the clock module communicates with the control module and the storage module respectively, and the clock module synchronously provides a clock signal CLK to the control module and the storage module; In the chip factory calibration mode, the SPI communication module receives the adjustment parameters configured by the host and forwards them to the control module; according to the clock signal CLK synchronously provided by the clock module to the control module and the storage module, the control module calls the calibration mode verification module to perform a verification operation on the adjustment parameters to obtain the verification result, and the control module writes the adjustment parameters and the verification result into the storage module; When the chip is connected to the working circuit and performs the user mode power-on process, the control module retrieves the adjustment parameters and verification results from the storage module to the register group based on the clock signal CLK synchronously provided by the clock module to the control module and the storage module, and the register group loads the adjustment parameters to control the target function simulation module to work.

3. The chip system with dynamic monitoring function of adjustment parameters according to claim 2, characterized in that: In the user mode working process, after power-on and reading the data in the memory, the clock module is disabled. According to the communication clock signal SCLK provided by the external host of the SPI communication module, the user mode verification module periodically performs verification operation on the adjustment parameters loaded in the register group to obtain the verification result, and compares and verifies whether the verification result is consistent with the verification result obtained by the verification operation in the chip factory calibration mode. If so, it is determined that the adjustment parameters loaded in the register group are correct; Otherwise, it is determined that the adjustment parameters loaded in the register group are wrong.

4. A chip according to claim 3, characterized in that: The calibration operation performed by the calibration mode verification module on the adjustment parameters in the chip factory calibration mode is the same as the calibration operation performed by the user mode verification module on the adjustment parameters in the user mode working process, and both use the target verification circuit to obtain the verification result; The target verification circuit includes a first XOR logic gate module, a second XOR logic gate module, a third XOR logic gate module, and registers D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, and D15 which are connected in series in sequence in a manner that an output Q end of an adjacent front register is connected to an input D end of an adjacent rear register; In the factory calibration mode of the chip, the clock CLK ends of each register in the target verification circuit are simultaneously connected to the clock signal CLK provided by the clock module; in the user mode working process, the clock CLK ends of each register in the target verification circuit are simultaneously connected to the communication clock signal SCLK provided by the SPI communication module external host; the input D end of register D0 is connected to the output end of the first XOR logic gate module, and one of the input ends of the first XOR logic gate module constitutes the input end of the target verification circuit, which is used to receive the bit data to be verified; the output Q end of register D1 and the input D end of register D2 are connected in series with the second XOR logic gate module, and the output Q end of register D14 and the input D end of register D15 are connected in series with the third XOR logic gate module. The input end of the target verification circuit is simultaneously connected to the input end of the second XOR logic gate module and the input end of the third XOR logic gate module, and the output Q end of register D15 constitutes the output end of the target verification circuit, which is used to output the result bit data corresponding to the bit data to be verified, and the output Q end of register D15 is simultaneously connected to the input end of the first XOR logic gate module, the input end of the second XOR logic gate module, and the input end of the third XOR logic gate module.

5. The chip system with dynamic monitoring function of adjustment parameters according to claim 4, characterized in that: The calibration mode verification module and the user mode verification module are respectively based on the verification operation performed by the target verification circuit, and according to the clock signal connected, the bit data to be verified in the adjustment parameter is sequentially transmitted to the input end of the target verification circuit in sequence, and after being processed by the target verification circuit, the result bit data corresponding to each bit data to be verified is sequentially outputted from the output end of the target verification circuit, and the result bit data are sequentially combined to form the verification result of the adjustment parameter; Alternatively, based on the verification operation of the target verification circuit corresponding to a preset number of iterations, the data groups to be verified of each continuous preset bit length in the adjustment parameter are transmitted sequentially to the input end of the target verification circuit according to the corresponding clock signal. After being processed by the target verification circuit, the target verification circuit outputs the result data groups corresponding to each data group to be verified in sequence, and the result data groups are sequentially combined to form the verification result of the adjustment parameter.

6. A chip system with a function of dynamically monitoring adjustment parameters according to any one of claims 1 to 5, characterized in that: Based on the SPI communication module being connected to an external host, the SPI communication module receives a communication clock signal SCLK, an SPI communication chip select signal CSB, an SPI communication data input signal SDI, and an SPI communication data output signal SDO provided by the host.

7. A chip system with a function of dynamically monitoring adjustment parameters according to any one of claims 3 to 5, characterized in that: The user mode power-on process to the user mode working process performs the following steps: Step A. IDLE state, when the chip is connected to the working circuit and performs the user mode power-on process, according to the clock signal CLK synchronously provided by the clock module to the control module and the storage module, the control module retrieves the adjustment parameters and the verification results from the storage module to the register group, which are used to initialize the values ​​of each register in the register group, and then enters step B; Step B. START state, the clock module is disabled, and the user mode check module starts timing according to the communication clock signal SCLK provided by the external host of the SPI communication module, and obtains the starting address of the adjustment parameter in the register group, and then enters step C; Step C. WAIT state, with the timing of the user mode verification module, the user mode verification module determines whether the timing reaches the verification period, if yes, it goes to step D; otherwise, it continues to time; Step D. CHECK state: according to the communication clock signal SCLK provided by the host external to the SPI communication module, the user mode check module checks one byte of data according to one communication clock signal SCLK, starting from the start address of the adjustment parameter in the register group, and sequentially performs a check operation on each byte of data in the adjustment parameter, thereby obtaining a check result under the corresponding check operation of the adjustment parameter, and then proceeds to step E; Step E. STOP state, the user mode verification module compares and verifies whether the verification result obtained in step D is consistent with the verification result obtained by the verification operation in the chip factory calibration mode, and updates the flag bit of whether the verification is successful or not, and then returns to step B.

8. A chip system with a function of dynamically monitoring adjustment parameters according to any one of claims 3 to 5, characterized in that: If it is determined that the trimming parameters loaded in the register group are wrong, the user mode verification module generates a trimming parameter error signal for the host externally connected to the SPI communication module to read. After the host reads the trimming parameter error signal, the host sends a reset instruction to the chip or executes the instruction of the user mode power-on process.

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