Method and device for achieving out-of-order transmission and order preservation of AXI bus and computer readable storage medium

Abstract

The invention provides a method for achieving out-of-order transmission and order preservation of an AXI bus. A bus controller sends instructions with the same ID of the same channel to an instruction register module for storage according to an instruction sending sequence; the bus controller distributes the received multiple instructions to different slave devices according to the slave devices pointed by the instructions; the state matrix module reads a plurality of instructions stored in the instruction register one by one, analyzes instruction information and stores the instruction information, the state matrix module adds state information and decoding / masking operation to each piece of instruction information, and only one instruction is given to a plurality of instructions with the same ID value each time to respond to the state information and decoding operation of the instructions; and the bus controller selects an instruction execution result returned by the slave device corresponding to the instruction of which the state information is a response instruction in the instruction information to the host. The invention further provides a device for realizing out-of-order transmission and order preservation of the AXI bus and a computer readable storage medium.

Description

Technical Field

[0001] The present invention belongs to the field of processor technology, and in particular, relates to a method, a device and a computer-readable storage medium for implementing order preservation in out-of-order transmission of an AXI bus. Background Art

[0002] AXI (Advanced eXtensible Interface) is a bus protocol. It is the most important part of the AMBA (Advaced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus for high performance, high bandwidth, and low latency, and is widely used in system-level integrated circuits. The address / control and data of the AXI protocol are separate channels. At the same time, in burst transmission, only the first address is required, and the transmission length can be up to 4KB. The AXI protocol supports separate read and write data channels, outstanding transmission access, and out-of-order transmission. Out-of-order transmission allows transmission requests to be transmitted on the bus according to different priorities. The basic idea is that transmission requests on the bus can be received and responded to at different times without waiting for the completion of the previous transmission request. This can maximize the use of bus bandwidth and system resources, thereby improving system efficiency and data throughput.

[0003] At present, in the AXI out-of-order transmission process, after multiple read instructions or write instructions with the same ID are sent to different slave devices, the order of the read data or write response signals returned by the multiple slave devices will not be consistent with the order in which the instructions are sent, which will lead to the problem that the data consistency cannot be guaranteed or the system function is abnormal, thus causing a series of unpredictable problems. Therefore, it is necessary to improve the existing AXI bus out-of-order transmission method so that the AXI bus can perform order-preserving operations on the return data or signals of multiple instructions with the same ID in out-of-order transmission to ensure data consistency. Summary of the invention

[0004] The present invention provides a method and device for implementing order preservation of AXI bus out-of-order transmission, which can ensure that the data or signal returned by instructions with the same ID are consistent with the order in which the instructions are issued, thereby ensuring the consistency of the data.

[0005] The present invention also provides a computer-readable storage medium for implementing a method for preserving order in out-of-order transmission of an AXI bus.

[0006] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for implementing order preservation in out-of-order transmission of an AXI bus, wherein multiple instructions sent by a host are received by a bus controller, and instructions with the same ID of the same channel are sent to an instruction storage module for storage in the order in which the instructions are sent; the bus controller distributes the received multiple instructions to different slave devices according to the slave devices pointed to by the instructions; the state matrix module reads the multiple instructions stored in the instruction storage one by one, and parses the instruction information for storage, wherein the instruction information at least includes the ID value, instruction content and corresponding slave device information of each instruction; the state matrix module adds status information and decoding / masking operations to each instruction information, and multiple instructions with the same ID value will only be assigned status information and decoding operations of one response instruction each time; the bus controller searches the state matrix for the slave device information corresponding to the instruction whose status information is a response instruction, and selects the instruction execution result returned by the slave device to the host to complete the execution of the instruction.

[0008] When the slave device corresponding to the instruction execution result returned to the bus controller does not match the slave device information corresponding to the instruction whose status information in the instruction information is a response instruction, the bus controller suspends the instruction execution result returned by the unmatched slave device until the comparison result matches.

[0009] The slave device information of the instruction in the state matrix includes the address information of the slave device; the bus controller searches for the required slave device among the slave devices that return the instruction execution result based on the slave device address information corresponding to the instruction that responds to the instruction in the state information in the state matrix, receives the instruction execution result, and suspends other slave devices.

[0010] After receiving the instruction from the device, the slave device has an execution timeout or an error state. The slave device sends a response signal on the response channel to indicate the error or timeout state. After reading the specific response signal, the bus controller terminates the execution of the corresponding instruction and deletes the instruction information of the terminated execution in the state matrix.

[0011] The bus controller deletes the instruction information of the instruction execution completed in the state matrix, and updates the state information of the next instruction with the same ID as the response instruction according to the instruction writing sequence, and adds a decoding operation at the same time.

[0012] The host and the slave device communicate with the bus controller via a host interface module and a slave device interface module respectively.

[0013] Another technical solution of the present invention provides a device for implementing order preservation of AXI bus out-of-order transmission, including a host, a slave device and a bus controller, the host and the slave device communicate with the bus controller, and the device is used to implement the method for implementing order preservation of AXI bus out-of-order transmission as described above, the bus controller communicates with the instruction storage module, and the bus controller sends the received instructions of the same ID of the same channel to the instruction storage module in sequence for storage; the instruction storage module communicates with the state matrix module, the state matrix module parses the instructions stored in the instruction storage module, and the obtained instruction information is written into the state matrix module in sequence; the state matrix module communicates with the bus controller, the bus controller distributes the instructions issued by the host to the slave device, and searches the state matrix module for the slave device information corresponding to the instruction whose state information is a response instruction, and receives the instruction execution result returned by the slave device that is consistent with the searched slave device information; after the instruction is executed, the bus controller controls the state matrix module to update the state matrix information, and executes the next instruction reading or data return operation.

[0014] The host and the slave device communicate with the bus controller via a host interface module and a slave device interface module respectively.

[0015] The bus controller controls the state matrix module to update the state matrix information, including deleting the instruction information of the completed instruction execution, and updating the state information of the next instruction information with the same ID as the response instruction and granting the decoding operation.

[0016] Another technical solution of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores program code, and the program code is called by a processor to execute the method described above.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include: the present invention stores the instructions with the same ID sent by the host in the register in sequence through the bus controller, and sends all the instructions to the slave device for processing. When the slave device returns the instruction processing result to the bus controller, the bus controller checks the status information in the status matrix for the slave device information corresponding to the instruction of the response instruction, and receives the instruction processing result returned by the slave device, thereby ensuring that the returned data remains consistent with the sent instruction.

[0018] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 The present invention is a schematic diagram of a device for implementing order preservation of out-of-order transmission on an AXI bus.

[0021] Figure 2 This is the state matrix structure diagram of the present invention.

[0022] Figure 3 It is a schematic diagram of updating the instruction information stored in the state matrix in the first embodiment of the present invention. DETAILED DESCRIPTION

[0023] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0024] Embodiment 1 Embodiment 1 provides a method for implementing order preservation in out-of-order transmission of an AXI bus, wherein multiple instructions sent by a host are received by a bus controller, and instructions with the same ID of the same channel are sent to an instruction storage module for storage in the order in which the instructions are sent; the bus controller distributes the received multiple instructions to different slave devices according to the slave devices pointed to by the instructions; a state matrix module reads multiple instructions stored in the instruction storage one by one, and parses out instruction information for storage, wherein the instruction information at least includes the ID value, instruction content and corresponding slave device information of each instruction; the state matrix module adds status information and decoding / masking operations to each instruction information, and multiple instructions with the same ID value are only assigned status information and decoding operations of one response instruction each time; the bus controller searches the state matrix for the slave device information corresponding to the instruction whose status information is a response instruction, and selects the instruction execution result returned by the slave device to the host to complete the execution of the instruction.

[0025] The following is a specific explanation of the method for implementing the AXI bus out-of-order transmission and order preservation of the present embodiment 1 in conjunction with the accompanying drawings. The method for implementing the AXI bus out-of-order transmission and order preservation of the present invention sends the instructions sent by the host to the bus controller via the host interface module, and the bus controller is responsible for the data transmission between the slave device and the host under the AXI bus transmission protocol. The bus controller distributes the received instructions according to the slave device address corresponding to the instructions. After the slave device receives the corresponding instructions, it processes and returns the result of the instruction processing to the bus controller. The AXI bus protocol has 5 transmission channels, namely, the write address channel, the write data channel, the read address channel, the read data channel and the response channel. When the AXI bus protocol performs out-of-order transmission, the instructions of the same channel, when the ID is different, do not affect the out-of-order transmission. However, when the instructions of the same channel have the same ID, it is necessary to ensure that the sending order of the instructions with the same ID and the return order of the instruction execution results are the same.

[0026] The ID refers to the transaction identifier under the AXI bus transmission protocol, which is used to identify each transmission operation in order to support out-of-order transmission and data flow management. In circuit implementation, it is the ID signal of the address channel in the AXI bus.

[0027] In order to realize the disorder transmission of the same ID instruction of the same channel, when the bus controller receives multiple instructions with the same ID in the same channel, it writes the instructions with the same ID received in the same channel into the instruction register module according to the instruction sending order. The instruction register module saves the instructions with the same ID of the same channel in the above order. The state matrix module parses the instructions stored in the instruction register module and writes the parsed instruction information into the state matrix in order. Figure 2 The parsed command information must at least include the command ID value and the corresponding slave device information ( Figure 2 S0, S1, S2...Sn in the instruction), the content of the instruction ( Figure 2 CMD1, CMD2, CMD3...CMDn in the command, CMD is a read command). At the same time, the state matrix module will also give status information to each saved command ( Figure 2The state matrix module adds the response instruction valid and the non-response instruction invalid) and the decoding / masking operation (decoding operation UNMASK and masking operation MASK) in the instruction information of the first instruction saved in the order of the host transmission instruction. The state information of each instruction in the remaining instruction information is a non-response instruction (invalid) and a masking operation (MASK) is assigned. When the bus controller receives the result returned from the slave device, it queries the state matrix in the state matrix module and searches for the instruction whose state information is a response instruction in the state matrix. The slave device information corresponding to this instruction is the slave device that the bus controller selects to receive the returned instruction execution result this time. The instruction execution results returned by the remaining slave devices will be suspended by the bus controller until the bus controller finds the instruction state information corresponding to the suspended slave device in the state matrix as a response instruction. Each time the bus controller receives the returned instruction execution result and sends it to the host, it will update the state matrix in the state matrix module. The update method is that for instructions whose status information is a response instruction, after the instruction return result of this instruction is sent to the host, the instruction execution is completed, the instruction is deleted, and the state information of the next instruction with the same ID is changed to a response instruction in sequence, and the mask operation is assigned as a decoding operation. After the bus controller finds the instruction, the instruction execution result returned from the device corresponding to the instruction is selected and sent to the host, and the bus controller continues to update the state matrix in the state matrix module. Repeat the above operation until all instructions are executed.

[0028] When the bus controller receives the returned instruction execution result, in order to quickly find the instruction execution result returned by the slave device that meets the needs, the slave device information corresponding to each instruction in the state matrix includes the address information of the slave device; the bus controller searches for the required slave device among the slave devices that return the instruction execution result based on the slave device address information corresponding to the instruction whose state information in the state matrix is ​​the response instruction, that is, searches for the slave device with the same slave device address information as the instruction whose state in the state matrix is ​​the response instruction, and receives the instruction execution result returned by the slave device, while suspending other slave devices. The state matrix is ​​updated and the next instruction execution result is received.

[0029] In order to ensure the security of instruction transmission and take into account efficiency, after receiving the instruction from the device, if there is no execution timeout or error status signal, the bus controller needs to remain in a waiting state. After receiving the instruction from the device, when the slave device has an execution timeout or an error state, the slave device sends a response signal on the response channel to indicate the error or timeout state. After reading the specific response signal, the bus controller terminates the execution of the corresponding instruction and deletes the instruction information corresponding to the instruction that is terminated in the state matrix.

[0030] The following Figure 3 Take as an example to illustrate a data transmission process of this implementation scheme 1.

[0031] Figure 3 Part a in it is the instruction information of the three instructions written into the status matrix. The IDs of the three instructions are all 0xf. In the first operation, the status information of the first instruction is the response status valid, and the decoding operation UNMASK is assigned. At this time, the first decoding operation is executed, and the read operation CMD1 is executed. After receiving the instruction sent by the host, the bus controller distributes multiple instructions at a time according to the slave devices corresponding to the instructions. All slave devices will respond after receiving the instructions, but the response speed of each slave device is different. For example, among multiple read instructions sent at a time, slave device 2 (SLAVE2) responds first and sends a response request to the bus controller, and requests to return the read data data2. When the bus controller receives requests from multiple slave devices, it will search the status matrix in the status matrix module and search for instructions whose status information in the status instruction is the response instruction valid, that is, Figure 3 The instruction CMD1 in the a part of the instruction corresponds to the slave device information of slave device 1 (SLAVE1). The bus controller will suspend the read request sent by non-slave device 1, and after slave device 1 sends a read request, respond to the request, receive the instruction execution result returned by slave device 1, and transmit it to the host. After the instruction execution result returned by slave device 1 is sent to the host, the instruction CMD1 is completed, the bus controller updates the status matrix, deletes the instruction information of instruction CMD1, and updates the status information of the next instruction CMD2 with the same ID to the response instruction valid, and assigns the decoding operation UNMASK, that is, Figure 3 The red instruction information in part b of the figure. After the update is completed, the bus controller continues to search until it finds the status information of instruction CMD2 as the response instruction valid, receives the instruction execution result returned by slave 2 (SLAVE2), and updates the state matrix according to the above scheme, that is, Figure 3 Part c in .

[0032] Embodiment 2 Embodiment 2 provides a device for implementing out-of-order transmission and order preservation on an AXI bus. Figure 1 The device for implementing AXI bus out-of-order transmission and order preservation is used to implement a method for implementing AXI bus out-of-order transmission and order preservation in embodiment 1, including a host, a slave device and a bus controller, the host and the slave device communicate with the bus controller, the bus controller communicates with the instruction storage module, the bus controller sends the received instructions of the same ID of the same channel to the instruction storage module in sequence for storage; the instruction storage module communicates with the state matrix module, the state matrix module parses the instructions stored in the instruction storage module, and the obtained instruction information is written into the state matrix module in sequence; the state matrix module communicates with the bus controller, the bus controller distributes the instructions issued by the host to the slave device, and searches the state matrix module for the slave device information corresponding to the instruction whose state information is a response instruction, and receives the instruction execution result returned by the slave device consistent with the searched slave device information; after the instruction is executed, the bus controller controls the state matrix module to update the state matrix information, and executes the operation of reading the next instruction or returning data. The bus controller controls the state matrix module to update the state matrix information, including deleting the instruction information of the completed instruction execution, updating the state information of the next instruction information with the same ID as the response instruction and granting the decoding operation.

[0033] As an implementable solution, the host and the slave device communicate with the bus controller via a host interface module and a slave device interface module respectively.

[0034] Embodiment 3 Embodiment 3 provides a computer-readable storage medium, in which a program code is stored, and the program code is called by a processor to execute the method described in Embodiment 1. The method in Embodiment 1 is written into a program code and called and executed by a processor, so that the order preservation of AXI bus out-of-order transmission can be achieved more efficiently.

[0035] The above is a detailed introduction to a method, device and computer-readable storage medium for implementing out-of-order transmission and order preservation of an AXI bus provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for implementing out-of-order transmission and order preservation on an AXI bus, characterized in that: The multiple commands sent by the host are received by the bus controller, and the commands with the same ID of the same channel are sent to the command storage module for storage according to the command sending sequence; The bus controller distributes the received multiple instructions to different slave devices according to the slave devices to which the instructions are directed; The state matrix module reads the multiple instructions stored in the instruction register one by one, and parses the instruction information for storage, wherein the instruction information at least includes the ID value of each instruction, the instruction content and the corresponding slave device information; The state matrix module adds state information and decoding / masking operations to each instruction information. Multiple instructions with the same ID value will only be assigned state information and decoding operations to one response instruction at a time. The bus controller searches the state matrix for the slave device information corresponding to the instruction whose state information is the response instruction, and selects the instruction execution result returned by the slave device to the host to complete the execution of the instruction.

2. A method for implementing out-of-order transmission and order preservation on an AXI bus according to claim 1, characterized in that: When the slave device corresponding to the instruction execution result returned to the bus controller does not match the slave device information corresponding to the instruction whose status information in the instruction information is a response instruction, the bus controller suspends the instruction execution result returned by the unmatched slave device until the comparison result matches.

3. A method for implementing AXI bus out-of-order transmission order preservation according to claim 2, characterized in that: The slave device information of the instruction in the state matrix includes address information of the slave device; The bus controller searches for the required slave device among the slave devices that return the instruction execution result based on the slave device address information corresponding to the instruction that responds to the instruction in the state information in the state matrix, receives the instruction execution result, and suspends other slave devices.

4. A method for implementing out-of-order transmission and order preservation of AXI bus according to claim 2, characterized in that: After receiving the instruction from the device, the slave device has an execution timeout or an error state. The slave device sends a response signal on the response channel to indicate the error or timeout state. After reading the specific response signal, the bus controller terminates the execution of the corresponding instruction and deletes the instruction information of the terminated execution in the state matrix.

5. A method for implementing out-of-order transmission and order preservation of AXI bus according to claim 1, characterized in that: The bus controller deletes the instruction information of the instruction execution completed in the state matrix, and updates the state information of the next instruction with the same ID as the response instruction according to the instruction writing sequence, and adds a decoding operation at the same time.

6. A method for implementing out-of-order transmission and order preservation of AXI bus according to claim 1, characterized in that: The host and the slave device communicate with the bus controller via a host interface module and a slave device interface module respectively.

7. A device for implementing out-of-order transmission and order preservation of an AXI bus, comprising a host, a slave device and a bus controller, wherein the host and the slave device communicate with the bus controller, characterized in that: The device is used to implement a method for implementing an AXI bus out-of-order transmission order preservation method as described in any one of claims 1 to 6, wherein the bus controller communicates with the instruction register module, and the bus controller sends received instructions of the same ID of the same channel to the instruction register module in order for storage; The instruction register module communicates with the state matrix module, the state matrix module parses the instructions stored in the instruction register module, and the obtained instruction information is written into the state matrix module in sequence; The state matrix module communicates with the bus controller, the bus controller distributes the instruction issued by the host to the slave device, searches the state matrix module for the slave device information corresponding to the instruction whose state information is the response instruction, and receives the instruction execution result returned by the slave device consistent with the searched slave device information; After the instruction is executed, the bus controller controls the state matrix module to update the state matrix information and execute the next instruction reading or data return operation.

8. The device for implementing out-of-order transmission and order preservation of AXI bus according to claim 7, characterized in that: The host and the slave device communicate with the bus controller via a host interface module and a slave device interface module respectively.

9. The device for implementing out-of-order transmission and order preservation of AXI bus according to claim 7, characterized in that: The bus controller controls the state matrix module to update the state matrix information, including deleting the instruction information of the completed instruction execution, and updating the state information of the next instruction information with the same ID as the response instruction and granting the decoding operation.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the method according to any one of claims 1 to 6.

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