Hardware verification method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a hardware verification method and device, electronic equipment and a readable storage medium. The method comprises the steps of generating a first asynchronous function and a second asynchronous function through a to-be-verified pin based on to-be-verified hardware; the first asynchronous function is used for reading and writing a to-be-verified pin, and the second asynchronous function is used for acquiring and outputting an output signal of the to-be-verified pin; constructing a model code through the first asynchronous function and the second asynchronous function; and verifying the to-be-verified pin through the model code. Therefore, according to the embodiment of the invention, two types of asynchronous functions are generated for the to-be-verified pin, hardware operation modeling of the pin can be carried out to form a simple asynchronous function interface in software, so that software programmers can start a hardware verification process more easily, and the hardware verification process can be better combined with a software test technology. Verification for hardware behaviors can be modeled into software verification, hardware description and verification languages do not need to be adopted, and the hardware verification efficiency is improved through an asynchronous function in software.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a hardware verification method, device, electronic equipment and readable storage medium. Background Art

[0002] With the development of computer technology, various chips have more and more functions. In order to ensure the normal operation of the chip, it is often necessary to verify the functional correctness of the Design Under Test (DUT) before the chip is taped out.

[0003] In the functional verification of the chip, it is usually necessary to model the hardware behavior, which is currently often implemented through the hardware description and verification language (SystemVerilog, SV). However, the SV language has high professional requirements for verifiers, which often leads to low verification efficiency. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a hardware verification method, device, electronic device and readable storage medium to solve the problem of low verification efficiency. The specific technical solution is as follows: In a first aspect of the present invention, a hardware verification method is first provided, the method comprising: Based on the pin to be verified of the hardware to be verified, a first asynchronous function and a second asynchronous function are generated; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain and output the output signal of the pin to be verified; Constructing a model code through the first asynchronous function and the second asynchronous function; The pin to be verified is verified by using the model code.

[0005] In a second aspect of the present invention, a hardware verification device is provided, the device comprising: A generation module, used to generate a first asynchronous function and a second asynchronous function based on a pin to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain and output an output signal of the pin to be verified; A construction module, used to construct a model code through the first asynchronous function and the second asynchronous function; A verification module is used to verify the pin to be verified through the model code.

[0006] In a third aspect of the present invention, there is also provided an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor is used to implement the method described in the first aspect when executing the program stored in the memory.

[0007] In a fourth aspect of the implementation of the present invention, a computer-readable storage medium is further provided, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in the first aspect above.

[0008] In a fifth aspect of the implementation of the present invention, there is also provided a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0009] The hardware verification method provided by the embodiment of the present invention generates a first asynchronous function and a second asynchronous function based on the pin to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain the output signal of the pin to be verified and output it; the model code is constructed by the first asynchronous function and the second asynchronous function; the pin to be verified is verified by the model code. In this way, by generating two types of asynchronous functions for the pin to be verified, the hardware operation of the pin can be modeled as a concise asynchronous function interface in the software, so that software programmers can start the hardware verification process more easily and can better combine it with software testing technology. Therefore, by constructing the model code through the first asynchronous function and the second asynchronous function and verifying the pin to be verified through the model code, the verification of hardware behavior can be modeled as software verification, without the need to use hardware description and verification language, and the efficiency of hardware verification can be greatly improved through the asynchronous function in the software. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0011] Figure 1 A flowchart of a hardware verification method according to an embodiment of the present invention; Figure 2 A schematic diagram of the structure of a hardware verification device in an embodiment of the present invention; Figure 3 Schematic diagram of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0014] Figure 1 FIG. 1 is a flowchart of a hardware verification method according to an embodiment of the present invention. Figure 1 As shown, the method includes: Step 101: Generate a first asynchronous function and a second asynchronous function based on a pin to be verified of hardware to be verified; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain and output an output signal of the pin to be verified.

[0015] Step 102: construct a model code through the first asynchronous function and the second asynchronous function.

[0016] Step 103: Verify the pin to be verified by using the model code.

[0017] With respect to the above steps 101 to 103, the embodiment of the present invention can be applied to any computer device, and the embodiment of the present invention does not limit this. Among them, the above hardware to be verified can be a chip design to be verified, that is, DUT. The chip design that has not been taped out can be determined as the above hardware to be verified according to actual needs, and the embodiment of the present invention does not limit this. Correspondingly, the above pins to be verified refer to the design pins of the DUT. A DUT often has multiple pins, and different pins are used to receive different signals and implement different functions. The embodiment of the present invention can generate different first asynchronous functions and second asynchronous functions for different pins to be verified, or it can divide the verification according to preset rules, and generate the first asynchronous function and the second asynchronous function for the pins to be verified divided into the same group. It can be set according to the actual situation, and the embodiment of the present invention does not limit this.

[0018] Among them, the above-mentioned first asynchronous function is used to read and write the pin to be verified, and the above-mentioned second asynchronous function is used to obtain the output signal of the pin to be verified and output it. Among them, the above-mentioned first asynchronous function and the second asynchronous function are both asynchronous functions. Specifically, the asynchronous function is a concept in software, which allows multiple functions to be executed concurrently. When using asynchronous functions to control hardware, an asynchronous function can wait for the trigger of the clock and also operate the designed pin at the same time. Specifically, the above-mentioned first asynchronous function and the second asynchronous function can be multiple, for example: a first asynchronous function can be generated for reading the pin to be verified, and accordingly, another first asynchronous function can be used to write the pin to be verified.

[0019] Specifically, the above-mentioned asynchronous function can be implemented by a software programming language (for example, Python), and the above-mentioned first asynchronous function can be used to read and write the pin to be verified, that is, to write parameters to the pin of the DUT or to read the current state of the pin of the DUT. Specifically, the read and write operations of the pin to be verified can be defined in the first asynchronous function, so that the active drive of the design to be tested can be completed by calling the first asynchronous function during the verification process. Exemplarily, for the read operation of the bus interface of the hardware to be verified, the bus read operation can be defined as an asynchronous function, which is used to complete the bus read, that is, to read the current state of the pin corresponding to the bus. The above-mentioned second asynchronous function can be used to obtain and output the output signal of the pin to be verified. Specifically, the second asynchronous function can output the output signal of the pin to be verified as the function return value. Specifically, during the verification process, the second asynchronous function can be called according to actual needs to obtain and output the output signal of the pin to be verified. Exemplarily, it can be used to monitor the pin to be verified, and the second asynchronous function can be called when the state of the design to be tested changes. If the second asynchronous function returns a valid value, the valid value can be output. Among them, whether the return value is valid can be set according to actual needs. For example, if the return value is empty, it can be confirmed that the return value is invalid. Correspondingly, if the return value is not empty, it can be confirmed that the return value is valid.

[0020] Specifically, the first asynchronous function and the second asynchronous function may be generated by receiving input information from relevant verification personnel, or may be generated by preset function writing rules, which is not limited in this embodiment of the present invention.

[0021] Furthermore, through the above step 101, the hardware behavior of the DUT can be converted into two types of asynchronous functions, and the hardware operation of the pin can be modeled as a concise asynchronous function interface in the software, so that software programmers can more easily start the hardware verification process and can better integrate with software testing technology. These two types of asynchronous functions complete the encapsulation of pin-level data into higher-abstract level data, and the high-abstract level data is passed through parameters and return values.

[0022] Furthermore, the model code can be constructed by generating the first asynchronous function and the second asynchronous function. Specifically, after generating the first asynchronous function and the second asynchronous function, the two can be encapsulated into one class, so that the pin to be verified can be abstracted into a class to obtain the model code, and then the test case can be used to interact with the model code. Among them, the above-mentioned model code can be used to characterize the abstract interaction model of the pin to be verified. Specifically, the output signal of the pin to be verified can be obtained through the above-mentioned first asynchronous function and the second asynchronous function. Accordingly, in the embodiment of the present invention, the output data of the design to be tested can be obtained by calling the first asynchronous function in the model code, so as to facilitate the subsequent inspection and obtain the verification result. Alternatively, the output data of the design to be tested can be obtained by reading the monitoring result of the second asynchronous function, so as to facilitate the subsequent inspection and obtain the verification result.

[0023] Furthermore, after constructing the model code, the pin to be verified can be verified through the model code. Specifically, the model code at this time can be used as an abstract model of the pin to be verified, and the test case does not need to interact with the hardware to be verified, but can directly interact with the model code. Specifically, test cases can be constructed according to the actual verification requirements of the hardware to be verified. Different test cases can be used to perform functional verification on different pins to be verified. For example, a test case can be constructed to verify whether the bus read function is normal, and a test case can be constructed to read the data of the bus interface. Accordingly, the test case can directly call the first asynchronous function corresponding to the bus interface in the model code, so as to obtain the verification result through the return value of the model code.

[0024] In summary, the hardware verification method provided by the embodiment of the present invention generates a first asynchronous function and a second asynchronous function based on the pin to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain the output signal of the pin to be verified and output it; the model code is constructed through the first asynchronous function and the second asynchronous function; the pin to be verified is verified through the model code. In this way, the embodiment of the present invention can model the hardware operation of the pin into a concise asynchronous function interface in the software by generating two types of asynchronous functions for the pin to be verified, so that software programmers can start the hardware verification process more easily and can better combine it with software testing technology. Therefore, by constructing the model code through the first asynchronous function and the second asynchronous function and verifying the pin to be verified through the model code, the verification of hardware behavior can be modeled as software verification, without the need to use hardware description and verification language, and the efficiency of hardware verification can be greatly improved through the asynchronous function in the software.

[0025] Optionally, the operation of generating the first asynchronous function and the second asynchronous function based on the pin to be verified of the hardware to be verified may specifically include: S21. Group the pins to be verified based on the types of the pins to be verified of the hardware to be verified to obtain at least one pin group.

[0026] S22: For any of the pin groups, generate the corresponding first asynchronous function and second asynchronous function for the pins to be verified included in the pin group.

[0027] Among them, the above types can be divided according to the structure and function of the pins, and pins with the same structure and function can be divided into the same pin group. Specifically, the interface identifiers of pins with the same structure are often the same, and the verification of pins with the same function is often the same. Therefore, pins of the same type can use the same first asynchronous function and second asynchronous function without repeated generation.

[0028] Specifically, different types of pins to be verified can be pre-divided according to the functional logic of each pin in the hardware to be verified, and different identifiers can be used to distinguish the types of different pins. On this basis, the pins to be verified with the same identifier can be divided into the same group to obtain a pin group. Specifically, a hardware to be verified often has multiple pins of different types. In some cases, a chip with a simpler structure can have pins of the same type, so at least one pin group can be obtained through the above step S21.

[0029] Furthermore, for each pin group, a corresponding first asynchronous function and a second asynchronous function may be generated for the pins to be verified contained in each pin group. Specifically, a pin group may correspond to one or more first asynchronous functions and second asynchronous functions.

[0030] In an embodiment of the present invention, based on the type of each pin to be verified of the hardware to be verified, the pins to be verified are grouped to obtain at least one pin group; for any of the pin groups, the corresponding first asynchronous function and second asynchronous function are generated for the pins to be verified included in the pin group. In this way, by grouping the pins and generating the first asynchronous function and the second asynchronous function according to the divided pin groups, the pins to be verified in the same pin group can share the first asynchronous function and the second asynchronous function, which reduces the workload to a certain extent and improves the reusability of the generated first asynchronous function and the second asynchronous function.

[0031] Optionally, constructing the model code through the first asynchronous function and the second asynchronous function includes: S31. For any of the pin groups, create a class for the pin group as a class to be verified corresponding to the pin group.

[0032] S32. Use a preset decorator to declare the first asynchronous function and the second asynchronous function corresponding to the pin group, respectively, and use the declared first asynchronous function and the second asynchronous function as the driving function and the monitoring function corresponding to the pin group, respectively.

[0033] S33, adding the driving function and the monitoring function to the class to be verified, and making the class to be verified inherit a preset base class to obtain a model code corresponding to the pin group.

[0034] The above class is used to provide an environment, and the first asynchronous function and the second asynchronous function are encapsulated by the class. Specifically, the above operation of creating a class can be implemented by a class creation instruction (for example: class).

[0035] Among them, the above-mentioned preset decorator can be a pre-set identifiable identifier, and the decorator is used to identify the function so that the function can be identified and called. Specifically, different decorators can be set for the first asynchronous function and the second asynchronous function respectively. For example, in Python, the first asynchronous function can be set to use the decorator @driver_method, and the second asynchronous function can be set to use the decorator @monitor_method. Of course, other decorators can also be set according to actual needs, and the embodiment of the present invention is not limited to this.

[0036] Specifically, using a preset decorator for declaration means using a preset decorator to identify the function so that the function can be identified and called. Further, the declared first asynchronous function and the second asynchronous function can be used as a driving function and a monitoring function corresponding to the pin group.

[0037] Furthermore, a driving function and a monitoring function can be added to the class to be verified, that is, the driving function and the monitoring function can be encapsulated into the class to be verified to achieve function standardization. Among them, the above-mentioned base class may include a pre-set part of the verification code, which can be used to call the driving function and / or the monitoring function in the class to be verified to implement a certain hardware operation. For example, automatic monitoring of the state of the DUT can be implemented in the base class, and the monitoring function can be called when the DUT changes are detected. The monitoring function can obtain the data output by the pin and return it, and can further process the obtained pin data and return it. Accordingly, it can be judged whether the monitoring function has completed the monitoring by judging whether the data returned by the monitoring function is a valid value (for example: a non-null value).

[0038] Furthermore, the class to be verified that inherits the base class can be used as the model code corresponding to the pin group. At this time, the model code is encapsulated as a class, and the class name of the class to be verified can be set according to actual needs. For example, its class name can be Agent.

[0039] In an embodiment of the present invention, for any of the pin groups, a class is created for the pin group as the class to be verified corresponding to the pin group; a preset decorator is used to declare the first asynchronous function and the second asynchronous function corresponding to the pin group, and the declared first asynchronous function and the second asynchronous function are used as the driving function and the monitoring function corresponding to the pin group, respectively; the driving function and the monitoring function are added to the class to be verified, and the class to be verified inherits the preset base class to obtain the model code corresponding to the pin group. In this way, the first asynchronous function and the second asynchronous function can be further encapsulated by the class, and the hardware operation of a group of pins to be verified can be encapsulated into a class, which further improves the standardization of hardware modeling and simplifies the verification environment.

[0040] Optionally, the embodiment of the present invention may further include: S41. When the model code corresponding to the pin group does not exist in the historical model code, execute the operation of creating a class for the pin group as the class to be verified corresponding to the pin group.

[0041] Or, S42, when a model code corresponding to the pin group exists in the historical model code, the historical model code corresponding to the pin group is determined as the model code corresponding to the pin group.

[0042] The above historical model code refers to the previously generated class to be verified. Since the pins of some chip designs may be the same, the corresponding class to be verified may have been generated for some chip designs, and this class to be verified can be reused in the current hardware to be verified. Therefore, the embodiment of the present invention can determine whether there is a model code corresponding to the current pin group in the historical model code, and if so, it can be directly reused.

[0043] Specifically, after executing the above step S33, the pin type identifier can be used to distinguish the model codes corresponding to different pin groups, and add them to the historical model library, so that the embodiment of the present invention can obtain the historical model code from the historical model library, and use the pin type identifier of the current pin group to search from the historical model library. If a historical model code with a consistent identifier is found, it can be directly used as the model code corresponding to the current pin group. If it is not found, that is, the model code corresponding to the pin group does not exist in the historical model code, then the above step S31 operation is executed.

[0044] In the embodiment of the present invention, when the model code corresponding to the pin group does not exist in the historical model code, the operation of creating a class for the pin group as the class to be verified corresponding to the pin group is performed; or when the model code corresponding to the pin group exists in the historical model code, the historical model code corresponding to the pin group is determined as the model code corresponding to the pin group. In this way, the model code can be reused to a certain extent, and the verification efficiency can be further improved.

[0045] Optionally, since the hardware to be verified may include multiple pin groups, and each pin group has corresponding model code, an embodiment of the present invention may set a packaging module (for example: Env) to package the model codes of all pin groups, thereby instantiating all model codes in the packaging module, and the packaging module uniformly manages the model codes of all pin groups.

[0046] Optionally, the operation of verifying the pin to be verified by using the model code may specifically include: S51, encapsulating the model codes corresponding to the pin groups to obtain encapsulation codes.

[0047] S52: Construct a test case by calling the model code.

[0048] S53: Use the test case to drive the package code, and verify the pin to be verified based on the output result of the package code.

[0049] Among them, the above model code includes driving functions, monitoring functions and calling driving functions and monitoring functions for interactive operations on DUT. At this time, the model code can be encapsulated as a whole into encapsulation code, and the instantiation of the class to be verified can be completed through the encapsulation code.

[0050] Furthermore, the above model code can be called to construct test cases, and different test cases are used to implement different verifications of different pins to be verified. Specifically, when constructing test cases, the driver function can be called to read and write the pin to be verified, or the output signal of the pin to be verified can be obtained by reading the return value of the monitoring function.

[0051] Furthermore, the packaged code can be driven by test cases, that is, the packaged code can be stimulated by test cases. The packaged code can then perform corresponding interactive operations on the pins to be verified according to the stimulus and output corresponding execution results. At this time, the verification result can be generated based on the output result of the packaged code.

[0052] Specifically, the verification result can be generated by directly checking the output data in the test case, or a reference model can be pre-set and the correctness of the output result can be checked by comparing it with the reference model. Furthermore, the test points to be verified can be pre-determined, and the test ends when the test case is sufficient to cover all the test points.

[0053] Optionally, the operation of verifying the pin to be verified based on the output result of the packaging code may specifically include: S531. Compare the output result of the packaging code with a preset reference result to generate a verification result of the pin to be verified.

[0054] Specifically, the above reference results can be pre-generated based on hardware that meets the actual requirements and test cases. Accordingly, the output results of the encapsulated code can be compared with the reference results. If the comparison is consistent, a verification result can be generated that the hardware to be verified meets the actual requirements. Correspondingly, if the comparison is inconsistent, a verification result can be generated that the hardware to be verified does not meet the actual requirements.

[0055] Furthermore, the output results corresponding to each test case and the reference results can be compared according to different test cases. Accordingly, in the event of an inconsistent comparison, the verification points at which the hardware to be verified does not meet the requirements can be determined based on the corresponding test cases. This can be set according to actual needs, and the embodiments of the present invention do not limit this.

[0056] It should be noted that chip verification is to verify the functional correctness of the chip using simulation and other methods before the chip is taped out, so as to avoid the introduction of functional errors that lead to tape-out failure. In the functional verification of the chip, it is often necessary to model the operation of the hardware behavior to more conveniently operate the DUT. For example, for the communication bus interface of the DUT, we can define a read operation and a write operation to more conveniently operate the DUT. After the modeling is completed, you only need to interact with these interfaces without having to perform complex clock and pin operations every time.

[0057] In chip verification, modeling specifications are usually completed by the verification framework. Traditional chip verification frameworks mainly include Verification Methodology Manual (VMM), Open Verification Methodology (OVM) and Universal Verification Methodology (UVM), etc. These verification frameworks are all built based on SystemVerilog language. UVM is developed from the first two and is currently widely used in the industry. UVM uses a multi-component structure and transaction-based communication (transaction level modeling, TLM) to model the operation of the DUT as a transaction. Sending a transaction represents an operation on the DUT. In practical applications, traditional hardware verification frameworks face many defects. For example, the existing modeling method makes the platform construction very complicated and lacks the efficient process of modern software testing. It is limited by the development efficiency of the SystemVerilog language.

[0058] Therefore, in recent years, the industry has gradually explored the possibility of using software programming languages ​​to perform chip verification. For example, the Coroutine-based Co-simulation Testbench (cocotb) enables Python to drive hardware design.

[0059] However, the current hardware modeling method is not applicable to the software field. There are problems such as the construction method does not conform to the software habits, the environment construction becomes very complicated and affects the efficiency, and it cannot be well combined with software testing technology.

[0060] The embodiment of the present invention models the complex hardware operations of the design pins and clocks into a concise asynchronous function interface in the software, so that software programmers can more easily start the hardware verification process and can better combine it with software testing technology.

[0061] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0062] Figure 2 FIG. 1 is a schematic diagram of a hardware verification device according to an embodiment of the present invention. Figure 2 As shown, the device 20 may include: A generating module 201 is used to generate a first asynchronous function and a second asynchronous function based on a pin to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain and output an output signal of the pin to be verified; A construction module 202, configured to construct a model code through the first asynchronous function and the second asynchronous function; The verification module 203 is used to verify the pin to be verified through the model code.

[0063] Optionally, the generation module includes: A grouping submodule, configured to group the pins to be verified based on the types of the pins to be verified of the hardware to be verified, to obtain at least one pin group; The generating submodule is used to generate, for any of the pin groups, the corresponding first asynchronous function and second asynchronous function for the pins to be verified contained in the pin group.

[0064] Optionally, the above building blocks include: A submodule is created, which is used to create a class for any of the pin groups as a class to be verified corresponding to the pin group; A declaration submodule, used for respectively declaring the first asynchronous function and the second asynchronous function corresponding to the pin group by using a preset decorator, and using the declared first asynchronous function and the second asynchronous function as the driving function and the monitoring function corresponding to the pin group respectively; An adding submodule is used to add the driving function and the monitoring function in the class to be verified, and make the class to be verified inherit a preset base class to obtain the model code corresponding to the pin group.

[0065] Optionally, the device further comprises: An execution module, configured to execute the operation of creating a class for the pin group as a class to be verified corresponding to the pin group when the model code corresponding to the pin group does not exist in the historical model code; Or, a determination submodule is used to determine the historical model code corresponding to the pin group as the model code corresponding to the pin group when the model code corresponding to the pin group exists in the historical model code.

[0066] Optionally, the verification module includes: A packaging submodule, used for packaging the model codes corresponding to each of the pin groups to obtain packaging codes; A calling submodule, used to build a test case by calling the model code; The driving submodule is used to drive the package code using the test case and verify the pin to be verified based on the output result of the package code.

[0067] Optionally, the driving submodule is specifically used for: The output result of the packaging code is compared with a preset reference result to generate a verification result of the pin to be verified.

[0068] In summary, the hardware verification device provided by the embodiment of the present invention generates a first asynchronous function and a second asynchronous function based on the pin to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain the output signal of the pin to be verified and output it; the model code is constructed by the first asynchronous function and the second asynchronous function; the pin to be verified is verified by the model code. In this way, by generating two types of asynchronous functions for the pin to be verified, the hardware operation of the pin can be modeled as a concise asynchronous function interface in the software, so that software programmers can start the hardware verification process more easily and can better combine it with software testing technology. Therefore, by constructing the model code through the first asynchronous function and the second asynchronous function and verifying the pin to be verified through the model code, the verification of hardware behavior can be modeled as software verification, without the need to use hardware description and verification language, and the efficiency of hardware verification can be greatly improved through the asynchronous function in the software.

[0069] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0070] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0071] Regarding the hardware verification device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0072] An embodiment of the present invention further provides an electronic device, comprising: a processor and a memory for storing instructions executable by the processor, wherein the processor is configured to execute the above-mentioned hardware verification method.

[0073] Reference Figure 3 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 3As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the hardware verification method of the aforementioned embodiment.

[0074] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0075] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmble Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0076] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0077] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable ReadOnly), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0078] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The hardware verification method shown.

[0079] The present invention also provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute Figure 1 The hardware verification method shown.

[0080] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned hardware verification method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0081] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0082] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0083] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0084] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0085] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0086] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0087] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0088] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0089] It should be noted that the various data-related processes in the embodiments of the present application are all carried out in compliance with the corresponding data protection laws and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

[0090] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0091] The above is a detailed introduction to a hardware verification method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A hardware verification method, characterized in that: The method comprises: Based on the pin to be verified of the hardware to be verified, a first asynchronous function and a second asynchronous function are generated; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain and output the output signal of the pin to be verified; Constructing a model code through the first asynchronous function and the second asynchronous function; The pin to be verified is verified by using the model code.

2. The method according to claim 1, characterized in that The generating of the first asynchronous function and the second asynchronous function based on the pin to be verified of the hardware to be verified includes: Based on the type of each pin to be verified of the hardware to be verified, grouping the pins to be verified to obtain at least one pin group; For any of the pin groups, the first asynchronous function and the second asynchronous function are generated corresponding to the pins to be verified included in the pin group.

3. The method according to claim 2, characterized in that The constructing of the model code through the first asynchronous function and the second asynchronous function includes: For any of the pin groups, create a class for the pin group as a class to be verified corresponding to the pin group; A preset decorator is used to declare the first asynchronous function and the second asynchronous function corresponding to the pin group, and the declared first asynchronous function and the second asynchronous function are used as the driving function and the monitoring function corresponding to the pin group, respectively; The driving function and the monitoring function are added to the class to be verified, and the class to be verified is made to inherit a preset base class to obtain a model code corresponding to the pin group.

4. The method according to claim 3, characterized in that The method further comprises: In the case that the model code corresponding to the pin group does not exist in the historical model code, executing the operation of creating a class for the pin group as the class to be verified corresponding to the pin group; Or, in a case where a model code corresponding to the pin group exists in the historical model code, the historical model code corresponding to the pin group is determined as the model code corresponding to the pin group.

5. The method according to claim 3, characterized in that: The verifying the pin to be verified by using the model code includes: Encapsulating the model code corresponding to each of the pin groups to obtain a packaged code; Constructing a test case by calling the model code; The package code is driven by the test case, and the pin to be verified is verified based on the output result of the package code.

6. The method according to claim 5, characterized in that The verifying the pin to be verified based on the output result of the packaging code includes: The output result of the packaging code is compared with a preset reference result to generate a verification result of the pin to be verified.

7. A hardware verification device, characterized in that: The device comprises: A generation module, used to generate a first asynchronous function and a second asynchronous function based on a pin to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pin to be verified, and the second asynchronous function is used to obtain and output an output signal of the pin to be verified; A construction module, used to construct a model code through the first asynchronous function and the second asynchronous function; A verification module is used to verify the pin to be verified through the model code.

8. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-6 when executing a program stored in a memory.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer program, characterized in that When the computer program is executed by a computer, the method according to any one of claims 1 to 6 is implemented.

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