Hardware Verification Method, Device, Electronic Device and Readable Storage Medium

Abstract

An embodiment of the present invention provides a hardware verification method, apparatus, electronic device, and readable storage medium. The method includes: generating a first asynchronous function and a second asynchronous function based on pins to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pins to be verified, and the second asynchronous function is used to obtain the output signals of the pins to be verified and output them; constructing model code through the first asynchronous function and the second asynchronous function; verifying the pins to be verified through the model code. In this way, in the embodiment of the present invention, by generating two types of asynchronous functions for the pins to be verified, the hardware operations of the pins can be modeled as simple asynchronous function interfaces in software, enabling software programmers to more easily start the hardware verification process and better integrate with software testing technologies. The verification of hardware behavior can be modeled as software verification, without the need to use hardware description and verification languages, and the efficiency of hardware verification can be improved through asynchronous functions in software.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a hardware verification method, apparatus, electronic device, and readable storage medium. Background Art

[0002] With the development of computer technology, various chips have more and more functions. In order to ensure the normal operation of the chips, it is often necessary to verify the functional correctness of the design under test (DUT) before chip tape-out.

[0003] In the functional verification of chips, it is usually necessary to model the hardware behavior. Currently, it is often implemented through the hardware description and verification language (SystemVerilog, SV). However, the SV language has relatively high professional requirements for verification personnel, resulting in relatively low verification efficiency. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a hardware verification method, apparatus, electronic device, and readable storage medium to solve the problem of relatively low verification efficiency. The specific technical solutions are as follows:

[0005] In the first aspect of the present invention, a hardware verification method is first provided. The method includes:

[0006] Generating a first asynchronous function and a second asynchronous function based on the pins to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pins to be verified, and the second asynchronous function is used to obtain the output signals of the pins to be verified and output them;

[0007] Constructing model code through the first asynchronous function and the second asynchronous function;

[0008] Verifying the pins to be verified through the model code.

[0009] In the second aspect of the present invention, a hardware verification apparatus is further provided. The apparatus includes:

[0010] A generating module, configured to generate a first asynchronous function and a second asynchronous function based on the pins to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pins to be verified, and the second asynchronous function is used to obtain the output signals of the pins to be verified and output them;

[0011] A constructing module, configured to construct model code through the first asynchronous function and the second asynchronous function;

[0012] A verifying module, configured to verify the pins to be verified through the model code.

[0013] In a third aspect of the implementation of the present invention, an electronic device is further provided, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus;

[0014] The memory is used to store a computer program;

[0015] The processor is used to implement the method described in the first aspect above when executing the program stored on the memory.

[0016] In a fourth aspect of the implementation of the present invention, a computer-readable storage medium is further provided. Instructions are stored in the computer-readable storage medium. When it runs on a computer, the computer is made to execute the method described in the first aspect above.

[0017] In a fifth aspect of the implementation of the present invention, a computer program product containing instructions is further provided. When it runs on a computer, the computer is made to execute the method described in the first aspect above.

[0018] The hardware verification method provided by the embodiments of the present invention generates a first asynchronous function and a second asynchronous function based on the pins to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pins to be verified, and the second asynchronous function is used to obtain the output signal of the pins to be verified and output it; a model code is constructed through the first asynchronous function and the second asynchronous function; the pins to be verified are verified through the model code. In this way, the embodiments of the present invention can model the hardware operations of the pins as simple asynchronous function interfaces in software by generating two types of asynchronous functions for the pins to be verified, enabling software programmers to more easily start the hardware verification process and better combine with software testing technologies. Therefore, by constructing a model code through the first asynchronous function and the second asynchronous function and verifying the pins to be verified through the model code, the verification of hardware behavior can be modeled as software verification, without using hardware description and verification languages, and the efficiency of hardware verification can be greatly improved through asynchronous functions in software. Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art.

[0020] Figure 1 It is a flowchart of the steps of a hardware verification method in an embodiment of the present invention;

[0021] Figure 2 It is a schematic structural diagram of a hardware verification device in an embodiment of the present invention;

[0022] Figure 3Schematic diagram of an electronic device in an embodiment of the present invention. Detailed implementation manners

[0023] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0024] The terms "first", "second", etc. in the description and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention can be implemented in an order different from those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the description and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In the embodiments of the present invention, the term "plurality" refers to two or more, and other quantifiers are similar.

[0025] Figure 1 Steps flowchart of a hardware verification method in an embodiment of the present invention, as Figure 1 shown, the method includes:

[0026] Step 101: Generate a first asynchronous function and a second asynchronous function based on the pins to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pins to be verified, and the second asynchronous function is used to obtain the output signal of the pins to be verified and output it.

[0027] Step 102: Construct model code through the first asynchronous function and the second asynchronous function.

[0028] Step 103: Verify the pins to be verified through the model code.

[0029] For the above steps 101-103, the embodiments of the present invention can be applied to any computer device, and the embodiments of the present invention do not limit this. Among them, the above hardware to be verified can be a chip design to be verified, that is, the DUT. The chip design that has not been taped out can be determined as the above hardware to be verified according to actual needs, and the embodiments of the present invention do not limit this. Correspondingly, the above pins to be verified refer to the design pins of the DUT. A DUT usually has multiple pins, and different pins are used to receive different signals and implement different functions. The embodiments of the present invention can generate different first asynchronous functions and second asynchronous functions for different pins to be verified respectively, or can divide the pins to be verified according to a preset rule, and generate a first asynchronous function and a second asynchronous function for the pins to be verified grouped into the same group. It can be set according to the actual situation, and the embodiments of the present invention do not limit this.

[0030] Among them, the above first asynchronous function is used to read and write the pins to be verified, and the above second asynchronous function is used to obtain and output the output signals of the pins to be verified. Among them, the above first asynchronous function and second asynchronous function are both asynchronous functions. Specifically, an asynchronous function is a concept in software that allows multiple functions to be executed concurrently. When using an asynchronous function to control hardware, a clock trigger can be waited for within an asynchronous function, and at the same time, operations can be performed on the design pins. Specifically, there can be multiple above first asynchronous functions and second asynchronous functions. For example: a first asynchronous function can be generated to read the pins to be verified, and correspondingly, another first asynchronous function can be used to write the pins to be verified.

[0031] Specifically, the above asynchronous function can be implemented by a software programming language (e.g., Python). The above first asynchronous function can be used to read and write the pins to be verified, that is, write parameters to the pins of the DUT or read the current status of the pins of the DUT. Specifically, the read and write operations on the pins to be verified can be defined in the first asynchronous function, so that the active driving of the design under test can be completed by calling the first asynchronous function during the verification process. Exemplarily, for the read operation of the bus interface of the hardware to be verified, the bus read operation can be defined as an asynchronous function, which is used to complete the bus read, that is, read the current status of the pins corresponding to the bus. The above second asynchronous function can be used to obtain and output the output signal of the pin to be verified. Specifically, the second asynchronous function can output the output signal of the pin to be verified as the function return value. Specifically, during the verification process, the second asynchronous function can be called according to actual needs to obtain and output the output signal of the pin to be verified. Exemplarily, it can be used to monitor the pins to be verified. The second asynchronous function can be called when the state of the design under test changes. If the second asynchronous function returns a valid value, the valid value can be output. Among them, whether the return value is valid can be set by itself according to actual needs. For example, if the return value is empty, it can be confirmed that the return value is invalid. Correspondingly, if the return value is non-empty, it can be confirmed that the return value is valid.

[0032] Specifically, the above first asynchronous function and second asynchronous function can be generated by receiving the input information of relevant verification personnel, or can also be generated by preset function writing rules. The embodiments of the present invention do not limit this.

[0033] Furthermore, through the above step 101, the hardware behavior of the DUT can be converted into two types of asynchronous functions, and the hardware operations of the pins are modeled as simple asynchronous function interfaces in software, enabling software programmers to more easily start the hardware verification process and better combine with software testing technologies. These two types of asynchronous functions complete the encapsulation of pin-level data into data at a higher abstraction level, and the data at the higher abstraction level is passed through parameters and return values.

[0034] Furthermore, the model code can be constructed by means of the generated first asynchronous function and second asynchronous function. Specifically, after the first asynchronous function and the second asynchronous function are generated, they can be encapsulated. The two functions are encapsulated into a class, so that the pins to be verified can be abstracted into a class, and the model code can be obtained. Subsequently, test cases can be used to interact with the model code. Among them, the above-mentioned model code can be used to represent the abstract interaction model of the pins to be verified. Specifically, the output signals of the pins to be verified can be obtained through both the above-mentioned first asynchronous function and the second asynchronous function. Correspondingly, in the embodiment of the present invention, the output data of the design under test can be obtained by calling the first asynchronous function in the model code, which is convenient for subsequent inspection to obtain the verification result. Alternatively, the output data of the design under test can also be obtained by reading the monitoring result of the second asynchronous function, which is convenient for subsequent inspection to obtain the verification result.

[0035] Furthermore, after the model code is constructed, the pins to be verified can be verified by means of the model code. Specifically, the model code at this time can be used as the abstract model of the pins to be verified. The test cases do not need to interact with the hardware to be verified, but can directly interact with the model code. Specifically, test cases can be constructed according to the actual verification requirements of the hardware to be verified. Different test cases can be used to perform functional verification on different pins to be verified. For example, a test case can be constructed to verify whether the bus read function is normal, and a test case can be constructed to read the data of the bus interface. Correspondingly, the test case can directly call the first asynchronous function corresponding to the bus interface in the model code, so as to obtain the verification result through the return value of the model code.

[0036] In summary, for the hardware verification method provided by the embodiment of the present invention, based on the pins to be verified of the hardware to be verified, a first asynchronous function and a second asynchronous function are generated; the first asynchronous function is used to read and write the pins to be verified, and the second asynchronous function is used to obtain the output signals of the pins to be verified and output them; the model code is constructed by means of the first asynchronous function and the second asynchronous function; the pins to be verified are verified by means of the model code. In this way, in the embodiment of the present invention, by generating two types of asynchronous functions for the pins to be verified, the hardware operations of the pins can be modeled as simple asynchronous function interfaces in software, enabling software programmers to more easily start the hardware verification process and better combine with software testing technologies. Therefore, by constructing the model code through the first asynchronous function and the second asynchronous function and verifying the pins to be verified by means of the model code, the verification of hardware behavior can be modeled as software verification, without using hardware description and verification languages, and the efficiency of hardware verification can be greatly improved through asynchronous functions in software.

[0037] Optionally, the operations of generating the first asynchronous function and the second asynchronous function based on the pins to be verified of the hardware to be verified may specifically include, in embodiments of the present invention:

[0038] S21. Group the pins to be verified based on the types of the pins to be verified of the hardware to be verified, to obtain at least one pin group.

[0039] S22. For any one of the pin groups, generate the corresponding first asynchronous function and second asynchronous function for the pins to be verified included in the pin group.

[0040] Among them, the above types can be divided according to the structure and function of the pins. Pins with the same structure and the same function can be divided into the same pin group. Specifically, pins with the same structure often have the same interface identifier, and the verification for pins with the same function is often the same. Therefore, pins of the same type can use the same first asynchronous function and second asynchronous function without repeated generation.

[0041] Specifically, the types of different pins to be verified can be pre-divided according to the functional logic of the pins in the hardware to be verified, and different identifiers are used to distinguish the types of different pins. On this basis, the pins to be verified with the same identifier can be divided into the same group to obtain a pin group. Specifically, a hardware to be verified often has multiple pins of different types. In some cases, a chip with a relatively simple structure can have pins of the same type, so at least one pin group can be obtained through the above step S21.

[0042] Further, for each pin group, the corresponding first asynchronous function and second asynchronous function can be generated for the pins to be verified included in each pin group. Specifically, one pin group can correspond to one or more first asynchronous functions and second asynchronous functions.

[0043] In embodiments of the present invention, the pins to be verified are grouped based on the types of the pins to be verified of the hardware to be verified, to obtain at least one pin group; for any one of the pin groups, the corresponding first asynchronous function and second asynchronous function are generated for the pins to be verified included in the pin group. In this way, by grouping the pins and generating the first asynchronous function and the second asynchronous function according to the divided pin groups, the pins to be verified in the same pin group can share the first asynchronous function and the second asynchronous function, which reduces the workload to a certain extent and improves the reusability of the generated first asynchronous function and second asynchronous function.

[0044] Optionally, the construction of the model code through the first asynchronous function and the second asynchronous function includes:

[0045] S31. For any of the said pin groups, create a class for the pin group as the class to be verified corresponding to the pin group.

[0046] S32. Use a preset decorator to declare the first asynchronous function and the second asynchronous function corresponding to the pin group respectively, and use the declared first asynchronous function and second asynchronous function as the driving function and the monitoring function corresponding to the pin group respectively.

[0047] S33. Add the driving function and the monitoring function to the class to be verified, and make the class to be verified inherit a preset base class to obtain the model code corresponding to the pin group.

[0048] Among them, the above class is used to provide an environment to encapsulate the first asynchronous function and the second asynchronous function through the class. Specifically, the operation of creating the class can be implemented through a class creation instruction (for example: class).

[0049] Among them, the above preset decorator can be a preset recognizable identifier. The decorator is used to identify the function so that the function can be recognized and called. Specifically, different decorators can be set for the first asynchronous function and the second asynchronous function respectively. For example, in Python, the first asynchronous function can be set with the decorator @driver_method, and the second asynchronous function can be set with the decorator @monitor_method. Of course, other decorators can also be set according to actual needs, and the embodiments of the present invention do not limit this.

[0050] Specifically, using the preset decorator for declaration means using the preset decorator to identify the function so that the function can be recognized and called. Further, the declared first asynchronous function and second asynchronous function can be used as the driving function and the monitoring function corresponding to the pin group.

[0051] Further, the driving function and the monitoring function can be added to the class to be verified, that is, the driving function and the monitoring function are encapsulated into the class to be verified to realize the standardization of the function. Among them, the above base class can include some preset verification codes, which can be used to call the driving function and / or the monitoring function in the class to be verified to implement a certain hardware operation. For example, the automatic monitoring of the state of the DUT can be implemented in the base class, and when the change of the DUT is detected, the monitoring function is called. The monitoring function can obtain the data output by the pin and return it, and can further process the obtained pin data and then return it. Correspondingly, it can be judged whether the monitoring function has completed the monitoring by judging whether the data returned by the monitoring function is a valid value (for example: a non-empty value).

[0052] Further, the class to be verified after inheriting the base class can be used as the model code corresponding to the pin group. At this time, the model code is encapsulated as a class, and the class name of the class to be verified can be set according to actual requirements. For example, its class name can be Agent.

[0053] In the embodiment of the present invention, for any one of the pin groups, a class is created for the pin group as the class to be verified corresponding to the pin group; the first asynchronous function and the second asynchronous function corresponding to the pin group are respectively declared by using a preset decorator, and the declared first asynchronous function and second asynchronous function are respectively used as the driving function and the monitoring function corresponding to the pin group; the driving function and the monitoring function are added to the class to be verified, and the class to be verified inherits a preset base class to obtain the model code corresponding to the pin group. In this way, the first asynchronous function and the second asynchronous function can be further encapsulated by the class, and the hardware operations on a group of pins to be verified are encapsulated as a class, further improving the standardization of hardware modeling and simplifying the verification environment.

[0054] Optionally, the embodiment of the present invention may specifically further include:

[0055] S41. In the case that the model code corresponding to the pin group does not exist in the historical model code, perform the operation of creating a class for the pin group as the class to be verified corresponding to the pin group.

[0056] Or, S42. In the case that the model code corresponding to the pin group exists in the historical model code, determine the historical model code corresponding to the pin group as the model code corresponding to the pin group.

[0057] Among them, the above historical model code refers to the class to be verified generated before. Since the pins of some chip designs may be the same, corresponding classes to be verified may have been generated for some chip designs, and this class to be verified can be reused in the current hardware to be verified. Therefore, the embodiment of the present invention can determine whether the model code corresponding to the current pin group exists in the historical model code, and if it exists, it can be directly reused.

[0058] Specifically, after performing the above step S33, the model codes corresponding to different pin groups can be distinguished by using the identifier of the pin type and added to the historical model library. Thus, the embodiment of the present invention can obtain the historical model code from the historical model library and search in the historical model library by using the identifier of the pin type of the current pin group. If a historical model code with the same identifier is found, it can be directly used as the model code corresponding to the current pin group. If not, that is, the model code corresponding to the pin group does not exist in the historical model code, then perform the operation of the above step S31.

[0059] In the embodiments of the present invention, when there is no model code corresponding to the pin group in the historical model code, the operation of creating a class for the pin group as the class to be verified corresponding to the pin group is executed; or, when there is model code corresponding to the pin group in the historical model code, the historical model code corresponding to the pin group is determined as the model code corresponding to the pin group. In this way, the reuse of model code can be realized to a certain extent, and the verification efficiency can be further improved.

[0060] Optionally, since the hardware to be verified may include multiple pin groups, and there is corresponding model code for each pin group, the embodiments of the present invention can set a packaging module (for example: Env) to package the model codes of all pin groups, so that all model codes are instantiated in the packaging module, and the packaging module uniformly manages the model codes of all pin groups.

[0061] Optionally, for the operation of verifying the pins to be verified through the model code, the embodiments of the present invention may specifically include:

[0062] S51. Package the model codes corresponding to each pin group to obtain packaged codes.

[0063] S52. Construct test cases by calling the model code.

[0064] S53. Drive the packaged codes with the test cases, and verify the pins to be verified based on the output results of the packaged codes.

[0065] Among them, the above model code includes a driving function, a monitoring function, and interaction operations on the DUT by calling the driving function and the monitoring function. At this time, the model code can be encapsulated as a packaged code, and the class to be verified can be instantiated through the packaged code.

[0066] Furthermore, the above model code can be called to construct test cases, and different test cases are used to implement different verifications for different pins to be verified. Specifically, when constructing test cases, the driving function can be called to read and write the pins to be verified, or the output signal of the pins to be verified can be obtained by reading the return value of the monitoring function.

[0067] Furthermore, the packaged codes can be driven by test cases, that is, the test cases are used to apply incentives to the packaged codes. Then, the packaged codes can perform corresponding interaction operations on the pins to be verified according to the incentives and output corresponding execution results. At this time, verification results can be generated based on the output results of the packaged codes.

[0068] Specifically, the verification result can be generated by directly verifying the output data in the test case, or a reference model can be preset and the correctness of the output result can be verified by comparing it with the reference model. Further, the test points to be verified can be determined in advance, and when the test case is sufficient to cover all test points, the test ends.

[0069] Optionally, the operation of verifying the pins to be verified based on the output result of the encapsulation code in the embodiments of the present invention may specifically include:

[0070] S531. Compare the output result of the encapsulation code with a preset reference result to generate the verification result of the pins to be verified.

[0071] Specifically, the above reference result can be pre-generated based on the hardware and test cases that meet the actual requirements. Correspondingly, the output result of the encapsulation code can be compared with the reference result. If the comparison is consistent, the verification result can be generated that the hardware to be verified meets the actual requirements. Correspondingly, if the comparison is inconsistent, the verification result can be generated that the hardware to be verified does not meet the actual requirements.

[0072] Further, according to different test cases, the output results and reference results corresponding to each test case can be compared. Correspondingly, in the case of inconsistent comparison, the verification points where the hardware to be verified does not meet the requirements can be determined based on the corresponding test cases, which can be set according to actual needs, and the embodiments of the present invention do not limit this.

[0073] It should be noted that chip verification is to verify the functional correctness of the chip by using methods such as simulation before chip tape-out to avoid introducing functional errors that may lead to tape-out failure. In the functional verification of the chip, it is often necessary to model the operations of the hardware behavior to more conveniently operate the DUT. For example, for the communication bus interface of the DUT, we can define a read operation and a write operation to more conveniently operate the DUT. After the modeling is completed, only interaction with these interfaces is required, without the need for complex clock and pin operations every time.

[0074] In chip verification, the specification of modeling is usually completed by a verification framework. Traditional chip verification frameworks mainly include the Verification Methodology Manual (VMM), the Open Verification Methodology (OVM), and the Universal Verification Methodology (UVM), etc. These verification frameworks are all built based on the SystemVerilog language. UVM is developed from the former two and is currently widely used in the industry. UVM uses a multi-component structure and transaction level modeling (TLM) to model the operations of the DUT as transactions. Sending a transaction represents an operation on the DUT. In practical applications, traditional hardware verification frameworks face many defects, such as the existing modeling methods making the platform construction very complex, lacking the efficient processes of modern software testing, and being restricted by the development efficiency of the SystemVerilog language, etc.

[0075] Therefore, in recent years, the industry has been gradually exploring the possibility of using software programming languages for chip verification. For example, the Coroutine-based Co-simulation Testbench (cocotb) enables Python to drive hardware designs.

[0076] However, the current hardware modeling methods are not applicable to the software field, and there are problems such as the construction method not conforming to software habits, the environment construction becoming very complex and affecting efficiency, and not being able to combine well with software testing technologies.

[0077] In the embodiment of the present invention, the complex hardware operations of designing pins and clocks are modeled as simple asynchronous function interfaces in software, enabling software programmers to more easily start the hardware verification process and be better combined with software testing technologies.

[0078] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequences, because according to the embodiments of the present invention, certain steps can be in other sequences or carried out simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0079] Figure 2 It is a schematic structural diagram of a hardware verification device in the embodiment of the present invention, asFigure 2 As shown, the device 20 may include:

[0080] A generation module 201, configured to generate a first asynchronous function and a second asynchronous function based on the pins to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pins to be verified, and the second asynchronous function is used to obtain and output the output signals of the pins to be verified;

[0081] A construction module 202, configured to construct model code through the first asynchronous function and the second asynchronous function;

[0082] A verification module 203, configured to verify the pins to be verified through the model code.

[0083] Optionally, the above-mentioned generation module includes:

[0084] A grouping sub-module, configured to group the pins to be verified based on the types of the pins to be verified of the hardware to be verified, to obtain at least one pin group;

[0085] A generation sub-module, configured to generate the corresponding first asynchronous function and second asynchronous function for the pins to be verified included in any one of the pin groups.

[0086] Optionally, the above-mentioned construction module includes:

[0087] A creation sub-module, configured to create a class for any one of the pin groups as the class to be verified corresponding to the pin group;

[0088] A declaration sub-module, configured to respectively declare the first asynchronous function and the second asynchronous function corresponding to the pin group by using a preset decorator, and respectively use the declared first asynchronous function and second asynchronous function as the driving function and the monitoring function corresponding to the pin group;

[0089] An addition sub-module, configured to add the driving function and the monitoring function to the class to be verified, and enable the class to be verified to inherit a preset base class, to obtain the model code corresponding to the pin group.

[0090] Optionally, the device further includes:

[0091] An execution module, configured to perform the operation of creating a class for the pin group as the class to be verified corresponding to the pin group when the model code corresponding to the pin group does not exist in the historical model code;

[0092] Or, a determination sub-module, configured to determine the historical model code corresponding to the pin group as the model code corresponding to the pin group when the model code corresponding to the pin group exists in the historical model code.

[0093] Optionally, the verification module includes:

[0094] An encapsulation sub-module for encapsulating the model codes corresponding to each of the pin groups to obtain encapsulated codes;

[0095] An invocation sub-module for constructing test cases by invoking the model codes;

[0096] A driving sub-module for driving the encapsulated codes by using the test cases and verifying the pins to be verified based on the output results of the encapsulated codes.

[0097] Optionally, the driving sub-module is specifically configured to:

[0098] Compare the output result of the encapsulated code with a preset reference result to generate a verification result for the pins to be verified.

[0099] In summary, the hardware verification device provided by the embodiments of the present invention generates a first asynchronous function and a second asynchronous function based on the pins to be verified of the hardware to be verified; the first asynchronous function is used to read and write the pins to be verified, and the second asynchronous function is used to obtain and output the output signals of the pins to be verified; model codes are constructed through the first asynchronous function and the second asynchronous function; and the pins to be verified are verified through the model codes. In this way, by generating two types of asynchronous functions for the pins to be verified, the hardware operations of the pins can be modeled as simple asynchronous function interfaces in software, enabling software programmers to more easily start the hardware verification process and better combine with software testing technologies. Therefore, by constructing model codes through the first asynchronous function and the second asynchronous function and verifying the pins to be verified through the model codes, the verification of hardware behaviors can be modeled as software verification, without using hardware description and verification languages, and the efficiency of hardware verification can be greatly improved through asynchronous functions in software.

[0100] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference can be made to the partial descriptions of the method embodiments.

[0101] The embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other.

[0102] Regarding the hardware verification device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0103] An embodiment of the present invention further provides an electronic device, including: a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the above-mentioned hardware verification method.

[0104] Referring to Figure 3 , it is a schematic structural diagram of the electronic device provided by the embodiment of the present invention. As Figure 3 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete mutual communication through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the hardware verification method of the foregoing embodiment.

[0105] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0106] The processor may be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), an FPGA (Field Programmble Gate Array, field programmable gate array), or other editable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination for implementing computing functions, such as a combination including one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0107] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture, extended industry standard architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 3 only one line is shown in

[0108] The memory may be a ROM (Read Only Memory), or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory), or other types of dynamic storage devices that can store information and instructions. It may also be an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk, optical data storage device, etc.

[0109] An embodiment of the present invention also provides a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is enabled to execute Figure 1 the hardware verification method shown.

[0110] An embodiment of the present invention also provides a computer program product containing instructions. When it runs on a computer, the computer is enabled to execute Figure 1 the hardware verification method shown.

[0111] An embodiment of the present application also provides a chip. The chip includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement each process of the above-mentioned hardware verification method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0112] It should be understood that the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, system chip, chip system, or system-on-a-chip, etc.

[0113] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0114] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, apparatus, or computer program product. Therefore, the embodiments of the present invention can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

[0115] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing terminal device generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0116] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a predictive manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable terminal device provide for implementing the steps in the process Figure 1 one process or multiple processes and / or blocks Figure 1 steps for the functions specified in one block or multiple blocks.

[0118] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0119] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. The key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0120] It should be noted that in the embodiments of this application, the processes of obtaining various data are all carried out on the premise of complying with the corresponding data protection regulations and policies of the country where it is located and obtaining the authorization given by the owner of the corresponding device.

[0121] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or terminal device comprising the element.

[0122] The above has introduced in detail a hardware verification method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A hardware verification method, characterized in that, The method includes: Based on the types of the pins to be verified of the hardware to be verified, grouping the pins to be verified to obtain at least one pin group; For any one of the pin groups, generating a corresponding first asynchronous function and a second asynchronous function for the pins to be verified included in the pin group; the first asynchronous function is used for reading and writing the pins to be verified, and the second asynchronous function is used for obtaining and outputting the output signals of the pins to be verified; the first asynchronous function and the second asynchronous function are implemented through a software programming language; For any one of the pin groups, creating a class for the pin group as the class to be verified corresponding to the pin group; Using a preset decorator to respectively declare the first asynchronous function and the second asynchronous function corresponding to the pin group, and taking the declared first asynchronous function and second asynchronous function as the driving function and the monitoring function corresponding to the pin group respectively; Adding the driving function and the monitoring function to the class to be verified, and making the class to be verified inherit a preset base class to obtain the model code corresponding to the pin group; Verifying the pins to be verified through the model code.

2. The method according to claim 1, characterized in that, The method further includes: In the case where the model code corresponding to the pin group does not exist in the historical model code, performing the operation of creating a class for the pin group as the class to be verified corresponding to the pin group; Or, in the case where the model code corresponding to the pin group exists in the historical model code, determining the historical model code corresponding to the pin group as the model code corresponding to the pin group.

3. The method according to claim 1, characterized in that, The verifying the pins to be verified through the model code includes: Encapsulating the model codes corresponding to the pin groups to obtain an encapsulated code; Constructing a test case by calling the model code; Driving the encapsulated code by using the test case, and verifying the pins to be verified based on the output result of the encapsulated code.

4. The method according to claim 3, wherein The verifying the pins to be verified based on the output result of the encapsulated code includes: Comparing the output result of the encapsulated code with a preset reference result to generate a verification result of the pins to be verified.

5. A hardware verification device, characterized in that, The device includes: A generating module, configured to generate a first asynchronous function and a second asynchronous function based on the pins to be verified of the hardware to be verified; the first asynchronous function is used for reading and writing the pins to be verified, and the second asynchronous function is used for obtaining and outputting the output signals of the pins to be verified; the first asynchronous function and the second asynchronous function are implemented through a software programming language; A constructing module, configured to construct model code through the first asynchronous function and the second asynchronous function; A verifying module, configured to verify the pins to be verified through the model code; The generating module includes: A grouping sub-module, configured to group the pins to be verified based on the types of the pins to be verified of the hardware to be verified to obtain at least one pin group; A generating sub-module, configured to generate the corresponding first asynchronous function and second asynchronous function for the pins to be verified included in any one of the pin groups; The constructing module includes: Create a sub-module to create a class for any of the pin groups as the class to be verified corresponding to the pin group. Declare a sub-module to respectively declare the first asynchronous function and the second asynchronous function corresponding to the pin group using a preset decorator, and use the declared first asynchronous function and second asynchronous function as the driving function and the monitoring function corresponding to the pin group respectively. Add a sub-module to add the driving function and the monitoring function to the class to be verified, and make the class to be verified inherit a preset base class to obtain the model code corresponding to the pin group.

6. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus. The memory is used to store a computer program. The processor is used to implement the method according to any one of claims 1-4 when executing the program stored on the memory.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method according to any one of claims 1-4.

8. A computer program product, characterized in that, When the computer program is run by a computer, it implements the method according to any one of claims 1-4.

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