A testing method, device, electronic device and readable storage medium

Abstract

An embodiment of the present invention provides a test method, device, electronic device, and readable storage medium. The method includes: grouping at least one clock gating to be controlled, and determining the number of control registers in the control chain according to the number of groups of clock gating; inserting the control chain into the scan chain; determining a target clock gating group to be enabled according to the clock signal required in the test circuit; and inputting a scan enable signal to the scan enable end of the scan chain and inputting a test vector to the scan input end of the scan chain according to the target clock gating group, so as to control the target clock gating group through the enable signal output by the demultiplexer. By grouping and controlling each group of clock gating, the embodiment of the present invention reduces the test power consumption and shortens the test time.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a testing method, apparatus, electronic device, and readable storage medium. Background Art

[0002] For large-scale chips, scan testing is an important means to ensure the chip yield. With the continuous progress of manufacturing technology and the development of design technology, the complexity of chips continues to increase, and the chip test power consumption also increases significantly due to the explosively growing test data volume and test time.

[0003] The factors affecting the effectiveness of design for testability are very complex, requiring designers to consider how to effectively perform low-power chip testing during the design phase. The common practice in the industry currently is to add test points in the scan chain and use the test points to enable the test enable terminal of the clock gating. However, this approach will control the full opening of the gating of the entire module, resulting in too high a module switching rate and thus high chip test power consumption. Summary of the Invention

[0004] Embodiments of this application provide a testing method, apparatus, electronic device, and readable storage medium, which can reduce the test power consumption and shorten the chip test time.

[0005] In a first aspect, embodiments of this application disclose a testing method, which includes:

[0006] Group at least one clock gating to be controlled, and determine the number of control registers in the control chain according to the number of groups of the clock gating; the control chain includes at least one control register and a demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to the test enable end of a group of clock gating;

[0007] Insert the control chain into the scan chain; the scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence;

[0008] Determine a target clock gating group to be enabled according to the clock signal required in the test circuit;

[0009] According to the target clock gating group, input a scan enable signal to the scan enable end of the scan chain, and input a test vector to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer.

[0010] Optionally, the determining the number of control registers in the control chain according to the number of groups of the clock gating includes:

[0011] Perform a base-2 logarithm operation on the number of groups to obtain a first operation result;

[0012] Determine the number of control registers in the control chain according to the first operation result.

[0013] Optionally, inputting a scan enable signal to the scan enable terminal of the scan chain includes:

[0014] Input a high-level scan enable signal to the scan enable terminal of the scan chain to set the working mode of the scan chain to the shift mode;

[0015] When the working modes of all scan registers in the scan chain are switched to the shift mode, switch the scan enable signal to a low level to set the working mode of the scan chain to the capture mode.

[0016] Optionally, according to the target clock gating group, inputting a scan enable signal to the scan enable terminal of the scan chain and inputting a test vector to the scan input terminal of the scan chain to control the target clock gating group through the enable signal output by the demultiplexer includes:

[0017] Determine a target test vector according to the target clock gating group;

[0018] Input a low-level scan enable signal to the scan enable terminal of the scan chain, and input the target test vector to the scan input terminal, so as to set the test enable terminal of the target clock gating group to a high level state through the enable signal output by the demultiplexer, and set the test enable terminals of the remaining target clock gating groups in the clock gating to be controlled to a low level state.

[0019] Optionally, the method further includes:

[0020] When the target clock gating group includes all clock gating groups, input a high-level scan enable signal to the scan enable terminal of the scan chain, so as to set the test enable terminals of the target clock gating group to a high level state through the enable signal output by the demultiplexer.

[0021] Optionally, when the working mode of the scan chain is the shift mode, the data in each scan register in the scan chain moves bit by bit; when the working mode of the scan chain is the capture mode, the data in each scan register in the scan chain remains unchanged.

[0022] In a second aspect, an embodiment of the present application discloses a test device, and the device includes:

[0023] At least one clock gating to be controlled;

[0024] A control chain, including an input register, at least one control register, and a demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to a test enable end of a group of clock gating; the control chain and the scan chain are connected in series; the number of the control registers is determined according to the number of groups of the clock gating to be controlled;

[0025] A scan chain, including at least one scan register, and the at least one scan register is connected in series in sequence.

[0026] In a third aspect, an embodiment of the present application discloses an electronic device, which includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the foregoing test method.

[0027] In a fourth aspect, an embodiment of the present application discloses a readable storage medium. When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor can execute the foregoing test method.

[0028] The embodiments of the present application include the following advantages:

[0029] An embodiment of the present invention provides a test method. By grouping at least one clock gating to be controlled, the number of control registers in the control chain is determined according to the number of groups of the clock gating; the control chain includes at least one control register and a demultiplexer; the output end of each control register is respectively connected to an input end of the demultiplexer, and each output end of the demultiplexer is connected to a test enable end of a group of clock gating; the control chain is inserted into the scan chain; the scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence; according to the clock signal required in the test circuit, the target clock gating group to be enabled is determined; according to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer. The embodiments of the present invention can control each group of clock gating by grouping, reduce the test power consumption, and shorten the test time. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0031] Figure 1It is a flowchart of steps of an embodiment of a test method provided by the present invention;

[0032] Figure 2 It is a schematic diagram of a scan chain provided by the present invention;

[0033] Figure 3 It is a structural block diagram of a test device provided by the present invention;

[0034] Figure 4 It is a structural block diagram of an electronic device provided by an example of the present invention. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0036] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention can be implemented in an order different from those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In the embodiments of the present invention, the term "plurality" refers to two or more, and other quantifiers are similar.

[0037] Method embodiment

[0038] Refer to Figure 1 , which shows a flowchart of steps of an embodiment of a test method of the present invention. The test method may include the following steps:

[0039] Step 101, group at least one clock gating to be controlled, and determine the number of control registers in the control chain according to the number of groups of the clock gating; the control chain includes at least one control register and a demultiplexer; the output end of each control register is respectively connected to an input end of the demultiplexer, and each output end of the demultiplexer is connected to the test enable end of a group of clock gating;

[0040] Step 102: Insert the control chain into the scan chain. The scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence.

[0041] Step 103: Determine the target clock gating group to be enabled according to the clock signal required in the test circuit.

[0042] Step 104: According to the target clock gating group, input a scan enable signal to the scan enable terminal of the scan chain, and input a test vector to the scan input terminal of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer.

[0043] The test method provided by the embodiment of the present invention can be applied to fields such as integrated circuit design and manufacturing, communication equipment manufacturing and maintenance, consumer electronics, and automotive electronics. Specifically, it is used to test the chips in various devices such as mobile phones, tablet computers, electronic control units, and industrial robots to ensure the safe operation of various devices.

[0044] Among them, clock gating, also known as gated clock, the structure of clock gating includes a clock input terminal (Clock Input, clk), an enable signal terminal (Enable, en), a test enable terminal, and an output terminal. The output terminal of clock gating is connected to the clock input terminal of the scan register to control whether the scan register receives the clock signal. When grouping the clock gating, all the clock gating to be controlled can be evenly grouped, that is, the number of clock gating in each group after grouping is the same; or it can be not evenly grouped, that is, the number of clock gating in each group after grouping is different. The embodiment of the present invention does not limit the grouping method. According to the number of groups of clock gating, determine the required demultiplexer. The number of output terminals of the demultiplexer needs to be greater than or equal to the number of groups of clock gating. Determine the number of control registers according to the number of selection terminals of the demultiplexer. The number of control registers is equal to the number of selection terminals of the demultiplexer.

[0045] The enable register and the control register are connected in series in sequence to obtain a control chain. The structure of the control register includes a scan input terminal, a clock input terminal, a data input terminal, an output terminal, and a scan enable terminal. The structures of the enable register and the control register are the same. Specifically, the enable register is used as the starting end of the control chain. The output terminal of the enable register is connected to the scan input terminal of a control register. The output terminal of this control register is connected to the scan input terminal of the next control register, and so on for the remaining control registers.

[0046] Such as Figure 2As shown, the scan chain is composed of serially connected scan registers, and each scan register is a register with a scan input terminal and a scan output terminal. The output terminal of the scan register at the end of the scan chain is the scan output terminal (Scan Output) of the entire scan chain. Specifically, the structure of the scan register includes a scan input terminal (Scan Input, SI), a clock input terminal (Clock), a data input terminal (Data Input), an output terminal (Data Output), and a scan enable terminal (ScanEnable, SE). It should be noted that the clock input terminals of the respective scan registers in the scan chain are controlled synchronously in a unified manner, and the scan enable terminals of the respective scan registers are also controlled synchronously in a unified manner. For example, when a high-level scan enable signal is sent to the scan input terminal of the scan chain, the scan enable terminals of the respective scan registers on the scan chain are all in the high-level state simultaneously. The output terminal of each scan register is connected to the scan input terminal of the next scan register.

[0047] Inserting the control chain into the scan chain means connecting the scan input terminal of the enable register at the start end of the control chain to the output terminal of a scan register in the scan chain, and connecting the output terminal of the control register at the end of the control chain to the scan input terminal of another scan register in the scan chain. It is also possible to place the control chain at both ends of the scan chain, that is, using the enable register at the start end of the control chain as the start of the inserted scan chain, or connecting the enable register of the control chain and the scan register at the end of the original scan chain, and using the control register at the end of the control chain as the end of the inserted scan chain. Among them, the clock input terminals of the respective registers in the control chain and the clock input terminals of the respective registers in the scan chain are controlled synchronously in a unified manner; the scan enable terminals of the respective registers in the control chain and the scan enable terminals of the respective registers in the scan chain are also controlled synchronously in a unified manner. It should be noted that the scan chain also receives the Scan_mode signal, and the scan_mode signal is a global test mode switch. When scan_mode is at a high level, the SE signal has the authority to control the scan chain; when scan_mode is at a low level, the SE signal cannot change the working mode of the scan chain. Specifically, when the Scan_mode signal is at a high level, the scan chain is activated and enters the test mode; when the Scan_mode signal is at a low level, the scan chain exits the test mode. In the case of the test mode, when SE is at a high level, the working mode of the scan chain is the shift mode; when SE is at a low level, the working mode of the scan chain is the capture mode (normal mode).

[0048] A demultiplexer (DEMUX) refers to a structure that includes a data input terminal, a selection terminal, and data output terminals. The data input terminal is used to receive an input signal, and the selection terminal is used to determine to which output terminal the input signal will be sent. According to different combinations of the high and low level states of the selection terminal, the input signal will be directed to a corresponding output terminal. If the input signal is high level, an enabling signal of high level is output from one output terminal of the demultiplexer, and the corresponding target clock gating group is turned on, while the remaining output terminals are in the low level state. It should be noted that the input signal can also be low level, in which case all output terminals of the demultiplexer are in the low level state, and the clock gating connected to all output terminals is turned off.

[0049] In an embodiment of the present invention, after inserting a control chain into a scan chain, a scan enabling signal is input to the scan enabling terminal of the scan chain to load test vectors into the scan chain. The test data stored in each control register in the control chain is output to the selection terminal of the demultiplexer, and the test data stored in the enabling register is output to the data input terminal of the demultiplexer; the demultiplexer determines the target output terminal of the enabling signal according to the control signal received by the selection terminal, distributes the input signal received by the data input terminal to the target output terminal, and controls the target clock gating group connected to the target output terminal according to the enabling signal output by the demultiplexer. According to the characteristics of the demultiplexer, each group of clock gating can be controlled separately, achieving the effects of reducing test power consumption and shortening test time.

[0050] It should be noted that there can be multiple scan chains on the same chip. The output terminals of the demultiplexer are connected to the clock gating on the current scan chain or the clock gating on other scan chains. One clock gating can be connected to at least one register; the register is triggered to flip through the clock gating, and then the circuit where the register is located is tested.

[0051] In an embodiment of the present invention, at least one clock gating to be controlled is grouped, and the number of control registers in the control chain is determined according to the number of groups of clock gating; the control chain includes at least one control register and a demultiplexer; the output terminal of each control register is respectively connected to an input terminal of the demultiplexer, and each output terminal of the demultiplexer is connected to the test enabling terminal of a group of clock gating; the control chain is inserted into the scan chain; the scan chain includes at least one scan register, and at least one scan register is connected in series in sequence; according to the clock signal required in the test circuit, the target clock gating group to be turned on is determined; according to the target clock gating group, a scan enabling signal is input to the scan enabling terminal of the scan chain, and a test vector is input to the scan input terminal of the scan chain, so as to control the target clock gating group through the enabling signal output by the demultiplexer.

[0052] Optionally, the determining the number of control registers in the control chain according to the number of groups of clock gating includes:

[0053] Step S11: Perform a base-2 logarithm operation on the number of groups to obtain a first operation result;

[0054] Step S12: Determine the number of control registers in the control chain according to the first operation result.

[0055] Specifically, the relationship between the selection terminal and the output terminal of the demultiplexer is that for n selection terminals, there are corresponding output terminals. Demultiplexers usually include 1-2 demultiplexers, 1-4 demultiplexers, and 1-8 demultiplexers, which respectively refer to a demultiplexer with one data input terminal and 2 output terminals, and this demultiplexer has one selection terminal; a demultiplexer with one data input terminal and 4 output terminals, and this demultiplexer has 2 selection terminals; a demultiplexer with one data input terminal and 8 output terminals, and this demultiplexer has 3 selection terminals.

[0056] It should be noted that the number of output terminals of the demultiplexer needs to be greater than or equal to the number of groups. Perform a base-2 logarithm operation on the number of output terminals of the demultiplexer to obtain a second operation result, and the second operation result is the number of selection terminals of the demultiplexer. The number of selection terminals needs to be greater than or equal to the first operation result, that is, the second operation result needs to be greater than the first operation result. Among them, the output terminal of one control register is connected to one selection terminal of the demultiplexer, that is, the number of selection terminals of the demultiplexer is equal to the number of control registers. Therefore, the number of control registers is greater than or equal to the first operation result. Round up the first operation result to obtain a third operation result, and the number of control registers is greater than or equal to the third operation result.

[0057] For example, when the clock gating is divided into 5 groups, the first operation result obtained by performing a base-2 logarithm operation on 5 is greater than 2 but less than 3. Therefore, a demultiplexer with two selection terminals cannot fully control 5 groups of clock gating, and a demultiplexer with at least 3 selection terminals needs to be used to control 5 groups of clock gating.

[0058] In the embodiment of the present invention, perform a base-2 logarithm operation on the number of groups of clock gating to obtain a first operation result; determine the number of control registers in the control chain according to the first operation result. Control the corresponding clock gating group through the control signal output from the control register to the selection terminal of the demultiplexer.

[0059] Optionally, the inputting the scan enable signal to the scan enable terminal of the scan chain in step 104 includes:

[0060] Step 21: Input a high-level scan enable signal to the scan enable terminal of the scan chain to set the working mode of the scan chain to the shift mode;

[0061] Step 22: When the working modes of all the scan registers in the scan chain are switched to the shift mode, switch the scan enable signal to a low level to set the working mode of the scan chain to the capture mode.

[0062] Specifically, first set the working mode of the scan chain to the shift mode to load the test vectors into each scan register in the scan chain; when all the test vectors are loaded into each scan register in the scan chain, set the working mode of the scan chain to the capture mode.

[0063] Before switching the scan enable signal from a high level to a low level, it is necessary to ensure that the shift operation has been completed, that is, the test vectors have been completely shifted into each register of the scan chain. For example, if the total length of the scan chain after inserting the control chain is N, then N clock cycles are required to complete the shift operation. At the rising edge of the clock signal in the (N + 1)-th clock cycle, switch the scan enable signal to a low level.

[0064] It should be noted that the switching of the scan enable signal needs to be synchronized with the clock signal. For example, if the scan enable signal has been stabilized to a low level before the next rising edge of the clock signal arrives, then the capture mode can be entered in the next clock cycle.

[0065] In the embodiment of the present invention, input a high-level scan enable signal to the scan enable terminal of the scan chain to set the working mode of the scan chain to the shift mode; when the working modes of all the scan registers in the scan chain are switched to the shift mode, switch the scan enable signal to a low level to set the working mode of the scan chain to the capture mode. Control the working mode of the scan chain through the scan enable signal, and switch the working mode of the scan chain to the capture mode at an appropriate time, so as to control the states of each group of clock gating by the values stored in each control register in the capture mode.

[0066] Optionally, step 104 of inputting a scan enable signal to the scan enable terminal of the scan chain according to the target clock gating group and inputting a test vector to the scan input terminal of the scan chain to control the target clock gating group through the enable signal output by the demultiplexer includes:

[0067] Step 31: Determine the target test vector according to the target clock gating group;

[0068] Step 32: Input a low-level scan enable signal to the scan enable terminal of the scan chain and input the target test vector to the scan input terminal, so as to set the test enable terminal of the target clock gating group to a high-level state and set the test enable terminals of the remaining target clock gating groups in the clock gating to be controlled to a low-level state through the enable signal output by the demultiplexer.

[0069] Specifically, according to the circuit to be tested, determine the target clock gating group connected to this part of the circuit. According to the correspondence between the output terminal and the selection terminal of the demultiplexer connected to the target clock gating group, determine the combination of control signals required for the selection terminal of the demultiplexer. According to the combination of control signals, the position of the control chain on the scan chain, and the length of the scan chain after inserting the control chain, determine the test vector. Among them, the length of the test vector is equal to the length of the scan chain after inserting the control chain, and the test vectors loaded into each control register in the control chain can enable the demultiplexer to distribute the signal output by the enable register to the target clock gating group.

[0070] It should be noted that after determining the target test vector according to the target clock gating, first input a high-level scan enable signal to the scan enable terminal of the scan chain to make the scan chain in the shift mode. In the shift mode, load the target test vector completely into the scan chain. Then input a low-level scan enable signal to the scan enable terminal of the scan chain to make the scan chain in the capture mode. In the capture mode, the demultiplexer determines the target output terminal according to the values stored in each control register in the control chain; outputs the input signal sent by the enable register received at the data input terminal from the target output terminal to control the corresponding target clock gating group.

[0071] Exemplarily, as Figure 3 shown, there is a scan chain with 4 scan registers, there are 16 groups of clock gating, a demultiplexer with 16 output ports A0...A15 is used. The demultiplexer with 16 output ports has 4 selection terminals, so 4 control registers and 1 enable register are required. The demultiplexer, 4 control registers and 1 enable register are combined to form a control chain, and the control chain is inserted into the scan chain, and the length of the scan chain becomes 9. When the target clock gating group to be enabled is connected to the A1 port, the values stored in the 4 control registers should be 0010; the value stored in the enable register should be 1; the values in the remaining positions of the test vector can be randomly generated. For example, the test vector can be 101001000. It should be noted that Figure 3 in, the dft_se signal and the scan enable signal input to the scan chain are controlled by the same signal, and the dft_scan_pclk and the clock signal input to the clock input terminal of the scan chain are controlled by the same clock signal. The dft_syn_gt_se signal and the dft_syn_gt_se_sel signal are used to set the dft_syn_gt_se signal and the dft_syn_gt_se_sel signal to high level when a fault occurs to forcibly control the opening of all clock gating. In the test mode of the embodiment of the present invention, the dft_syn_gt_se signal and the dft_syn_gt_se_sel signal are both in the low level state.

[0072] In an embodiment of the present invention, a target test vector is determined according to a target clock gating group; a scan enable signal with a low level is input to the scan enable terminal of the scan chain, and the target test vector is input to the scan input terminal, so that the test enable terminal of the target clock gating group is set to a high level state through the enable signal output by the demultiplexer, and the test enable terminals of the remaining target clock gating groups in the clock gating to be controlled are set to a low level state, so as to achieve grouped control of the clock gating, avoid turning on unnecessary clock gating and unnecessary register flips, thereby reducing test consumption and shortening the test time.

[0073] Optionally, the method further includes:

[0074] When the target clock gating group includes all clock gating groups, a scan enable signal with a high level is input to the scan enable terminal of the scan chain, so that the test enable terminals of the target clock gating group are all set to a high level state through the enable signal output by the demultiplexer.

[0075] When the scan enable signal is at a high level, after the logical AND operation of the scan enable signal and the enable signal output by the demultiplexer, both are at a high level, and each group of clock gating connected to the demultiplexer is turned on.

[0076] In an embodiment of the present invention, when the target clock gating group includes all clock gating groups, a scan enable signal with a high level is input to the scan enable terminal of the scan chain, so that the test enable terminals of the target clock gating group are all set to a high level state through the enable signal output by the demultiplexer, so as to forcibly control all clock gating to be turned on, and by inputting a scan enable signal with a low level to the scan enable terminal of the scan chain, each group of clock gating is controlled in groups according to the input test vector.

[0077] Optionally, when the working mode of the scan chain is the shift mode, the data in each scan register in the scan chain moves bit by bit; when the working mode of the scan chain is the capture mode, the data in each scan register in the scan chain remains unchanged.

[0078] When the scan enable signal is at a high level, the scan chain is in the shift mode. A test vector is input to the SI terminal of the scan chain, and the test vector is shifted among the respective scan registers. Each scan register receives the test data output from the previous scan register and outputs the stored test data to the next scan register at the edge of the clock signal according to the clock signal received by the clock gating output. Specifically, if the scan register is designed to be triggered at the rising edge of the clock signal, then when the clock signal jumps from a low level to a high level, the test data in each scan register is shifted. If the scan register is designed to be triggered at the falling edge of the clock signal, then when the clock signal jumps from a high level to a low level, the test data in each scan register is shifted. For example, the test vector is "0110", there are 4 scan registers, namely scan register A, scan register B, scan register C, and scan register D, and the shift operation is triggered at the rising edge of each clock cycle. As shown in Table 1, the initial states of the 4 scan registers in the scan chain are all 0, and after 4 clock cycles, the test vector is fully loaded into the scan chain.

[0079] Table 1 Shift Mode of Scan Chain

[0080]

[0081] In the embodiment of the present invention, the output terminals and data input terminals of the control registers and enable registers in the control chain are directly connected. When the scan enable signal is at a low level, the scan chain is in the capture mode. Each register no longer shifts but operates as a normal register. In the capture mode, the output result of the combinational logic circuit is captured into each register in the scan chain through the data input terminal. Since the data input terminals of the respective registers in the control chain in the present invention are connected to their own output ports to form a loop. Therefore, when the scan chain is in the capture mode, the values of the respective registers in the scan chain remain unchanged.

[0082] In an embodiment of the present invention, when the scan enable signal is at a high level, the scan chain is in the shift mode. A test vector is input to the scan input terminal of the scan chain, and the test vector is shifted among the respective scan registers. Each scan register receives the test data output from the previous scan register at the edge of the clock signal according to the clock signal received from the clock gating output, and outputs the stored test data to the next scan register. When the scan enable signal is at a low level, the scan chain is in the capture mode, and each register no longer shifts. The output result of the combinational logic circuit is captured into the respective registers in the scan chain through the data input terminal. Since in the present invention, the data input terminals of the respective registers in the control chain are connected to their own output ports to form a loop. Therefore, when the scan chain is in the capture mode, the values of the respective registers in the scan chain remain unchanged for testing and observation, and the demultiplexer is controlled by the values stored in the registers to control each group of clock gating.

[0083] In summary, the test method provided by the embodiment of the present invention can group at least one clock gating to be controlled, determine the number of control registers in the control chain according to the number of groups of clock gating; the control chain includes at least one control register and a demultiplexer; the output terminal of each control register is respectively connected to an input terminal of the demultiplexer, and each output terminal of the demultiplexer is connected to the test enable terminal of a group of clock gating; insert the control chain into the scan chain; the scan chain includes at least one scan register, and at least one scan register is connected in series in sequence; determine the target clock gating group to be enabled according to the clock signal required in the test circuit; according to the target clock gating group, input a scan enable signal to the scan enable terminal of the scan chain, and input a test vector to the scan input terminal of the scan chain to control the target clock gating group through the enable signal output by the demultiplexer. Specifically, determine the target test vector according to the target clock gating group; input a scan enable signal at a low level to the scan enable terminal of the scan chain, and input the target test vector to the scan input terminal, so that through the enable signal output by the demultiplexer, set the test enable terminal of the target clock gating group to a high level state, and set the test enable terminals of the remaining target clock gating groups in the clock gating to be controlled to a low level state, realize the separate control of each group of clock gating, and turn on the corresponding clock gating according to the test requirements, reduce the test power consumption, and shorten the test time.

[0084] Device Embodiment

[0085] As Figure 3 shown, a structural block diagram of a test device of the present invention is shown. The device may specifically include:

[0086] At least one clock gating to be controlled;

[0087] A control chain, including an enable register, at least one control register, and a demultiplexer; an output terminal of the enable register is connected to a data input terminal of the demultiplexer; an output terminal of each control register is respectively connected to a selection terminal of the demultiplexer, and each output terminal of the demultiplexer is connected to a set of test enable terminals of clock gating; the control chain and the scan chain are connected in series; the number of the control registers is determined according to the number of groups of the clock gating to be controlled;

[0088] A scan chain, including at least one scan register, and the at least one scan register is connected in series in sequence.

[0089] Optionally, an input terminal of the enable register at the starting end in the control chain is connected to an output terminal of the first scan register in the scan chain; an output terminal of the control register at the ending end of the control chain is connected to an input terminal of the second scan register in the scan chain; each register in the control chain is connected in series in sequence; a scan output terminal and a respective data input terminal of each register in the control chain are connected in a loop.

[0090] In summary, the test device provided by the embodiment of the present invention can group at least one clock gating to be controlled, and determine the number of control registers in the control chain according to the number of groups of the clock gating; the control chain includes at least one control register and a demultiplexer; an output terminal of each control register is respectively connected to an input terminal of the demultiplexer, and each output terminal of the demultiplexer is connected to a set of test enable terminals of clock gating; insert the control chain into the scan chain; the scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence; determine a target clock gating group to be enabled according to the clock signal required in the test circuit; according to the target clock gating group, input a scan enable signal to the scan enable terminal of the scan chain, and input a test vector to the scan input terminal of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer. Specifically, determine a target test vector according to the target clock gating group; input a low-level scan enable signal to the scan enable terminal of the scan chain, and input the target test vector to the scan input terminal, so as to set the test enable terminal of the target clock gating group to a high-level state through the enable signal output by the demultiplexer, and set the test enable terminals of the remaining target clock gating groups in the clock gating to be controlled to a low-level state, realize separate control of each group of clock gating, and turn on the corresponding clock gating according to the test requirements, reduce the test power consumption, and shorten the test time.

[0091] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, please refer to the partial description of the method embodiment.

[0092] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0093] Regarding the processor in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0094] Refer to Figure 4 , which is a structural block diagram of an electronic device for testing provided by an embodiment of the present invention. As Figure 4 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the testing method of the foregoing embodiments.

[0095] The processor may be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination for implementing computing functions, such as a combination including one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0096] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture, extended industry standard architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 4 only one line is shown in , but it does not mean that there is only one bus or one type of bus.

[0097] The memory may be a ROM (Read Only Memory), or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory), or other types of dynamic storage devices that can store information and instructions. It can also be an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk, optical data storage device, etc.

[0098] Embodiments of the present invention also provide a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 the test method shown.

[0099] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0100] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a device, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0101] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram can be realized by computer program instructions, and the combination of the processes and / or blocks in the flowchart and / or block diagram can also be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for realizing the specified functions in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0102] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a predictive manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction device that implements the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 specified in one block or multiple blocks.

[0103] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, such that a series of operational steps are performed on the computer or other programmable terminal device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 specified in one block or multiple blocks.

[0104] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0105] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or terminal device comprising the element.

[0106] The above has introduced in detail a testing method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this text to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A testing method, characterized in that: The method comprises: At least one clock gating to be controlled is grouped, and the number of control registers in a control chain is determined according to the number of groups of the clock gating; the control chain comprises an enable register, at least one control register and a demultiplexer; the output end of the enable register is connected to the data input end of the demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to a group of test enable ends of the clock gating; Inserting the control chain into a scan chain; the scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence; Determine the target clock gating group to be enabled according to the clock signal required in the test circuit; According to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer.

2. The method according to claim 1, characterized in that Determining the number of control registers in the control chain according to the number of groups of clock gating includes: Performing a logarithm operation with base 2 on the group of numbers to obtain a first operation result; The number of control registers in the control chain is determined according to the first operation result.

3. The method according to claim 1, characterized in that The step of inputting a scan enable signal to a scan enable terminal of the scan chain comprises: Inputting a high-level scan enable signal to a scan enable terminal of the scan chain to set the working mode of the scan chain to a shift mode; When the operation modes of the scan registers in the scan chain are switched to the shift mode, the scan enable signal is switched to a low level to set the operation mode of the scan chain to the capture mode.

4. The method according to claim 1, characterized in that: The step of inputting a scan enable signal to a scan enable end of the scan chain and a test vector to a scan input end of the scan chain according to the target clock gating group, so as to control the target clock gating group through the enable signal output by the demultiplexer, comprises: Determining a target test vector according to the target clock gating group; A low-level scan enable signal is input to the scan enable end of the scan chain, and the target test vector is input to the scan input end, so as to set the test enable end of the target clock gating group to a high level state through the enable signal output by the demultiplexer, and set the test enable ends of the remaining target clock gating groups in the clock gating to be controlled to a low level state.

5. The method according to claim 1, characterized in that The method further comprises: When the target clock gating group includes all clock gating groups, a high level scan enable signal is input to the scan enable end of the scan chain to set the test enable ends of the target clock gating group to a high level state through the enable signal output by the demultiplexer.

6. The method according to claim 1, characterized in that When the working mode of the scan chain is the shift mode, the data in each scan register in the scan chain is shifted bit by bit; when the working mode of the scan chain is the capture mode, the data in each scan register in the scan chain remains unchanged.

7. A testing device, characterized in that: Applied to testing a circuit, the testing device comprises: at least one clock gate to be controlled; A control chain, comprising an enable register, at least one control register and a demultiplexer; the output end of the enable register is connected to the data input end of the demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to a group of clock-gated test enable ends; the control chain and the scan chain are connected in series; the number of the control registers is determined according to the number of clock-gated groups to be controlled; The scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence.

8. The device according to claim 7, characterized in that The input end of the enable register at the starting end of the control chain is connected to the output end of the first scan register in the scan chain; the output end of the control register at the end of the control chain is connected to the input end of the second scan register in the scan chain; each register in the control chain is connected in series in sequence; the scan output end of each register in the control chain is connected in a loop with its respective data input end.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the testing method according to any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to perform the testing method according to any one of claims 1 to 6.

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