Method and device for testing connectivity of stacked chips
By synthesising stacked chips and adding virtual circuits during the design stage of integrated circuits, the problem of difficulty in identifying effective electrical connections between chips is solved, and the accuracy and efficiency of connectivity inspection is improved.
Patent Information
- Application Number
- CN202311365262.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-19
- Publication Date
- 2025-04-22
Smart Images
Figure CN119862841A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip verification technology, and in particular to a method and device for checking the connectivity of stacked chips. Background Art
[0002] Integrated circuits generally include multiple chips stacked together. Electrical connections between chips can be achieved by setting through-silicon vias in the chip substrate and setting solder balls between two adjacent chips, with the solder balls covering the through-silicon vias. As the design of integrated circuits becomes more and more complex, connectivity checks between dies and between dies and wafers become particularly important during the design stage of integrated circuits. Summary of the invention
[0003] The present application provides a method and device for checking the connectivity of stacked chips, which are used to check the connectivity between stacked chips during the design stage of an integrated circuit.
[0004] In the first aspect, the embodiment of the present application provides a method for checking the connectivity of stacked chips, which may include: obtaining the layout corresponding to the multiple chips in the stacking arrangement; obtaining a fusion layout based on the obtained layouts; when it is determined that there is a direct link in the fusion layout, adding a virtual circuit in the direct link; checking the connectivity between the multiple chips corresponding to the fusion layout with the added virtual circuit. The direct link may be: a link formed by connecting multiple pins that are not connected to the semiconductor device, and the multiple pins may be two pins, or more than two pins, so the direct link will not be connected to any semiconductor device, which makes it difficult to accurately identify whether the direct link has achieved an effective electrical connection during verification; if a virtual circuit is added to the direct link so that the direct link is connected to the virtual circuit, then the multiple pins forming the direct link can be used as the ports of the virtual circuit, so that when verifying, it is possible to accurately identify whether the ports have achieved an effective electrical connection, thereby improving the accuracy of the connectivity check between the chips.
[0005] The added virtual circuit may be any component or circuit composed of components known to those skilled in the art, such as at least one of a resistor, an inductor, a capacitor, and a transistor. Furthermore, if the layout needs to be simulated after the connectivity check is completed, the virtual circuit may be selected based on the simulation requirements. For example, if a link with a virtual circuit is required to be added as a path during simulation, the virtual circuit may be: a resistor with a relatively small resistance, or an inductor with a relatively simple structure.
[0006] Of course, when it is determined that there is no direct link in the fusion layout, the connectivity between the multiple chips corresponding to the fusion layout can be checked. In this way, unnecessary operations can be avoided when there is no direct link, and the execution steps when there is a direct link can be simplified, which is conducive to improving the inspection efficiency.
[0007] For example, when verifying connectivity, a LayoutVersus Schematic (LVS) tool may be used, but is not limited to, to verify connectivity between chips. Of course, in addition to the LVS tool, other tools that can verify connectivity between chips may also be used, which are not limited here.
[0008] It should be understood that the GDS (Graphic Data System) file contains graphic layer information. GDS is a standard file format in semiconductor chip design, which stores the layout information of the chip. In the GDS file, each physical layer is assigned to a graphic layer, and each graphic layer has a unique layer number, which is usually an integer. Through the graphic layer information, the position, shape, size and other information of each physical layer in the layout can be determined, which is convenient for chip design and manufacturing related operations.
[0009] Based on this, the inspection method may also include: before obtaining the fused layout, determining whether the layer numbers of the graphic layers in the GDS files corresponding to each layout are the same; if so, adjusting the layer numbers of the graphic layers with the same layer numbers so that the layer numbers of the graphic layers in the GDS files corresponding to each layout are different, and then obtaining the fused layout based on each layout; if not, obtaining the fused layout based on each layout. In this way, before obtaining the fused layout, the layer numbers of the graphic layers in each GDS file can be made different, so as to avoid different graphic layers in the fused layout obtained when the layer numbers of the graphic layers in each GDS file are the same having the same layer number, thereby avoiding abnormalities in the GDS file corresponding to the fused layout, thereby further improving the accuracy of the connectivity inspection and avoiding the reduction of the inspection accuracy due to abnormalities in the fused layout.
[0010] When adjusting the layer numbers of graphic layers with the same layer number, it can specifically include: for each graphic layer with the same layer number, keep the layer number of one of the graphic layers unchanged, and modify the layer numbers of other graphic layers so that the layer numbers of these graphic layers are different, which can reduce the number of modified layer numbers, thereby reducing the amount of calculation, improving the efficiency of layer number adjustment, and thus improving inspection efficiency. Alternatively, modify the layer numbers of each graphic layer with the same layer number respectively so that the layer numbers of these graphic layers are different, so that the layer numbers of each graphic layer can be accurately adjusted to avoid adjustment errors. In addition, in order to ensure that the layer numbers of each graphic layer in each GDS file are different, when adjusting the layer number of a certain graphic layer, it can be adjusted according to the layer numbers of other graphic layers to avoid the layer number formed by the adjustment from being repeated with the layer numbers of other graphic layers, thereby improving the accuracy of the adjustment.
[0011] Furthermore, the inspection method may also include: before determining whether the layer numbers of the graphic layers in the GDS files corresponding to the layouts are the same, determining whether the LVS check of each layout has passed. That is, after obtaining the layouts corresponding to each chip, the LVS check is first performed on each layout, and when the LVS check is passed, it is determined whether the layer numbers of the graphic layers in the corresponding GDS files are the same, so that the structure in each layout can be ensured to meet the requirements, and misjudgment can be avoided when the connectivity check is performed on the basis of non-compliance with the requirements, thereby improving the accuracy of the connectivity check.
[0012] It should be understood that LVS checking is the process of comparing the electrical nodes extracted from the layout with the designed circuit diagram. Only when the types of devices in the layout and their connection methods are consistent with the circuit diagram, the circuit diagram can be checked. Figure 1 Only when they correspond to each other and are consistent, the LVS inspection can pass. Therefore, determining that each layout has passed the LVS inspection can include: finding the layouts with semiconductor devices from each layout, and determining that these layouts have passed the LVS inspection. If there is no semiconductor device in a certain layout, it means that the layout is in the research and development stage and has not been designed yet. Since there is no semiconductor device, it cannot be compared with the circuit diagram, and thus the LVS inspection cannot be performed. For this reason, when performing the LVS inspection, the layout with semiconductor devices is targeted, and only the layout with semiconductor devices can pass the LVS inspection.
[0013] Among them, the LVS check can be regarded as a layout self-check, and the subsequent connectivity verification is performed after the layout self-check passes. In addition, the LVS tool can also be used to implement the layout self-check, but because the layout self-check and connectivity verification check different objects, the LVS tools used are also different. In other words, the parameters in the LVS tools used are different to achieve different inspection purposes.
[0014] Exemplarily, when obtaining a fused layout based on each acquired layout, two methods may be included:
[0015] Method 1: Merge each layout to obtain a fused layout. At this time, when judging whether the layer numbers of the graphic layers in the GDS files corresponding to each layout are the same, the layer numbers of the graphic layers in the GDS files corresponding to the entire layout are targeted, so that it can be comprehensively determined whether the layer numbers of the graphic layers in the GDS files corresponding to each layout are the same, thereby improving the accuracy of connectivity testing.
[0016] Method 2: Merge the interface layers of each layout to obtain a fused layout. For any layout, the layout includes multiple graphic layers, and the graphic layer with pins connected to the outside world is called the interface layer of the layout. Therefore, in this method 2, it is not necessary to merge each layout, but it is necessary to merge the interface layers corresponding to each layout. This can reduce the amount of calculation during the merging process, thereby improving the efficiency of connectivity testing. At this time, when judging whether the layer numbers of the graphic layers in the GDS file corresponding to each layout are the same, it can include: judging whether the layer numbers of each interface layer are the same, so that it only needs to determine whether the layer numbers of each interface layer are the same, reducing the amount of calculation for layer number judgment and improving the efficiency of layer number judgment.
[0017] Moreover, regardless of the above-mentioned method 1 or method 2, the stacking order and connection relationship of each layout are predetermined, so the various layouts can be merged according to the stacking order and connection relationship between the chips, and the pins in each layout can be interconnected to form a fused layout.
[0018] It should be understood that in the embodiments of the present application, the number of chips to be tested is not limited. For example, the number of chips to be tested may be two, three, four or more, and the chips to be tested may be chips that have been designed, or chips that are under development but have not yet been designed, or chips from different manufacturers, with different structures or different processes, so that the inspection method provided in the embodiments of the present application has wider universality.
[0019] For example, after the connectivity check is successful, each successfully verified layout can be automatically output to facilitate subsequent design and production based on each layout. Of course, the successfully verified layout can be regarded as the layout before the layer number is adjusted, that is, the layout initially obtained. From the perspective of the layout structure, the successfully verified layout is the same as the initially obtained layout. The purpose of performing this step is to indicate that the output layout is a successfully verified layout, and subsequent chip production can be based on this layout.
[0020] In the second aspect, the embodiments of the present application further provide an electronic device, which may include: at least one computing unit; at least one memory, the at least one memory is coupled to the at least one computing unit, and stores instructions for execution by the at least one computing unit, and when the instructions are executed by the at least one computing unit, the electronic device executes the method described in the first aspect and any one of the embodiments of the first aspect. It should be understood that since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned inspection method, the implementation and technical effects of the electronic device can refer to the implementation and technical effects of the aforementioned inspection method, and the repeated parts will not be repeated.
[0021] In a third aspect, the embodiments of the present application further provide a computer storage medium, which stores executable instructions. When the executable instructions are executed by a computer, the method described in the first aspect and any one of the embodiments of the first aspect is executed. It should be understood that since the principle of solving the problem by the computer storage medium is similar to the principle of solving the problem by the aforementioned inspection method, the implementation and technical effects of the computer storage medium can refer to the implementation and technical effects of the aforementioned inspection method, and the repeated parts will not be repeated.
[0022] In a fourth aspect, the embodiments of the present application further provide a computer program product, the computer program product comprising computer executable instructions, which, when executed by a processor, enable a computer to implement the method described in the first aspect and any one of the embodiments of the first aspect. It should be understood that since the principle of solving the problem by the computer program product is similar to the principle of solving the problem by the aforementioned inspection method, the implementation and technical effects of the computer program product can refer to the implementation and technical effects of the aforementioned inspection method, and the repeated parts will not be repeated.
[0023] In a fifth aspect, an embodiment of the present application further provides an electronic device, which may include: an acquisition unit for acquiring a layout corresponding to a plurality of chips in a stacked arrangement; a fusion unit for obtaining a fusion layout based on the acquired layouts; a connectivity verification unit for adding a virtual circuit to a direct link when it is determined that there is a direct link in the fusion layout; wherein the direct link is: a link formed by connecting a plurality of pins that are not connected to a semiconductor device; and the connectivity between the plurality of chips corresponding to the fusion layout with the virtual circuit added is verified. If a virtual circuit is added to a direct link so that the direct link is connected to the virtual circuit, then the plurality of pins forming the direct link can be used as the ports of the virtual circuit, so that when performing verification, it is possible to accurately identify whether an effective electrical connection is achieved between the ports, thereby improving the accuracy of the connectivity verification between the chips.
[0024] Of course, the connectivity check unit is also used to check the connectivity between multiple chips corresponding to the fusion layout when it is determined that there is no direct link in the fusion layout. In this way, it is possible to avoid unnecessary operations when there is no direct link, simplify the execution steps when there is a direct link, and thus help improve the inspection efficiency.
[0025] Exemplarily, the fusion unit is specifically used to merge the interface layers of each layout to obtain a fused layout, which can reduce the amount of calculation during the merging process, thereby improving the efficiency of connectivity testing.
[0026] In addition, the electronic device may further include: a layer number adjustment unit, which is used to determine whether the layer numbers of the graphic layers in the GDS files corresponding to each layout are the same before obtaining the fused layout; if so, the layer numbers of the graphic layers with the same layer number are adjusted so that the layer numbers of the graphic layers in the GDS files corresponding to each layout are different, and then the fused layout is obtained based on each layout; if not, the fused layout is obtained based on each layout. In this way, before the layout is merged, the layer numbers of the graphic layers in each GDS file can be made different, so as to avoid different graphic layers in the fused layout obtained when the layer numbers of the graphic layers in each GDS file are the same having the same layer number, thereby avoiding abnormalities in the GDS file corresponding to the fused layout, thereby improving the accuracy of the connectivity test and avoiding the reduction of the test accuracy due to abnormalities in the fused layout.
[0027] Furthermore, the layer number adjustment unit is specifically used to determine whether the layer numbers of the graphic layers in the GDS file corresponding to each interface layer are the same when the interface layers of each layout are merged to obtain a fused layout. Therefore, it is only necessary to determine whether the layer numbers of each interface layer are the same, which reduces the amount of calculation for layer number determination and improves the efficiency of layer number determination. Of course, the layer number adjustment unit is also specifically used to determine whether the layer numbers of the graphic layers in the GDS files corresponding to different entire layouts are the same when the layouts are merged to obtain a fused layout, so that it can be comprehensively determined whether the layer numbers of the graphic layers in the GDS files corresponding to each layout are the same, thereby improving the accuracy of connectivity testing.
[0028] The electronic device may also include: an LVS check unit, which is used to determine whether the LVS check of each layout has passed before determining whether the layer numbers of the graphic layers in the GDS files corresponding to each layout are the same. That is to say, after obtaining the layout corresponding to each chip, the LVS check is first performed on each layout, and when the LVS check passes, it is determined whether the layer numbers of the graphic layers in the corresponding GDS files are the same. This can ensure that the structure in each layout meets the requirements, avoid misjudgment when performing connectivity checks on the basis of non-compliance with the requirements, and thus improve the accuracy of the connectivity check.
[0029] Among them, the LVS inspection unit is specifically used to find out the layouts with semiconductor devices from various layouts, and determine whether these layouts have passed the LVS inspection. If there is no semiconductor device in a layout, it means that the layout is in the research and development stage and has not been designed yet. Since there is no semiconductor device, it cannot be compared with the circuit diagram, and thus the LVS inspection cannot be performed. For this reason, when performing the LVS inspection, the layout with semiconductor devices is targeted, and only the layout with semiconductor devices can pass the LVS inspection.
[0030] It should be understood that since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned inspection method, the implementation and technical effects of the electronic device can refer to the implementation and technical effects of the aforementioned inspection method, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 A flowchart of a design and manufacturing process of an integrated circuit provided in an embodiment of the present application;
[0032] Figure 2 A flowchart of a verification method provided in an embodiment of the present application;
[0033] Figure 3 A schematic diagram of a fusion layout provided in an embodiment of the present application;
[0034] Figure 4 A flowchart of another verification method provided in an embodiment of the present application;
[0035] Figure 5 A flowchart of another verification method provided in an embodiment of the present application;
[0036] Figure 6 A schematic diagram of another fusion layout provided in an embodiment of the present application. DETAILED DESCRIPTION
[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.
[0038] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.
[0039] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its application scenario is first described below.
[0040] Figure 1 The flow chart of the design and manufacturing process of an integrated circuit is shown. The design and manufacturing process starts with specification formulation 110. In the specification formulation 110 stage, the requirements for the functions and performances that the integrated circuit needs to achieve are determined. Then, in the integrated circuit design 120 stage, the circuit design 121 is first performed with the help of EDA (electronic design automation, EDA) software. After the circuit is determined, the layout and wiring of the circuit units in the integrated circuit are determined by performing physical design 122, thereby obtaining a circuit layout. After obtaining the circuit layout, mask making 123 can be performed to obtain a mask for forming the designed circuit on a wafer. Subsequently, in the manufacturing 130 stage, an integrated circuit is formed on the wafer through processes such as lithography, etching, ion implantation, thin film deposition, and polishing. In the packaging 140 stage, the wafer is cut to obtain a bare die, and the bare die is packaged to obtain a chip through processes such as pasting, welding, and mold sealing. The obtained chip is tested in the testing 150 stage to ensure that the performance of the finished chip meets the requirements determined in the specification formulation 110. Finally, the chip 160 that has passed the test can be delivered to the customer.
[0041] The technical solution provided in the embodiment of the present application can be applied in the integrated circuit design 120 stage. After the circuit layout is obtained through the physical design 122 and before the mask production 123 is performed, the connectivity between the stacked chips can be checked based on the layout. After the inspection is passed, the mask production 123 can be continued. Of course, when the inspection fails, the layout can be corrected to ensure that the connectivity between the chips is normal and the subsequent process is continued, thereby improving the yield of the chip 160. The program for executing the verification process can be installed in an electronic device, and the electronic device can be a device with computing functions such as a personal computer, a workstation, a server, etc., and the scope of the present disclosure is not limited in this respect.
[0042] The verification method and the electronic device for implementing the verification method are explained and illustrated below in conjunction with specific embodiments.
[0043] Figure 2 A flowchart of a verification method in an embodiment of the present application is shown as an example. Figure 2 As shown, the verification method may include:
[0044] S201, obtaining a layout corresponding to a plurality of chips arranged in a stack;
[0045] S202, confirming that the LVS check of each layout has passed;
[0046] LVS checking is the process of comparing the electrical nodes extracted from the layout with the designed circuit diagram. Figure 1 Only when they correspond to each other and are consistent, the LVS inspection can pass. Therefore, determining that each layout has passed the LVS inspection can include: finding the layouts with semiconductor devices from each layout, and determining that these layouts have passed the LVS inspection. If there is no semiconductor device in a certain layout, it means that the layout is in the research and development stage and has not been designed yet. Since there is no semiconductor device, it cannot be compared with the circuit diagram, and thus the LVS inspection cannot be performed. For this reason, when performing the LVS inspection, the layout with semiconductor devices is targeted, and only the layout with semiconductor devices can pass the LVS inspection.
[0047] S203, determine whether the layer numbers of the graphic layers in the GDS files corresponding to the layouts are the same; if so, execute S204; if not, execute S205;
[0048] S204, adjusting the layer numbers of the graphic layers with the same layer number so that the layer numbers of the graphic layers in each GDS file are different; executing S205;
[0049] When adjusting the layer numbers of graphic layers with the same layer number, it can specifically include: for each graphic layer with the same layer number, keep the layer number of one of the graphic layers unchanged, and modify the layer numbers of other graphic layers so that the layer numbers of these graphic layers are different, which can reduce the number of modified layer numbers, thereby reducing the amount of calculation, improving the efficiency of layer number adjustment, and thus improving inspection efficiency. Alternatively, modify the layer numbers of each graphic layer with the same layer number respectively so that the layer numbers of these graphic layers are different, so that the layer numbers of each graphic layer can be accurately adjusted to avoid adjustment errors. In addition, in order to ensure that the layer numbers of each graphic layer in each GDS file are different, when adjusting the layer number of a certain graphic layer, it can be adjusted according to the layer numbers of other graphic layers to avoid the layer number formed by the adjustment from being repeated with the layer numbers of other graphic layers, thereby improving the accuracy of the adjustment.
[0050] That is to say, the above step S204 can be understood as: by adjusting the layer number, each layout is mapped to the layer number of the graphic layer in the corresponding GDS file, that is, the layout Figure 1 A set of mappings is formed with the layer number of the graphic layer in the corresponding GDS file. Figure 2 Another set of mapping is formed with the layer number of the graphic layer in the corresponding GDS file, thereby avoiding subsequent misjudgment.
[0051] S205, merging the various layouts to obtain a fused layout;
[0052] S206, determine whether there is a direct link in the fusion map; if so, execute S207; if not, execute S208;
[0053] The direct link may be a link formed by connecting multiple pins that are not connected to the semiconductor device. Figure 3 As shown, the fusion layout includes Figure 1 ,version Figure 2 , and version Figure 3 ,in Figure 3 Except for the version Figure 1 Japanese version Figure 2 Structures other than Figure 3 The structure in the hypothetical version Figure 1 There are pins ( Figure 3 ) and semiconductor devices ( Figure 3 Not shown), Figure 2 There are pins but no semiconductor devices, and the board Figure 2 There are multiple pins in the board, which are marked as D2port3, D2port4, and D2port5. Figure 3 There are pins but no semiconductor devices, and the board Figure 3 There are multiple pins in the board, which are recorded as Bump1, Bump2, Bump3, Bump4, and Bump5; Bump1 and Bump2 are both Figure 1 The pins in the Bump3 are connected to the Figure 1 Pins and board Figure 2 D2port3 is connected to Bump4 and the board Figure 2 D2port4 is connected to Bump5 and Figure 2 Since Bump4 and D2port4 are two pins that are not connected to the semiconductor device, the link formed by connecting Bump4 and D2port4 is a direct link. Similarly, the link formed by connecting Bump5 and D2port5 is also a direct link, so a virtual circuit 40 can be added to the direct link. Figure 1 Pins and board Figure 2 D2port3 connection in the Figure 1 There are semiconductor devices in it, so the version Figure 1 The pins in the circuit must also be connected to the semiconductor device, and then Bump3 is connected to the board Figure 1 Pins and board Figure 2 The link formed by connecting D2port3 in must also be connected to the semiconductor device, so the link is not a direct link.
[0054] S207, adding a virtual circuit in the direct link; executing S208;
[0055] The added virtual circuit can be any component or circuit composed of components known to those skilled in the art, such as at least one of a resistor, an inductor, a capacitor, and a transistor. Furthermore, if the layout needs to be simulated after the connectivity check is completed, the virtual circuit can be selected based on the simulation requirements. For example, if the simulation requires adding a link with a virtual circuit as a path, the virtual circuit can be: a resistor with a relatively small resistance, or an inductor with a relatively simple structure.
[0056] S208, checking the connectivity between the multiple chips corresponding to the fusion layout.
[0057] Among them, when verifying the connectivity, the LVS tool can also be used for verification, and the connectivity between each chip can be verified by using the LVS tool. In addition, the LVS check in the above S202 can be regarded as a layout self-check, and the subsequent connectivity verification is performed after the layout self-check passes. Since the layout self-check and the connectivity verification have different objects to be checked, the LVS tools used are also different. In other words, the parameters in the LVS tools used are different to achieve different inspection purposes. Of course, whether it is a layout self-check or a connectivity verification, in addition to using the LVS tool, other tools that can verify the connectivity between each chip can also be used, such as but not limited to DRC (Design Rule Checking) tools or ANT (Antenna Effect) tools, which are not limited here.
[0058] Exemplarily, after the verification is passed, each successfully verified layout can be output. It should be understood that the successfully verified layout can be regarded as the layout before the layer number is adjusted, that is, the layout initially obtained. From the perspective of the layout structure, the successfully verified layout is the same as the initially obtained layout. The purpose of performing this step is to indicate that the output layout is a successfully verified layout, and subsequent chip production can be based on this layout.
[0059] Of course, when executing S208, if the verification result is not successful, then each layout can be modified, and then the process from S202 to S208 can be continued until the verification is successful.
[0060] That is to say, combined Figure 4 As shown, by executing S201, the layout corresponding to each chip can be obtained, as shown in Figure (a), 10 represents the layout Figure 1 , 20 indicates version Figure 2 , 30 indicates the version Figure 3; By executing S202 to S204, when the graphic layers in the GDS file corresponding to each layout have the same layer number, the layer number is adjusted to obtain a layout after the layer number is adjusted, as shown in Figure (b). It should be understood that there is no structural difference between the layout after the layer number adjustment and the layout before the layer number adjustment, except that the layer number of the graphic layer in the GDS file has changed, so 10' in Figure (b) represents a layout with the layer number adjusted. Figure 1 , 20' means the version with adjusted layer number Figure 2 , 30' means the version with adjusted layer number Figure 3 ; By executing S205 to S208, the fusion processing and verification process is performed, as shown in Figure (c); after the verification is successful, each layout that has been successfully verified can be output, as shown in Figure (d), and the output layout is the layout initially acquired.
[0061] Thus, on the one hand, by adding a virtual circuit to the direct link, the direct link is connected to the virtual circuit, and the multiple pins forming the direct link can be used as the ports of the virtual circuit, so that when verifying, it is possible to accurately identify whether effective electrical connection is achieved between the ports, thereby improving the accuracy of connectivity testing between chips. On the other hand, by adjusting the layer number, it is possible to avoid different graphic layers in the fused layout having the same layer number when the layer numbers of the graphic layers in each GDS file are the same, thereby avoiding abnormalities in the GDS file corresponding to the fused layout, thereby further improving the accuracy of connectivity testing between chips.
[0062] Figure 5 A flowchart of a verification method in an embodiment of the present application is shown as an example. Figure 5 As shown, the verification method may include:
[0063] S501, obtaining a layout corresponding to a plurality of chips in a stacked arrangement;
[0064] S502, confirming that the LVS check of each layout has passed;
[0065] S503, extracting the interface layer in each layout;
[0066] For any layout, the layout includes multiple graphic layers, and the graphic layer with pins connected to the outside world is called the interface layer of the layout.
[0067] S504, determine whether the layer numbers of the interface layers are the same; if so, execute S505; if not, execute S506;
[0068] S505, adjusting the layer number so that the layer number of each interface layer is different; executing S506;
[0069] S506, merging the interface layers of each layout to obtain a fused layout;
[0070] S507, determine whether there is a direct link in the fusion map; if so, execute S508; if not, execute S509;
[0071] Combination Figure 6 As shown, the fusion layout includes Figure 1 ,version Figure 2 , and version Figure 3 ,in Figure 6 Except for the version Figure 1 Japanese version Figure 2 Structures other than Figure 3 The structure in the hypothetical version Figure 1 There are pins and semiconductor devices ( Figure 6 Not shown in the figure), and Figure 1 There are multiple pins in the board, which are recorded as Port1, Port2, and Port3. Figure 2 There are pins and semiconductor devices ( Figure 6 Not shown in the figure), and Figure 2 There are multiple pins in the board, which are recorded as D2port3, D2port4, and D2port5. Figure 3 There are pins but no semiconductor devices, and the board Figure 3 There are multiple pins in the board, which are recorded as Bump1, Bump2, Bump3, Bump4, and Bump5. Figure 1 Port1 is connected to Bump2 and Figure 1 Port2 in the board is connected, and Bump3 is connected to the board Figure 1 Port3 and version Figure 2 D2port3 is connected to Bump4 and the board Figure 2 D2port4 is connected to Bump5 and Figure 2 D2port5 connection in the Figure 1 Japanese version Figure 2 There are semiconductor devices in them, so Figure 1 Japanese version Figure 2 The pins in the connection must be connected to their respective semiconductor devices, and the link formed by connecting Bump1 to Port1 will also be connected to the semiconductor device, so this link is not a direct link. Similarly, the link formed by connecting Bump2 to Port2, the link formed by connecting Bump3 to Port3 and D2port3, the link formed by connecting Bump4 to D2port4, and the link formed by connecting Bump5 to D2port5 are not direct links.
[0072] S508, adding a virtual circuit in the direct link; executing S509;
[0073] S509, checking the connectivity between the multiple chips corresponding to the fusion layout.
[0074] It should be understood that since the verification method in this embodiment is different from the above Figure 2 The verification method in the first embodiment shown is basically similar, and the similarities can be seen in the above Figure 2 The description of the first embodiment shown will not be repeated any more.
[0075] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A method for checking the connectivity of stacked chips, characterized in that: include: Obtaining a layout corresponding to a plurality of chips in a stacking arrangement; Based on the obtained layouts, a fused layout is obtained; When it is determined that a direct link exists in the fusion layout, a virtual circuit is added to the direct link; wherein the direct link is: a link formed by connecting a plurality of pins that are not connected to the semiconductor device; The connectivity between the multiple chips corresponding to the fusion layout with the virtual circuit added is checked.
2. The method according to claim 1, characterized in that The virtual circuit includes at least one of a resistor, an inductor, a capacitor, and a transistor.
3. The method according to claim 1 or 2, characterized in that Based on the acquired layouts, a fused layout is obtained, including: merging the interface layers of the layouts to obtain the fused layout.
4. The method according to any one of claims 1 to 3, characterized in that: Also includes: Before obtaining the fused layout, determining whether the layer numbers of the graphic layers in the GDS files corresponding to the layouts are the same; If yes, the layer numbers of the graphic layers with the same layer number are adjusted so that the layer numbers of the graphic layers in the GDS file corresponding to the layouts are different, and then the fused layout is obtained based on the layouts; If not, then based on each of the layouts, the fused layout is obtained.
5. The method according to claim 4, characterized in that Also includes: Before determining whether the layer numbers of the graphic layers in the GDS files corresponding to the layouts are the same, it is determined that the LVS check of the layouts has passed.
6. The method according to claim 4 or 5, characterized in that Determining whether the layer numbers of the graphic layers in the GDS files corresponding to the layouts are the same includes: When the interface layers of the layouts are merged to obtain the fused layout, it is determined whether the layer numbers of the interface layers are the same.
7. The method according to any one of claims 1 to 6, characterized in that: Also includes: When it is determined that the direct link does not exist in the fusion layout, the connectivity between the multiple chips corresponding to the fusion layout is checked.
8. An electronic device, characterized in that: include: at least one computing unit; At least one memory, the at least one memory is coupled to the at least one computing unit and stores instructions for execution by the at least one computing unit, and when the instructions are executed by the at least one computing unit, the electronic device executes the method according to any one of claims 1-7.
9. A computer storage medium, characterized in that The computer storage medium stores executable instructions, and when the executable instructions are executed by a computer, the method according to any one of claims 1 to 7 is executed.
10. A computer program product, characterized in that The computer program product comprises computer executable instructions, which, when executed by a processor, enable a computer to implement the method according to any one of claims 1 to 7.
11. An electronic device, characterized in that: include: An acquisition unit, used for acquiring a layout corresponding to a plurality of chips arranged in a stack; A fusion unit, used for obtaining a fused layout based on the acquired layouts; A connectivity checking unit, configured to add a virtual circuit to a direct link when it is determined that there is a direct link in the fusion layout; wherein the direct link is a link formed by connecting a plurality of pins that are not connected to the semiconductor device; The connectivity between the multiple chips corresponding to the fusion layout with the virtual circuit added is checked.
12. The electronic device according to claim 11, characterized in that: The fusion unit is specifically used to merge the interface layers of each of the layouts to obtain the fused layout.
13. The electronic device according to claim 11 or 12, characterized in that: Also includes: A layer number adjustment unit, used for determining whether the layer numbers of the graphic layers in the GDS files corresponding to the layouts are the same before obtaining the fused layout; If so, the layer numbers of the graphic layers with the same layer numbers are adjusted so that the layer numbers of the graphic layers in the GDS file corresponding to each of the layouts are different, and then the fused layout is obtained based on each of the layouts; if not, the fused layout is obtained based on each of the layouts.
14. The electronic device according to claim 13, characterized in that: Also includes: The LVS checking unit is used to determine whether the LVS check of each layout is passed before judging whether the layer numbers of the graphic layers in the GDS files corresponding to each layout are the same.
15. The electronic device according to claim 13 or 14, characterized in that: The layer number adjustment unit is specifically used to determine whether the layer numbers of the graphic layers in the GDS file corresponding to the interface layers are the same when the interface layers of the layouts are merged to obtain the fused layout.
16. The electronic device according to any one of claims 11 to 15, characterized in that: The connectivity checking unit is further configured to check the connectivity between the multiple chips corresponding to the fusion layout when it is determined that the direct link does not exist in the fusion layout.