A Method for Generating a Visualization Pcell Layout of MOS and MOM Capacitors

Abstract

The present invention discloses a method for generating a visual Pcell layout of MOS and MOM capacitors, which relates to the technical field of integrated circuits. The present invention conducts multiple simulations by constructing a simulation circuit, records the capacitance value changes of MOS transistors under different voltages, generates a detailed capacitance value data table, forms Pcell parameters associated with geometric parameters, and integrates them into a layout design tool, realizing fast calculation and visualization in the layout. Then, the calculation range of POLY density is defined and calculated in real time to ensure that it meets the process requirements. By selecting the optimal metal layer combination and adjusting the metal area, the design of MOM capacitors is optimized. Then, the calculation results of MOS transistor capacitors and MOM capacitors are integrated into the Pcell, the Pcell parameters are called, the corresponding capacitance layout is generated, and design rule checking and circuit layout comparison verification are carried out to ensure that the layout meets the process requirements.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and specifically to a method for generating a visual Pcell layout of MOS and MOM capacitors. Background Art

[0002] In the field of chip design, MOS transistors are often used as filter capacitors, but this design has obvious defects. When the source and drain of the MOS transistor are connected, its capacitance value changes with Vgs, and this change cannot be directly reflected during the layout RC extraction, resulting in only the parasitic capacitance of the poly, diffusion, and metal layers being extracted. Most of the capacitance needs to be calculated within the frequency bandwidth through circuit design, which makes it difficult to intuitively evaluate the capacitance value of the MOS transistor in the pre-simulation stage and is not conducive to the evaluation of the layout area. As the IP design frequency increases, a larger capacitance value is required for the filter capacitor, resulting in an increase in the layout area. To save area, MOM capacitors are often stacked on top of MOS transistor capacitors. However, the change in the MOM capacitor voltage difference will change the metal wire spacing, affecting PV verification, and it is easy to cause connection short circuits or DRC errors due to the change in the positions of the positive and negative plates during calling, requiring redrawing of the layout. In addition, manufacturing MOM capacitors may add a voltage identification layer, which will increase the voltage when connecting to other nets, causing unnoticed DRC errors. And with the continuous reduction of the process node, the flatness of the layout is becoming increasingly important for the yield of the chip. This requires strict control of the density of each layer during layout design. When filter capacitors are used on a large scale, the density of the POLY is easily beyond the required range, which needs to be considered during the layout design layout to avoid redrawing the layout due to insufficient layout area in the later stage, increasing the workload. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for generating a visual Pcell layout of MOS and MOM capacitors, which can efficiently generate a visual capacitance value Pcell layout of MOS transistors and MOM capacitors based on the FinFET process, and improve the efficiency and accuracy of layout design.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present application provides a method for generating a visual Pcell layout of MOS and MOM capacitors, including the following steps:

[0006] Record the capacitance value changes of a 1.8V MOS transistor at different Vgs voltages through a simulation circuit, draw a curve graph, and analyze the linear relationship between finger and Length and the capacitance value;

[0007] According to the simulation results, calculate the capacitance change slope of the MOS transistor at different voltages, generate the reference capacitance C1, calculate the capacitances C2 and C at different Lengths and fingers, and generate a capacitance data table for the MOS transistor;

[0008] According to the capacitance data table of the MOS transistor, associate it with the geometric parameters to form Pcell parameters for rapid calculation and visualization in the layout;

[0009] According to the simulation result data, select the metal layers of Metal4 and above, calculate the capacitance value of the MOM capacitor per unit area in combination with the process conditions, and calculate the overall metal capacitance according to the designed metal area.

[0010] According to the capacitance of the MOS transistor and the overall metal capacitance, define the calculation range of POLY density, calculate POLY density in real time, reduce the POLY density ratio by adjusting the layout parameters, and determine whether it meets the layout CMP requirements.

[0011] Furthermore, record the capacitance value changes of the 1.8V MOS transistor at different Vgs voltages through the simulation circuit, draw a curve graph, and analyze the linear relationship between finger and Length and the capacitance value, specifically including:

[0012] According to the parameters of the 1.8V MOS transistor, construct a MOS transistor circuit model in the simulation circuit design software, set different Vgs voltage values, and perform multiple simulations through the circuit simulation software to obtain the capacitance value data of the MOS transistor at different Vgs voltages;

[0013] Sort out the obtained capacitance value data, draw a curve graph of the capacitance value versus the Vgs voltage through data analysis software, and analyze the linear relationship between the finger and Length parameters of the MOS transistor and the capacitance value according to the drawn curve graph to obtain the influence law of finger and Length on the capacitance value;

[0014] For the capacitance value data at different Vgs voltages, use the curve fitting algorithm to judge the trend of the capacitance value changing with the Vgs voltage, obtain the mathematical model between the capacitance value and the Vgs voltage, and then use the machine learning algorithm to train the mapping relationship model between the capacitance value and the Vgs voltage, finger, and Length parameters to predict the capacitance value of the MOS transistor under any parameter combination;

[0015] According to the established mathematical model and machine learning model, optimize the finger and Length parameter design of the MOS transistor to obtain the optimal capacitance value and linear characteristics while meeting the circuit performance requirements.

[0016] Furthermore, generate a capacitance data table for the MOS transistor, specifically including:

[0017] According to the simulation result data, extract information such as voltage parameters, transistor parameters, and transistor types, establish a multi-dimensional array to store the simulation capacitance values under different conditions, traverse the voltages and transistor parameters of different transistor types, call the capacitance calculation formula, obtain the capacitance under the corresponding conditions, and update it to the corresponding multi-dimensional array;

[0018] From the multi-dimensional array, select the MOS transistor data of the same size, perform linear fitting on the capacitance values under different voltages, obtain the slope of the capacitance change with voltage under the corresponding size, then select the reference Length and finger as the initial values, and extrapolate and calculate the capacitance at zero voltage as the reference capacitance C1 according to the capacitance change slope under this size;

[0019] Among them, starting from the reference Length, apply the Length slope formula, traverse different Lengths, calculate the capacitance C2 under the corresponding conditions, and update the Length-capacitance mapping table; starting from the reference finger, traverse different values of finger, call the mapping formula between the exponent and the capacitance, calculate the capacitance C under different finger values, and continuously update the finger-capacitance mapping table;

[0020] Combine the Length-capacitance mapping table and the finger-capacitance mapping table to generate a capacitance data table covering different Lengths, fingers, and voltage conditions.

[0021] Furthermore, according to the capacitance data table of the MOS transistor, form Pcell parameters in association with geometric parameters, specifically including:

[0022] Obtain the capacitance data table of the MOS transistor, extract the corresponding relationship data between the capacitance and geometric parameters, establish a Pcell parameterization model of the MOS transistor capacitance according to the extracted corresponding relationship data between the capacitance and geometric parameters, and perform an associative mapping between the capacitance and geometric parameters; in the Pcell parameterization model, set the geometric parameters as input variables and the capacitance as output variables, establish a parameterization calculation formula, integrate the Pcell parameterization model into the layout design tool, perform real-time associative calculation of the geometric parameters and the capacitance change slope, and according to the Pcell parameterization model, perform visual adjustment of the geometric parameters. During the layout design process, calculate the capacitance of the MOS transistor by calling the Pcell parameterization model. When the capacitance of the MOS transistor needs to be adjusted in the layout design, calculate the capacitance of the adjusted MOS transistor according to the geometric parameters of the adjusted MOS transistor capacitance, and update the visualization of the MOS transistor capacitance in real time in the layout.

[0023] Further, after forming the Pcell parameters in association with geometric parameters, it further includes: obtaining the capacitance values of MOM capacitors at different metal levels, analyzing the relationship between the capacitance values of MOM capacitors, metal levels, and areas, establishing a Pcell model for MOM capacitors, where the Pcell model includes the mapping relationship between metal levels, areas, and capacitance values, and during layout design, according to the metal level and area parameters of the MOM capacitor, using the Pcell model of the MOM capacitor to calculate the corresponding capacitance value of the MOM capacitor.

[0024] Further, calculating the overall metal capacitance according to the designed metal area, specifically including: obtaining the metal levels above Metal4, extracting the corresponding metal capacitance values, obtaining the capacitance value data under the same process conditions as the MOM capacitor, combining the extracted metal capacitance values to calculate the capacitance value per unit area, according to the metal area designed in the Pcell model, obtaining the corresponding capacitance value per unit area by looking up a table or interpolation, multiplying the metal area by the capacitance value per unit area to obtain the overall metal capacitance, and then using the overall metal capacitance as a parameter of the MOM capacitor to calculate the overall capacitance value to obtain the calculation result.

[0025] Further, according to the calculation result, it further includes: analyzing the capacitance characteristics of different metal levels, selecting the optimal combination of metal levels; adjusting the metal area according to the design requirements, using the calculation method of MOS transistors to obtain the corresponding capacitance value, obtaining the optimized metal level, area, and the corresponding capacitance value, and using the optimized values as the input parameters of the Pcell model of the MOM capacitor to calculate the metal capacitance and visually display it in the layout.

[0026] Furthermore, define the POLY density calculation range, calculate the POLY density in real time, reduce the POLY density ratio by adjusting the layout parameters, and determine whether it meets the layout CMP requirements, which specifically includes: obtaining the MOS capacitance value and the metal capacitance value, determining that the calculation range of POLY density is the BOX range starting from the lower left corner of POLY and ending at the upper right corner. Within the defined BOX range, calculate the area of the POLY layer, and at the same time, calculate the total area of the BOX range; calculate the POLY density ratio in real time according to the ratio of the POLY area within the calculation range to the total BOX area; then obtain the POLY Dn requirement threshold of the process, and determine whether the calculated POLY density meets the requirements; when the POLY density exceeds the threshold, reduce the POLY density by adjusting the MOS transistor layout parameters while keeping the MOS capacitance value unchanged; repeat the calculation of the POLY density ratio and the determination of whether POLY Dn meets the requirement threshold until the POLY density meets the CMP requirement threshold; then determine whether the layout area is sufficient according to the adjusted layout parameters; when the layout area is insufficient, continue to adjust the layout parameters until the layout area meets the requirements, and output the final layout parameters and the layout area.

[0027] Integrate the calculation results of the MOS transistor capacitance and the MOM capacitance into a Pcell to form a complete capacitance module. In the layout design, by calling the Pcell parameters, quickly generate the corresponding capacitance layout according to the design requirements, perform automatic placement and routing of the capacitance module, and perform design rule checking and circuit layout comparison verification on the generated Pcell layout to make the layout meet the process requirements.

[0028] Furthermore, form a complete capacitance module from the calculation results of the MOS transistor capacitance and the MOM capacitance. According to the design requirements, determine the parameter specifications of the capacitance module and use them as the input parameters of the Pcell. By calling the corresponding capacitance Pcell and passing in the design parameters, the Pcell automatically generates a capacitance layout that meets the requirements according to the preset placement and routing algorithm and design rules;

[0029] Perform design rule checking on the generated capacitance layout to check whether the layout meets the design specifications of the process. When the check fails, adjust the Pcell parameters to regenerate the layout until the DRC check passes;

[0030] Then perform LVS circuit layout comparison verification on the generated capacitance layout and the schematic diagram to check whether the electrical connections of the layout and the schematic diagram are consistent. When the layout comparison verification fails, return to modify the Pcell parameters to regenerate the layout until the layout comparison verification passes.

[0031] The beneficial effects of the present invention are as follows:

[0032] By constructing a simulation circuit and performing multiple simulations, recording the capacitance value changes of MOS transistors under different voltages, generating a detailed capacitance value data table, forming Pcell parameters associated with geometric parameters, and then integrating these Pcell parameters into a layout design tool, fast calculation and visualization in the layout are achieved. This not only improves the efficiency of layout design but also ensures the accuracy of the design, enabling intuitive evaluation of the MOS transistor capacitance value in the front-end simulation stage and avoiding the problem of inaccurate layout area evaluation caused by capacitance value changes. In addition, by optimizing the finger and Length parameter designs of MOS transistors, the linear characteristics of the capacitance value are further improved, meeting the circuit performance requirements;

[0033] By defining the calculation range of POLY density and calculating POLY density in real time to ensure compliance with process requirements, when the POLY density exceeds the threshold, by adjusting the layout parameters of MOS transistors (such as nfinSpace), without changing the MOS capacitance value, the POLY density ratio is reduced, quickly determining whether it meets the layout CMP requirements. This effectively avoids the problem of redrawing due to insufficient layout area caused by too high POLY density, reducing the workload. At the same time, by selecting the optimal metal layer combination and adjusting the metal area, the design of MOM capacitors is optimized, ensuring the flatness of the layout and the yield of the chip. Then, integrating the calculation results of MOS transistor capacitance and MOM capacitance into a Pcell to form a complete capacitance module, by calling the Pcell parameters, the corresponding capacitance layout is quickly generated, and design rule checking and circuit layout comparison verification are performed to ensure that the layout meets the process requirements, improving the reliability and performance of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] For better understanding and implementation, the technical solutions of the present application will be described in detail below with reference to the drawings.

[0035] Figure 1 It is a schematic flow chart of a method for generating a visualization Pcell layout of MOS and MOM capacitors provided by the present application;

[0036] Figure 2 It is a schematic flow chart of constructing a simulation circuit and setting different Vgs voltage values for circuit simulation in a method for generating a visualization Pcell layout of MOS and MOM capacitors provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] To further illustrate the technical means and effects adopted by the present invention to achieve the intended invention purpose, exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of methods and systems consistent with some aspects of the present application as detailed in the appended claims.

[0038] The terms used in the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0039] The following will detail the specific embodiments, features, and effects of the present invention in conjunction with the accompanying drawings and preferred embodiments.

[0040] Please refer to Figure 1 - Figure 2 , this embodiment provides a method for generating a MOS and MOM capacitor visualization Pcell layout, including the following steps:

[0041] Among them, the FinFET process is an advanced semiconductor manufacturing technology. By adopting a three-dimensional fin structure and a double-gate design, it significantly improves the performance and energy efficiency of transistors. This process not only enhances the channel control ability, reduces leakage current, but also improves the drive current and integration density, making the chip perform excellently in high-performance computing and low-power applications, and at the same time having good scalability to meet the needs of future technology development;

[0042] S1. Record the capacitance value changes of a 1.8V MOS transistor at different Vgs voltages through a simulation circuit, draw a curve graph, and analyze the linear relationship between finger and Length and the capacitance value;

[0043] Specifically, a simulation circuit is constructed and different Vgs voltage values are set for circuit simulation. Record the capacitance value changes of the MOS transistor at different voltages of the 1.8V MOS transistor, organize the simulation results and draw a curve graph, analyze the linear relationship between the finger and Length of the MOS transistor and the capacitance value, and the trend of capacitance change with voltage at different voltages;

[0044] Among them, Finger refers to multiple parallel and slender active regions between the source and drain in a FinFET, and Length is the channel length between the source and drain in a FinFET.

[0045] Furthermore, by recording the capacitance value changes of a 1.8V MOS transistor at different Vgs voltages through a simulation circuit, plotting a curve graph, and analyzing the linear relationship between finger and Length and the capacitance value, specifically including:

[0046] S11. According to the parameters of the 1.8V MOS transistor, construct a MOS transistor circuit model in the simulation circuit design software, set different Vgs voltage values, and perform multiple simulations through the circuit simulation software to obtain the capacitance value data of the MOS transistor at different Vgs voltages;

[0047] S12. Organize the obtained capacitance value data, plot a curve graph of the capacitance value versus the Vgs voltage through data analysis software, and analyze the linear relationship between the finger and Length parameters of the MOS transistor and the capacitance value according to the plotted curve graph to obtain the influence law of finger and Length on the capacitance value;

[0048] S13. For the capacitance value data at different Vgs voltages, use the curve fitting algorithm to judge the trend of the capacitance value changing with the Vgs voltage, obtain the mathematical model between the capacitance value and the Vgs voltage, and then use machine learning algorithms such as support vector machines or neural networks to train the mapping relationship model between the capacitance value and the Vgs voltage, finger, Length and other parameters to predict the capacitance value of the MOS transistor under any parameter combination;

[0049] S14. According to the established mathematical model and machine learning model, optimize the design of the finger and Length parameters of the MOS transistor to obtain the optimal capacitance value and linear characteristics while meeting the circuit performance requirements.

[0050] Specifically, by constructing a simulation circuit and setting different Vgs voltage values for multiple simulations, recording the capacitance value changes of the 1.8V MOS transistor at different voltages, generating a detailed capacitance value data table, and forming Pcell parameters associated with geometric parameters. These Pcell parameters are integrated into the layout design tool to achieve fast calculation and visualization in the layout, improving the design efficiency and accuracy. At the same time, by analyzing the linear relationship between finger and Length and the capacitance value, and the trend of the capacitance changing with the voltage, the design of the finger and Length parameters of the MOS transistor is optimized to ensure obtaining the optimal capacitance value and linear characteristics while meeting the circuit performance requirements.

[0051] S2. According to the simulation results, calculate the capacitance change slope of the MOS transistor at different voltages, generate the reference capacitance C1, calculate the capacitances C2 and C at different Lengths and fingers, and generate the capacitance data table of the MOS transistor;

[0052] Specifically, based on the simulation result data, through the formula Scan the capacitances of different voltages, different transistor parameters, and different transistor types. According to the scanned result data, calculate the capacitance change slope of the MOS transistor of the same size at different voltages, convert it into a linear result to obtain the reference capacitance C1, and select the reference Length and finger. Calculate the capacitance C2 at different Lengths according to the slope of Length, and then calculate the capacitance C at different fingers to generate the capacitance data table of the MOS transistor;

[0053] Furthermore, generate the capacitance data table of the MOS transistor, specifically including:

[0054] According to the simulation result data, extract information such as voltage parameters, transistor parameters, and transistor types, establish a multi-dimensional array to store the simulated capacitance data under different conditions, traverse the voltages and transistor parameters of different transistor types, call the capacitance calculation formula, obtain the capacitance under the corresponding conditions, and update it to the corresponding multi-dimensional array;

[0055] Select the MOS transistor data of the same size from the multi-dimensional array, perform linear fitting on the capacitance data at different voltages, obtain the slope of the capacitance change with voltage under the corresponding size, then select the reference Length and finger as the initial values, and extrapolate and calculate the capacitance at zero voltage as the reference capacitance C1 according to the capacitance change slope under this size;

[0056] Among them, starting from the reference Length, apply the Length slope formula, traverse different Lengths, calculate the capacitance C2 under the corresponding conditions, and update the Length-capacitance mapping table; starting from the reference finger, traverse different values of finger, call the mapping formula between the exponent and the capacitance, calculate the capacitance C under different finger values, and continuously update the finger-capacitance mapping table;

[0057] Combine the Length-capacitance mapping table and the finger-capacitance mapping table to generate a capacitance data table covering different Lengths, fingers, and voltage conditions.

[0058] For example, for the voltage range from 1V to 1.1V, the calculated capacitance slope is 20, and the capacitance at 1V is 275.2 fF. Therefore, the reference capacitance C1 can be expressed as: ; Assume that the designed MOS transistor length L is not equal to 0.15u. According to the change between the slopes of 1644.7 and 1657.6, the capacitance value C2 at different Lengths can be calculated. The formula is: , where VB is the capacitance difference of the MOS transistor. The capacitance value C at different fingers is calculated. The formula is:

[0059] ; where

[0060] 3.8378 and 3.8639 are the slopes obtained from the simulation results, and 72 is the reference finger for the simulation.

[0061] Among them, the MOS transistor capacitance is the capacitance formed by using the gate, source, and drain of the MOS transistor. When the source and drain are connected together, a capacitance is formed between the gate and the source-drain. The MOM capacitance is the capacitance formed by using the dielectric layer between metal layers, and it consists of multiple metal layers and the dielectric layers between them. The size of the capacitance mainly depends on the area of the metal layer, the number of layers, and the dielectric constant of the dielectric layer.

[0062] Specifically, through detailed data analysis and mathematical modeling, a capacitance value data table of the MOS transistor is generated. This data table covers the capacitance value changes under different voltages, different transistor parameters, and different transistor types. This data table not only provides the reference capacitance value C1, but also obtains the capacitance values C2 and C at different Length and finger values through slope calculation, thus providing an accurate reference for the design and optimization of the MOS transistor capacitance. In addition, through the comparison and integration with the MOM capacitance, the design of the capacitance module is further optimized, the efficiency and accuracy of the layout design are improved, and it is ensured that the capacitance value can be quickly and accurately evaluated and adjusted under different design conditions to meet the circuit performance requirements.

[0063] S3. According to the capacitance value data table of the MOS transistor, associate it with geometric parameters to form Pcell parameters for rapid calculation and visualization in the layout;

[0064] Among them, Pcell (Parametric Cell) is a parametric unit in semiconductor design, used to generate circuit elements with specific electrical characteristics and geometric shapes. Pcell technology allows designers to generate circuit elements with different sizes and characteristics by adjusting parameters, thereby improving design efficiency and flexibility.

[0065] Furthermore, according to the capacitance value data table of the MOS transistor, associate it with geometric parameters to form Pcell parameters, specifically including:

[0066] Obtain the capacitance data sheet of the MOS transistor, extract the corresponding relationship data between the capacitance and geometric parameters, establish a Pcell parametric model of the MOS transistor capacitance according to the extracted corresponding relationship data between the capacitance and geometric parameters, and perform an associated mapping between the capacitance and geometric parameters; in the Pcell parametric model, set the geometric parameters as input variables and the capacitance as output variables, establish a parametric calculation formula, integrate the Pcell parametric model into the layout design tool, realize the real-time associated calculation of the geometric parameters and the capacitance change slope, and according to the Pcell parametric model, realize the visual adjustment of the geometric parameters. During the layout design process, by calling the Pcell parametric model, quickly calculate the capacitance of the MOS transistor. When the capacitance of the MOS transistor needs to be adjusted in the layout design, according to the geometric parameters of the adjusted MOS transistor capacitance, quickly calculate the capacitance of the adjusted MOS transistor and update the visualization of the MOS transistor capacitance in the layout in real time.

[0067] Specifically, by forming Pcell parameters associated with geometric parameters, the rapid calculation and visualization of MOS transistor capacitance in layout design are realized. Specifically, using the capacitance data sheet of the MOS transistor, a Pcell parametric model is established, and an associated mapping is performed between the capacitance and geometric parameters (such as Length and finger). This model is integrated into the layout design tool, enabling designers to adjust geometric parameters in real time during the design process and immediately see the corresponding capacitance changes, thereby quickly optimizing the design and improving design efficiency and accuracy. This real-time calculation and visualization function greatly simplifies the layout design process and ensures the flexibility and reliability of the design.

[0068] S4. According to the simulation result data, select the metal layer of Metal4 and above, and calculate the capacitance value per unit area of the MOM capacitor in combination with the process conditions, and calculate the overall metal capacitance according to the designed metal area;

[0069] Specifically, according to the simulation result data, select the metal layer of Metal4 and above, extract the capacitance value of the metal and combine it with the capacitance value of the MOM capacitor under the same process conditions to calculate the capacitance value per unit area. In the Pcell model of the MOM capacitor, according to the designed metal area, calculate the overall metal capacitance value through calculation to perform a rapid calculation of the metal capacitance.

[0070] Among them, the same conditions of the MOM capacitor are the capacitance values calculated by the Pcell model of the MOM capacitor under the process conditions such as the same metal layer, the dielectric material between metal layers, the thickness of the metal layer, and the spacing of the metal layer.

[0071] Further, after forming Pcell parameters in association with geometric parameters, it further includes: obtaining the capacitance values of MOM capacitors at different metal levels, analyzing the relationship between the capacitance values of MOM capacitors, metal levels, and areas, establishing a Pcell model for MOM capacitors, where the Pcell model includes the mapping relationship between metal levels, areas, and capacitance values, and during layout design, according to the metal level and area parameters of the MOM capacitor, using the Pcell model of the MOM capacitor to quickly calculate the corresponding capacitance value of the MOM capacitor.

[0072] The rapid calculation and visualization of MOS transistor capacitors and MOM capacitors achieved through the above Pcell model greatly improve the efficiency of layout design and shorten the design cycle.

[0073] Further, calculating the overall metal capacitance according to the designed metal area specifically includes: obtaining metal levels above Metal4, extracting the corresponding metal capacitance values, obtaining capacitance value data under the same process conditions as the MOM capacitor, combining the extracted metal capacitance values to calculate the capacitance value per unit area, according to the metal area designed in the Pcell model, obtaining the corresponding capacitance value per unit area through look-up table or interpolation methods, multiplying the metal area by the capacitance value per unit area to obtain the overall metal capacitance, and then using the overall metal capacitance as a parameter of the MOM capacitor to quickly calculate the overall capacitance value to obtain the calculation result.

[0074] Further, according to the calculation result, it further includes: analyzing the capacitance characteristics of different metal levels (such as above Metal4), selecting the optimal combination of metal levels; precisely adjusting the metal area according to the design requirements, using the calculation method of MOS transistors to quickly obtain the corresponding capacitance value, obtaining the optimized metal level, area, and the corresponding capacitance value, and using the optimized values as input parameters of the Pcell model of the MOM capacitor to perform rapid and accurate calculation of the metal capacitance and visually display it in the layout, ensuring that the capacitance value calculation of the MOM capacitor is more accurate and the layout display is clearer, thereby further enhancing the visualization effect and design efficiency of the MOM capacitor.

[0075] Specifically, by selecting metal levels above Metal4 and combining the capacitance value data under process conditions, the capacitance value per unit area of the MOM capacitor is calculated, and the overall metal capacitance is quickly calculated according to the designed metal area in the Pcell model. This process not only realizes the rapid calculation and visualization of the MOM capacitor, but also optimizes the selection of metal levels and areas by analyzing the capacitance characteristics of different metal levels, ensuring that the capacitance value calculation of the MOM capacitor is more accurate. Finally, using the optimized parameters as the input of the Pcell model further enhances the visualization effect and design efficiency of the MOM capacitor and significantly shortens the layout design cycle.

[0076] S5. Define the calculation range of POLY density based on the capacitance value of the MOS transistor and the overall metal capacitance value, calculate the POLY density in real time, reduce the POLY density ratio by adjusting the layout parameters, and determine whether it meets the layout CMP requirements;

[0077] Specifically, based on the capacitance value of the MOS transistor and the overall metal capacitance value, define the calculation range of POLY density. Calculate the occupancy ratio of POLY within the BOX range starting from the lower left corner of POLY and ending at the upper right corner of POLY, and use the POLYDn requirement of the process. During the layout design of the layout, calculate the POLY density in real time to ensure that it meets the process requirements. By adjusting the layout parameters of the MOS transistor (such as nfinSpace), without changing the MOS capacitance value, reduce the POLY density ratio, quickly determine whether it meets the layout CMP requirements, avoid redrawing due to excessive POLY density resulting in insufficient layout area in the later stage, and reduce the workload; where the POLY Dn requirement is <45%.

[0078] Among them, POLY density (polysilicon density) refers to the area occupancy ratio of the polysilicon (POLY) layer in a specific area, expressed as a percentage, and the calculation formula is:

[0079] ;

[0080] In semiconductor manufacturing, POLY density is an important process parameter because it directly affects the performance, reliability, and manufacturing yield of the chip. POLY Dn is expressed as a percentage and specifies the maximum allowable area occupancy ratio of the polysilicon layer in a specific area, where POLY Dn < 45% means that the area occupancy ratio of the polysilicon layer cannot exceed 45%; nfinSpace is a parameter used to control the polysilicon (POLY) layer spacing in the FinFET process, referring to the minimum spacing between the polysilicon layers of adjacent FinFET transistors.

[0081] Furthermore, obtain the capacitance values of MOS transistors and metal capacitors, and determine the calculation range of POLY density as the BOX range starting from the lower left corner of POLY and ending at the upper right corner; within the defined BOX range, calculate the area of the POLY layer, and at the same time, calculate the total area of the BOX range. This area is the total area of the region where the POLY layer is located, including the area of the POLY layer and other layers; according to the ratio of the POLY area within the calculation range to the total BOX area, calculate the proportion of POLY density in real time; then obtain the required threshold value of POLY Dn for the process, and judge whether the calculated POLY density meets the requirements; when the POLY density exceeds the threshold, reduce the POLY density while keeping the MOS capacitance value unchanged by adjusting MOS transistor layout parameters such as nfinSpace; repeat the calculation of the proportion of POLY density and the judgment of whether POLY Dn meets the required threshold until the POLY density meets the CMP required threshold; then, according to the adjusted layout parameters, determine whether the layout area is sufficient; when the layout area is insufficient, continue to adjust the layout parameters until the layout area meets the requirements, and output the final layout parameters and layout area.

[0082] Specifically, by defining the calculation range of POLY density and calculating POLY density in real time during the layout design of the layout, ensure that it meets the process requirements (POLY Dn requirement < 45%). When the POLY density exceeds the threshold, reduce the POLY density ratio without changing the MOS capacitance value by adjusting the layout parameters of the MOS transistor (such as nfinSpace), and quickly judge whether it meets the layout CMP requirements. This process effectively avoids the problem of redrawing due to insufficient layout area caused by too high POLY density, reduces the workload, and improves the efficiency and reliability of the layout design.

[0083] S6. Integrate the calculation results of MOS transistor capacitance and MOM capacitance into a Pcell to form a complete capacitor module. In the layout design, by calling the Pcell parameters, quickly generate the corresponding capacitor layout according to the design requirements, perform automatic layout and wiring of the capacitor module, and perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification on the generated Pcell layout to ensure that the layout meets the process requirements and there are no design errors. By comparing with the test results, verify the accuracy and reliability of the Pcell layout to ensure that its performance in actual applications meets the design expectations.

[0084] Further, form the calculation results of the MOS transistor capacitor and the MOM capacitor into a complete capacitor module. According to the design requirements, determine the parameter specifications of the capacitor module, including capacitance value, area, shape, etc., as the input parameters of the Pcell. By calling the corresponding capacitor Pcell and passing in the design parameters, the Pcell automatically generates a capacitor layout that meets the requirements according to the preset layout and routing algorithm and design rules;

[0085] Perform a design rule check (DRC) on the generated capacitor layout to check whether the layout complies with the design specifications of the process technology. When the check fails, adjust the Pcell parameters and regenerate the layout until the DRC check passes;

[0086] Then, perform an LVS circuit layout comparison and verification on the generated capacitor layout and the schematic diagram to check whether the electrical connections of the layout and the schematic diagram are consistent. When the LVS verification fails, return to modify the Pcell parameters and regenerate the layout until the LVS verification passes.

[0087] Specifically, in the layout design, by calling the Pcell to quickly generate the capacitor layout, the design efficiency can be greatly improved, and the workload of manual layout and routing can be reduced. At the same time, the built-in layout and routing algorithm of the Pcell can ensure the layout quality and consistency. Performing a DRC design rule check and an LVS circuit layout comparison and verification on the generated Pcell layout can timely discover problems in the layout design, improve the correctness and reliability of the design, and avoid errors in later plate making and production. Through the Pcell parametric design, the rapid iteration and optimization of the capacitor module can be realized. By adjusting the Pcell parameters, capacitor layouts with different specifications and performances can be conveniently generated to meet different design requirements.

[0088] In this embodiment, in the construction of the simulation circuit and data acquisition, by constructing the simulation circuit and setting different Vgs voltage values for simulation, record the capacitance value changes of the 1.8V MOS transistor at different voltages, draw a curve graph and analyze the linear relationship between finger and Length and the capacitance value, as well as the trend of capacitance change with voltage at different voltages; generate the capacitance data table. According to the simulation result data, scan out the capacitance values of different voltages, different transistor parameters, and different transistor types through the formula, calculate the capacitance change slope of the MOS transistor with the same size at different voltages, convert it into a linear result to obtain the reference capacitance C1, and calculate the capacitance C2 at different Lengths and the capacitance C at different fingers. This enables the intuitive evaluation of the MOS transistor capacitance in the pre-simulation stage, is beneficial to the layout area evaluation, and solves the problem of difficult evaluation in the pre-simulation stage caused by the capacitance value change of the MOS transistor.

[0089] Then, the capacitance value change slope is derived from the simulation data of the calculation results of the MOS transistor capacitance to form Pcell parameters associated with geometric parameters, realizing fast calculation and visualization in the layout; at the same time, the calculation of the MOM capacitance forms Pcell parameters associated with the metal layer and area by extracting the capacitance value of the metal layer and combining process conditions, realizing fast calculation and visualization in the layout; for the fast calculation of the metal capacitance, according to the simulation result data, the metal layer of Metal4 and above is selected, and the capacitance value per unit area is calculated by extracting the capacitance value of Metal C and combining the capacitance value under the same conditions of the process MOM capacitance. The overall metal capacitance is calculated according to the designed metal area in the Pcell, realizing the fast calculation of the metal capacitance; the calculated metal capacitance is associated with parameters such as the selection of the metal layer and the metal area to form Pcell parameters. In the layout design, by selecting different metal layers and adjusting the metal area, the corresponding capacitance value can be quickly obtained using the calculation method of the MOS transistor and visually displayed in the layout, realizing the visualization of the MOM capacitance; this not only avoids the problem that the metal wire pitch affects the PV verification due to the change of the MOM capacitance voltage difference, but also reduces the situations of connection short - circuit or DRC errors caused by the change of the positive and negative plate positions, and at the same time avoids the DRC errors caused by the possible addition of the voltage identification layer when fabricating the MOM capacitance, solving a series of problems in the MOM capacitance design.

[0090] In addition, it includes POLY density optimization. According to the formed Pcell parameters, the calculation range of the POLY density is defined. During the layout design layout, the POLY density is calculated in real - time to ensure that it meets the process requirements. By adjusting the layout parameters of the MOS transistor, without changing the MOS capacitance value, the POLY density ratio is reduced, quickly judging whether it meets the layout CMP requirements, avoiding redrawing due to excessive POLY density resulting in insufficient layout area in the later stage and reducing the workload; this effectively solves the problem that the POLY density is prone to exceed the required range when filtering capacitors are used on a large scale, ensures the rationality during the layout design layout, avoids redrawing the layout due to insufficient layout area in the later stage, and increases the workload.

[0091] Capacitor module integration and verification. Integrate the calculation results of MOS transistor capacitors and MOM capacitors into a Pcell to form a complete capacitor module. In the layout design, by calling the Pcell parameters, the corresponding capacitor layout can be quickly generated according to the design requirements, and automatic placement and routing of the capacitor module can be carried out. Perform DRC and LVS verification on the generated Pcell layout to ensure that the layout meets the process requirements and there are no design errors. By comparing with the test results, verify the accuracy and reliability of the Pcell layout to ensure that its performance in actual applications meets the design expectations; this ensures the correctness and reliability of the layout design and avoids subsequent problems caused by layout design errors. The whole process from obtaining simulation data to layout design and verification is closely linked and progressive, and finally realizes an efficient and accurate capacitor layout design, effectively solving many problems mentioned in the background technology.

[0092] The above are only preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes, but as long as they do not depart from the technical content of the present invention, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for generating a visualized Pcell layout of MOS and MOM capacitors, characterized in that: The steps include: The capacitance change of 1.8V MOS tube under different Vgs voltages is recorded through simulation circuit, and a curve is drawn to analyze the linear relationship between finger, length and capacitance. According to the simulation results, the capacitance change slope of the MOS tube under different voltages is calculated to generate the reference capacitance C1, the capacitance C2 and C under different lengths and fingers are calculated, and the capacitance data table of the MOS tube is generated; According to the capacitance data table of MOS tube, it is associated with geometric parameters to form Pcell parameters, and then quickly calculate and visualize them in the layout; According to the simulation result data, select Metal4 and above metal levels, calculate the MOM capacitor capacitance per unit area based on the process conditions, and calculate the overall metal capacitance based on the designed metal area; Define the POLY density calculation range based on the MOS tube capacitance and the overall metal capacitance, calculate POLYdensity in real time, adjust the layout parameters to reduce the POLY density ratio, and determine whether the layout meets the CMP requirements; Wherein, after the Pcell parameters are formed by associating with the geometric parameters, the method further comprises: obtaining the capacitance of the MOM capacitors at different metal levels, analyzing the relationship between the capacitance of the MOM capacitor and the metal level and area, establishing a Pcell model of the MOM capacitor, wherein the Pcell model includes a mapping relationship between the metal level, area and capacitance, and during layout design, according to the metal level and area parameters of the MOM capacitor, using the Pcell model of the MOM capacitor, calculating the capacitance of the corresponding MOM capacitor; Among them, the overall metal capacitance is calculated according to the designed metal area, including: obtaining Metal4 and above metal levels, extracting the corresponding metal capacitance, obtaining the capacitance data under the same process conditions as the MOM capacitor, combining the extracted metal capacitance, and calculating the capacitance per unit area. According to the metal area designed in the Pcell model of the MOM capacitor, the corresponding capacitance per unit area is obtained by table lookup or interpolation, the metal area is multiplied by the capacitance per unit area to obtain the overall metal capacitance, and then the overall metal capacitance is used as a parameter of the MOM capacitor to quickly calculate the overall capacitance and obtain the calculation result.

2. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: The capacitance change of 1.8V MOS tube under different Vgs voltages is recorded through simulation circuit, and a curve is drawn to analyze the linear relationship between finger, length and capacitance, including: According to the parameters of the 1.8V MOS tube, a MOS tube circuit model is constructed in the simulation circuit design software, and different Vgs voltage values ​​are set. Multiple simulations are performed through the circuit simulation software to obtain the capacitance value data of the MOS tube under different Vgs voltages; The acquired capacitance value data is sorted out, and a curve graph of capacitance value and Vgs voltage is drawn through data analysis software. According to the drawn curve graph, the linear relationship between the finger and Length parameters of the MOS tube and the capacitance value is analyzed to obtain the influence of finger and Length on the capacitance value. For the capacitance value data under different Vgs voltages, the trend of capacitance value changing with Vgs voltage is judged by curve fitting algorithm, and the mathematical model between capacitance value and Vgs voltage is obtained. Then, the mapping relationship model between capacitance value and Vgs voltage, finger, and Length parameters is trained by machine learning algorithm to predict the capacitance value of MOS tube under any parameter combination. According to the established mathematical model and machine learning model, the finger and length parameter design of the MOS tube are optimized to obtain the optimal capacitance value and linear characteristics while meeting the circuit performance requirements.

3. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: Generate the capacitance data table of MOS tube, including: According to the simulation result data, the voltage parameters, tube parameters and tube type information are extracted, and a multidimensional array is established to store the simulated capacitance data under different conditions. The voltages and tube parameters of different tube types are traversed, and the capacitance calculation formula is called to obtain the capacitance under the corresponding conditions, and the capacitance is updated to the corresponding multidimensional array. From the multidimensional array, select the MOS tube data of the same size, perform linear fitting on the capacitance data under different voltages, and obtain the slope of the capacitance change with voltage under the corresponding size. Then select the reference Length and finger as the initial value, and according to the capacitance change slope under the size, extrapolate and calculate the capacitance under zero voltage as the reference capacitance C1; Among them, starting from the reference Length, applying the Length slope formula, traversing different Lengths, calculating the capacitance C2 under the corresponding conditions, and updating the Length-capacitance mapping table; starting from the reference finger, traversing different values ​​of finger, calling the mapping formula of index and capacitance, calculating the capacitance C under different finger values, and continuously updating the finger-capacitance mapping table; The length-capacitance mapping table and the finger-capacitance mapping table are combined to generate a capacitance data table covering different lengths, fingers, and voltage conditions.

4. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: According to the capacitance data table of MOS tube, Pcell parameters are formed by associating with geometric parameters, including: Obtain the capacitance data table of the MOS tube, extract the corresponding relationship data between the capacitance and the geometric parameters, establish the Pcell parameterized model of the MOS tube capacitor according to the extracted corresponding relationship data between the capacitance and the geometric parameters, and associate and map the capacitance and the geometric parameters; in the Pcell parameterized model, set the geometric parameters as input variables and the capacitance as output variables, establish a parameterized calculation formula, integrate the Pcell parameterized model into the layout design tool, perform real-time association calculation between the geometric parameters and the capacitance change slope, and perform visual adjustment of the geometric parameters according to the Pcell parameterized model. In the layout design process, the MOS tube capacitance is calculated by calling the Pcell parameterized model. When the layout design needs to adjust the MOS tube capacitance, the capacitance of the adjusted MOS tube capacitance is calculated according to the geometric parameters of the adjusted MOS tube capacitance, and the visualization of the MOS tube capacitance is updated in real time in the layout.

5. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: According to the calculation results, it also includes: analyzing the capacitance characteristics of different metal levels and selecting the optimal metal level combination; adjusting the metal area according to design requirements, using the MOS tube calculation method to obtain the corresponding capacitance value, and obtaining the optimized metal level, area and corresponding capacitance value, and using the optimized value as the input parameter of the Pcell model of the MOM capacitor to calculate the metal capacitance and display it intuitively in the layout.

6. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: Define the POLY density calculation range, calculate the POLY density in real time, adjust the layout parameters to reduce the POLYdensity ratio, and judge whether it meets the layout CMP requirements, including: obtain the MOS tube capacitance and metal capacitance, determine the POLYdensity calculation range as the BOX range with the lower left corner of the POLY as the starting point and the upper right corner as the end point, calculate the area of ​​the POLY layer within the defined BOX range, and at the same time, calculate the total area of ​​the BOX range; calculate the POLY density ratio in real time according to the ratio of the POLY area within the calculation range to the total BOX area; then obtain the POLY Dn requirement threshold of the process to judge whether the calculated POLY density meets the requirements; when the POLY density exceeds the threshold, adjust the MOS tube layout parameters to reduce the POLY density while keeping the MOS capacitance unchanged; repeatedly calculate the POLY density ratio and judge whether the POLY Dn meets the requirement threshold until the POLY density meets the CMP requirement threshold; then determine whether the layout area is sufficient according to the adjusted layout parameters; when the layout area is insufficient, continue to adjust the layout parameters until the layout area meets the requirements, and output the final layout parameters and layout area.

7. A MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, characterized in that: Also includes: The calculation results of MOS tube capacitance and MOM capacitance are integrated into a Pcell to form a complete capacitance module. In the layout design, by calling the Pcell parameters, the corresponding capacitance layout is quickly generated according to the design requirements, and the capacitance module is automatically laid out and wired. The generated Pcell layout is checked for design rules and compared with the circuit layout to ensure that the layout meets the process requirements.

8. A method for generating a MOS and MOM capacitor visualization Pcell layout according to claim 7, characterized in that: The calculation results of MOS tube capacitance and MOM capacitance are used to form a complete capacitance module. According to the design requirements, the parameter specifications of the capacitance module are determined and used as the input parameters of Pcell. By calling the corresponding capacitance Pcell, the design parameters are passed in. The Pcell automatically generates a capacitance layout that meets the requirements according to the preset layout and routing algorithm and design rules. Perform a design rule check on the generated capacitor layout to check whether the layout meets the design specifications of the process. If the check fails, adjust the Pcell parameters to regenerate the layout until the DRC check passes. Then compare the generated capacitor layout with the schematic diagram for LVS circuit layout verification to check whether the electrical connections of the layout and the schematic diagram are consistent. If the layout comparison verification fails, return to modify the Pcell parameters and regenerate the layout until the layout comparison verification passes.

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