Write operation sequential logic circuit and memory

Abstract

The invention provides a write operation sequential logic circuit, which identifies the last effective falling edge of a data sampling pulse according to a write operation instruction, a system clock and the data sampling pulse, and controls the circuit to be self-locked to latch multi-bit parallel data from a parallel data generation module after the falling edge samples the data. And the write operation instruction is released until the next write operation instruction arrives, so that the risk of data loss caused by too small duration (twpst) of a sampled signal after writing can be completely avoided.

Description

Technical Field

[0001] The invention relates to a write operation sequential logic circuit, in particular to a write operation sequential logic circuit used for memories such as DDR3. Background Art

[0002] Regarding memory, it can be divided into read-only memory (ROM) and random read-write memory (RAM) according to the read-write function. The content stored in the read-only memory is fixed and can only be read but not written; while the random read-write memory is a memory that can be read and written. In addition, the random read-write memory can be divided into SRAM (static) and DRAM (dynamic). Among them, SRAM includes SDR SRAM, DDR SRAM, QDR SRAM, ZBT SRAM, etc.; DRAM includes SDRAM, DDR DRAM, RDRAM.

[0003] DRAM is a clock synchronous memory that operates based on the clock signal sent by the processor. The command signal used to define the action and the address signal used to specify the memory cell are sent in parallel and synchronized with the rising edge of the clock. In DDR data transmission, the DQ Strobe (DQS) signal becomes the reference to replace the clock, and data is transmitted through the DQ bus. The command signal and address signal are only synchronized to the rising edge of the clock, while the data signal is synchronized to the rising and falling edges of DQS. The clock, command signal, and address signal are input unidirectionally from the processor to the DRAM, while DQS and DQ are bidirectional, input to the DRAM when writing and output from the DRAM when reading.

[0004] In a write operation, after completing the sampling of the last data, DQS (data sampling pulse) needs to maintain the differential signal for a period of time before the write operation is allowed to be completely completed. This period of time is defined as twpst, which is the duration of the write postamble signal. Write Postamble is used to help the receiver perform data verification and reconstruction. Its main function is to ensure the integrity and accuracy of data transmission and prevent transmission errors caused by various factors. Summary of the invention

[0005] However, the minimum twpst defined by the DDR3 technical specification is only 0.3 clock cycles, or a minimum of 281.4ps. After this period of time, the data sampling pulse is no longer constrained. If the data sampling pulse deviates significantly from the intermediate level at this time, the data sampling pulse clock will sample the data (DQ) again, which will cause the latched valid data to be lost. Figure 5The calculation process of twpst is described. If this time is exceeded, DQS-DQSb will no longer be strictly constrained after returning to 0V. Figure 5 It is a schematic diagram showing the system clock and data sampling pulse in the write operation timing logic circuit and the duration time (twpst) of the write post-sampling signal (Write Postamble).

[0006] In a complete write operation, after the data is latched by the data sampling pulse, it also needs to be synchronized to the CK (system clock) domain. Figure 3 For the traditional circuit implementation, Figure 4 Describes the timing relationship between data and data sampling pulse, clock, and write operation control instructions. Taking 4-bit data as an example, all data will be latched by the last falling edge of DQS when passing through the last latch, and wait for the CK domain control signal to latch synchronization.

[0007] Figure 3 1 is a circuit diagram showing the specific structure of a write operation sequential logic circuit in the prior art. Figure 4 1 is a timing diagram showing the timing of each signal in a write operation timing logic circuit of the prior art. Figure 3 and Figure 4 It can be seen that if DQS-DQSb deviates significantly after returning to 0V, the data sampling pulse will be resampled. However, at this time, the 4th bit of data has ended, and the valid data will be incorrectly overwritten. The CK domain needs to complete data sampling or synchronization within the minimum twpst time, that is, within 281.4p. Considering the existence of tdqss (the time of the DQS rising edge relative to the CK rising edge), this is difficult to do.

[0008] The present invention is completed in view of the above situation, and its purpose is to provide a write operation timing logic circuit, which identifies the last valid falling edge of the data sampling pulse according to the write operation instruction, the system clock and the data sampling pulse, and controls the circuit to self-lock after sampling the data on the falling edge to latch the multi-bit parallel data from the parallel data generation module, and will not release it until the next write operation instruction arrives, thereby completely avoiding the risk of data loss caused by too short a duration (twpst) of the write post-sampling signal (Write Postamble).

[0009] Technical solutions to technical problems

[0010] In order to solve the above problem, the write operation sequential logic circuit involved in the first aspect of the present invention includes:

[0011] A parallel data generation module, which generates multi-bit parallel data according to the input serial data and data sampling pulses;

[0012] a data latch module, which is connected to the parallel data generation module, latches the multi-bit parallel data from the parallel data generation module according to a write operation instruction, a system clock and the data sampling pulse, and generates a system clock domain synchronization signal; and

[0013] A system clock synchronization module is connected to the data latch module, and synchronizes the latched multi-bit parallel data to the system clock domain according to the latched multi-bit parallel data and the system clock domain synchronization signal.

[0014] Furthermore, the data latch module generates a data latch signal according to a write operation instruction, a system clock and the data sampling pulse, and latches the multi-bit parallel data according to the data latch signal.

[0015] Furthermore, the pulse width of the data latch signal is smaller than a specified width.

[0016] Further, the data latch module includes a first trigger unit, a first trigger, a multi-bit latch, a first inverting unit, a second inverting unit, a third inverting unit, an AND gate unit, and a first inverter.

[0017] The first trigger unit is connected to one end of the first inverting unit, one end of the second inverting unit, and one end of the third inverting unit, and the write operation instruction and the system clock are input to the first trigger unit.

[0018] The data input terminal of the first trigger is connected to the other end of the first inverting unit, the reset terminal of the first trigger is connected to the AND gate unit, the data output terminal of the first trigger is connected to one end of the first inverter, and a data sampling pulse is input to the clock input terminal of the first trigger.

[0019] The clock input end of the multi-bit latch is connected to the other end of the first inverter and the AND gate unit, the data output end of the multi-bit latch is connected to the data input end of the system clock synchronization module, and the multi-bit parallel data is input to the data input end of the multi-bit latch.

[0020] The other end of the second inverting unit is connected to the AND gate unit.

[0021] The other end of the third inverting unit is connected to the clock input end of the system clock synchronization module.

[0022] Furthermore, the first trigger unit generates a write operation control signal that delays the write operation instruction by a specified number of clock cycles according to the write operation instruction and the system clock, and outputs the signal to the first inverting unit.

[0023] The first trigger unit generates a control signal for turning on the first trigger before the last valid falling edge of the data sampling pulse arrives according to the write operation instruction and the system clock, and outputs the control signal to the second inverting unit.

[0024] The first trigger unit generates the system clock domain synchronization signal according to the write operation instruction and the system clock, and outputs the system clock domain synchronization signal to the third inverting unit.

[0025] Furthermore, the first inverting unit includes 8 inverters connected in series.

[0026] The second inverting unit includes 9 inverters connected in series.

[0027] The third inverting unit includes eight inverters connected in series.

[0028] Furthermore, the AND gate unit includes a first AND gate, a second AND gate, and a third AND gate.

[0029] The output end of the first AND gate is connected to the first input end of the second AND gate, the first input end of the first AND gate is connected to the other end of the second inverting unit, and the second input end of the first AND gate is connected to the first trigger unit.

[0030] The second input terminal of the second AND gate is connected to the output terminal of the third AND gate, and the output terminal of the second AND gate is connected to the first input terminal of the third AND gate and the reset terminal of the first trigger.

[0031] The second input terminal of the third AND gate is connected to the clock input terminal of the multi-bit latch.

[0032] Furthermore, the first trigger unit includes at least one trigger.

[0033] Furthermore, the system clock synchronization module is a multi-bit trigger.

[0034] The memory involved in the second aspect of the present invention includes the above-mentioned write operation sequential logic circuit.

[0035] Effects of the Invention

[0036] According to the write operation timing logic circuit of the present invention, the last valid falling edge of the data sampling pulse is identified according to the write operation instruction, the system clock and the data sampling pulse, and after the falling edge samples the data, the control circuit is self-locked to lock the multi-bit parallel data from the parallel data generation module, and will not release it until the next write operation instruction arrives, thereby completely avoiding the risk of data loss caused by the duration (twpst) of the write post sampling signal (Write Postamble) being too short. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 1 is a circuit diagram showing an example of a specific structure of a write operation sequential logic circuit according to an embodiment of the present invention.

[0038] Figure 2 1 is a timing chart showing an example of the timing of each signal in the write operation sequential logic circuit according to the embodiment of the present invention.

[0039] Figure 3 1 is a circuit diagram showing the specific structure of a write operation sequential logic circuit in the prior art.

[0040] Figure 4 FIG. 1 is a timing diagram showing the timing of each signal in a write operation sequential logic circuit of the prior art.

[0041] Figure 5 It is a schematic diagram showing the system clock and data sampling pulse in the write operation timing logic circuit and the duration time (twpst) of the write post-sampling signal (Write Postamble).

[0042] Description of symbols

[0043] 101 parallel data generation module

[0044] 102 data latch module

[0045] 103 system clock synchronization module

[0046] 1021 first inverting unit

[0047] 1022 Second Inverting Unit

[0048] 1023 Third Inverting Unit

[0049] 1024 AND gate units DETAILED DESCRIPTION

[0050] The present invention is described in detail below in conjunction with the accompanying drawings and specific implementations. This implementation is implemented based on the technical solution of the present invention, and a detailed implementation and specific operation process are given, but the protection scope of the present invention is not limited to the following implementation.

[0051] For ease of description, spatially relative terms, such as "under," "below," "down," "above," "on," etc., may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation other than the orientation shown in the figures. For example, if the device in the figure is turned over, elements described as being "under" or "below" other elements or features will be oriented "above" the other elements or features.

[0052] Unless otherwise defined, the terms used herein have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. The terms should be understood to have the same meanings as those in the context of the relevant technology and should not be understood in an idealized or overly formal sense unless explicitly defined in this manner.

[0053] <Structure of sequential logic circuit for write operation>

[0054] Hereinafter, with reference to the accompanying drawings, the specific structure of the write operation sequential logic circuit involved in the embodiment of the present invention will be described in detail.

[0055] Figure 1 1 is a circuit diagram showing an example of a specific structure of a write operation sequential logic circuit according to an embodiment of the present invention.

[0056] like Figure 1 As shown, as an example, the write operation sequential logic circuit 10 involved in the embodiment of the present invention includes a parallel data generation module 101, a data latch module 102, and a system clock synchronization module 103. Taking BL4 (4-bit data read and write) as an example, the system clock synchronization module 103 can be a multi-bit trigger DFF6<3:0>.

[0057] As an example, the parallel data generation module 101 generates multi-bit parallel data DQ0, DQ1, DQ2, and DQ3 according to the input serial data DQ and the data sampling pulse DQS / DQSb. The data latch module 102 is connected to the parallel data generation module 101, and latches the multi-bit parallel data from the parallel data generation module 101 according to the write operation instruction Write Command, the system clock CK, and the data sampling pulse DQS / DQSb, and generates a system clock domain synchronization signal SCAS_WT. The system clock synchronization module 103 is connected to the data latch module 102, and synchronizes the latched multi-bit parallel data to the system clock domain according to the latched multi-bit parallel data DQ_D0, DQ_D1, DQ_D2, and DQ_D3 and the system clock domain synchronization signal SCAS_WT.

[0058] Specifically, as an example, the data latch module 102 includes a first trigger unit DFF(n), a first trigger DFF5, a multi-bit latch LATCH2<3:0>, a first inverting unit 1021, a second inverting unit 1022, a third inverting unit 1023, an AND gate unit 1024, and a first inverter 1025. The first trigger unit DFF(n) may include at least one trigger, and the number of the first trigger units DFF(n) may be changed according to the setting of system latency to adjust the size of delaying the write operation instruction.

[0059] The first trigger unit DFF(n) is connected to one end of the first inverting unit 1021 , one end of the second inverting unit 1022 , and one end of the third inverting unit 1023 , and a write operation instruction WriteCommand and a system clock CK are input to the first trigger unit DFF(n).

[0060] The data input terminal D of the first trigger DFF5 is connected to the other end of the first inverting unit 1021, the reset terminal Reset of the first trigger DFF5 is connected to the AND gate unit 1024, the data output terminal Q of the first trigger DFF5 is connected to one end of the first inverter 1025, and the data sampling pulse DQSb is input to the clock input terminal CK of the first trigger DFF5.

[0061] The clock input terminal CK of the multi-bit latch LATCH2<3:0> is connected to the other end of the first inverter 1025 and the AND gate unit 1024, the data output terminal Q of the multi-bit latch LATCH2<3:0> is connected to the data input terminal D of the system clock synchronization module 103, and multi-bit parallel data DQ0, DQ1, DQ2, DQ3 are input to the data input terminal D of the multi-bit latch LATCH2<3:0>.

[0062] The other end of the second inverting unit 1022 is connected to the AND gate unit 1024 , and the other end of the third inverting unit 1023 is connected to the clock input terminal CK of the system clock synchronization module 103 .

[0063] also, Figure 1 As an example, the first inverting unit 101 includes 8 inverters connected in series, the second inverting unit 102 includes 9 inverters connected in series, and the third inverting unit 103 includes 8 inverters connected in series, but the present invention is not limited thereto.

[0064] In addition, as an example, the AND gate unit 1024 includes a first AND gate 1024a, a second AND gate 1024b, and a third AND gate 1024c. The output end of the first AND gate 1024a is connected to the first input end of the second AND gate 1024b, the first input end of the first AND gate 1024a is connected to the other end of the second inverting unit 1022, and the second input end of the first AND gate 1024a is connected to the first trigger unit DFF(n). The second input end of the second AND gate 1024b is connected to the output end of the third AND gate 1024c, and the output end of the second AND gate 1024b is connected to the first input end of the third AND gate 1024c and the reset end Reset of the first trigger DFF5. The second input end of the third AND gate 1024c is connected to the other end of the first inverter 1025 and the clock input end CK of the multi-bit latch LATCH2<3:0>.

[0065] In addition, if Figure 1 As shown, taking BL4 (4-bit data read and write) as an example, the parallel data generation module 101 includes a trigger DFF1, a trigger DFF2, a trigger DFF3, a trigger DFF4, and a latch LATCH1.

[0066] The data input terminal D of the flip-flop DFF1 is connected to the data input terminal D of the flip-flop DFF3, the data output terminal Q of the flip-flop DFF1 is connected to the data input terminal D of the latch LATCH1, the serial data DQ is input to the data input terminal D of the flip-flop DFF1, and the data sampling pulse DQS is input to the clock input terminal CK of the flip-flop DFF1. The clock input terminal CK of the latch LATCH1 is connected to the clock input terminal CK of the flip-flop DFF2, the clock input terminal CK of the flip-flop DFF3, and the clock input terminal CK of the flip-flop DFF4, the data output terminal Q of the latch LATCH1 is connected to the data input terminal D of the flip-flop DFF2, the output signal from the data output terminal Q of the flip-flop DFF1 is input to the data input terminal D of the latch LATCH1, the data sampling pulse DQSb is input to the clock input terminal CK of the latch LATCH1, and the data DQ2 is output from the data output terminal Q of the latch LATCH1. The output data DQ2 from the latch LATCH1 is input to the data input terminal D of the flip-flop DFF2, the data sampling pulse DQSb is input to the clock input terminal CK of the flip-flop DFF2, and the data DQ0 is output from the data output terminal Q of the flip-flop DFF2.

[0067] The data output terminal Q of the flip-flop DFF3 is connected to the data input terminal D of the flip-flop DFF4, the serial data DQ is input to the data input terminal D of the flip-flop DFF3, the data sampling pulse DQSb is input to the clock input terminal CK of the flip-flop DFF3, and the data DQ3 is output from the data output terminal Q of the flip-flop DFF3. The output data DQ3 from the flip-flop DFF3 is input to the data input terminal D of the flip-flop DFF4, the data sampling pulse DQSb is input to the clock input terminal CK of the flip-flop DFF4, and the data DQ1 is output from the data output terminal Q of the flip-flop DFF4.

[0068] In addition, the multi-bit parallel data DQ0 , DQ1 , DQ2 , and DQ3 are input to the data input terminal D of the multi-bit latch LATCH2 <3:0> in the data latch module 102 .

[0069] Figure 2 1 is a timing chart showing an example of the timing of each signal in the write operation sequential logic circuit according to the embodiment of the present invention. Figure 2 In the example, BL4 (4-bit data reading and writing) is used for explanation.

[0070] like Figure 1 and Figure 2As shown, the first trigger unit DFF(n) generates a write operation control signal SCAS_WT_PRE_1CLK according to the write operation instruction Write Command and the system clock CK, which delays the write operation instruction Write Command by a specified clock cycle (WL+1)*tck, and outputs it to the first inverting unit 1021, and then further outputs it to the data input terminal D of the first trigger DFF5 through the first inverting unit 1021.

[0071] The write operation control signal SCAS_WT_PRE_1CLK includes the last valid falling edge of DQS. After the last valid falling edge of DQS is sampled by the first trigger DFF5 to the write operation control signal SCAS_WT_PRE_1CLK, after a short delay, the output Q5 of the first trigger DFF5 is set to 0. After Q5 passes through the first inverter 1025, the output DQ_LATCH becomes a low-level narrow pulse triggered by the last valid falling edge of DQS. Figure 2 As shown, the pulse width of the low-level narrow pulse is much smaller than twpst. Since the first trigger DFF5 has been set to 0, any change in DQS will not affect the low-level narrow pulse after the twpst time. The low-level narrow pulse will pass through the data DQ at a low level and latch the 4-bit DQ data on the rising edge.

[0072] In addition, the first trigger unit DFF(n) generates a control signal SCAS_WT_PRE_1d5CLK for turning on the first trigger DFF5 before the last valid falling edge of the data sampling pulse DQS arrives according to the write operation instruction Write Command and the system clock CK, and outputs it to the second inverting unit 1022, and then further outputs it to the reset terminal Reset of the first trigger DFF5 via the second inverting unit 1022 and the AND gate unit 1024. Among them, SCAS_WT_PRE_1d5CLK is a control signal that is half a clock cycle faster than SCAS_WT_PRE_1CLK, and is used to turn on the first trigger DFF5 before the last valid falling edge of the data sampling pulse DQS arrives.

[0073] In addition, the first trigger unit DFF(n) generates a system clock domain synchronization signal SCAS_WT according to the write operation instruction Write Command and the system clock CK, and outputs it to the third inverting unit 1023, and then further outputs it to the clock input terminal CK of the system clock synchronization module 103 via the third inverting unit 1023. The system clock domain synchronization signal SCAS_WT is one clock cycle slower than SCAS_WT_PRE_1CLK, and it is responsible for synchronizing the latched 4-bit data DQ_D0, DQ_D1, DQ_D2, and DQ_D3 to the system clock domain through the multi-bit trigger DFF6<3:0> (system clock synchronization module 103) at the rising edge.

[0074] In addition, in BL4 (4-bit data reading and writing), the interval between two write operations is at least tccd (4 clock cycles), and the 4-bit data will be latched for at least 4 clock cycles tck for the system clock domain synchronization signal SCAS_WT to latch and synchronize; in BL8 (8-bit data reading and writing), the 8-bit data is divided into two 4-bit data and written in sequence. The two SCAS_WT_PRE_1CLK signals are at least 2 clock cycles apart, and each 4-bit data will be latched for 2 clock cycles tck for the system clock domain synchronization signal SCAS_WT to latch and synchronize. There is plenty of time, thereby avoiding the risk of data loss caused by DQS not being constrained after the twpst time.

[0075] According to the write operation timing logic circuit of the present invention, the last valid falling edge of the data sampling pulse is identified according to the write operation instruction, the system clock and the data sampling pulse, and after the falling edge samples the data, the control circuit is self-locked to lock the multi-bit parallel data from the parallel data generation module, and will not release it until the next write operation instruction arrives, thereby completely avoiding the risk of data loss caused by the duration (twpst) of the write post sampling signal (Write Postamble) being too short.

[0076] In addition, the present invention further provides a memory, which includes the write operation sequential logic circuit involved in the implementation manner of the present invention.

[0077] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present invention, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present invention. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present invention, the various embodiments are not meant to be restrictive, but exemplary embodiments. In the case of reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

[0078] Industrial Applicability

[0079] The write operation sequential logic circuit of the present invention can be widely used in memories such as DDR3.

Claims

1. A write operation sequential logic circuit, characterized in that: include: A parallel data generation module, which generates multi-bit parallel data according to the input serial data and data sampling pulses; A data latch module, which is connected to the parallel data generation module, latches the multi-bit parallel data from the parallel data generation module according to a write operation instruction, a system clock and the data sampling pulse, and generates a system clock domain synchronization signal; as well as A system clock synchronization module is connected to the data latch module and synchronizes the latched multi-bit parallel data to the system clock domain according to the latched multi-bit parallel data and the system clock domain synchronization signal.

2. The write operation sequential logic circuit according to claim 1, characterized in that: The data latch module generates a data latch signal according to a write operation instruction, a system clock and the data sampling pulse, and latches the multi-bit parallel data according to the data latch signal.

3. The write operation sequential logic circuit according to claim 2, characterized in that: The pulse width of the data latch signal is smaller than a specified width.

4. The write operation sequential logic circuit according to claim 1, characterized in that: The data latch module includes a first trigger unit, a first trigger, a multi-bit latch, a first inverting unit, a second inverting unit, a third inverting unit, an AND gate unit, and a first inverter. The first trigger unit is connected to one end of the first inverting unit, one end of the second inverting unit, and one end of the third inverting unit, and the write operation instruction and the system clock are input to the first trigger unit. The data input terminal of the first trigger is connected to the other end of the first inverting unit, the reset terminal of the first trigger is connected to the AND gate unit, the data output terminal of the first trigger is connected to one end of the first inverter, and a data sampling pulse is input to the clock input terminal of the first trigger. The clock input end of the multi-bit latch is connected to the other end of the first inverter and the AND gate unit, the data output end of the multi-bit latch is connected to the data input end of the system clock synchronization module, and the multi-bit parallel data is input to the data input end of the multi-bit latch. The other end of the second inverting unit is connected to the AND gate unit. The other end of the third inverting unit is connected to the clock input end of the system clock synchronization module.

5. The write operation sequential logic circuit according to claim 4, characterized in that: The first trigger unit generates a write operation control signal that delays the write operation instruction by a specified number of clock cycles according to the write operation instruction and the system clock, and outputs the signal to the first inverting unit. The first trigger unit generates a control signal for turning on the first trigger before the last valid falling edge of the data sampling pulse arrives according to the write operation instruction and the system clock, and outputs the control signal to the second inverting unit. The first trigger unit generates the system clock domain synchronization signal according to the write operation instruction and the system clock, and outputs the system clock domain synchronization signal to the third inverting unit.

6. The write operation sequential logic circuit according to claim 4, characterized in that: The first inverting unit includes eight inverters connected in series. The second inverting unit includes 9 inverters connected in series. The third inverting unit includes eight inverters connected in series.

7. The write operation sequential logic circuit according to claim 4, characterized in that: The AND gate unit includes a first AND gate, a second AND gate, and a third AND gate. The output end of the first AND gate is connected to the first input end of the second AND gate, the first input end of the first AND gate is connected to the other end of the second inverting unit, and the second input end of the first AND gate is connected to the first trigger unit. The second input terminal of the second AND gate is connected to the output terminal of the third AND gate, and the output terminal of the second AND gate is connected to the first input terminal of the third AND gate and the reset terminal of the first trigger. The second input terminal of the third AND gate is connected to the clock input terminal of the multi-bit latch.

8. The write operation sequential logic circuit according to claim 4, characterized in that: The first trigger unit includes at least one trigger.

9. The write operation sequential logic circuit according to claim 1, characterized in that: The system clock synchronization module is a multi-bit trigger.

10. A memory, characterized in that: A write operation sequential logic circuit comprising any one of claims 1 to 9.

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