Method and device for determining holding current of phase change memory array and medium

Abstract

The invention provides a holding current determination method and device for a phase change memory array and a medium, and the method comprises the steps: obtaining a setting current range for carrying out setting operation on the phase change memory array, and obtaining threshold voltage distribution when a plurality of setting currents in the setting current range are respectively applied to the phase change memory array; obtaining a target voltage under each setting current according to a standard deviation of a preset multiple of threshold voltage distribution corresponding to each setting current; calculating a voltage difference value between target voltages corresponding to two adjacent setting currents in the setting current range according to a direction in which the setting currents are sequentially increased to obtain a plurality of voltage difference values; and determining the setting current corresponding to the voltage difference value meeting the voltage abrupt change condition in the plurality of voltage difference values as the holding current of the phase change memory array. The holding current of the phase change memory array is determined simply, quickly, accurately and efficiently.

Description

[0001] This application claims priority to a Chinese patent application filed with the State Intellectual Property Office of China on December 27, 2024, with application number 202411949686.9 and invention name “A method, device and medium for determining the holding current of a phase change memory array”, the entire contents of which are incorporated by reference in this application. Technical Field

[0002] The present invention relates to the field of semiconductors, and in particular to a method, device and medium for determining a holding current of a phase change memory array. Background Art

[0003] Phase Change Memory (PCM) fills the performance gap between Dynamic Random Access Memory (DRAM) and flash memory. It has the advantages of high-speed reading, high erasable and write times, non-volatility, small component size, low power consumption, strong vibration resistance and radiation resistance, and is widely used.

[0004] Unlike DRAM and flash, which store data in the form of electric charge, phase change memory uses the properties of the crystalline and amorphous states of phase change materials to store data. For example, different electric pulses are used to induce phase change materials to undergo rapid and reversible phase changes between amorphous and crystalline states. The process of using electric current to heat the phase change material from an amorphous state to a crystalline state is called a SET (set) operation; or, the process of converting the phase change material from a crystalline state to an amorphous state is called a RESET (reset) operation. This state change of the phase change material can represent a bit of data "0" or "1".

[0005] The hold current is one of the necessary conditions to keep the phase change memory open, and the hold current has a great influence on the operation of the phase change memory, especially the SET operation. Currently, there is a need to determine the hold current of the phase change memory array so as to reflect the actual situation of the phase change memory array according to the hold current. Summary of the invention

[0006] In view of this, an object of the present application is to provide a method, device and medium for determining a holding current of a phase change memory array, which can determine the holding current of the phase change memory array simply, quickly, accurately and efficiently.

[0007] The present application provides a method for determining a holding current of a phase change memory array, the method comprising:

[0008] Acquire a set current range for performing a set operation on a phase change memory array, wherein the phase change memory array includes a plurality of phase change memories;

[0009] Obtaining a threshold voltage distribution when a plurality of set currents within the set current range are respectively applied to the phase change memory array, wherein the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current;

[0010] Obtaining a target voltage at each of the set currents according to a standard deviation of a preset multiple of a threshold voltage distribution corresponding to each of the set currents;

[0011] Calculating a voltage difference between target voltages corresponding to two adjacent set currents within the set current range according to a direction in which the set current increases sequentially, to obtain a plurality of voltage differences;

[0012] The set current corresponding to the voltage difference value that meets the voltage mutation condition among the plurality of voltage differences is determined as the holding current of the phase change memory array.

[0013] Optionally, the obtaining of threshold voltage distributions when a plurality of set currents within the set current range are respectively applied to the phase change memory array comprises:

[0014] Performing an ergodic operation on a plurality of set currents at a preset current interval within the set current range;

[0015] A threshold voltage distribution when each of the set currents is applied to the phase change memory array is obtained.

[0016] Optionally, obtaining the threshold voltage distribution when each of the set currents is applied to the phase change memory array comprises:

[0017] Acquiring a read voltage range of the phase change memory array, wherein the read voltage range includes a plurality of read voltages;

[0018] The number of phase change memories corresponding to different read voltages when each of the set currents is applied to the phase change memory array is obtained, and a threshold voltage distribution is obtained according to the plurality of read voltages and the number of phase change memories corresponding to each of the read voltages.

[0019] Optionally, the preset multiple is 3.5.

[0020] Optionally, determining the set current corresponding to the voltage difference value satisfying the voltage mutation condition among the plurality of voltage differences as the holding current of the phase change memory array comprises:

[0021] A target current corresponding to a maximum difference among the plurality of voltage differences is determined as a holding current of the phase change memory array, wherein the target current is a set current corresponding to a subtrahend in a calculation process of the maximum difference.

[0022] Optionally, the phase change memory array is divided into a plurality of electrical regions according to electrical distance; and the holding currents of the phase change memories in different electrical regions are different.

[0023] Optionally, before acquiring a set current range for performing a set operation on the phase change memory array, the method further includes:

[0024] Acquiring the number of cycle operations of the phase change memory array, wherein the cycle operations include a write operation and an erase operation;

[0025] The step of determining the set current corresponding to the voltage difference value satisfying the voltage mutation condition among the plurality of voltage differences as the holding current of the phase change memory array comprises:

[0026] The set current corresponding to the voltage difference value that meets the voltage mutation condition among the plurality of voltage differences is determined as the holding current of the phase change memory array after the number of cycle operations.

[0027] Optionally, the setting operation includes multiple stages, and the multiple stages include a second stage;

[0028] The obtaining of a set current range for performing a set operation on the phase change memory array comprises:

[0029] A set current range corresponding to the second stage of performing a set operation on the phase change memory array is obtained.

[0030] The present application provides a holding current determination device for a phase change memory array, the device comprising:

[0031] A first acquisition unit, configured to acquire a set current range for performing a set operation on a phase change memory array, wherein the phase change memory array includes a plurality of phase change memories;

[0032] A second acquisition unit is used to acquire a threshold voltage distribution when a plurality of set currents within the set current range are respectively applied to the phase change memory array, wherein the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current;

[0033] A third acquisition unit, configured to acquire a target voltage at each of the set currents according to a standard deviation of a preset multiple of a threshold voltage distribution corresponding to each of the set currents;

[0034] a calculation unit, configured to calculate a voltage difference between target voltages corresponding to two adjacent set currents within the set current range according to a direction in which the set current increases sequentially, to obtain a plurality of voltage difference values;

[0035] The determination unit is used to determine the set current corresponding to the voltage difference value that meets the voltage mutation condition among the plurality of voltage differences as the holding current of the phase change memory array.

[0036] The present application provides a computer-readable medium, comprising instructions, which, when executed on a computer, enable the computer to execute any of the methods described above.

[0037] The present application provides a method for determining a holding current of a phase change memory array, the method comprising: obtaining a setting current range for performing a setting operation on the phase change memory array, the phase change memory array comprising a plurality of phase change memories; obtaining a threshold voltage distribution when a plurality of setting currents within the setting current range are respectively applied to the phase change memory array, the threshold voltage distribution being the number of phase change memories corresponding to different read voltages under the same setting current, the threshold voltage distribution of different setting currents being able to reflect the difference between the setting current and the holding current, thereby assisting in the subsequent determination of the holding current value using the value of the setting current; obtaining a target voltage under each setting current according to a standard deviation of a preset multiple of the threshold voltage distribution corresponding to each setting current, and calibrating the holding current of the plurality of phase change memories in the phase change memory array using the target voltage obtained by using the standard deviation of the preset multiple. Accurately determine; according to the direction in which the set current increases successively, calculate the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range to obtain multiple voltage difference values; determine the set current corresponding to the voltage difference value that meets the voltage mutation condition among the multiple voltage difference values ​​as the holding current of the phase change memory array, that is, when the target voltage difference corresponding to two adjacent set currents meets the voltage mutation condition, it represents that the two adjacent set currents are the currents closest to the holding current, thereby quickly determining the holding current. It can be seen that the present application obtains the target voltage corresponding to the standard deviation of the preset multiple by using the threshold voltage distribution obtained by using multiple set currents, and then uses whether the voltage difference between the target voltages meets the voltage mutation condition to achieve simple, fast, accurate and efficient determination of the holding current of the phase change memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic flow chart of a method for determining a holding current of a phase change memory array provided in an embodiment of the present application is shown;

[0040] Figure 2 A waveform diagram of a set current provided in an embodiment of the present application is shown;

[0041] Figure 3A threshold voltage distribution diagram of a phase memory array under different set currents provided by an embodiment of the present application is shown;

[0042] Figure 4 A schematic diagram of a current-voltage curve provided in an embodiment of the present application is shown;

[0043] Figure 5 A schematic diagram of a current-voltage curve of different electrical distances provided in an embodiment of the present application is shown;

[0044] Figure 6 A schematic diagram of a current-voltage curve for different numbers of cycle operations provided in an embodiment of the present application is shown;

[0045] Figure 7 A schematic structural diagram of a current holding device of a phase change memory array provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0048] Phase change memory stores data based on the resistance change of the phase change material of the memory cell (for example, in a high resistance state or a low resistance state). Phase change memory has a transistor-free cross-point architecture that places the memory cell at the intersection of vertical conductors, where the vertical conductors include word lines (Word Line, WL) and bit lines (Bit Line, BL) that intersect each other vertically, and WL and BL are generally composed of 20nm / 20nm equal width lines (Line / Space, L / S) formed after the patterning process.

[0049] Unlike DRAM and flash that store data in the form of electric charge, phase change memory uses the characteristics of the crystalline and amorphous states of phase change materials to store data. The storage unit of the phase change memory is heated by electric current, so that the phase change material changes from the amorphous state to the crystalline state. The change from the amorphous state to the crystalline state is also called nucleation, that is, the phase change material changes from a high resistance state to a low resistance state. This process is called SET (set) operation; or, the phase change material is converted from the crystalline state to the amorphous state, that is, the phase change material changes from a low resistance state to a high resistance state. This process is called RESET (reset) operation. This state change of the phase change material can represent a bit of data "0" or "1".

[0050] The core of the storage unit of the phase change memory is the phase change material based on the sulfide compound (such as GST material, specifically, Ge2Sb2Te5). For the phase change memory, the storage unit needs to be read and written repeatedly. Before the conventional read and write operations are performed on the storage unit, the phase change memory is usually subjected to SET and RESET operations.

[0051] The Hold current is one of the necessary conditions to keep the phase change memory open. The Hold current has a great influence on the operation of the phase change memory, especially the SET operation. There is currently a need to determine the hold current of the phase change memory array so as to reflect the actual situation of the phase change memory array according to the hold current. Therefore, measuring the Hold current in the phase change memory array is of great significance to the operation of the phase change memory and monitoring the changes of the phase change memory.

[0052] Currently, there is no method to test the Hold current in a phase-change memory array. The Hold current can be measured by performing a current-voltage (IV) test on the devices in a test simplified array (TSK), and this can be used to reflect the Hold current in the phase-change memory array. However, since TSK is a simplification of the phase-change memory array, the Hold current obtained by this method cannot reflect the actual situation in the phase-change memory array. In addition, since it is difficult for the devices in the TSK to perform a read-write operation cycle of the order of 100k, it is difficult to understand the Hold current of the phase-change memory after multiple cycles.

[0053] Therefore, there is currently a need to determine the holding current of a phase change memory array so as to reflect the actual situation of the phase change memory array according to the holding current.

[0054] Based on this, the present application provides a method for determining a holding current of a phase change memory array, the method comprising: obtaining a set current range for performing a set operation on the phase change memory array, the phase change memory array comprising a plurality of phase change memories; obtaining a threshold voltage distribution when a plurality of set currents within the set current range are respectively applied to the phase change memory array, the threshold voltage distribution being the number of phase change memories corresponding to different read voltages under the same set current, the threshold voltage distribution of different set currents being able to reflect the difference between the set current and the holding current, thereby assisting in the subsequent determination of the holding current value using the value of the set current; obtaining a target voltage under each set current according to a standard deviation of a preset multiple of the threshold voltage distribution corresponding to each set current, and performing a hold current adjustment on the plurality of phase change memories in the phase change memory array using the target voltage obtained by using the standard deviation of the preset multiple. row accurately determined; according to the direction in which the set current increases successively, the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range is calculated to obtain multiple voltage difference values; the set current corresponding to the voltage difference value that meets the voltage mutation condition among the multiple voltage difference values ​​is determined as the holding current of the phase change memory array, that is, when the target voltage difference corresponding to two adjacent set currents meets the voltage mutation condition, it represents that the two adjacent set currents are the currents closest to the holding current, thereby quickly determining the holding current. It can be seen that the present application obtains the target voltage corresponding to the standard deviation of the preset multiple by using the threshold voltage distribution obtained by using multiple set currents, and then uses whether the voltage difference between the target voltages meets the voltage mutation condition to achieve simple, fast, accurate and efficient determination of the holding current of the phase change memory array.

[0055] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0056] See also Figure 1 , which is a flow chart of a method for determining a holding current of a phase change memory array provided in an embodiment of the present application.

[0057] The method for determining the holding current of a phase change memory array provided in this embodiment comprises the following steps:

[0058] S101, obtaining a set current range for performing a set operation on a phase change memory array, where the phase change memory array includes a plurality of phase change memories.

[0059] In the embodiment of the present application, the phase change memory cell is heated by electric current, so that the phase change material can be transformed from an amorphous state to a crystalline state, i.e., a SET operation. Therefore, if a SET operation is performed on the phase change memory, it is necessary to first obtain a set current for performing the SET operation on the phase change memory.

[0060] Specifically, the set operation may include multiple phases, including a first phase (phase 1), a second phase (phase 2), a third phase (phase 3), a fourth phase (phase 4), and a fifth phase (phase 5). The set current of each phase may be different, refer to Figure 2 As shown, Figure 2 A waveform diagram of a set current provided in an embodiment of the present application is shown.

[0061] The second stage is also called the nucleation stage. The second stage plays a key role in the SET operation, that is, in the SET operation, the set current in the second stage mainly plays a role in nucleation. Therefore, when the set current in the second stage is lower than the hold current, the phase change memory device is in an oscillating state with a larger peak current. When the set current in the second stage is equal to or higher than the hold current, the phase change memory is in an on state and can perform better nucleation.

[0062] Considering that the present application is to determine the holding current of a phase change memory array including multiple phase change memories, based on the high-low relationship between the holding current and the set current, the holding current can be determined by the set current. Therefore, the set current range for performing a set operation on the phase change memory array can be obtained. The set current range includes multiple set currents, thereby realizing the use of multiple set currents to assist in determining the holding current of the phase change memory array.

[0063] Specifically, a set current range corresponding to the second stage of performing a set operation on the phase change memory array may be obtained, and the set current range corresponding to the second stage includes a plurality of set currents corresponding to the second stage.

[0064] As an example, the waveform corresponding to the set current of the phase change memory array performing the set operation is referenced as follows: Figure 2 As shown, the set current of the first stage, the set current of the second stage, the set current of the third stage, and the set current of the fifth stage are different.

[0065] S102, obtaining a threshold voltage distribution when a plurality of set currents within a set current range are respectively applied to a phase change memory array, wherein the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current.

[0066] In the embodiment of the present application, a set current is applied to the phase change memory to perform a set operation, so that the phase change memory can be turned on. At this time, the phase change memory can be read using a read voltage to obtain the number of phase change memories that have been turned on under the current read voltage, that is, the number of phase change memories corresponding to different read voltages under the same set current is obtained, and different read voltages and the number of phase change memories corresponding to the read voltage constitute a threshold voltage distribution. Therefore, the threshold voltage distribution when multiple set currents within the set current range are respectively applied to the phase change memory array can be obtained, so that the threshold voltage distribution of different set currents can be used to assist in the determination of the subsequent holding current of the phase change memory array.

[0067] As a possible implementation, the multiple set currents included in the set current range are obtained based on a preset current interval. The multiple set currents can be traversed within the set current range at the preset current interval, that is, the multiple set currents are applied to the phase change memory array respectively to perform the set operation, and the threshold voltage distribution when each set current is applied to the phase change memory array is obtained.

[0068] refer to Figure 3 , which is a threshold voltage distribution diagram of a phase memory array under different set currents provided by an embodiment of the present application. Figure 3 The horizontal axis is the threshold voltage (Vt), and the vertical axis is the number of phase change memories. Figure 3 The threshold voltage distribution at different set currents is shown in FIG. Figure 3 In the threshold voltage distribution curve, the set currents of blue, red, light green, purple, brown and dark green increase in sequence. When the set current is a certain value, the threshold voltage distribution of the phase change memory array shows an obvious set tail phenomenon. Figure 3 The middle ellipse indicates that this is caused by the set current being less than the holding current. When the set current is a certain value, the threshold voltage distribution of the phase change memory array has no obvious tailing phenomenon, which is because the phase change memory is in the on state and can perform good nucleation.

[0069] When any set current is applied to the phase change memory array, a read voltage range of the phase change memory array can be obtained, the read voltage range includes multiple read voltages, and the read voltage range can be divided based on a preset voltage interval to obtain multiple read voltages. The number of phase change memories corresponding to different read voltages when each set current is applied to the phase change memory array is obtained, and the threshold voltage distribution is obtained according to the multiple read voltages and the number of phase change memories corresponding to each read voltage.

[0070] S103, obtaining a target voltage at each set current according to a standard deviation of a preset multiple of a threshold voltage distribution corresponding to each set current.

[0071] In an embodiment of the present application, after obtaining the threshold voltage distribution corresponding to each set current, the target voltage at each set current can be obtained based on the standard deviation of the preset multiples of the threshold voltage distribution corresponding to each set current, so as to accurately determine the retention current of multiple phase change memories in the phase change memory array using the target voltage obtained by the preset multiples of the standard deviation.

[0072] As a possible implementation, the preset multiple is 3, that is, the target voltage at each set current is obtained by using 3 times the standard deviation of the threshold voltage distribution. 3 times the standard deviation is 3σ, and the 3σ principle can be used to achieve that the target voltage at each set current can cover most of the phase change memories included in the phase change memory array.

[0073] As another possible implementation, the preset multiple is 3.5, that is, the target voltage at each set current is obtained by using 3.5 times the standard deviation of the threshold voltage distribution. 3.5 times the standard deviation is 3.5σ. Compared with 3σ, 3.5σ can further achieve that the target voltage at each set current can cover most of the phase change memories included in the phase change memory array.

[0074] S104, calculating a voltage difference between target voltages corresponding to two adjacent set currents within a set current range according to a direction in which the set current increases sequentially, to obtain a plurality of voltage differences.

[0075] In an embodiment of the present application, after obtaining the target voltage at each set current based on the standard deviation of preset multiples of the threshold voltage distribution corresponding to each set current, a current-voltage (IV) correspondence between the set current and the target voltage can be constructed, and the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range can be calculated in the direction in which the set current increases successively, to obtain multiple voltage differences.

[0076] refer to Figure 4 As shown, Figure 4 A schematic diagram of a current-voltage curve provided in an embodiment of the present application. Figure 4 The multiple curves in FIG. 1 represent the current-voltage curves of different phase change memory arrays. Figure 4 The set current is a plurality of values, and each set current has a corresponding target voltage. According to the direction in which the set current increases in sequence, the voltage differences between the target voltages corresponding to adjacent set currents within the set current range are calculated to obtain a plurality of voltage differences. Figure 4 The horizontal axis is the set current (Iset2) of the second stage, and the vertical axis is 3.5 times the standard deviation of the threshold voltage (Vt_3.5sigma).

[0077] S105, determining a set current corresponding to a voltage difference value satisfying a voltage mutation condition among a plurality of voltage differences as a holding current of the phase change memory array.

[0078] In an embodiment of the present application, after obtaining the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range, the set current corresponding to the voltage difference that satisfies the voltage mutation condition among multiple voltage differences can be determined as the holding current of the phase change memory array, wherein the voltage mutation condition can indicate a state change of the phase change memory, that is, when the voltage difference between the target voltages corresponding to two adjacent set currents satisfies the voltage mutation condition, it represents that the two adjacent set currents are the currents closest to the holding current, thereby quickly determining the holding current.

[0079] As a possible implementation, the voltage mutation condition may be that there is a maximum difference among multiple voltage differences, and in this case, the maximum difference represents that the target voltage has a mutation. Therefore, the target current corresponding to the maximum difference among multiple voltage differences can be determined as the holding current of the phase change memory array, and the target current is the set current corresponding to the subtrahend in the maximum difference calculation process. In other words, the latter of the two set currents corresponding to the maximum difference is determined as the holding current.

[0080] In practical applications, considering the possibility that the voltage difference is positive or negative, this application notice compares the absolute value of the voltage difference when comparing the voltage difference to determine the maximum difference. Since different set voltages correspond to different target voltages, and the current-voltage curve has an inflection point, the voltage difference after the target voltage rises can be ignored, that is, the voltage difference at which the target voltage drops and the drop is the largest is taken as the maximum difference.

[0081] refer to Figure 4 As shown, the voltage difference between the target voltages corresponding to the set currents A and B is the maximum difference within the set current range, so B can be determined as the holding current of the phase change memory array.

[0082] As another possible implementation, the voltage mutation condition may be the voltage difference with the largest multiple of the first voltage difference among the multiple voltage differences, in which case the voltage difference with the largest multiple represents a sudden change in the target voltage. Therefore, the target current corresponding to the voltage difference with the largest multiple of the first voltage difference among the multiple voltage differences can be determined as the holding current of the phase change memory array, and the target current is the set current corresponding to the subtrahend in the calculation process. In other words, the latter of the two set currents corresponding to the voltage difference with the largest multiple of the first voltage difference is determined as the holding current.

[0083] It can be seen that the present application obtains the threshold voltage distribution by using multiple set currents to obtain a target voltage corresponding to a preset multiple of the standard deviation, and then uses whether the voltage difference between the target voltages meets the voltage mutation condition to achieve a simple, fast, accurate and efficient determination of the holding current of the phase change memory array.

[0084] In an embodiment of the present application, a phase change memory array is divided into a plurality of electrical regions according to an electrical distance, wherein the electrical distance (ED) refers to the distance between the applying unit and the applying unit of the set current. The plurality of electrical regions may include a near end (NN), a middle end (MM), and a far end (FF). The holding current of the phase change memory in different electrical regions is different, that is, the holding current of the phase change memory is affected by the electrical distance.

[0085] As a possible implementation manner, as the electrical distance increases, the retention current of the phase change memory gradually decreases.

[0086] refer to Figure 5 As shown, Figure 5 A schematic diagram of a current-voltage curve for different electrical distances provided in an embodiment of the present application. Figure 5 The multiple curves in FIG. 1 represent the current-voltage curves of different phase change memory arrays, and the different phase change memory arrays are chip 1 (D01), chip 2 (D02), chip 3 (D03), chip 4 (D04) and chip 5 (D05). Figure 5 It can be seen that the holding current at the near end is greater than the holding current at the middle end, and the holding current at the middle end is greater than the holding current at the far end. Figure 5 The horizontal axis is the set current (Iset2) of the second stage, and the vertical axis is 3.5 times the standard deviation of the threshold voltage (Vt_3.5sigma).

[0087] In an embodiment of the present application, before obtaining the set current range for performing a set operation on the phase change memory array, that is, before performing the set operation, the number of cycle operations of the phase change memory array can also be obtained, so as to test the holding current of the phase change memory array after the number of cycle operations. Wherein, the cycle operation includes a write operation and an erase operation, and one write operation and one erase operation are one cycle operation, that is, the number of cycle operations of the phase change memory array for performing a write operation and an erase operation can be obtained.

[0088] After the number of cycle operations is obtained, steps S101 to S105 are performed, and the obtained retention current of the phase change memory array is determined as the retention current of the phase change memory array after the number of cycle operations.

[0089] As a possible implementation manner, as the number of cycle operations increases, the retention current of the phase change memory gradually increases or remains unchanged.

[0090] refer to Figure 6 As shown, Figure 6 A schematic diagram of a current-voltage curve for different numbers of cycle operations provided in an embodiment of the present application is shown. Figure 6 The multiple curves in the figure represent the current-voltage curves of different cycle operation times, and the different cycle operation times are 0, 100000 (100k), 300000 (300k), 600000 (600k) and 1000000 (1M). Figure 6 It can be seen that the holding current when the cycle operation number is 0 is smaller than the holding current when the cycle operation number is 100k, the holding current when the cycle operation number is 100k is smaller than the holding current when the cycle operation number is 300k, the holding current when the cycle operation number is 300k, the holding current when the cycle operation number is 600k and the holding current when the cycle operation number is 1M are the same. Figure 6 The horizontal axis is the set current (Iset2) of the second stage, and the vertical axis is 3.5 times the standard deviation of the threshold voltage (Vt_3.5sigma).

[0091] It can be seen that the cycle operation of the phase change memory array in the embodiment of the present application is simpler and faster than the cycle operation of TSK. The cycle performance of the phase change memory included in the phase change memory array is also better, and the Hold current of the phase change memory array after the cycle can be measured more accurately. The method for determining the holding current of the phase change memory array provided in the embodiment of the present application has a short test time, a small amount of data, and simple data processing. Regardless of the quality of the phase change memory, the Hold current in the phase change memory array can be accurately measured.

[0092] Based on the method for determining the holding current of a phase change memory array provided in the above embodiment, an embodiment of the present application further provides a device for determining the holding current of a phase change memory array, which is described in detail below in conjunction with the accompanying drawings.

[0093] See also Figure 7 , which is a structural schematic diagram of a holding current determination device for a phase change memory array provided in an embodiment of the present application.

[0094] The holding current determination device 200 of the phase change memory array provided in this embodiment includes:

[0095] A first acquisition unit 210, configured to acquire a set current range for performing a set operation on a phase change memory array, wherein the phase change memory array includes a plurality of phase change memories;

[0096] A second acquisition unit 220 is used to acquire a threshold voltage distribution when a plurality of set currents within the set current range are respectively applied to the phase change memory array, wherein the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current;

[0097] A third acquisition unit 230, configured to acquire a target voltage at each of the set currents according to a standard deviation of a preset multiple of a threshold voltage distribution corresponding to each of the set currents;

[0098] A calculation unit 240, configured to calculate a voltage difference between target voltages corresponding to two adjacent set currents within the set current range according to a direction in which the set current increases sequentially, to obtain a plurality of voltage difference values;

[0099] The determination unit 250 is used to determine the set current corresponding to the voltage difference value that meets the voltage mutation condition among the plurality of voltage differences as the holding current of the phase change memory array.

[0100] In some embodiments, the second acquiring unit 220 is configured to:

[0101] Performing an ergodic operation on a plurality of set currents at a preset current interval within the set current range;

[0102] A threshold voltage distribution when each of the set currents is applied to the phase change memory array is obtained.

[0103] In some embodiments, the second acquiring unit 220 is configured to:

[0104] Acquiring a read voltage range of the phase change memory array, wherein the read voltage range includes a plurality of read voltages;

[0105] The number of phase change memories corresponding to different read voltages when each of the set currents is applied to the phase change memory array is obtained, and a threshold voltage distribution is obtained according to the plurality of read voltages and the number of phase change memories corresponding to each of the read voltages.

[0106] In some embodiments, the preset multiple is 3.5.

[0107] In some embodiments, the determining unit 250 is configured to:

[0108] A target current corresponding to a maximum difference among the plurality of voltage differences is determined as a holding current of the phase change memory array, wherein the target current is a set current corresponding to a subtrahend in a calculation process of the maximum difference.

[0109] In some embodiments, the phase change memory array is divided into a plurality of electrical regions according to electrical distance; the retention currents of the phase change memories in different electrical regions are different.

[0110] In some embodiments, before the first acquisition unit 210 acquires the set current range for performing a set operation on the phase change memory array, the apparatus further includes: a fourth acquisition unit;

[0111] The fourth acquisition unit is used for:

[0112] Acquiring the number of cycle operations of the phase change memory array, wherein the cycle operations include a write operation and an erase operation;

[0113] The determining unit 250 is configured to:

[0114] The set current corresponding to the voltage difference value that meets the voltage mutation condition among the plurality of voltage differences is determined as the holding current of the phase change memory array after the number of cycle operations.

[0115] In some embodiments, the set operation includes a plurality of stages, the plurality of stages including a second stage;

[0116] The first acquisition unit 210 is used to:

[0117] A set current range corresponding to the second stage of performing a set operation on the phase change memory array is obtained.

[0118] Based on the method for determining the holding current of a phase change memory array provided in the above embodiment, an embodiment of the present application further provides a device for determining the holding current of a phase change memory array, and the device for determining the holding current of a phase change memory array includes:

[0119] The processor and the memory may be one or more processors. In some embodiments of the present application, the processor and the memory may be connected via a bus or other means.

[0120] The memory may include a read-only memory and a random access memory, and provides instructions and data to the processor. A portion of the memory may also include an NVRAM. The memory stores an operating system and operating instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, wherein the operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks.

[0121] The processor controls the operation of the terminal device and may also be referred to as a CPU.

[0122] The method disclosed in the above embodiment of the present application can be applied to a processor or implemented by a processor. The processor can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor can be a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor can be combined to perform. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0123] The embodiment of the present application also provides a computer-readable medium for storing program code, where the program code is used to execute any one of the methods of the aforementioned embodiments.

[0124] It should be noted that the computer-readable medium mentioned above in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0125] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0126] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A method for determining a holding current of a phase change memory array, characterized in that: The method comprises: Acquire a set current range for performing a set operation on a phase change memory array, wherein the phase change memory array includes a plurality of phase change memories; Obtaining a threshold voltage distribution when a plurality of set currents within the set current range are respectively applied to the phase change memory array, wherein the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current; Obtaining a target voltage at each of the set currents according to a standard deviation of a preset multiple of a threshold voltage distribution corresponding to each of the set currents; Calculating a voltage difference between target voltages corresponding to two adjacent set currents within the set current range according to a direction in which the set current increases sequentially, to obtain a plurality of voltage differences; The set current corresponding to the voltage difference value that meets the voltage mutation condition among the plurality of voltage differences is determined as the holding current of the phase change memory array.

2. The method according to claim 1, characterized in that The step of obtaining the threshold voltage distribution when a plurality of set currents within the set current range are respectively applied to the phase change memory array comprises: Performing an ergodic operation on a plurality of set currents at a preset current interval within the set current range; A threshold voltage distribution when each of the set currents is applied to the phase change memory array is obtained.

3. The method according to claim 2, characterized in that The obtaining of the threshold voltage distribution when each of the set currents is applied to the phase change memory array comprises: Acquiring a read voltage range of the phase change memory array, wherein the read voltage range includes a plurality of read voltages; The number of phase change memories corresponding to different read voltages when each of the set currents is applied to the phase change memory array is obtained, and a threshold voltage distribution is obtained according to the plurality of read voltages and the number of phase change memories corresponding to each of the read voltages.

4. The method according to claim 1, characterized in that: The preset multiple is 3.

5.

5. The method according to claim 1, characterized in that The step of determining the set current corresponding to the voltage difference value satisfying the voltage mutation condition among the plurality of voltage differences as the holding current of the phase change memory array comprises: A target current corresponding to a maximum difference among the plurality of voltage differences is determined as a holding current of the phase change memory array, wherein the target current is a set current corresponding to a subtrahend in a calculation process of the maximum difference.

6. The method according to claim 1, characterized in that The phase change memory array is divided into a plurality of electrical regions according to electrical distance; the holding currents of the phase change memories in different electrical regions are different.

7. The method according to any one of claims 1 to 6, characterized in that: Before acquiring a set current range for performing a set operation on the phase change memory array, the method further includes: Acquiring the number of cycle operations of the phase change memory array, wherein the cycle operations include a write operation and an erase operation; The step of determining the set current corresponding to the voltage difference value satisfying the voltage mutation condition among the plurality of voltage differences as the holding current of the phase change memory array comprises: The set current corresponding to the voltage difference value that meets the voltage mutation condition among the plurality of voltage differences is determined as the holding current of the phase change memory array after the number of cycle operations.

8. The method according to any one of claims 1 to 6, characterized in that: The set operation includes a plurality of stages, the plurality of stages including a second stage; The acquiring of a set current range for performing a set operation on the phase change memory array comprises: A set current range corresponding to the second stage of performing a set operation on the phase change memory array is obtained.

9. A holding current determination device for a phase change memory array, characterized in that: The device comprises: A first acquisition unit, configured to acquire a set current range for performing a set operation on a phase change memory array, wherein the phase change memory array includes a plurality of phase change memories; A second acquisition unit is used to acquire a threshold voltage distribution when a plurality of set currents within the set current range are respectively applied to the phase change memory array, wherein the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current; A third acquisition unit, configured to acquire a target voltage at each of the set currents according to a standard deviation of a preset multiple of a threshold voltage distribution corresponding to each of the set currents; a calculation unit, configured to calculate a voltage difference between target voltages corresponding to two adjacent set currents within the set current range according to a direction in which the set current increases sequentially, to obtain a plurality of voltage difference values; The determination unit is used to determine the set current corresponding to the voltage difference value that meets the voltage mutation condition among the plurality of voltage differences as the holding current of the phase change memory array.

10. A computer-readable medium, characterized in that The method comprises instructions which, when executed on a computer, cause the computer to execute the method according to any one of claims 1 to 8.

Images