Storage and calculation integrated chip, storage unit array structure and electronic equipment

Abstract

The invention discloses a storage and calculation integrated chip, a storage unit array structure and electronic equipment. A storage unit array in the storage and calculation integrated chip comprises a plurality of storage unit sub-arrays arranged in an array; the storage unit subarray comprises a plurality of switch units and a plurality of storage units arranged in an array, and the threshold voltage of the storage units is adjustable; the first ends of all the storage units in each column are connected with a source line, the second ends of all the storage units in each row are connected with a bit line, the third ends of all the storage units in each row are connected with a word line through a switch unit, the storage units in multiple rows are correspondingly connected with a plurality of switch units, and the control ends of the switch units are connected with local word lines of the storage unit sub-array. By controlling the local word line to control whether the storage unit subarrays are activated or not, all the storage unit subarrays in each row share a plurality of DACs, and all the storage unit subarrays in each column share a plurality of ADCs, so that the circuit area is reduced, the circuit cost is reduced, and the requirements of integration and low cost are met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a storage-computing integrated chip and a storage unit array structure. Background Art

[0002] In recent years, in order to solve the bottleneck of traditional von Neumann computing system architecture, the integrated memory and computing chip architecture has received widespread attention. Its basic idea is to directly use the memory for logical calculations, thereby reducing the amount of data transmission and transmission distance between the memory and the processor, reducing power consumption while improving performance.

[0003] The integrated storage and computing chip architecture is currently considered to be one of the efficient hardware platforms for solving the real-time intelligent processing of big data, and the storage cell array is the core circuit of the integrated storage and computing chip. For a typical storage cell array, it is necessary to be equipped with peripheral circuits such as digital-to-analog conversion modules, analog-to-digital conversion modules, and conversion devices.

[0004] In order to meet the complex computing requirements, the integrated storage and computing chip generally has multiple storage cell arrays for performing different computing tasks. Each of the multiple storage cell arrays needs to be equipped with corresponding digital-to-analog conversion modules, analog-to-digital conversion modules, conversion devices, decoders and other peripheral circuits. Usually, the area of ​​the peripheral circuits, especially the area of ​​ADC and DAC, is much larger than the area of ​​the storage cell array, and the cost is high. Therefore, the circuit area of ​​the existing integrated storage and computing chip architecture is large and the cost is high, which cannot meet the needs of integration and low cost. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a storage-computing integrated chip and a storage unit array structure to solve the problems of large circuit area, high cost and inability to adapt to the requirements of integration and low cost in the existing storage-computing integrated chip architecture.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] In a first aspect, a storage-computing integrated chip is provided, comprising:

[0008] A digital-to-analog conversion module, used for converting digital signals into analog signals;

[0009] A storage unit array, connected to the digital-to-analog conversion module, for performing analog vector-matrix multiplication operations on the analog signal and outputting analog operation results;

[0010] An analog-to-digital conversion module, connected to the storage unit array, for converting the analog operation result into a digital output signal;

[0011] Wherein, the storage cell array comprises: a plurality of storage cell sub-arrays arranged in an array, for respectively performing different simulated vector-matrix multiplication operations;

[0012] The memory cell subarray comprises: a plurality of switch units and a plurality of memory cells arranged in an array, wherein the threshold voltage of the memory cells is adjustable; the first ends of all the memory cells in each column are connected to a source line, the second ends are connected to a bit line, the third ends of all the memory cells in each row are connected to a word line via a switch unit, a plurality of rows of memory cells are correspondingly connected to a plurality of switch units, the control ends of the plurality of switch units are connected to a local word line of the memory cell subarray, and whether the memory cell subarray is activated is controlled by controlling the local word line.

[0013] Further, the switch unit includes: a first switch element and a second switch element;

[0014] The first end of the first switch element is connected to the first level, the second end is connected to the first end of the second switch element, the second end of the second switch element is connected to the word line, the third end of the first switch element and the third end of the second switch element are both connected to the local word line, and the third ends of all storage cells in the corresponding row of the switch unit are connected between the second end of the first switch element and the first end of the second switch element;

[0015] When working, one of the first switch element and the second switch element of the switch unit corresponding to the storage unit sub-array is in an on state, and the other is in an off state.

[0016] Furthermore, the storage unit is a programmable semiconductor device.

[0017] Furthermore, the programmable semiconductor device is a floating gate transistor.

[0018] Further, the storage unit includes: a non-volatile memory device and a third switch element;

[0019] The first end of the third switch element serves as the first end of the storage unit, the second end is connected to one end of the nonvolatile memory device, the third end serves as the third end of the storage unit, and the other end of the nonvolatile memory device serves as the second end of the storage unit.

[0020] Furthermore, the nonvolatile memory device is a resistive memory device, a phase change memory device or a spin memory device.

[0021] In a second aspect, a memory cell array structure is provided, comprising: a plurality of memory cell sub-arrays arranged in an array;

[0022] The memory cell subarray comprises: a plurality of switch units and a plurality of memory cells arranged in an array, the first ends of all memory cells in each column are connected to a source line, the second ends are connected to a bit line, the third ends of all memory cells in each row are connected to a word line via a switch unit, a plurality of rows of memory cells are correspondingly connected to a plurality of switch units, the control ends of the plurality of switch units are connected to a local word line of the memory cell subarray, and whether the memory cell subarray is activated is controlled by controlling the local word line.

[0023] Further, the switch unit includes: a first switch element and a second switch element;

[0024] The first end of the first switch element is connected to the first level, the second end is connected to the first end of the second switch element, the second end of the second switch element is connected to the word line, the third end of the first switch element and the third end of the second switch element are both connected to the local word line, and the third ends of all storage cells in the corresponding row of the switch unit are connected between the second end of the first switch element and the first end of the second switch element;

[0025] When working, one of the first switch element and the second switch element of the switch unit corresponding to the storage unit sub-array is in an on state, and the other is in an off state.

[0026] Furthermore, the storage unit is a programmable semiconductor device.

[0027] Further, the storage unit includes: a non-volatile memory device and a third switch element;

[0028] The first end of the third switch element serves as the first end of the storage unit, the second end is connected to one end of the nonvolatile memory device, the third end serves as the third end of the storage unit, and the other end of the nonvolatile memory device serves as the second end of the storage unit.

[0029] The present invention provides a storage-computing integrated chip and a storage cell array structure, wherein the storage cell array comprises: a plurality of storage cell sub-arrays arranged in an array; the storage cell sub-array comprises: a plurality of switch units and a plurality of storage cells arranged in an array, wherein the threshold voltage of the storage cell is adjustable; the first ends of all storage cells in each column are connected to a source line, the second ends are connected to a bit line, the third ends of all storage cells in each row are connected to a word line via a switch unit, multiple rows of storage cells are correspondingly connected to multiple switch units, the control ends of the multiple switch units are connected to a local word line of the storage cell sub-array, and the activation of the storage cell sub-array is controlled by controlling the local word line, thereby realizing that all storage cell sub-arrays in each row share multiple DACs, and all storage cell sub-arrays in each column share multiple ADCs, thereby reducing circuit area, reducing circuit cost, and meeting the requirements of integration and low cost.

[0030] Among them, multiple storage unit sub-arrays can work in time-sharing, and multiple storage unit sub-arrays in different rows and columns can work in parallel, which is suitable for different computing tasks and is flexible and convenient to use.

[0031] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A structural diagram of a storage-computing integrated chip according to an embodiment of the present invention is shown;

[0034] Figure 2 The circuit diagram of the memory cell array in the embodiment of the present invention is shown. Figure 1 ;

[0035] Figure 3 Shows Figure 2 A circuit diagram of a memory cell subarray in FIG.

[0036] Figure 4 The circuit diagram of the memory cell array in the embodiment of the present invention is shown. Figure 2 ;

[0037] Figure 5 A circuit structure of a storage unit in an embodiment of the present invention is shown;

[0038] Figure 6 Shows Figure 2 Another circuit diagram of a memory cell subarray;

[0039] Figure 7 A schematic diagram showing time-sharing operation of multiple storage unit sub-arrays in an embodiment of the present invention is shown;

[0040] Figure 8 A schematic diagram showing a plurality of storage unit sub-arrays operating in parallel in an embodiment of the present invention is shown;

[0041] Fig. 9 A structural diagram of another storage-computing integrated chip according to an embodiment of the present invention is shown;

[0042] Fig.10 The structure diagram of the programmable arithmetic operation unit 30 in the embodiment of the present invention is shown;

[0043] Fig.11 is a structural diagram of a programmable arithmetic operation subunit in an embodiment of the present invention;

[0044] Fig.12 Schematic diagram of a programmable arithmetic operation module implementing compound operations in an embodiment of the present invention

[0045] Fig.13 A structural diagram of another storage-computing integrated chip according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0047] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or apparatuses.

[0048] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] Unless otherwise specified, the expression “element A is connected to element B” means that element A is “directly” connected to element B or “indirectly” connected to element B through one or more other elements.

[0050] Existing integrated storage and computing chips generally have multiple memory cell arrays, and each of the multiple memory cell arrays needs to be respectively provided with corresponding digital-to-analog conversion modules, analog-to-digital conversion modules, conversion devices, decoders and other peripheral circuits, resulting in large circuit area and high cost, which cannot meet the needs of integration and low cost.

[0051] In order to solve the above-mentioned technical problems in the prior art, an embodiment of the present invention provides a storage and computing integrated chip, which controls whether the storage cell subarray is activated through the local word line in each storage cell subarray, so that all storage cell subarrays in each row share multiple DACs, and all storage cell subarrays in each column share multiple ADCs, thereby reducing the circuit area, reducing the circuit cost, and meeting the requirements of integration and low cost.

[0052] Figure 1 FIG. 1 shows a structural diagram of a storage-computing integrated chip according to an embodiment of the present invention. Figure 3 As shown, the integrated storage and computing chip includes: a digital-to-analog conversion module 60 , a storage cell array 20 and an analog-to-digital conversion module 70 .

[0053] The digital-to-analog conversion module is used to convert a digital signal into an analog signal; the storage unit array is connected to the digital-to-analog conversion module, and is used to perform an analog vector-matrix multiplication operation on the analog signal and output the analog operation result; the analog-to-digital conversion module is connected to the storage unit array, and is used to convert the analog operation result into a digital output signal;

[0054] Specifically, see Figure 2 The memory cell array comprises: a plurality of memory cell sub-arrays 20 arranged in an array 11 ~20 nm , used to perform different simulated vector-matrix multiplication operations respectively;

[0055] Each memory cell sub-array includes: a plurality of switch units K and a plurality of memory cells M arranged in an array. The threshold voltage of the memory cell is adjustable. By adjusting the threshold voltage of the memory cell, each memory cell is regarded as a variable equivalent analog weight, which is equivalent to analog matrix data. An analog voltage is applied to the memory cell array to realize a matrix multiplication operation function.

[0056] The first ends of all storage cells in each column are connected to the source line SL, and the second ends are connected to the bit line BL. The third ends of all storage cells in each row are connected to the word line WL through a switch unit K. Multiple rows of storage cells are correspondingly connected to multiple switch units, and the control ends of the multiple switch units are connected to the local word line SWL of the storage cell subarray. 11 , by controlling the local word line, controlling whether the memory cell subarray is activated.

[0057] Specifically, when the memory cell subarray is required to participate in the operation, the local word line SWL is controlled 11 , and then controlling the on / off state of each switch unit of the memory cell subarray to control the activation or inactivation of the memory cell subarray.

[0058] In order to facilitate those skilled in the art to fully understand the solution of the embodiment of the present invention, Figure 1 and Figure 2 , the operation process of the storage cell array is explained:

[0059] First, the memory cell sub-arrays that need to be put into operation are activated by controlling the local word lines of the memory cell sub-arrays.

[0060] The signal to be operated can be a digital signal with multiple digital bits. Each digital bit is converted into an analog signal through a DAC. The multiple digital bits are converted into multiple analog signals through multiple DACs respectively. The multiple analog signals are respectively input into multiple word lines WL corresponding to the activated storage cell subarray. After the analog vector-matrix multiplication operation is performed on the activated storage cell subarray, the operation results are output through the multiple bit lines corresponding to the activated storage cell subarray. The multiple bit lines correspond to multiple ADCs. The multiple analog signals output by the multiple bit lines are converted into digital signals by the multiple ADCs and then output.

[0061] In an optional embodiment, the switch unit may include: a first switch element and a second switch element;

[0062] The first end of the first switch element is connected to the first level, the second end is connected to the first end of the second switch element, the second end of the second switch element is connected to the word line, the third end of the first switch element and the third end of the second switch element are both connected to the local word line, and the third ends of all storage cells in the corresponding row of the switch unit are connected between the second end of the first switch element and the first end of the second switch element;

[0063] When working, one of the first switch element and the second switch element of the switch unit corresponding to the storage unit sub-array is in an on state, and the other is in an off state.

[0064] Those skilled in the art will understand that the switch element can be implemented by an NMOS transistor or a PMOS transistor, the first end of the switch element can be a source, the second end of the switch element can be a drain, and the third end of the switch element can be a gate. Of course, in the embodiment of the present invention, the first end of the switch element can also be a drain, and the second end of the switch element can be a source. The present invention does not limit this, and can be reasonably selected according to the type of transistor.

[0065] In addition, the first level may be a low level or a ground level.

[0066] Among them, the first switch element may be an NMOS transistor, and the second switch element may be a PMOS transistor; or, the first switch element may be a PMOS transistor, and the second switch element may be an NMOS transistor. The embodiment of the present invention does not limit this. It only needs to meet the requirement that during operation, one of the first switch element and the second switch element of the switch unit corresponding to the storage unit subarray is in the on state and the other is in the off state, that is, the two are complementary to each other.

[0067] For example, when the first switch element is a PMOS transistor and the second switch element is an NMOS transistor, when a high level is loaded on the local word line of a memory cell subarray, the NMOS transistor is turned on, the PMOS transistor is turned off, the memory cell subarray is activated, and the third end of each memory cell receives an input signal on the word line. When a ground level is loaded on the local word line of a memory cell subarray, the NMOS transistor is turned off, the PMOS transistor is turned off, the memory cell subarray is not activated, and the third end of each memory cell is grounded through the PMOS transistor.

[0068] In an alternative embodiment, see Figure 3 , the memory cell is a programmable semiconductor device, the programmable semiconductor device is a three-terminal device, such as a floating gate transistor, wherein the first terminal of the memory cell may be the source of the floating gate transistor, the second terminal of the memory cell may be the drain of the floating gate transistor, and the third terminal of the memory cell may be the gate of the floating gate transistor. Of course, in the embodiment of the present invention, the first terminal of the memory cell may also be the drain of the floating gate transistor, and the second terminal of the memory cell may be the source of the floating gate transistor, Figure 4 A circuit diagram of a memory cell array is shown when the memory cells are floating gate transistors.

[0069] In an alternative embodiment, see Figure 5 , the storage unit includes: a non-volatile storage device W1 and a switch element T;

[0070] The first end of the switch element T serves as the first end of the storage unit, the second end is connected to one end of the nonvolatile memory device W1, the third end serves as the third end of the storage unit, and the other end of the nonvolatile memory device W1 serves as the second end of the storage unit.

[0071] The non-volatile memory device may be a resistive memory device, a phase change memory device, a spin memory device, etc.

[0072] Those skilled in the art will understand that the switch element can be implemented by an NMOS transistor or a PMOS transistor, the first end of the switch element can be a source, the second end of the switch element can be a drain, and the third end of the switch element can be a gate. Of course, in the embodiment of the present invention, the first end of the switch element can also be a drain, and the second end of the switch element can be a source. The present invention does not limit this, and can be reasonably selected according to the type of transistor. Figure 6 The circuit structure of the memory cell subarray when the memory cell is composed of a switching element and a nonvolatile memory device is shown.

[0073] It is worth mentioning that the integrated storage and computing chip has two operation modes, one is that some storage unit subarrays work in time-sharing mode, and the other is that some storage unit subarrays work in parallel mode.

[0074] Next, taking the use of the integrated storage and computing chip to realize neural network calculations as an example, the time-sharing working principle of some storage unit subarrays is explained.

[0075] A neural network generally contains multiple layers of neurons. Each layer of neurons mainly implements matrix multiplication operations. The operation of the next layer of neurons depends on the operation results of the previous layer of neurons. Therefore, the operation of each layer of neurons is performed in time-sharing. Taking a 4-layer neural network as an example, each layer of neurons corresponds to a matrix multiplication operation. Four storage unit subarrays are required to implement the operation of the four layers of neurons respectively, and the four storage unit subarrays work in time-sharing. At this time, any four storage unit subarrays t1~t4 can be selected (see Figure 7 ), pre-configure the threshold voltages of the storage cells in the four storage cell subarrays t1 to t4, each storage cell is equivalent to storing a weight data, which is equivalent to a neuron. The four storage cell subarrays t1 to t4 respectively implement the operations of the 1st to 4th layers of neurons. During the operation, the storage cell subarray t1 is first activated, and then the input features are input into the word line corresponding to the storage cell subarray t1. The output of the bit line corresponding to the storage cell subarray t1 is the operation result of the first layer of neurons. Then the storage cell subarray t2 is activated, and the operation result of the first layer of neurons is input into the word line corresponding to the storage cell subarray t2. The output of the bit line corresponding to the storage cell subarray t2 is the operation result of the first layer of neurons. And so on, the operation result of the four-layer neural network is finally obtained.

[0076] By utilizing some storage cell subarrays to work in time-sharing mode, all storage cell subarrays in each row can share multiple DACs, and all storage cell subarrays in each column can share multiple ADCs, thereby reducing circuit area and circuit cost to meet the needs of integration and low cost.

[0077] In addition, for some complex operations or operations on a relatively large scale, some storage cell subarrays need to work in parallel to achieve the required operations. At this time, because the inputs and outputs of the multiple storage cell subarrays working in parallel may be different, it is necessary to select multiple storage cell subarrays in different rows and columns to participate in the work.

[0078] For example, when four memory cell subarrays need to work in parallel to implement a large-scale operation, see Figure 8, four memory cell subarrays D1 to D4 that are not in the same row or column can be selected to work at the same time, and the threshold voltages of the memory cells in the four memory cell subarrays D1 to D4 are configured in advance, and each memory cell is equivalent to storing a weight data. During the operation, the local word lines of the memory cell subarrays D1 to D4 are controlled to activate the memory cell subarrays D1 to D4, and then the input features are input into the word lines corresponding to the memory cell subarrays D1 to D4. The output of the bit lines corresponding to the memory cell subarrays D1 to D4 is the operation result.

[0079] Among them, by selecting multiple storage unit subarrays of different rows and columns to work in parallel, the adaptability of the embodiment of the present invention can be greatly improved, and it can adapt to large-scale or even ultra-large-scale calculations, and can also adapt to neural networks with large amounts of calculations in image processing, navigation, etc. At this time, the calculations corresponding to each layer of neurons can be implemented by multiple storage unit subarrays working in parallel, which can adapt to different computing tasks, greatly improving the flexibility of the use of the storage and computing integrated chip.

[0080] In an optional embodiment, the digital-to-analog conversion module 60 includes a plurality of DACs; the plurality of DACs are respectively connected to the front ends of a plurality of word lines, and are used to convert digital signals applied to the word lines into analog signals.

[0081] In an optional embodiment, the analog-to-digital conversion module 70 includes a plurality of ADCs; the plurality of ADCs are respectively connected to the rear ends of a plurality of bit lines, and are used to convert the analog operation results on the bit lines into digital output signals.

[0082] In an optional embodiment, if Fig. 9 As shown, the integrated storage and computing chip may further include: a programmable arithmetic operation module 30, which is arranged at the output end of the analog-to-digital conversion module 70 and is used to perform arithmetic operations on the digital output signal.

[0083] Those skilled in the art can understand that for some complex operations, on the basis of simulating vector-matrix multiplication operations, some arithmetic operations will also be needed, such as multiplication, addition, subtraction, division, shift, activation function, maximum value, minimum value, average value, pooling, etc., or a combination of several of them, in order to obtain the final operation result.

[0084] Therefore, by setting a programmable arithmetic operation module at the output end of the analog-to-digital conversion module, further arithmetic operations are performed on the operation results output by the storage cell array, thereby improving the applicability of the integrated storage and computing chip and expanding the scope of application.

[0085] The programmable arithmetic operation module 30 includes a plurality of programmable arithmetic operation units 301 to 302 for respectively implementing different arithmetic operations.n Among them, the programmable arithmetic operation unit is implemented in hardware and is used to perform specific arithmetic operations.

[0086] The programmable arithmetic operation module 30 includes a plurality of programmable arithmetic operation units 301 to 30 n Serial connection, each of the programmable arithmetic operation units includes: a multiplexer 30a, an arithmetic operation subunit 30b and a multiplexer 30c, see Fig.10 .

[0087] The input end of the multiplexer 30a is connected to a programmable arithmetic operation unit or the analog-to-digital conversion module 70, one of its output ends is connected to the arithmetic operation sub-unit 30b, the output end of the arithmetic operation sub-unit 30b and another output end of the multiplexer 30a are connected to the next programmable arithmetic operation unit or the output register stack 80 through a multiplexer 30c. In addition, the control ends of the multiplexer 30a and the multiplexer 30c are both connected to the control module 10.

[0088] Specifically, the input end of the multiplexer in the first programmable arithmetic operation unit 301 is connected to the output end of the analog-to-digital conversion module 70, one of the output ends is connected to the input end of the arithmetic operation subunit in the first programmable arithmetic operation unit 301, and the other output end and the output end of the arithmetic operation subunit are connected to the input end of the second programmable arithmetic operation unit 302 through a multiplexer, and the control end of the multiplexer and the multiplexer are connected to the control module 20.

[0089] The input end of the demultiplexer in the second programmable arithmetic operation unit 302 is connected to the output end of the first programmable arithmetic operation unit 301, one of the output ends is connected to the input end of the arithmetic operation subunit in the second programmable arithmetic operation unit 302, the other output end and the output end of the arithmetic operation subunit are connected to the input end of the third programmable arithmetic operation unit 303 through a multiplexer, and the control end of the demultiplexer and the multiplexer are connected to the control module 20. And so on, until the nth programmable arithmetic operation unit 30 n , the nth programmable arithmetic operation unit 30 n The input end of the multiplexer is connected to the n-1th programmable arithmetic operation unit 30 n-1 The output terminals of the nth programmable arithmetic operation unit 30 are connected to one of the output terminals. n The input end of the arithmetic operation subunit in the arithmetic operation subunit, the other output end and the output end of the arithmetic operation subunit are connected to the input end of the output register stack 80 through a multiplexer, and the multiplexer and the control end of the multiplexer are connected to the control module 10.

[0090] The control module 10 is connected to the multiplexer and the multiplexer in each programmable arithmetic operation unit, and controls the multiplexer and the multiplexer in each programmable arithmetic operation unit to select whether the arithmetic operation sub-unit in the programmable arithmetic operation unit participates in the operation, thereby realizing the arrangement and combination configuration of multiple programmable arithmetic operation units, realizing different complex operations, and flexibly configuring the arithmetic operation function.

[0091] In an optional embodiment, each of the programmable arithmetic operation subunits may include a plurality of arithmetic operators arranged in parallel, such as one or more of a multiplier, an adder, a subtractor, a divider, a shifter, an activation function device, a maximum value operator, a minimum value operator, an average value operator, and a pooler. The arithmetic operators are connected in parallel, and the input ends are respectively connected to the output ends of the corresponding multiplexers, and the output ends are respectively connected to the input ends of the corresponding multiplexers, see Fig.11 .

[0092] The programmable arithmetic operation module performs compound operations as follows: Fig.12 shown.

[0093] In an optional embodiment, the storage and computing integrated chip may also include: an input interface 40 , an input register stack 50 , an output register stack 80 , an output interface module 90 and a control module 10 .

[0094] The control module 10 dynamically configures the chip topology according to the configuration information and the finite state machine information.

[0095] Among them, the configuration information and the finite state machine information can be obtained through the compilation tool according to the actual application requirements.

[0096] Among them, configuration information is usually static, such as specifying the status of each module involved in the task and the configuration size of each unit; configuration information is usually stored in the memory and scheduled before the task is run. Finite state machine information is usually dynamic, and when the task is running, it controls the timing and status of the actual task.

[0097] Specifically, the control module 10 combines and configures the multiple storage cell sub-arrays and the multiple programmable arithmetic operation units according to the configuration information, selects the storage cell sub-arrays and programmable arithmetic operation units to be put into operation, and controls the combination pairing mode of the storage cell sub-arrays and the programmable arithmetic operation units to achieve specific operations.

[0098] It can be understood that each of the multiple programmable arithmetic operation units can implement one or several arithmetic operations, and the multiple programmable arithmetic operation units can be arranged and combined to perform multiple composite operations, and cooperate with multiple storage unit sub-arrays to achieve multiple combination configurations, thereby realizing complex computing functions.

[0099] The input end of the input interface module 40 is connected to an external device for receiving input data (ie, data to be calculated) from the external device.

[0100] The input end of the input register file 50 is connected to the output end of the input interface module 40 for temporarily storing the input data or data to be processed.

[0101] The input end of the digital-to-analog conversion module 60 is connected to the output end of the input register stack 50, and the output end is connected to the input end of the storage cell array 20, and is used to convert the external input data or the data to be processed output from the input register stack 50 into an analog signal and input it to the storage cell array 20. The storage cell array 20 performs an analog vector-matrix multiplication operation on the analog signal and outputs the analog vector-matrix multiplication operation result.

[0102] The input end of the analog-to-digital conversion module 70 is connected to the storage cell array 20, and the output end is connected to the programmable arithmetic operation module 30, and is used to convert the analog vector-matrix multiplication result into a digital signal and input it to the programmable arithmetic operation module 30. The programmable arithmetic operation module 30 performs arithmetic operation on the digital signal and outputs the arithmetic operation result.

[0103] The input end of the output register stack 80 is connected to the programmable arithmetic operation module 30 , and the output end is connected to the input register stack 50 , so as to temporarily store the arithmetic operation result, and output the arithmetic operation result or input it to the input register stack 50 as the data to be processed.

[0104] The input end of the output interface module 90 is connected to the output end of the output register stack 80 , receives output data of the output register stack 80 , and outputs the output data to an external device.

[0105] Specifically, the input end of the input register file 50 is connected to the output end of the input interface module 40 and the output end of the output register file 80 through a first multiplexer to selectively receive external input data from the input interface module 40 or data to be processed from the output register file 80 .

[0106] The output end of the output register stack 80 is selectively connected to the input end of the output interface module 90 or the input end of the input register stack 50 through a multiplexer to select whether the output result of the output register stack 80 is input to the output interface module 90 or the input register stack 50. When the output result of the output register stack 80 is selected to be input to the input register stack 50, it means that a new round of calculation processing will be performed on the output result.

[0107] In an optional embodiment, the output end of the input register stack 50 can also be selectively connected to the input end of the digital-to-analog conversion module 50 or the input end of the programmable arithmetic operation module 30 through a multiplexer to select whether to connect the output end of the input register stack 50 to the input end of the digital-to-analog conversion module 50 or the input end of the programmable arithmetic operation module 30, wherein when the output end of the input register stack 50 is connected to the input end of the digital-to-analog conversion module 50, it means that analog vector-matrix multiplication operations and arithmetic operations are performed on the output of the input register stack 50; when the output end of the input register stack 50 is connected to the input end of the input end of the programmable arithmetic operation module 30, it means that certain arithmetic operations are performed on the output of the input register stack 50, thereby further increasing the flexibility of the chip architecture.

[0108] In an optional embodiment, the software-definable storage and computing integrated chip may also include: a programming circuit 22 , which is connected to the control module 10 .

[0109] The programming circuit 22 is connected to the source, gate and / or substrate of each memory cell in the memory cell array, and is used to adjust the threshold voltage of the memory cell under the control of the control module 10 .

[0110] The programming circuit includes: a voltage generating circuit for generating a programming voltage or an erasing voltage and a voltage control circuit for loading the programming voltage to a selected storage cell.

[0111] Specifically, the programming circuit utilizes the hot electron injection effect and applies a high voltage to the source of the memory cell according to the threshold voltage requirement data of the memory cell, thereby accelerating the channel electrons to a high speed to increase the threshold voltage of the memory cell.

[0112] Furthermore, the programming circuit utilizes the tunneling effect to apply a high voltage to the gate or substrate of the memory cell according to the threshold voltage requirement data of the memory cell, thereby reducing the threshold voltage of the memory cell.

[0113] In addition, the control module 10 is connected to the programming circuit and is used to control the programming circuit to adjust the weights stored in the storage cell array 20 .

[0114] In an optional embodiment, the integrated storage and computing chip may further include: a row-column decoder. The row-column decoder is connected to the storage cell array 20 and the control module 10 and is used to perform row-column decoding on the storage cell array 20 under the control of the control module 10.

[0115] The storage cell array may be a NOR flash memory cell array, a NAND flash memory cell array, a RRAM device, etc. However, the present invention is not limited thereto.

[0116] In an optional embodiment, the storage and computing integrated chip further includes: a conversion device, wherein the conversion device includes multiple conversion branches, and the multiple conversion branches are respectively connected to the output ends of multiple DACs, and are used to convert the analog current signal output by the DAC into an analog voltage signal.

[0117] In an alternative embodiment, see Fig.13 The conversion device includes a plurality of conversion branches, each conversion branch includes a storage unit, the gate and drain of the storage unit are connected to the corresponding analog voltage input terminal, and the source is connected to the first bias voltage.

[0118] It can be understood that the first bias voltage connected to the source can be a ground voltage, that is, the source is grounded.

[0119] In an optional embodiment, the conversion branch includes a resistor, one end of the resistor is connected to the output end of the DAC, and the other end is connected to the first bias voltage, wherein it can be understood that the first bias voltage can be a ground voltage, that is, the other end of the resistor is grounded.

[0120] In summary, the storage and computing integrated chip provided by the embodiment of the present invention divides a large storage unit array into n small arrays, and each sub-array corresponds to completing the matrix multiplication and addition operation of a layer of neural network. Multiple sub-arrays (satisfying non-same row and non-same column) can work in parallel, which can not only reduce the circuit area, reduce the cost, and improve the throughput, but also improve the parallelism and the processing speed. At the same time, it is compatible with multi-task time division multiplexing and is flexible and convenient to use.

[0121] An embodiment of the present invention also provides a memory cell array structure, comprising: a plurality of memory cell sub-arrays arranged in an array; the memory cell sub-arrays comprise: a plurality of switch units and a plurality of memory cells arranged in an array, the first ends of all memory cells in each column are connected to a source line, the second ends are connected to a bit line, the third ends of all memory cells in each row are connected to a word line via a switch unit, multiple rows of memory cells are correspondingly connected to a plurality of switch units, the control ends of the plurality of switch units are connected to a local word line of the memory cell sub-array, and whether the memory cell sub-array is activated is controlled by controlling the local word line.

[0122] Specifically, when the memory cell subarray is required to participate in the work, the local word line SWL is controlled 11 , and then controlling the on / off state of each switch unit of the memory cell subarray to control the activation or inactivation of the memory cell subarray.

[0123] In an optional embodiment, the switch unit includes: a first switch element and a second switch element;

[0124] The first end of the first switch element is connected to the first level, the second end is connected to the first end of the second switch element, the second end of the second switch element is connected to the word line, the third end of the first switch element and the third end of the second switch element are both connected to the local word line, and the third ends of all storage cells in the corresponding row of the switch unit are connected between the second end of the first switch element and the first end of the second switch element;

[0125] When working, one of the first switch element and the second switch element of the switch unit corresponding to the storage unit sub-array is in an on state, and the other is in an off state.

[0126] Those skilled in the art will understand that the switch element can be implemented by an NMOS transistor or a PMOS transistor, the first end of the switch element can be a source, the second end of the switch element can be a drain, and the third end of the switch element can be a gate. Of course, in the embodiment of the present invention, the first end of the switch element can also be a drain, and the second end of the switch element can be a source. The present invention does not limit this, and can be reasonably selected according to the type of transistor.

[0127] In addition, the first level may be a low level or a ground level.

[0128] Among them, the first switch element may be an NMOS transistor, and the second switch element may be a PMOS transistor; or, the first switch element may be a PMOS transistor, and the second switch element may be an NMOS transistor. The embodiment of the present invention is not limited to this. It only needs to meet the requirement that during operation, one of the first switch element and the second switch element of the switch unit corresponding to the storage unit subarray is in the on state and the other is in the off state.

[0129] In an optional embodiment, the memory cell is a programmable semiconductor device. The programmable semiconductor device is a three-terminal device, such as a floating gate transistor, wherein the first terminal of the memory cell may be a floating gate transistor source, the second terminal of the memory cell may be a floating gate transistor drain, and the third terminal of the memory cell may be a floating gate transistor gate. Of course, in the embodiment of the present invention, the first terminal of the memory cell may also be a floating gate transistor drain, and the second terminal of the memory cell is a floating gate transistor source.

[0130] In an optional embodiment, the storage unit includes: a non-volatile memory device and a transistor;

[0131] The first end of the transistor serves as the first end of the storage unit, the second end is connected to one end of the nonvolatile memory device, the third end serves as the third end of the storage unit, and the other end of the nonvolatile memory device serves as the second end of the storage unit.

[0132] The non-volatile memory device may be a resistive memory device, a phase change memory device, a spin memory device, etc.

[0133] Those skilled in the art will understand that the switch element can be implemented by an NMOS transistor or a PMOS transistor, the first end of the switch element can be a source, the second end of the switch element can be a drain, and the third end of the switch element can be a gate. Of course, in the embodiment of the present invention, the first end of the switch element can also be a drain, and the second end of the switch element can be a source. The present invention does not limit this, and can be reasonably selected according to the type of transistor.

[0134] For more details of the memory cell array structure, please refer to the memory cell array in the above-mentioned storage and computing integrated chip, which will not be repeated here.

[0135] It can be seen from the above technical solution that the storage cell array structure can flexibly control the number of storage cell sub-arrays participating in the work, and can remove idle storage cell sub-arrays or damaged storage cell sub-arrays to save energy consumption and increase the service life and practical flexibility of the storage cell array.

[0136] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned storage and computing integrated chip.

[0137] The electronic device can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0138] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A memory cell array structure, characterized in that: include: A plurality of memory cell sub-arrays arranged in an array, wherein one memory cell sub-array corresponds to one local word line, the memory cell sub-array comprises memory cells arranged in an array in a plurality of rows and a plurality of switch units, and one row of memory cells corresponds to one switch unit; In the memory cell sub-array, control terminals of the plurality of switch units are connected to local word lines corresponding to the memory cell sub-array, and activation of the memory cell sub-array is controlled by controlling the switch units through the local word lines.

2. The memory cell array structure according to claim 1, characterized in that: The storage unit includes a first end, a second end and a third end; In the memory cell subarray, first ends of memory cells in the same column are connected in a common line, second ends of memory cells in the same column are connected in a common line, and third ends of memory cells in the same row are connected in a common line and connected to a word line through a corresponding switch unit.

3. The memory cell array structure according to claim 2, characterized in that: The plurality of array-arranged storage cell subarrays include: a first storage cell subarray and a second storage cell subarray, wherein the first storage cell subarray includes a first storage cell row and a first switch unit, and the second storage cell subarray includes a second storage cell row and a second switch unit, wherein the first storage cell row and the second storage cell row are located in the same row; The third terminals of the memory cells in the first memory cell row are connected to the first word line through the first switch unit; The third terminals of the memory cells in the second memory cell row are connected to the first word line through the second switch unit.

4. The memory cell array structure according to claim 2, characterized in that: The plurality of array-arranged storage cell subarrays include: a third storage cell subarray and a fourth storage cell subarray, the third storage cell subarray includes a first storage cell column, the fourth storage cell subarray includes a second storage cell column, wherein the first storage cell column and the second storage cell column are located in the same column; In the third storage cell sub-array and the fourth storage cell sub-array, the storage cells located in the same column have first ends connected in a common line and second ends connected in a common line.

5. The memory cell array structure according to claim 4, characterized in that: In the first memory cell sub-array and the second memory cell sub-array, the memory cells in the same column have first ends connected to the same source line, and second ends connected to the same bit line.

6. The memory cell array structure according to claim 2, characterized in that: The switch unit comprises: a first switch element and a second switch element; The first end of the first switch element is used to couple the first level, the second end is connected to the first end of the second switch element, the second end of the second switch element is connected to the word line, the third end of the first switch element and the third end of the second switch element are connected to the local word line, and the third ends of the storage cells in the corresponding row of the switch unit are connected to the second end of the first switch element and the first end of the second switch element; The activation of the memory cell sub-array corresponding to the local word line is controlled by controlling the first switch element connected thereto to be turned off and the second switch element to be turned on.

7. A storage and computing integrated chip, characterized in that: include: A digital-to-analog conversion module, used for converting digital signals into analog signals; A storage unit array, connected to the digital-to-analog conversion module, configured to perform analog vector-matrix multiplication operations on the analog signals and output analog operation results; An analog-to-digital conversion module, connected to the storage unit array, for converting the analog operation result into a digital output signal; The memory cell array comprises the memory cell array structure according to any one of claims 1 to 6.

8. The integrated storage and computing chip according to claim 7, characterized in that: Also includes: A control module is used to dynamically configure the topology of the storage and computing integrated chip.

9. The storage and computing integrated chip according to claim 8, characterized in that: Also includes: The programmable arithmetic operation module is used to receive the digital output signal and perform arithmetic operation on the digital output signal.

10. The storage-computing integrated chip according to claim 9, characterized in that: The programmable arithmetic operation module includes a plurality of programmable arithmetic operation units connected in series; The control module is used to combine and configure the multiple storage cell subarrays and the multiple programmable arithmetic operation units according to the configuration information, select the storage cell subarrays and programmable arithmetic operation units to be put into operation, and control the combination pairing mode of the storage cell subarrays and the programmable arithmetic operation units.

11. The storage-computing integrated chip according to claim 7, characterized in that: A first operation mode is included, and in the first operation mode, some storage cell sub-arrays in the plurality of storage cell sub-arrays operate in time-sharing manner.

12. The storage-computing integrated chip according to claim 7, characterized in that: A second operation mode is included, and in the second operation mode, some memory cell subarrays in the plurality of memory cell subarrays operate in parallel, wherein the plurality of memory cell subarrays in non-same rows and columns operate in parallel.

13. An electronic device, characterized in that: It comprises a storage-computing integrated chip as described in any one of claims 7 to 12.

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