Apparatus and method for changing read voltage applied for reading data

Abstract

The invention discloses an apparatus and a method for changing a read voltage applied for reading data. A read retry table generator is coupled to a plurality of memory dies through data paths. The read retry table generator is configured to: collect data from a plurality of memory cells coupled with a plurality of word lines in a plurality of memory dies; determining a pass rate of the collected data belonging to the plurality of clusters; selecting a cluster candidate among a plurality of clusters based on a pass rate of the collected data; and clustering the collected data into cluster candidates to generate a read retry table.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Korean Patent Application No. 10-2023-0140252, filed on October 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments of the present disclosure described herein relate to a memory device, and more particularly, to an apparatus and method for generating or changing a read voltage for reading data stored in a nonvolatile memory cell in the memory device. Background Art

[0004] Memory devices are usually provided in computers or other electronic devices as internal semiconductor integrated circuits and / or external removable devices. There are various types of memory, including volatile memory and non-volatile memory. Volatile memory may require power to retain the data stored therein. Volatile memory may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM) and synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain the data stored therein when power is not supplied. Non-volatile memory may include NAND flash memory, NOR flash memory, phase change random access memory (PCRAM), resistance random access memory (RRAM) and magnetic random access memory (MRAM). Improving memory devices may include integrated control of different types of memory, reducing power consumption, improving the reliability of data retention, preventing potential modification of data due to power supply interruption and / or reducing manufacturing costs. Summary of the invention

[0005] Embodiments of the present disclosure may provide a device and method capable of generating a read retry table for changing the level of a read voltage applied to a word line to read data stored in a non-volatile memory cell. The device may be configured to: collect sampled data from a plurality of memory dies including non-volatile memory cells; select cluster candidates based on a pass rate; perform a first clustering of a plurality of word lines in the cluster candidates based on an error correction capability of an ECC module for the collected data; perform a second clustering of outliers after the first clustering; and generate a read retry table based on the clustered word lines.

[0006] Embodiments of the present disclosure may provide an apparatus and an operating method for reducing the cost and time required to develop and produce a plurality of memory dies by sampling data from a wafer having a plurality of memory dies formed thereon, selecting cluster candidates based on a pass rate, and generating a read retry table based on a machine learning mechanism using a clustering algorithm.

[0007] Embodiments of the present disclosure may provide a device and method for reducing resources consumed in generating a read retry table based on a machine learning mechanism using sampled data when the read retry table needs to be modified or updated based on the operating status, loss or life of multiple memory tube cores included in the memory system.

[0008] In an embodiment of the present disclosure, a read retry table generator may be connected to a plurality of memory dies via a data path. The read retry table generator may be configured to: collect data from a plurality of memory cells connected to a plurality of word lines in the plurality of memory dies; determine a pass rate of the collected data belonging to a plurality of clusters; select cluster candidates among the plurality of clusters based on the pass rate of the collected data; and cluster the collected data into cluster candidates to generate a read retry table.

[0009] Multiple memory dies can be arranged in the same row or column on the same wafer.

[0010] The plurality of word lines may correspond to at least one same row address sampled from a memory block or a word line group included in each of the plurality of memory dies.

[0011] The read retry table generator may be coupled to multiple memory dies via the same channel of the data path.

[0012] The read retry table generator can be configured to cluster the collected data into cluster candidates in the following manner: performing a first clustering on multiple word lines based on the error correction capability of the error correction circuit on the collected data; performing a second clustering on abnormal values ​​of the first cluster; and generating or updating the read retry table based on values ​​obtained from the first cluster and the second cluster.

[0013] The read retry table generator may include: a cluster candidate selector configured to, for at least one cluster on a plurality of word lines, increase a pass rate of at least one cluster if a fail bit count is within an error correction capability of an error correction circuit, and sequentially select cluster candidates starting from a highest pass rate among the pass rates of each cluster; and a first read retry table generator configured to generate a first read retry table by performing a first clustering on the cluster candidates and performing a second clustering on the outliers.

[0014] The first clustering may include: searching for a centroid corresponding to cluster candidates; adding word lines belonging to a Voronoi distance range from the centroid to the cluster candidates, the Voronoi distance range corresponding to the error correction capability of the error correction circuit; and classifying word lines not belonging to the cluster candidates as outliers of the first cluster.

[0015] The read retry table generator may be configured to calculate a fail bit count for each of the plurality of word lines based on a preset level of a read voltage corresponding to a selected value among multi-bit data stored in the plurality of memory cells.

[0016] The second clustering may include: adding outliers of the first cluster to an additional cluster having a Voronoi distance range calculated based on an error correction capability of the error correction circuit and a fail bit count obtained by applying a value stored or predetermined in a read retry table before a read retry table generator generates or updates the read retry table; and calculating a value of the read retry table to add all outliers of the first cluster to the additional cluster.

[0017] The read retry table generator may further include: a second read retry table generator configured to generate a second read retry table based on information about cluster candidates through the first cluster and another cluster different from the second cluster; and a comparator configured to compare the first read retry table with the second read retry table and select one of the first read retry table and the second read retry table based on the comparison result.

[0018] The comparator may compare ranges of the first read retry table and the second read retry table and select one of the read retry tables having a wider range.

[0019] The comparator may compare the number of tables belonging to each of the first read retry table and the second read retry table and select one of the read retry tables having a smaller number of tables.

[0020] In another embodiment of the present disclosure, a method for operating a data processing device may include: collecting data from multiple memory cells connected to multiple word lines in multiple memory tube cores via a data path; determining a pass rate of the collected data belonging to multiple clusters; selecting cluster candidates among multiple clusters based on the pass rate of the collected data; performing a first clustering on the multiple word lines based on the cluster candidates and the error correction capability of the error correction circuit on the collected data; performing a second clustering on abnormal values ​​of the first cluster; and generating or updating a first read retry table based on values ​​obtained from the first cluster and the second cluster.

[0021] Generating or updating the first read retry table may include: receiving values ​​obtained from the first cluster and the second cluster over a network; generating or updating the first read retry table based on the values; and storing the first read retry table in a non-volatile memory device.

[0022] Selecting the cluster candidates may include: setting a plurality of clusters for the plurality of word lines and calculating a pass rate of each of the plurality of clusters; and sequentially selecting the cluster candidates starting from a cluster corresponding to a highest pass rate among the pass rates of the plurality of clusters.

[0023] Calculating the pass rate may include: if a first word line among multiple word lines is applied to a first cluster among multiple clusters, when a fail bit count of the first word line is within the error correction capability of the error correction circuit, increasing the pass rate of the first cluster; and when the fail bit count of the first word line exceeds the error correction capability of the error correction circuit, reducing the pass rate of the first cluster.

[0024] Performing the first clustering may include: searching for a centroid corresponding to a cluster candidate; adding word lines belonging to a Voronoi distance range from the centroid to the cluster candidate, the Voronoi distance range corresponding to the error correction capability of the error correction circuit; and classifying word lines that do not belong to the cluster candidate as outliers of the first cluster.

[0025] Performing the second clustering may include: adding outliers of the first cluster to an additional cluster having a Voronoi distance range calculated based on an error correction capability of the error correction circuit and a fail bit count, the fail bit count being obtained by applying a value stored or predetermined in the read retry table before generating or updating the first read retry table; and calculating values ​​of the first read retry table to add all outliers of the first cluster to the additional cluster.

[0026] The method may further include: generating a second read retry table based on information about cluster candidates by the first clustering and another clustering different from the second clustering; and selecting one of the first read retry table and the second read retry table.

[0027] Selecting one of the first read retry table and the second read retry table may include: comparing the number of tables belonging to each of the first read retry table and the second read retry table or the range of the first read retry table and the second read retry table; and selecting a read retry table with fewer tables or a read retry table with a wider range. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present description refers to the drawings, wherein like reference numerals refer to like parts throughout.

[0029] Figure 1 A memory testing apparatus according to an embodiment of the present disclosure is described.

[0030] Figure 2 A read retry operation according to an embodiment of the present disclosure is described.

[0031] Figure 3 A read retry table according to an embodiment of the present disclosure is described.

[0032] Figure 4 A first method of generating a read retry table according to an embodiment of the present disclosure is shown.

[0033] Figure 5 Parameters used in a machine learning algorithm for generating a read retry table according to an embodiment of the present disclosure are shown.

[0034] Figure 6 A first read retry table generator according to an embodiment of the present disclosure is shown.

[0035] Figure 7 A cluster candidate selector according to an embodiment of the present disclosure is shown.

[0036] Figure 8 A second read retry table generator according to another embodiment of the present disclosure is shown.

[0037] Fig. 9 A data sampling method according to an embodiment of the present disclosure is shown.

[0038] Fig.10 A data clustering method according to an embodiment of the present disclosure is shown.

[0039] Fig.11 The coverage of the read retry table according to an embodiment of the present disclosure is shown.

[0040] Fig.12 A data processing system according to an embodiment of the present disclosure is shown.

[0041] Fig.13 A second method of generating a read retry table according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments that are variations of any of the disclosed embodiments.

[0043] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “optional embodiments,” etc.) are intended to indicate that any of these features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0044] In this disclosure, the terms "comprising", "including", "includes" and "comprising" are open ended. As used in the appended claims, these terms specify the presence of the stated elements and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components, such as interface units, circuits, etc.

[0045] In the present disclosure, various units, circuits, or other components may be described or stated as being "configured to" perform one or more tasks. In this context, "configured to" is used to represent a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even when the block / unit / circuit / component is not currently running (e.g., not turned on or activated), it can be said that the specified block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuit / components used with the "configured to" language include hardware, circuits, memories storing program instructions that can be run to implement operations, etc. In addition, "configured to" can include general structures (e.g., general circuits) manipulated by software and / or firmware (e.g., FPGAs or general processors running software) to operate in a manner that can perform the relevant (multiple) tasks. "Configured to" can also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture devices (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0046] As used in this disclosure, the terms "machine", "circuit" or "logic" refer to all of the following: (a) pure hardware circuit implementations (e.g., implementations in analog and / or digital circuits only), and (b) combinations of circuits with software and / or firmware, such as (as applicable to): (i) a combination of (multiple) processors or (ii) (multiple) processors / software that work together to enable a device such as a mobile phone or server to perform various functions, including (multiple) digital signal processors, software, and (multiple) memory (s); and (c) circuits that require software or firmware to operate even if the software or firmware is not physically present, such as (multiple) microprocessors or (multiple) microprocessor (s) A portion of a microprocessor. This definition of "machine", "circuit" or "logic" applies to all uses of the term in this application (including any claims). As another example, as used in this application, the term "machine", "circuit" or "logic" also covers implementations of only one processor or multiple processors or a portion of a processor and its (or their) accompanying software and / or firmware. For example, if applicable to a particular claim element, the term "machine", "circuit" or "logic" also covers an integrated circuit of a storage device.

[0047] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns preceding them, and do not imply any type of ordering, such as space, time, logic, etc. The terms "first" and "second" do not necessarily mean that the first value must be written before the second value. In addition, although these terms can be used to identify various elements in this article, these elements are not limited by these terms. These terms are used to distinguish one element from another element, otherwise they will have the same or similar names. For example, a first circuit can be distinguished from a second circuit.

[0048] Additionally, the term "based on" is used to describe one or more factors that influence a determination. The term does not exclude other factors that may influence the determination. That is, a determination may be based only on those factors or at least in part on those factors. Consider the phrase "determining A based on B." While in this case, B is a factor that influences the determination of A, this statement does not exclude that the determination of A is also based on C. In other cases, A may be determined based only on B.

[0049] These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments of the present disclosure and the accompanying drawings. Embodiments will now be described with reference to the drawings, wherein like reference numerals refer to like elements.

[0050] Figure 1 A memory testing apparatus according to an embodiment of the present disclosure is described.

[0051] Reference Figure 1 , the memory device 950 may include a plurality of nonvolatile memory cells 924, an output buffer 922, a read voltage generator 926, and a read retry table (RRT) 928. Herein, the memory device 950 may include at least one memory die.

[0052] The memory test device 900 is coupled to the memory device 950. The memory test device 900 may be configured to check at least one defect and operation characteristic of the memory device 950. According to an embodiment, the memory test device 900 may include various components according to a test purpose, test performance, etc. For ease of description, Figure 1 , the memory test device 900 includes an RRT generating and updating (generating / updating) device 910, which is configured to test a read operation performed on a memory device 950 and generate or update an RRT.

[0053] The RRT may be stored in a plurality of nonvolatile memory cells 924 included in the memory device 950. In the process of applying a read voltage to the plurality of nonvolatile memory cells 924 in the memory device 950 through a word line and reading data stored in the plurality of nonvolatile memory cells 924 in the memory device 950, a read error may occur. The memory device 950 may include or store information about a read retry mechanism for resolving read errors. An example of information about a read retry mechanism may include an RRT. The read retry mechanism may use the RRT to record the location where the read error occurred and apply an appropriate correction value to the level of the read voltage applied through the word line for rereading the data stored in the plurality of nonvolatile memory cells 924, thereby improving or ensuring data integrity.

[0054] The RRT generation / update device 910 may include: a data verification module 912 configured to verify the read data; a parameter buffer 916 configured to store variables, parameters and results of a machine learning (ML) mechanism about the RRT; and an RRT generation module 914 configured to execute a machine learning (ML) mechanism to determine the value contained in the RRT. According to an embodiment, the memory test device 900 may store the RRT in the parameter buffer 916 or in an internal storage space.

[0055] Examples of machine learning (ML) algorithms performed by the RRT generation / update device 910 may include clustering algorithms. Here, clustering is an unsupervised learning method and a technique for grouping similar data. In terms of classifying data, clustering can be similar to a classification algorithm. The difference between the two is that the classification algorithm is supervised learning, while clustering is an unsupervised learning method. For example, a large amount of data can be clustered based on a standard in the two algorithms. The purpose of clustering is to divide given data into different groups, and the observations within each group may be very similar. Clustering can be used as a data mining technique. Since clustering is an unsupervised learning method, no prior knowledge about data clustering is required. Clustering can also be used to process large amounts of data. Examples of clustering algorithms include K-Means Clustering, Mean Shift, Gaussian Mixture Model, Density-based spatial clustering of applications with noise (DBSCAN), and Agglomerative Clustering.

[0056] According to an embodiment, the RRT generation / update device 910 may include a cluster candidate selector 918. When the RRT generation / update device 910 calculates the value of the read retry table (RRT) that can maximize the coverage of the cluster or reduce the number of clusters through clustering, the updated read retry table (RRT) can be optimized in terms of read latency or read delay. However, since clustering is an unsupervised learning method, it may be difficult to check or determine whether the read retry table (RRT) updated by clustering has been optimized.

[0057] The cluster candidate selector 918 can select a cluster candidate or a cluster candidate group based on the pass rate obtained from the data collected from the memory device 950. For example, the cluster candidate selector 918 can calculate the number of error bits (e.g., fail bit count, FBC) of each word line in the cluster based on the data obtained from the memory device 950. If the fail bit count (FBC) is within the error correction capability range of the error correction circuit or error correction code (ECC) module, the cluster candidate selector 918 can increase the pass rate of the corresponding cluster. On the contrary, if the fail bit count (FBC) exceeds the error correction capability of the error correction circuit or ECC module, the cluster candidate selector 918 can reduce the pass rate of the corresponding cluster. The cluster candidate selector 918 can select cluster candidates sequentially from the highest pass rate among the pass rates of each of the multiple clusters. In an embodiment, the pass rate can show how many word lines or how many proportions of word lines have a fail bit count (FBC) within the error correction capability range of the ECC module when the word line belongs to a specific cluster. The RRT generation / update device 910 can perform clustering from a larger cluster based on the information of the cluster candidate. Based on this scheme, the RRT generating / updating device 910 can calculate a read retry table (RRT) that can maximize the coverage of clusters or reduce the number of clusters through clustering.

[0058] According to an embodiment, the RRT generation / update device 910 including the cluster candidate selector 918 may perform an operation of generating different classifiers and combining predictions to obtain a more accurate prediction (e.g., ensemble learning). The operation of the RRT generation / update device 910 including the cluster candidate selector 918 will be described later. Figures 5 to 7 Give a description.

[0059] Due to rapid process expansion and multi-level cell (MLC) technology, the storage capacity of NAND flash memory, one of the non-volatile memory devices, can be increased by tens to thousands of times. The continuous increase in storage capacity can make non-volatile memory devices economically viable in various applications from consumer electronics to data storage systems. However, as the density of non-volatile memory devices increases, non-volatile memory cells may be more susceptible to noise occurring in various devices and circuit levels, so the reliability and durability of non-volatile memory cells may gradually deteriorate. For example, the program and erase (P / E) cycle durability of multi-level cells in NAND flash memory has decreased, for example, the P / E cycle durability for 5×nm flash memory has decreased to 10k, and the P / E cycle durability for 2×nm flash memory has decreased to 3k. As the number of data bits stored in each memory cell increases and the size of the memory cell decreases, the reliability and durability of non-volatile memory devices may continue to decrease. Due to this trend, when designing a nonvolatile memory device or a memory system including a nonvolatile memory device, it may be tempting to apply a stronger error correction code (ECC) to a controller or a module in order to withstand the increasing error rate of the nonvolatile memory device.

[0060] In NAND flash memory, the logic value stored in a memory cell can be determined by the threshold voltage window or threshold voltage distribution to which the threshold voltage of the memory cell belongs. As the size of the memory cell decreases and the number of data bits stored in each memory cell increases, the width of the threshold voltage window representing each logic value will become smaller, thereby increasing the error rate when determining the logic value stored in the memory cell. This is because when the amount of charge stored in the memory cell decreases as the feature size (e.g., the minimum distance between the source and drain of a MOS transistor or half the distance between memory cells) decreases, process variations become more common, resulting in large differences in the threshold voltages of different memory cells storing the same logic value. Therefore, it becomes increasingly difficult to determine which logic value the threshold voltage of a memory cell corresponds to.

[0061] According to an embodiment, the BCH code is one of the most commonly used ECC mechanisms in a memory system. The BCH code can perform hard decisions on the logic values ​​corresponding to the threshold voltage. In other words, the BCH code is a hard decoding error code. If the amount of charge stored in each memory cell is reduced to a smaller feature size, the hard decision may limit the scalability of the ECC code (e.g., the BCH code), resulting in a narrower threshold voltage window representing the logic value stored in the memory cell. The error correction capability of the BCH code may be reduced to withstand the raw bit error rate of the memory cell, which increases exponentially with the increase in the number of program / erase (P / E) cycles.

[0062] To address this issue, soft decision decoding can be used as a more powerful ECC mechanism, which represents the logic values ​​stored in the memory cells as a probability distribution. For example, low-density parity check (LDPC) codes can be used in memory systems and can achieve error correction capabilities close to the Shannon limit. If there is significant noise (variation) in the signal (threshold voltage) used to represent the logic values ​​present in other memory cells, LDPC and other similar soft decoding can provide stronger correction. In order to develop such a powerful ECC, the threshold voltage distribution on multiple non-volatile memory cells 924 in the memory device 950 can be characterized and modeled by the memory test device 900. In addition, such characterization or modeling can achieve other potential improvements in the reliability and life of the memory device 950. This will be referred to later. Figures 9 to 12 Describes the ECC module that implements the ECC mechanism and the ECC performance (eg, error correction capability).

[0063] The memory test apparatus 900 can use the read retry function of the memory device 950 to accurately identify the threshold voltage associated with the logic value stored in the memory cell. The memory test apparatus 900 can determine the threshold voltage distribution model by using statistical techniques that use a large number of threshold voltage measurements and machine learning mechanisms to analyze the observed threshold voltages. In addition, the memory test apparatus 900 can estimate the change in the threshold voltage distribution according to the increase of the program / erase (P / E) cycle of the memory device 950.

[0064] Figure 2 Describe the read retry operation according to an embodiment of the present disclosure. Specifically, Figure 2 A program state of a nonvolatile memory cell storing 2-bit data, a level of a read voltage for reading the program data, and a change in the level of the read voltage according to a read retry operation are described.

[0065] Reference Figure 2, the nonvolatile memory cell may have an erase state P0 and three programming states P1 to P3. For example, the memory device 950 may apply a second reference voltage REF2 to the nonvolatile memory cell to distinguish the erase state P0 and the first programming state P1 from the second programming state P2 and the third programming state P3. In the memory device 950, the erase state P0 may be distinguished from the first programming state P1 using the first reference voltage REF1. The memory device 950 may distinguish the second programming state P2 and the third programming state P3 from each other using the third reference voltage REF3. For example, the erase state P0 may represent 2-bit data "11", the first programming state P1 may represent 2-bit data "10", the second programming state P2 may represent 2-bit data "00", and the third programming state P3 may represent 2-bit data "01". According to an embodiment, the number of data bits that can be stored in the nonvolatile memory cell may vary. In addition, the number of reference voltages (or reference voltage levels) used to distinguish multi-bit data may also vary.

[0066] In the process of programming a nonvolatile memory cell from an erased state P0 to one of a first programming state P1 to a third programming state P3, a plurality of programming pulses may be applied. When a programming pulse is applied to a particular memory cell, the threshold voltage of the corresponding memory cell may be gradually increased. For example, before storing or programming any data, the nonvolatile memory cell may have a threshold voltage corresponding to the erased state P0. When a programming pulse is applied, the threshold voltage distribution of the nonvolatile memory cell may change from the erased state P0 to the first programming state P1, from the first programming state P1 to the second programming state P2, and from the second programming state P2 to the third programming state P3.

[0067] After data is stored in the nonvolatile memory cell, the threshold voltage of the nonvolatile memory cell may belong to one of the threshold voltage distributions corresponding to the erase state P0 and the first to third programming states P1 to P3. For example, when the memory device applies the third reference voltage REF3 to the nonvolatile memory cell belonging to the threshold voltage distribution corresponding to the third programming state P3, data corresponding to the threshold voltage of the corresponding nonvolatile memory cell, i.e., data corresponding to the third programming state P3, may be read.

[0068] Reference Figure 2, memory cells programmed with the same n-bit value may belong to the same threshold voltage window (distribution) of threshold voltage even with different threshold voltages. The non-overlapping space between two threshold voltage distributions or windows may be understood as a distribution margin. For an n-bit MLC NAND flash memory, 2^n-1 preset read reference voltages (i.e., 2^n-1 read voltage levels to be applied to the memory cell through the word line) are used to distinguish 2^n memory cell states. These read reference voltages (e.g., REF1, REF2, REF3) may be located in the non-overlapping space (e.g., distribution margin) between two threshold voltage distributions. Each threshold voltage distribution may be determined when upper and lower read reference voltages are applied. During a read operation, the threshold voltage of a memory cell may be repeatedly compared to a preset read reference voltage until the upper and lower read reference voltages are identified to determine the stored n-bit value. Optionally, according to an embodiment, when a specific bit among the n-bit values ​​is read from a memory cell during a read operation, the reference voltage of the memory cell may be compared to a single preset read reference voltage. When the threshold voltage of a memory cell belongs to a value corresponding to Figure 2 When the threshold voltage distribution or window corresponding to the erase state P0 and the first programming state P1 to the third programming state P3 described in , the 2-bit data stored in each memory cell can be determined by three read reference voltages (e.g., REF1, REF2, REF3). However, if the threshold voltage distribution is distorted (e.g., due to P / E cycles, charge loss over time, or programming interference or disturbance caused by programming of adjacent memory cells), the threshold voltage distribution may be offset, or the tail of the threshold voltage distribution (e.g., at least one end of the threshold voltage distribution) may intersect with the adjacent read reference voltage level (e.g., reducing or removing the non-overlapping space between the threshold voltage distributions). In this case, if the read reference voltage level does not change, the memory cell storing a specific logic value may be mistakenly read as a memory cell storing another logic value. In order to avoid or prevent such errors, the change of the threshold voltage distribution can be checked or tracked by dynamically adjusting the read reference voltage level by means of a read retry operation. According to an embodiment, information of the read retry operation, such as RRT, can be stored in the form of a lookup table.

[0069] Figure 3 A read retry table (RRT) according to an embodiment of the present disclosure is described. According to an embodiment, the RRT may include one or more tables, each table being designed for each operation state or condition of the memory device 950.

[0070] Reference Figure 3, RRT may include changes in a plurality of read reference voltages (e.g., R1, R6, R8, R11) corresponding to a plurality of data that can be stored in the nonvolatile memory cell according to the number of read retry operations (RRT1 to RRT50) on the nonvolatile memory cell. According to an embodiment, the changes in the plurality of read reference voltages (e.g., R1, R6, R8, R11) may be set to a ratio of increase or decrease (e.g., %) or an amount of increase or decrease (e.g., a specific value).

[0071] Reference Figure 3 , depending on the number of read retry operations (RRT1 to RRT50), the change in the read reference voltage according to RRT may be disproportionate or inversely proportional (e.g., Figure 2 When repeatedly reading data stored in the same memory cell, the repeated read operation may cause noise or disturbance, such as interference, in the memory cell or adjacent memory cells. The variation of the multiple read reference voltages R1, R6, R8, and R11 in RRT can be set to reduce such adverse effects.

[0072] Figure 4 A first method of generating a read retry table according to an embodiment of the present disclosure is shown. Figure 5 Parameters used in a machine learning algorithm for generating a read retry table according to an embodiment of the present disclosure are shown.

[0073] Reference Figure 4 , a first method of generating an RRT may include collecting data from a selected word line (operation 340), selecting cluster candidates based on a pass rate obtained from the collected data (operation 342), clustering the selected word line based on the cluster candidates (operation 344), clustering outliers (operation 346), and generating an RRT corresponding to the clustered data (operation 348). Here, operation 344 of clustering the selected word line based on the cluster candidates and the collected data is described as a first clustering, and operation 346 of clustering outliers is described as a second clustering.

[0074] Reference Figure 5 , describes an example of storing 3-bit data of the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB) in each memory cell. The method of storing 3-bit data in a memory cell may be variously modified, and the embodiments of the present disclosure may not be limited to the method of programming 3-bit data. Each memory cell may have one of eight states RV0 to RV7 corresponding to the 3-bit data. Here, the eight states RV0 to RV7 may indicate a threshold voltage window or a threshold voltage distribution corresponding to each 3-bit data.

[0075] Reference Figures 1 to 5, the logic value stored in the non-volatile memory cell 924 in the memory device 950 can be determined based on the threshold voltage window or threshold voltage distribution to which the threshold voltage of the memory cell belongs. However, it may be inefficient to program all data in all memory cells in the memory device 950 and then read the corresponding data to obtain the threshold voltage window or threshold voltage distribution to which the threshold voltage of the memory cell belongs. The RRT generation / update device 910 can select some word lines instead of all word lines, and apply a read reference voltage that does not reflect the RRT of some selected word lines (i.e., a default level) and another read reference voltage that has a constant reference change amount (e.g., an offset, 20mV from -600mV to +600mV) relative to the read reference voltage (i.e., the default level). The RRT generation / update device 910 can estimate a fail bit count (FBC) based on each different read reference voltage (see Figure 2 and Figure 5 ).

[0076] Reference Figure 4 and Figure 5 , the RRT generation / update device 910 for generating or updating the RRT can use an adaptive machine learning algorithm. For the test of running the adaptive machine learning algorithm, the RRT generation / update device 910 can initialize variables and parameters. For example, the first parameter is related to the number of iterations of the adaptive machine learning algorithm. The second parameter is related to a set of initial K values ​​to be tested by the K-means clustering test, where K is a positive integer. When the first parameter is 5, the second parameter can be set to a set of {1,3,5,7,9}. The third parameter can be a value obtained by subtracting the number of error bits (fail bit count, FBC) from the error correction capability of the ECC module. For example, when each memory cell stores 3 bits of data, the third parameter Para3_LSB of the least significant bit (LSB) page can be determined according to the following equation.

[0077] Para3_LSB = (ECC hard decision error correction capability) - (max_(min_FBC_RV3 + min_FBC_RV7))

[0078] Here, the third parameter Para3_LSB of the least significant bit (LSB) page can be determined based on the number of error bits (FBC) of the two states RV3 and RV7 where the CSB and MSB pages are the same and only the LSB pages are different. "min" can indicate when the default read reference voltage (default level) of RRT is not reflected and the constant standard change (offset, see Figure 2) is applied to a word line associated with an LSB page. “max” may indicate a value obtained from the sum of “min” values ​​regarding possible error bit numbers (FBC) corresponding to a plurality of data obtained from a word line.

[0079] The RRT generation / update device 910 may select or sample a plurality of word lines included in the memory device 950 and read data through the selected or sampled word lines (operation 342). For example, preset data may be stored in a plurality of memory cells 924 connected to the selected or sampled word lines, and data output from the plurality of memory cells 924 may be collected by applying a read reference voltage to the selected word lines.

[0080] According to an embodiment, the RRT generating / updating device 910 may generate additional information (side_Info, see Figure 6 ), and executes a clustering algorithm in response to the additional information side_Info. Herein, the additional information side_Info may include information about cluster candidates selected according to the pass rate. In conventional clustering, which is an unsupervised learning method, the number of clusters to be clustered is not fixed, so the resources required to generate or update the read retry table (RRT) may increase. However, the cluster candidate selector 918 may generate and transmit additional information about cluster candidates according to the pass rate, thereby reducing the resources required to determine the optimal number of clusters. This will be referred to later. Figures 6 to 8 The configuration and operation of the cluster candidate selector 918 is described, which selects cluster candidates based on the pass rates obtained from the collected data.

[0081] In the first clustering (operation 344) performed by the RRT generation / update device 910, the word lines may be clustered based on the read reference voltage applied to the selected or sampled word lines. In this case, the range of the cluster may correspond to the error correction capability of the ECC module interworking with the memory device 950. If multiple clusters are established on multiple word lines until the centroids of the multiple clusters no longer change, the RRT generation / update device 910 may find or identify word lines that are considered to be outliers that do not belong to any of the multiple clusters. If there are no outliers, the second clustering (operation 346) may not be performed.

[0082] In general machine learning algorithms, outliers may not be considered. However, the RRT generation / update device 910 can establish an additional cluster for outliers through the second clustering (operation 346). In the second clustering (operation 346), outliers can be added to the additional cluster while changing the read reference voltage level. Outliers will be added to the additional cluster until the centroid of the additional cluster no longer changes. The second clustering (operation 346) will continue until no outliers appear in the second cluster (i.e., all outliers of the first cluster are added to the additional cluster). Therefore, the RRT generation / update device 910 can check the degree of change of the read reference voltage level (e.g., the amount of change in the read reference voltage level). After performing the second clustering, the optimal value (e.g., RR offset) associated with the change in the read reference voltage level can be found or calculated. Based on the optimal value, the RTT (operation 348) can be generated or updated.

[0083] According to an embodiment, in order to perform the first clustering and the second clustering, the RRT generation / update device 910 may use K-means clustering or K-means++clustering. Here, K-means clustering, which is referred to as an unsupervised learning algorithm, is a mechanism for clustering data. K-means clustering may divide data into K clusters, each of which has a centroid. For example, the RRT generation / update device 910 may establish some of the word lines in a plurality of selected or sampled word lines as one of the K centroids, and then assign the other word lines to the adjacent centroids in the K centroids. This operation may be repeated and continued until the centroids of the clusters and the assigned word lines remain unchanged. K-means clustering may be operated based on the Voronoi distance. Conventional K-means clustering may use a method for randomly selecting K centroids from a plurality of selected or sampled word lines. However, K-means++clustering may use different methods to select K centroids that are far from each other to compensate for randomness. However, in an embodiment of the present disclosure, the cluster candidate selector 918 may generate additional information about at least one cluster candidate according to the pass rate, so that the RRT generating / updating device 910 may easily determine the number of clusters or from which cluster to start performing the first clustering and the second clustering.

[0084] The Voronoi calculation can be used in the assignment operation of assigning each word line to the nearest centroid during K-means clustering. The Voronoi diagram is a plane divided into multiple regions based on the distance from a specific set of points (e.g., the centroid in this case) to the nearest point. The Voronoi set can represent the boundaries between clusters. Each word line can be assigned to the cluster with the nearest centroid in Euclidean distance. In K-means clustering, this operation is repeated until convergence. Finally, multiple word lines can appear as K clusters.

[0085] In traditional K-means clustering, an outlier clustering algorithm can be used to identify outliers and prevent outliers from affecting the clustering results. Even if the cluster includes outliers, an outlier clustering algorithm, such as the Possibilistic-Fuzzy-C-Means (PFCM) algorithm, can also be used to eliminate changes in cluster characteristics. In order to identify outliers, an outlier detection method or a method that utilizes data domain knowledge can be used. After identifying the outliers, the outliers can be removed or processed so that the outliers do not affect the clustering results. However, if certain word lines in the memory device 950 are determined to be outliers and the corresponding word lines are ignored, the security and reliability of the data stored in the memory cells connected to the corresponding word lines cannot be guaranteed. Therefore, in the first method of generating RRT according to an embodiment of the present disclosure, a second clustering 346 for clustering outliers can be performed to ensure the security and reliability of the data.

[0086] During the second clustering (operation 346), regardless of the result of the first clustering (operation 344), the RRT generation / update device 910 can extract an abnormal value by comparing the error correction capability of the ECC module with the value (e.g., minimum FBC) of the number of error bits (fail bit count, FBC) obtained when the read reference voltage determined based on the RRT is applied to the word line. When the read reference voltage determined based on the RRT is applied to a specific word line, the number of error bits (FBC) may exceed the error correction capability of the ECC module. This means that even if the read reference voltage is changed according to the current RRT and the changed read reference voltage is applied to the corresponding word line, the error occurring in the corresponding word line may exceed the error correction capability of the ECC module. In this case, the corresponding word line can be extracted as an abnormal value. For the security and reliability of the data, it is necessary to update the current RRT based on the value obtained by performing the second clustering on the abnormal value.

[0087] According to an embodiment, during the second cluster (operation 346), the RRT generation / update device 910 may extract a word line including an error exceeding the third parameter in the first cluster (operation 344) as an abnormal value. When the read reference voltage (default level) that does not reflect the RRT and reflects the constant standard variation (offset, see Figure 2 ) is applied to the selected or sampled word line, a third parameter may be obtained. Errors exceeding the third parameter in the first cluster (operation 344) may indicate that the number of error bits (fail bit count, FBC) when reflecting the current RRT is greater than the number of error bits when not reflecting the current RRT. In this case, the current RRT needs to be updated.

[0088] As described above, when outliers of the second cluster 346 are extracted, the RRT generation / update device 910 adds the extracted word lines to additional clusters until there are no more outliers. The second clustering may be performed and repeated until convergence.

[0089] After completing the first clustering (operation 344) and the second clustering (operation 346), the RRT generation / update device 910 can generate or update the RRT based on the clustered data (operation 348). The RRT generation / update device 910 can compare the value of the newly generated or updated RRT with the value of the current RRT or the constant standard change (offset) and delete the overlapping values ​​therebetween. When the amount of the value of the newly generated or updated RRT is less than the amount of the value of the previous RRT or the reference offset, the newly generated or updated RRT can be determined as the new optimal RRT. On the contrary, if the amount of the value of the newly calculated RRT is greater than the amount of the value of the previous RRT or the reference offset, the newly generated or updated RRT may be difficult to use as the new optimal RRT.

[0090] Figure 6 A first read retry table generator according to an embodiment of the present disclosure is shown.

[0091] Reference Figure 6 , the first read retry table (RRT) generation module 914A may include a cluster candidate selector 918, a first read retry table generator 917, a second read retry table generator 915, and a first read retry table comparator 919A.

[0092] Reference Figure 1 and Figure 5 , the first RRT generation module 914A may receive the number of error bits (e.g., fail bit count, FBC) of eight states RV0 to RV7 corresponding to 3-bit data stored in each memory cell connected to a sampling word line included in the memory device 950. A data processing apparatus (or device), such as Figure 1 The data verification module 912 described in the above may process information about data obtained from the memory device 950, error information of the data, and an operating state of the memory device 950. For example, when performing a test to check the operating performance of a memory die, a program / erase cycle of a memory cell included in the memory device 950 may be changed. In addition, in the memory device 950, a data retention time may change, or stress or interference due to a read or program operation may be caused. The data verification module 912 may collect or classify data or information according to an operating environment of the memory die or the memory device 950.

[0093] According to an embodiment, the memory device 950 may include a plurality of memory dies (see Fig. 9). The data processing device may analyze the data collected from the plurality of memory dies and calculate more comprehensive and overall operating characteristics of the plurality of memory dies based on the data collected from the plurality of memory dies. The first RRT generation module 914A may receive processed information (e.g., optimal offset) from the data processing device. Herein, the optimal offset may include a preset interval or potential corresponding to each programming state (e.g., RV0 to RV7) (see Figure 2 and Figure 5 ) of the RRT (e.g., a set of read voltage levels). The optimal offset may be a value calculated in response to the programming state (e.g., RV0 to RV7) of the memory cells included in the memory device 950. However, the optimal offset may depend on changes in the operating state or operating environment of the memory device 950. The optimal offsets of the read voltage levels corresponding to each programming state (e.g., RV0 to RV7) may be different from each other.

[0094] The cluster candidate selector 918 can calculate the pass rate of the cluster based on the number of error bits (FBC) for each programming state (e.g., RV0 to RV7) corresponding to the data stored in the memory cell. For example, if the number of error bits (FBC) of the LSB data collected by the sampling word line included in a particular memory die can be corrected using the error correction capability of the ECC module, the cluster candidate selector 918 can increase the pass rate of the cluster of LSB data. On the other hand, if the number of error bits (FBC) of the LSB data collected by the corresponding word line exceeds the error correction capability of the ECC module, the cluster candidate selector 918 can reduce the pass rate of the cluster of LSB data. In this way, the cluster candidate selector 918 can calculate the pass rate of the cluster corresponding to each programming state (e.g., RV0 to RV7) corresponding to the data stored in the memory cell.

[0095] Based on the pass rate, the cluster candidate selector 918 may select k' cluster candidates k'RR. The k' cluster candidates k'RR may be selected in order from the highest to the lowest pass rate. Herein, k' may be equal to or greater than Figure 4 and Figure 5 The number of clusters k in the first clustering described in . The number of cluster candidates k' output by the cluster candidate selector 918 is the maximum number of clusters in the first clustering. The first clustering can be performed on k clusters that are equal to or less than k' clusters. Additional information side_Info about the k' cluster candidates k'RR selected by the cluster candidate selector 918 will be input to the first read retry table generator 917 and the second read retry table generator 915.

[0096] The first read retry table generator 917 may execute in sequence Figure 4. The first clustering and the second clustering described in . The first read retry table generator 917 can perform the first clustering in response to information about the k' cluster candidates k'RR input from the cluster candidate selector 918. When the first clustering is performed by a K-means clustering algorithm (e.g., K-means clustering or K-means++clustering), randomness can be reduced by preferentially clustering the k' cluster candidates k'RR. That is, in the process of setting k clusters equal to or less than k', the first read retry table generator 917 can determine which clusters to select and how many clusters to set. Therefore, this operation can be performed more efficiently because the number of word lines included in the cluster candidates with a high pass rate is greater than the range of the randomly selected clusters. Multiple cluster candidates with a higher pass rate may include more sampled word lines than multiple randomly selected clusters. By such an operation on the first clustering, unnecessary operations can be reduced, thereby improving the operational efficiency of the first clustering performed by the first read retry table generator 917.

[0097] In addition, the first read retry table generator 917 may perform second clustering on the abnormal values ​​classified in the first clustering. The first read retry table generator 917 may update a read retry table (RRT) based on information calculated through the first clustering and the second clustering, thereby generating a first read retry table RRT1.

[0098] According to an embodiment, the first RRT generation module 914A may include a second read retry table generator 915. The second read retry table generator 915 may receive additional information side_Info from the cluster candidate selector 918, just like the first read retry table generator 917. The second read retry table generator 915 may generate a second read retry table RRT2 by performing a clustering method different from that of the first read retry table generator 917. For example, the first read retry table generator 917 may perform a first clustering on k clusters of the k' cluster candidates, and perform a second clustering on the outliers in the first cluster. On the other hand, the second read retry table generator 915 may perform different clustering on the k' cluster candidates based on the pass rate output by the cluster candidate selector 918.

[0099] According to an embodiment, the second read retry table generator 915 may select and sort a portion of the previous read retry table based on the pass rate calculated by the cluster candidate selector 918. Alternatively, the second read retry table generator 915 may change or replace some values ​​included in the previous read retry table in response to the pass rate, thereby generating the second read retry table RRT2.

[0100] The first read retry table generator 917 may generate a first read retry table RRT1 based on the pass rate output by the cluster candidate selector 918, and the second read retry table generator 915 may generate a second read retry table RRT2 based on the pass rate output by the cluster candidate selector 918. Here, the first read retry table RRT1 and the second read retry table RRT2 may be different because they are output from different devices that perform different operations or clustering mechanisms. The first read retry table comparator 919A may select, determine, or output one of the first read retry table RRT1 and the second read retry table RRT2 with a wider coverage (see Fig.11 ).

[0101] Figure 7 A cluster candidate selector 918 is shown according to an embodiment of the present disclosure.

[0102] Reference Figure 7 The cluster candidate selector 918 may include a cluster candidate selection module 906 and a pass rate comparison module 908 .

[0103] The cluster candidate selection module 906 may select a cluster candidate based on information input to the first read retry table generation module 914A. For example, the cluster candidate selection module 906 may receive the number of error bits (fail bit count, FBC) of 8 states (e.g., RV0 to RV7) corresponding to 3-bit data stored in each memory cell included in the memory device 950, and / or receive processed information (e.g., optimal offset) from a data processing device. Based on the received data and information, the cluster candidate selection module 906 may include (or add) a sampled word line corresponding to the received data to at least one of the plurality of cluster candidates. The cluster candidate selection module 906 may calculate the pass rate of a particular cluster based on whether the sampled word line is included in the particular cluster.

[0104] The pass rate comparison module 908 can compare the pass rates of the clusters calculated by the cluster candidate selection module 906, and feed the results back to the cluster candidate selection module 906 in the order of pass rates (e.g., from the highest to the lowest). According to an embodiment, based on the feedback information, the cluster candidate selection module 906 can first determine the cluster that will include another word line. Until the data input to the cluster candidate selector 918 and the word line of the data are included in at least one of the multiple cluster candidates, the cluster candidate selection module 906 can select a new cluster in response to whether the word line is included in the multiple cluster candidates, and calculate the pass rates of these clusters. In addition, the pass rate comparison module 908 can repeat the operation of comparing the pass rates of each cluster.

[0105] In clustering, the coverage of each cluster RR can be understood as the error correction capability range of the ECC module at the center of each cluster RR. Before performing clustering, the cluster candidate selector 918 can receive data. The cluster candidate selector 918 can determine whether a word line corresponding to the received data is included in the cluster based on the number of error bits corresponding to the error correction capability of the ECC module. For example, data can be output from 20 memory cells connected to the first word line. Return to reference Figure 5 , when the LSB data is "1" or "0", it can be divided into two programming state groups (i.e., R0 to R3 corresponding to the LSB data "1" and R4 to R7 corresponding to the LSB data "0"). If there is no error bit in the two programming states R3 and R4 of the data output from the 20 memory cells, the first word line connected to the 20 memory cells can be included in at least one cluster corresponding to the LSB data. If there is an error bit in the two programming states R3 and R4 of the data output from the 20 memory cells, and it is determined that the error bit can be detected and corrected by the error correction capability of the ECC module, the first word line corresponding to the LSB data can be included in at least one cluster.

[0106] As described above, for all word lines that output data in response to the data distribution obtained from the memory device 950, the number of word lines that have no errors or detection and correction performed within the error correction capability of the ECC module when applied to each cluster RR can be calculated as a pass rate or word line pass rate (WL Pass Rate). The pass rate can be defined as the number of word lines in each cluster RR whose fail bit count (FBC) relative to the total number of word lines is within the error correction capability of the ECC module. This can be described by the following equation:

[0107]

[0108] Wherein "i" is an integer used to distinguish each cluster RR and may be equal to or less than the maximum number of clusters that can be established based on the received data.

[0109] If the data received through all word lines belonging to a particular cluster has no errors or only errors within the range that can be detected and corrected by the error correction capability of the ECC module, the pass rate of the cluster may be "1" (i.e., 100%). It can be understood that the greater the pass rate of a given cluster, the greater the coverage of the cluster.

[0110] If all word lines of output data are included in a plurality of clusters according to the data distribution obtained from the memory device 950, the pass rate of each cluster can be compared. For example, 100 word lines can be included in all 8 clusters. The pass rate comparison module 908 can compare the pass rates of the 8 clusters and output the cluster candidates k'RR in the order of the pass rates from the highest to the lowest. For example, the first cluster RR0 can have the highest pass rate, the second cluster RR1 can have the second highest pass rate, and the third cluster RR2 can have the third highest pass rate.

[0111] According to an embodiment, when the pass rates of a plurality of clusters are the same, the pass rate comparison module 908 may determine a higher-order cluster candidate because the maximum fail bit count (FBC) of the corresponding cluster is lower.

[0112] The cluster candidate selector 918 may include all word lines in a plurality of cluster candidates and then assign priorities to the plurality of cluster candidates according to pass rates. Figure 6 As shown, the first read retry table generator 917 may perform the first clustering in response to the cluster candidates. This may produce more efficient results than the first read retry table generator 917 performing the first clustering based on randomness, or may consume resources more efficiently even if the cluster results are the same or similar.

[0113] When new data is received according to a change in an operating condition or operating environment of the memory device 950 , the cluster candidate selector 918 may initialize all previous cluster candidates and select or determine a new cluster candidate for the new data.

[0114] Figure 8 A second read retry table generator 914B according to another embodiment of the present disclosure is shown.

[0115] Reference Figure 8 , the second read retry table (RRT) generation module 914B may include a cluster candidate selector 918, a first read retry table generator 917, a second read retry table generator 915 and a second read retry table comparator 919B. For ease of description, the focus will be on Figure 8 The second RRT generation module 914B described in Figure 6 The differences between the first RRT generation module 914A described in .

[0116] Reference Figure 6 and Figure 8, the first read retry table generator 917 can perform a first clustering on k clusters among the k' cluster candidates based on the pass rate output by the cluster candidate selector 918 and perform a second clustering on the outliers of the first cluster, thereby generating a first read retry table RRT1. On the other hand, the second read retry table generator 915 can cluster the k' cluster candidates based on the pass rate output by the cluster candidate selector 918, thereby generating a second read retry table RRT2.

[0117] Reference Figure 8 , the second read retry table comparator 919B may compare the properties of the first read retry table RRT1 (k+a, for example, properties based on k clusters and a clusters) with the properties of the second read retry table RRT2 (for example, properties based on k' clusters). Here, the properties of the first read retry table and the second read retry table may include the number of tables each of which includes the first read retry table and the second read retry table, the pass rates of the first read retry table and the second read retry table, or the maximum number of error bits (maximum FBC) based on the first read retry table and the second read retry table.

[0118] The fewer the number of tables included in the read retry table, the higher the operation efficiency of the memory device or memory system based on the read retry table. Therefore, the second read retry table comparator 919B can select a read retry table with fewer tables from the first read retry table RRT1 and the second read retry table RRT2.

[0119] In another embodiment, the higher the pass rate of the read retry table, the higher the operation efficiency of the memory device or memory system based on the read retry table. Therefore, the second read retry table comparator 919B can select a read retry table with a higher pass rate between the first read retry table RRT1 and the second read retry table RRT2.

[0120] In another embodiment, the smaller the maximum number of error bits (maximum FBC) based on the read retry table is, the higher the operation efficiency of the memory device or memory system based on the read retry table is. Therefore, the second read retry table comparator 919B can select a read retry table with a smaller maximum number of error bits (maximum FBC) between the first read retry table RRT1 and the second read retry table RRT2.

[0121] Fig. 9 A data sampling method according to an embodiment of the present disclosure is shown.

[0122] Reference Figures 1 to 9, in order to generate or update the RRT, data is collected from a memory device 950 including a plurality of non-volatile memory cells 924. It may be important to check the operating characteristics (e.g., threshold voltage window or threshold voltage distribution) based on the data stored in and read from the memory cells. It may be inefficient to check the threshold voltage window or threshold voltage distribution of all memory cells coupled to all word lines in the memory device 950 based on all data that may be stored in all memory cells. However, as the number of selected or sampled word lines increases, a more accurate estimate may be made.

[0123] Reference Fig. 9 , a read reference voltage may be applied to selected or sampled word lines WL0, WL1, ..., WLm included in a plurality of memory dies Die 0, ..., Die k, ..., Die n produced by a single wafer Wafer #01 to estimate a threshold voltage window or threshold voltage distribution of data stored in a memory cell connected to the selected or sampled word lines WL0, WL1, ..., WLm. A plurality of memory dies Die 0, ..., Die k, ..., Die n obtained from the same wafer Wafer #01 may have similar operating characteristics. In addition, it is more likely that a plurality of memory dies Die 0 to Die k or Die 0 to Die n arranged in the same row or column in the same wafer Wafer #01 have similar operating characteristics. Moreover, it is more likely that a plurality of word lines or a plurality of storage blocks having the same address or offset in a plurality of memory dies Die 0 to Die k or Die 0 to Die n have similar operating characteristics.

[0124] According to an embodiment, information about at least one memory die Die0, ..., Die k, ..., or Die n included therein may be recorded in the memory device 950. For example, information related to at least one memory die Die 0, ..., Die k, ..., or Die n may include wafer information, such as Wafer#01. The wafer information may include a serial number of a wafer containing the corresponding memory die or a position (e.g., a row number or a column number) of the corresponding memory die on the wafer. If the memory device 950 includes information about at least one memory die Die 0, ..., Die k, ..., or Die n included therein, it may be easier to generate or update an RRT having an estimated value corresponding to an operating characteristic.

[0125] Figure 1The memory test device 900 described in the specification can perform various tests or inspections to check errors and defects contained in multiple memory dies Die 0, ..., Die k, ..., Die n obtained from wafer Wafer #01. For several tests, the memory test device 900 can perform operations of programming data into multiple memory dies Die 0, ..., Die k, ..., Die n or operations of reading programmed data from multiple memory dies Die0, ..., Die k, ..., Die n. According to an embodiment, the RRT generation / update device 910 can perform other tests using data collected from the sampling word lines when a read reference voltage is applied to the sampling word lines, instead of performing separate or additional operations, such as data programming or reading operations for generating or updating the RRT. In addition, as Figure 5 As shown, when a read reference voltage (default level and constant standard variation level, for example, an offset varying from -600mV to +600mV at 20mV intervals) is applied by sampling the word line, the number of error bits (fail bit count, FBC) can also be calculated.

[0126] Data processing devices, such as Figure 1 The data verification module 912 described in the above can determine or calculate the optimal offset and fail bit count (FBC) for each programming state based on the data received from the memory device 950. The data verification module 912 can check whether there is a word line with the same optimal offset value for each programming state (e.g., R0 to R7) by receiving data from multiple memory dies (Die 0, ..., Die k, ... Die n). In addition, the data verification module 912 can check whether there is a word line with the same optimal offset value for each page (data position) in the multiple memory dies (Die 0, ..., Die k, ... Die n). According to an embodiment, the cluster candidate selector 918 can find a cluster by classifying the word line according to each programming state based on the information processed in the data verification module 912. Alternatively, the cluster candidate selector 918 can find a cluster by classifying the word line corresponding to each page (data position) and each programming state in the multiple memory dies (Die 0, ..., Die k, ... Die n).

[0127] First, if the information sent from the data verification module 912 includes word lines having the same optimal offset value for each programming state (e.g., R0 to R7), the cluster candidate selector 918 can select clusters for word lines for each programming state (e.g., R0 to R7) in multiple ways.

[0128] For example, the cluster candidate selector 918 may select a cluster based on the best offset frequency for each programming state (e.g., R0 to R7). The cluster candidate selector 918 may find multiple best offset values ​​where the word line frequency for each programming state (e.g., R0 to R7) is highest or above a certain threshold. The cluster candidate selector 918 may select cluster candidates from all possible combinations for each page grouping (e.g., a combination of RV3 and RV7 in the case of LSB data).

[0129] According to an embodiment, the cluster candidate selector 918 may select a cluster based on an average or median of two end values ​​of the optimal offset for each programming state (e.g., R0 to R7). Herein, the two end values ​​of the optimal offset may indicate the minimum and maximum frequencies of the word lines. If the cluster candidate selector 918 uses the average or median of the two end values ​​of the optimal offset as a reference, the number of sampled word lines that fall within the error correction capability range of the ECC module centered on the position of the programming state combination of each page (e.g., RV3, RV7) may be maximized. In order to further increase the number of word lines, when the offset value is included in the preset range of the average or median of the two end values ​​of the optimal offset (see Figure 2 and Figure 3 ), the coverage of the cluster can become larger.

[0130] According to an embodiment, the cluster candidate selector 918 may select a cluster according to the number of error bits (e.g., fail bit count, FBC) of each programming state (e.g., R0 to R7). The cluster candidate selector 918 may select an offset value having a minimum maximum number of error bits (maximum FBC) within a range between a minimum and maximum offset value of each programming state (e.g., R0 to R7). Through this operation, a group may be selected for each programming state combination of each page.

[0131] When the information sent by the data verification module 912 includes word lines with the same optimal offset value for each page (data location) in multiple memory dies (Die 0, ..., Die k, ..., Die n), the group candidate selector 918 can use various methods to select a group for each page (data location) and each programming state (e.g., R0 to R7) in the multiple memory dies (Die 0, ..., Die k, ..., Die n). At this time, the information sent by the data verification module 912 may have the same or overlapping word line offsets based on data output from multiple dies or multiple planes. In this case, multiple word lines may overlap and be based on Fig. 9 The two programming states (eg, RV3 and RV7) described in are shown as one in the two-dimensional diagram.

[0132] For example, the cluster candidate selector 918 may select all sampled word lines that can be sorted according to programming states as cluster candidates. When multiple memory dies (Die 0, ..., Die k, ..., Die n) are obtained from a wafer (Wafer#01) according to the same manufacturing environment and manufacturing method, the offset values ​​calculated for each page (data location) and each programming state (e.g., R0 to R7) therein may be the same or fall within substantially the same range. Therefore, even if the cluster candidate selector 918 selects overlapping word lines as a cluster candidate, the number of cluster candidates may not increase significantly. In addition, in this case, the maximum cluster candidate of all sampled word lines may be selected, which increases complexity. However, it can be determined that the generated or updated read retry table (RRT) has better read performance of the memory device 950 including multiple memory dies (Die 0, ..., Die k, ..., Die n). .

[0133] According to an embodiment, to reduce complexity, the cluster candidate selector 918 may select a preset number of clusters for each page (data location) and each programming state (e.g., R0 to R7), the clusters including word lines classified by frequency-based offset combinations. In this case, the clusters may be selected in order of highest to lowest sampled word line density.

[0134] Fig.10 A data clustering method according to an embodiment of the present disclosure is shown. Fig.10 Describes Figure 4 , Figure 6 and Figure 8 A specific example of the first clustering and the second clustering described in .

[0135] Reference Figures 1 to 10 , when 3-bit data is stored in the nonvolatile memory cell 924, eight threshold voltage windows corresponding to the data stored in the plurality of nonvolatile memory cells 924 connected to each word line can be predicted. When a read reference voltage is applied to check two states RV3, RV7, a third parameter Para3_LSB of the least significant bit (LSB) page can be obtained, in which the CSB page data is the same as the MSB page data and the LSB page data is different from the CSB page data and the MSB page data. Each word line can be located in a 2D domain having a read reference voltage of a default level and other levels changed from the default level based on a constant reference change (offset) to check the two states RV3, RV7. A first clustering (operation 344) can be performed on the selected or sampled word line located in the 2D domain. A first cluster RR0 can be established by the first clustering (operation 344).

[0136] Reference Figures 4 to 10, based on the first cluster RR0, the second word line WL1 is outside the error correction capability of the ECC module. The second word line WL1 that exceeds the error correction capability of the ECC module can be extracted as an outlier. By performing a second clustering (operation 346) on the second word line WL1 extracted as an outlier of the first cluster (operation 344), a second cluster RR1 can be established.

[0137] When the plurality of clusters RR0 , RR1 are established through the first clustering (operation 344 ) and the second clustering (operation 346 ), the ratio of the sampled word lines belonging to the plurality of clusters RR0 , RR1 may be calculated according to the following equation.

[0138]

[0139] Here, the ratio of sampled word lines in cluster i is i It can be calculated by dividing the number of sampled word lines (#WL samples) belonging to the ith cluster (cluster i) by the total number of sampled word lines (#total WL samples).

[0140] Through the first clustering (operation 344) and the second clustering (operation 346), the plurality of clusters RR0, RR1 may be arranged in descending order based on the ratio of the sampled word lines. For example, the first cluster RR0 may have a higher ratio of sampled word lines than the second cluster RR1. The higher the ratio of the sampled word lines, the higher the weight of determining the value in the RRT.

[0141] Fig.11 1 shows the coverage of the read retry table according to an embodiment of the present disclosure. Specifically, Fig.11 Show according to Figures 4 to 10 Here, the coverage of two RRTs (one is achieved by conventional methods (i.e. Fig.11 RRT coverage in ), and another one is implemented by a method according to an embodiment of the present disclosure (i.e. Fig.11 The improved RRT coverage)) can correspond to the same range of error correction capabilities of the ECC module for data output in the memory system. To estimate the coverage, data can be collected from the nonvolatile memory cell 924 when a read reference voltage that changes corresponding to two RRTs is applied to the nonvolatile memory cell.

[0142] The operating characteristics of the memory device 950 including the plurality of nonvolatile memory cells 924 are not fixed and may change, and the results of the first clustering (operation 344) and the second clustering (operation 346) for generating or updating the RRT may also be different each time. By repeating the clustering operation for generating or updating the RRT, the value of the optimal RRT can be calculated through such repetition, so that the coverage of the RRT can be improved.

[0143] Fig.12 A data processing system according to an embodiment of the present disclosure is shown.

[0144] Reference Fig.12 , the data processing system 100 may include a host 102 that interfaces or couples with a memory system, such as a memory system 110. For example, the host 102 and the memory system 110 may be coupled to each other via a data bus, a host cable, etc. to perform data communication.

[0145] According to an embodiment, the data processing system 100 may include Figure 1 The memory testing device 900 described in the specification and implementation of the present invention can be connected to the memory system 110 or the host 102 through a network.

[0146] According to an embodiment, Figure 1 The RRT generation / update device 910 described in the above may be included in the host 102. The RRT generation / update device 910 that executes the machine learning algorithm may require a processing device (e.g., a GPU) with a fast calculation speed and a memory capable of storing data generated during the calculation process. The RRT generation / update device 910 may utilize components included in the host 102.

[0147] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 may be physically separated components or elements. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a passage.

[0148] The memory device 150 may include a plurality of memory chips (e.g., flash memory chips) 252 connected to the controller 130 through a plurality of channels CH0, CH1, ..., CHn and paths W0, ..., W_k. The memory chip 252 may include a plurality of memory planes or a plurality of memory dies. According to an embodiment, the memory plane may be a logical or physical partition, including at least one storage block, a driving circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that may temporarily store data input to or output from a non-volatile memory cell. Each memory plane or each memory die may support an interleaved mode in which multiple data input and output (input / output) operations are performed in parallel or simultaneously. According to an embodiment, the storage blocks included in each memory plane or each memory die included in the memory device 150 may be grouped into a plurality of input / output data entries as a super storage block. Fig.12 The internal configuration of the memory device 150 shown may be changed based on the operating performance of the memory system 110. Fig.12 According to an embodiment, the memory device 150 may include Figure 1 2. In addition, according to an embodiment, the plurality of memory chips 252 may correspond to the memory device 950 of FIG. Fig. 9 As shown, multiple memory dies Die 0, ..., Die k, ..., Die n are obtained from the same wafer Wafer#01.

[0149] According to an embodiment, the memory device 150 and the controller 130 may be functionally separate components or elements. In addition, according to an embodiment, the memory device 150 and the controller 130 may be implemented with a single chip or multiple chips.

[0150] The controller 130 may perform data input / output operations such as a read operation, a program operation, an erase operation, etc. in response to a request or a command input from an external device such as the host 102. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of nonvolatile memory cells included in the memory device 150 are transferred to the controller 130. In addition, the controller 130 may independently perform operations regardless of a request or a command input from the host 102. With respect to the operating state of the memory device 150, the controller 130 may perform operations such as garbage collection (GC), wear leveling (WL), and bad block management (BBM) to check whether a storage block is a bad block and process the bad block.

[0151] The memory device 150 may include a plurality of memory blocks, each of which includes a plurality of memory cells. Figure 1The memory device 950 shown includes a plurality of nonvolatile memory cells 924. A memory block may be understood as a group of nonvolatile memory cells in which data is removed together by a single erase operation. Although not shown, a memory block may include a page, which is a group of nonvolatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include a plurality of pages. The memory device 150 may include a voltage supply circuit capable of providing at least one voltage to the memory block. The voltage supply circuit may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the nonvolatile memory cells included in the memory block. The voltage supply circuit may include Figure 1 In addition, the voltage supply circuit can be based on the read voltage generator 926 described in the above. Figure 1 The read retry table 928 described in applies the read voltage Vrd to the plurality of nonvolatile memory cells 924. Herein, the read retry table 928 may include a plurality of tables for each of a plurality of situations based on a read retry mechanism.

[0152] The host 102 interacting with the memory system 110, or the data processing system 100 including the memory system 110 and the host 102, may be a mobile electronic device (such as a vehicle), a portable electronic device (such as a mobile phone, an MP3 player, a laptop, etc.), and a non-portable electronic device (such as a desktop computer, a game console, a TV, a projector, etc.). The host 102 may provide interaction between the host 102 and a user using the data processing system 100 or the memory system 110 through at least one operating system (OS). The host 102 sends a plurality of commands corresponding to user requests to the memory system 110, and the memory system 110 performs data input / output operations corresponding to the plurality of commands (e.g., operations corresponding to the user requests).

[0153] Reference Fig.12 , the controller 130 in the memory system operates with the host 102 and the memory device 150. As shown in the figure, the controller 130 may have a layered structure including a host interface layer (HIL) 220, a flash translation layer (FTL) 240, and a memory interface (flash interface layer, FIL) 260.

[0154] Fig.12 The host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the flash interface layer (FIL) 260 described in the embodiment are shown as one embodiment. The host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the flash interface layer (FIL) 260 can be implemented in various forms according to the operating performance of the memory system 110.

[0155] The host 102 and the memory system 110 may use a predetermined data communication rule or set of procedures or a preset interface to send and receive data between the host 102 and the memory system 110. Examples of rules or sets of procedures of data communication standards or interfaces for sending and receiving data supported by the host 102 and the memory system 110 include: Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Express (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industrial Processor Interface (MIPI), etc. According to an embodiment, the host 102 and the memory system 110 may be connected to each other via a Universal Serial Bus (USB). Universal Serial Bus (USB) is a highly scalable, hot-swappable, plug-and-play serial interface that ensures cost-effective standard connections with peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, video conferencing cameras, etc.

[0156] The memory system 110 may support high-speed non-volatile memory (NVMe). High-speed non-volatile memory (NVMe) is an interface based at least on a high-speed peripheral component interconnect (PCIe) designed to enhance the performance and design flexibility of a host 102, a server, a computing device, etc. equipped with the memory system 110. PCIe may use a slot or a dedicated cable to connect a computing device (e.g., a host 102) and a peripheral device (e.g., a memory system 110). For example, PCIe may use a plurality of pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication at a speed of several hundred MB per second. According to an embodiment, the PCIe scheme may achieve a bandwidth of tens to hundreds of gigabits per second.

[0157] The buffer manager 280 in the controller 130 may control the input / output of data or operation information together with the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the flash interface layer (FIL) 260. To this end, the buffer manager 280 may be configured to: Fig.12144 described in the above, and controls the data input / output of these buffers, caches or queues, or the data transmission between these buffers, caches or queues in response to the request or command generated by the host interface layer (HIL) 220, the flash translation layer (FTL) 240 and the flash interface layer (FIL) 260. For example, in response to the request of the host 102, the controller 130 may temporarily store the read data provided from the memory device 150 before providing the read data to the host 102. Moreover, the controller 130 may temporarily store the write data provided from the host 102 and then store the write data in the memory device 150. When controlling the operations such as the read operation, the program operation and the erase operation performed in the memory device 150, the read data or the write data sent or generated between the controller 130 and the memory device 150 in the memory system 110 may be stored and managed by the buffer, queue, etc. established in the memory by the buffer manager 280. In addition to reading data or writing data, the buffer manager 280 may also store signals or information (e.g., mapping data, read commands, programming commands, etc. for performing operations such as programming and reading data between the host 102 and the memory device 150) in buffers, caches, queues, etc. established in the memory. The buffer manager 280 may set up or manage command queues, programming memories, data memories, write buffers / cache, read buffers / cache, data buffers / cache, mapping buffers / cache, etc.

[0158] The host interface layer (HIL) 220 may process commands, data, etc. sent from the host 102. By way of example and not limitation, the host interface layer 220 may include a command queue manager 222 and an event queue manager 224. The command queue manager 222 may store commands, data, etc. received from the host 102 in a command queue in order, and output them to the event queue manager 224, for example, in the order in which they are stored in the command queue manager 222. The event queue manager 224 may send events for processing commands, data, etc. received from the command queue in order. According to an embodiment, the event queue manager 224 may classify, manage, or adjust commands, data, etc. received from the command queue. In addition, according to an embodiment, the host interface layer 220 may include an encryption manager 226, which is configured to encrypt a response or output data to be sent to the host 102, or to decrypt an encrypted portion of a command or data sent from the host 102.

[0159] A plurality of commands or data having the same characteristics may be sent from the host 102, or commands and data having different characteristics may be sent to the memory system 110 after being mixed or shuffled by the host 102. For example, a plurality of commands for reading data (i.e., read commands) may be delivered, or commands for reading data (i.e., read commands) and commands for programming / writing data (i.e., write commands) may be sent alternately to the memory system 110. The command queue manager 222 of the host interface layer 220 may sequentially store the commands, data, etc. sent from the host 102 in the command queue. Thereafter, the host interface layer 220 may estimate or predict which internal operation the controller 130 will perform based on the characteristics of the commands, data, etc. that have been sent from the host 102. The host interface layer 220 may determine the processing order and priority of commands, data, etc. based on their characteristics. According to the characteristics of the command, data, etc. sent from the host 102, the event queue manager 224 in the host interface layer 220 is configured to receive from the buffer manager 280 an event that should be processed or handled inside the memory system 110 or the controller 130 according to the command, data, etc. input from the host 102. Then, the event queue manager 224 can transmit the event including the command, data, etc. to the flash translation layer (FTL) 240.

[0160] According to an embodiment, the flash translation layer (FTL) 240 may include a host request manager (HRM) 242, a mapping manager (MM) 244, a state manager 246, and a block manager 248. In addition, according to an embodiment, the flash translation layer (FTL) 240 may implement a multithreading scheme to perform data input / output (I / O) operations. The multithreaded FTL may be implemented by a multi-core processor using multithreading included in the controller 130. For example, the host request manager (HRM) 242 may manage events sent from an event queue. The mapping manager (MM) 244 may handle or control mapping data. The state manager 246 may perform operations such as garbage collection (GC) or wear leveling (WL) after checking the operating state of the memory device 150. The block manager 248 may execute commands or instructions to blocks in the memory device 150.

[0161] The host request manager (HRM) 242 may handle or process requests using the mapping manager (MM) 244 and the block manager 248 according to the read and program commands and events delivered from the host interface layer 220. The host request manager (HRM) 242 may send a query request to the mapping manager (MM) 244 to determine the physical address corresponding to the logical address input with the event. The host request manager (HRM) 242 may send a read request with the physical address to the memory interface layer 260 to process the read request, i.e., handle the event. In one embodiment, the host request manager (HRM) 242 may send a program request (or a write request) to the block manager 248 to program data to a specific empty page (no data is stored) in the memory device 150, and then a mapping update request corresponding to the program request may be sent to the mapping manager (MM) 244 to update the entry related to the programmed data in the information mapping the logical and physical addresses to each other.

[0162] The block manager 248 may convert the program requests passed from the host request manager (HRM) 242, the mapping manager (MM) 244, and / or the state manager 246 into flash program requests for the memory device 150 to manage the flash blocks in the memory device 150. In order to maximize or enhance the programming or writing performance of the memory system 110, the block manager 248 may collect the program requests and send the flash program requests for multi-plane and single-shot programming operations to the memory interface layer 260. In an embodiment, the block manager 248 sends several flash program requests to the memory interface layer 260 to enhance or maximize the parallel processing of the multi-channel and multi-directional flash controller.

[0163] In an embodiment, the block manager 248 may manage the blocks in the memory device 150 according to the number of valid pages, select and erase blocks without valid pages when a free block is needed, and select blocks including the minimum number of valid pages when it is determined that garbage collection will be performed. The state manager 246 may perform garbage collection to move valid data stored in the selected blocks to the empty blocks and erase data stored in the selected blocks so that the memory device 150 may have sufficient free blocks (i.e., empty blocks without data).

[0164] When the block manager 248 provides information about the block to be erased to the state manager 246, the state manager 246 may check all flash memory pages of the block to be erased to determine whether each page of the block is valid. For example, to determine the validity of each page, the state manager 246 may identify the logical address recorded in the out-of-band (OOB) area of ​​each page. To determine whether each page is valid, the state manager 246 may compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. The state manager 246 sends a program request to the block manager 248 for each valid page. When the programming operation is completed, the mapping table may be updated by the mapping manager 244.

[0165] The mapping manager 244 may manage mapping data, such as a logical-physical mapping table. The mapping manager 244 may process various requests generated by the host request manager (HRM) 242 or the state manager 246, such as queries, updates, etc. The mapping manager 244 may store the entire mapping table in the memory device 150 (e.g., a flash memory / non-volatile memory) and cache mapping entries according to the storage capacity of the memory 144. When a mapping cache miss occurs while processing a query or update request, the mapping manager 244 may send a read request to the memory interface layer 260 to load the relevant mapping table stored in the memory device 150. When the number of dirty cache blocks in the mapping manager 244 exceeds a certain threshold, a programming request may be sent to the block manager 246 to generate a clean cache block, and the dirty mapping table may be stored in the memory device 150.

[0166] When performing garbage collection, the state manager 246 copies the valid page to the free block, and the host request manager (HRM) 242 can program the latest version of the data for the same logical address of the page and issue an update request at the same time. When the state manager 246 requests a mapping update in a state where the copy of the valid page is not completed normally, the mapping manager 244 may not perform a mapping table update. This is because when the state manager 246 requests a mapping update and the valid page copy is completed later, the mapping request is issued together with the old physical information. When or only when the latest mapping table still points to the old physical address, the mapping manager 244 can perform a mapping update operation to ensure accuracy.

[0167] The memory interface layer 260 may exchange data, commands, status information, etc. with the plurality of memory chips 252 in the memory device 150 through a data communication method. According to an embodiment, the memory interface layer 260 may include a status check scheduler 262 and a data path manager 264. The status check scheduler 262 may check and determine the operation status of the plurality of memory chips 252 connected to the controller 130, the operation status of the plurality of channels CH0, CH1, ..., CHn and the plurality of paths W0, ..., W_k, etc. The transmission and reception of data or commands may be scheduled in response to the operation status of the plurality of memory chips 252 and the plurality of channels CH0, CH1, ..., CHn. The data path manager 264 may control the transmission and reception of data, commands, etc. through the plurality of channels CH0, CH1, ..., CHn and the paths W0, ..., W_k based on the information sent by the status check scheduler 262. According to an embodiment, the data path manager 264 may include a plurality of transceivers, each of which corresponds to each of the plurality of channels CH0, CH1, ..., CHn. Furthermore, according to an embodiment, the status check schedule manager 262 and the data path manager 264 included in the memory interface layer 260 may be implemented as the memory control sequence generator 332 or coupled with the memory control sequence generator 332 .

[0168] According to an embodiment, the memory interface layer 260 may further include an error correction code (ECC) circuit 266 configured to perform error checking and correction on data transmitted between the controller 130 and the memory device 150. The ECC circuit 266 may be implemented as a separate module, circuit, or firmware in the controller 130, but may also be implemented in each memory chip 252 included in the memory device 150 according to an embodiment. The ECC circuit 266 may include a program, circuit, module, system, or device for detecting and correcting error bits of data processed by the memory device 150.

[0169] In order to find and correct any errors in the data transmitted from the memory device 150, the ECC circuit 266 may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder may perform error correction encoding on the data to be programmed in the memory device 150 to generate encoded data with parity bits added, and store the encoded data in the memory device 150. When the controller 130 reads the data stored in the memory device 150, the ECC decoder may detect and correct the error bits included in the data read from the memory device 150. For example, after performing error correction decoding on the data read from the memory device 150, the ECC circuit 266 may determine whether the error correction decoding is successful, and output an instruction signal based on the result of the error correction decoding, such as a correction success signal or a correction failure signal. The ECC circuit 266 may use the parity bits generated during the ECC encoding process for the data stored in the memory device 150 to correct the error bits of the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, the ECC circuit 266 may not correct the error bits, but may output a correction failure signal indicating that the correction of the error bits failed.

[0170] According to an embodiment, the ECC circuit 266 may perform error correction operations based on coded modulation such as low-density parity check (LDPC) codes, Bose-Chaudhri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), and block coded modulation (BCM), etc. The ECC circuit 266 may include all circuits, modules, systems, and / or devices that perform error correction operations based on at least one of the above codes.

[0171] For example, the encoder in the ECC circuit 266 can generate a codeword as a unit for applying ECC data. A codeword with a length of n bits can include k bits of user data and (nk) bits of parity. The code rate can be calculated as (k / n). The higher the code rate, the more user data can be stored in a given codeword. Since the length of the codeword is long and the code rate is small, the error correction capability of the ECC circuit 266 can be improved. In addition, the ECC circuit 266 uses information read from channels CH0, CH1, ..., CHn for decoding. According to the number of bits representing the information to be decoded, the decoder in the ECC circuit 266 can be divided into a hard decision decoder and a soft decision decoder. The hard decision decoder uses the memory unit output information represented by 1 bit to perform decoding, and the 1 bit of information used at this time is called hard decision information. The soft decision decoder uses more accurate memory unit output information composed of 2 bits or more bits, which is called soft decision information. The ECC circuit 266 can use hard decision information or soft decision information to correct errors contained in the data.

[0172] According to an embodiment, to improve the error correction capability, the ECC circuit 266 may use a concatenated code consisting of two or more codes. In addition, the ECC circuit 266 may use a product code that divides a codeword into several rows and columns and applies different relatively short ECCs to each row and column.

[0173] According to an embodiment, the manager included in the host interface layer 220, the flash translation layer (FTL) 240, and the memory interface layer 260 may be implemented using a general-purpose processor, an accelerator, a dedicated processor, a coprocessor, a multi-core processor, etc. According to an embodiment, the manager may be implemented with firmware that cooperates with the processor.

[0174] According to an embodiment, the memory device 150 is implemented as a nonvolatile memory such as a flash memory, for example, a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a magnetic random access memory (MRAM), a NAND flash memory, a NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of a phase change random access memory (PCRAM), a resistance random access memory (ReRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0175] Fig.13 A second method for generating a read retry table according to an embodiment of the present invention is shown.

[0176] Figure 1 and Fig.12 The operating state of the non-volatile memory cell included in the memory device 950, 150 described in the embodiment may change, so the security and reliability of the data obtained by the read operation using the previously generated or updated RRT may not be guaranteed. In this case, the controller may determine that the non-volatile memory cell is no longer available. However, if the RRT can be updated based on the current operating state of the non-volatile memory cell, the non-volatile memory cell can continue to be used. That is, when the RRT is updated, the service life of the memory device 950, 150 can be increased.

[0177] Reference Fig.13 , the second method of generating RRT may include checking the conditions for generating or updating RRT (operation 358), collecting data from memory cells connected to the selected word line (operation 360), selecting cluster candidates based on the pass rate (operation 362), clustering the word lines based on the collected data (operation 364), clustering the outliers (operation 366), and generating or updating RRT based on the clustered data (operation 368). Here, operation 364 of clustering the word lines based on the collected data can be understood as the first clustering, and operation 366 of clustering the outliers can be understood as the second clustering. For ease of description, the clustering based on Figure 4 The difference between the first method and the second method described in Fig.13 The second method described in .

[0178] exist Fig.12 In the case of the memory system 110 described in , the loss of the memory device 150 occurs through data input / output operations. It may be necessary to generate or update the RRT stored in the memory system 110 in response to the loss of the memory device 150 because the operating characteristics may change due to the loss of the memory device 150. According to the embodiment, the conditions for generating or updating the RRT may be different. For example, when a preset number of uncorrectable error correction code (UECC) errors occur in the memory device 150, the memory system 110 may determine that the RRT needs to be generated or updated. As another example, when the program / erase cycle (P / E cycle) in the memory device 150 exceeds a predetermined standard, the memory system 110 may determine that the RRT needs to be generated or updated.

[0179] When the memory system 110 determines that the RRT needs to be generated or updated, the memory system 110 may request the host 102 or the memory test device 900 connected through the bus or network to generate or update the RRT stored in the memory system 110. The RRT generation / update device 910 included in the host 102 or the memory test device 900 may transmit information about the sampling word line to the memory system 110. The memory system 110 may transmit data collected from the memory cells connected to the sampling word line to the RRT generation / update device 910.

[0180] The RRT generation / update device 910 may execute Figure 4 and Fig.13 , and generates or updates the RRT based on the values ​​or results obtained from the first clusters 344, 364 and the second clusters 346, 366. The RRT generating / updating device 910 may transmit the values ​​or results to the memory system 110. The memory system 110 may generate or update the RRT based on the values ​​or results transmitted from the RRT generating / updating device 910.

[0181] According to an embodiment, the RRT in the memory system 110 is generated or updated by the RRT generation / update device 910 included in the host 102 or the memory test device 900. This process may be performed when the memory system 110 is in an idle state, thereby avoiding a decrease in I / O throughput.

[0182] As described above, according to an embodiment of the present disclosure, the input / output performance of a memory system can be improved by reducing the consumed resources used for machine learning algorithms to provide broad or targeted coverage of RRT corresponding to the error correction capabilities of an error correction circuit or error correction code (ECC) module.

[0183] Furthermore, a memory device or a memory system according to an embodiment of the present disclosure may reduce uncorrectable error correction code (UECC) errors based on an improved RRT, thereby reducing defects and avoiding shortening of the life of the memory device or the memory system.

[0184] The method, process and / or operation described herein can be performed by a code or instruction to be run by a computer, processor, controller or other signal processing device. The computer, processor, controller or other signal processing device can be a device described herein, or an element other than the element described herein. Because the algorithm constituting the basis of the operation of the method or computer, processor, controller or other signal processing device is described in detail, the code or instruction for implementing the operation of the method embodiment can convert the computer, processor, controller or other signal processing device into a special processor for performing the method herein.

[0185] In addition, another embodiment may include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the above-mentioned code or instructions. The computer-readable medium may be a volatile or non-volatile memory or other storage device, which may be removably or fixedly connected to a computer, processor, controller or other signal processing device to be run to execute the code or instructions for performing the operation of the method embodiment or the device embodiment of the present invention.

[0186] For example, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented in non-transient logic including hardware, software, or both. For example, when implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may be any of a variety of integrated circuits including, but not limited to, application specific integrated circuits, field programmable gate arrays, combinations of logic gates, systems on chip, microprocessors, or other types of processing or control circuits.

[0187] For example, when implemented at least in part with software, controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include a memory or other storage device for storing a code or instruction to be run by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be a device described herein or may be an element other than the elements described herein. Because the algorithm constituting the basis of the operation of the method or computer, processor, microprocessor, controller, or other signal processing device is described in detail, the code or instruction for implementing the operation of the method embodiment may convert the computer, processor, controller, or other signal processing device into a dedicated processor for performing the method described herein.

[0188] Although the present invention has been described and illustrated for specific embodiments, it will be apparent to those skilled in the art from this disclosure that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the following claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A read retry table generator coupled to a plurality of memory dies via a data path, wherein the read retry table generator: collecting data from a plurality of memory cells coupled to a plurality of word lines in the plurality of memory dies; determining the pass rate of the collected data belonging to the plurality of clusters; selecting cluster candidates from among the plurality of clusters based on a pass rate of the collected data; as well as The collected data is clustered into the cluster candidates to generate a read retry table. 2 . The read retry table generator of claim 1 , wherein the plurality of memory dies are arranged in a same row or a same column of a same wafer. 3 . The read retry table generator of claim 2 , wherein the plurality of word lines correspond to at least one same row address sampled from a memory block or a word line group included in each of the plurality of memory dies. 4 . The read retry table generator of claim 1 , wherein the read retry table generator is coupled to the plurality of memory dies via a same channel of the data path.

5. The read retry table generator according to claim 1, wherein the read retry table generator clusters the collected data into the cluster candidates in the following manner: performing a first clustering of the plurality of word lines based on an error correction capability of an error correction circuit on the collected data; performing a second clustering on the outliers of the first cluster; and The read retry table is generated or updated based on values ​​obtained from the first cluster and the second cluster.

6. The read retry table generator according to claim 5, comprising: a cluster candidate selector that, for at least one cluster on the plurality of word lines, increases a pass rate of the at least one cluster if a fail bit count is within an error correction capability of the error correction circuit, and sequentially selects the cluster candidates starting from a highest pass rate among the pass rates of each cluster; as well as A first read retry table generator generates a first read retry table by performing the first clustering on the cluster candidates and performing the second clustering on the outliers.

7. The read retry table generator of claim 6, wherein the first cluster comprises: searching for a centroid corresponding to the cluster candidate; adding word lines belonging to a Voronoi distance range from the centroid to the cluster candidates, the Voronoi distance range corresponding to an error correction capability of the error correction circuit; as well as Word lines that do not belong to the cluster candidates are classified as outliers of the first cluster.

8. The read retry table generator of claim 6, wherein the read retry table generator calculates a fail bit count for each of the plurality of word lines based on a preset level of a read voltage, the preset level corresponding to a selected value among multi-bit data stored in the plurality of memory cells.

9. The read retry table generator of claim 5, wherein the second cluster comprises: adding outliers of the first cluster to an additional cluster, the additional cluster having a Voronoi distance range calculated based on an error correction capability of the error correction circuit and a fail bit count obtained by applying a value stored or predetermined in the read retry table before the read retry table generator generates or updates the read retry table; as well as The read retry table is valued to add all outliers of the first cluster to the additional cluster.

10. The read retry table generator according to claim 5, further comprising: a second read retry table generator that generates a second read retry table based on information about the cluster candidates by using the first cluster and another cluster different from the second cluster; as well as A comparator compares the first read retry table with the second read retry table and selects one of the first read retry table and the second read retry table based on a comparison result.

11. The read retry table generator according to claim 10, wherein the comparator compares ranges of the first read retry table and the second read retry table and selects one of the read retry tables having a wider range. 12 . The read retry table generator according to claim 10 , wherein the comparator compares the number of tables belonging to each of the first read retry table and the second read retry table, and selects one of the read retry tables having a smaller number of tables.

13. A method of operating a data processing device, the method comprising: collecting data from a plurality of memory cells coupled to a plurality of word lines in a plurality of memory dies via a data path; determining the pass rate of the collected data belonging to the plurality of clusters; selecting cluster candidates from among the plurality of clusters based on a pass rate of the collected data; performing a first clustering of the plurality of word lines based on the cluster candidates and an error correction capability of an error correction circuit on the collected data; performing a second clustering on the outliers of the first cluster; as well as A first read retry table is generated or updated based on the values ​​obtained from the first cluster and the second cluster.

14. The method of claim 13, wherein generating or updating the first read retry table comprises: receiving, via a network, values ​​obtained from the first cluster and the second cluster; generating or updating the first read retry table based on the value; as well as The first read retry table is stored in a non-volatile memory device.

15. The method according to claim 13, wherein selecting the cluster candidate comprises: setting a plurality of clusters for the plurality of word lines and calculating a pass rate of each of the plurality of clusters; as well as The cluster candidates are sequentially selected starting from a cluster corresponding to a highest pass rate among the pass rates of the plurality of clusters.

16. The method according to claim 15, wherein calculating the pass rate comprises: If a first word line among the plurality of word lines is applied to a first cluster among the plurality of clusters, when a fail bit count of the first word line is within an error correction capability of the error correction circuit, increasing a pass rate of the first cluster; as well as When the fail bit count of the first word line exceeds the error correction capability of the error correction circuit, the pass rate of the first cluster is reduced.

17. The method of claim 13, wherein performing the first clustering comprises: searching for a centroid corresponding to the cluster candidate; adding word lines belonging to a Voronoi distance range from the centroid to the cluster candidates, the Voronoi distance range corresponding to an error correction capability of the error correction circuit; as well as Word lines that do not belong to the cluster candidates are classified as outliers of the first cluster.

18. The method of claim 13, wherein performing the second clustering comprises: adding outliers of the first cluster to an additional cluster having a Voronoi distance range calculated based on an error correction capability of the error correction circuit and a fail bit count obtained by applying a value stored or predetermined in the read retry table before generating or updating the first read retry table; as well as The first read retry table is valued to add all outliers of the first cluster to the additional cluster.

19. The method of claim 13, further comprising: generating a second read retry table based on information about the cluster candidates by the first cluster and another cluster different from the second cluster; as well as One of the first read retry table and the second read retry table is selected.

20. The method of claim 19, wherein selecting one of the first read retry table and the second read retry table comprises: comparing the number of tables belonging to each of the first read retry table and the second read retry table or the range of the first read retry table and the second read retry table; as well as A read retry table with a smaller number of tables or a read retry table with a wider range is selected.

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