Memory including ECC engine and method of operating memory

Abstract

The invention relates to a memory including an ECC engine and a method of operating the memory. A memory may include: a memory core; an error correction code (ECC) engine that reads the data and the error correction code from the memory core, and detects an error in the data using the data and the error correction code; and an error information generation circuit that generates error information to be output to the outside of the memory in response to an error detection result of the ECC engine, the error information including a number of errors less than a number of errors included in the error detection result.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0140213, filed on October 19, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to memory. Background Art

[0004] In the early days of the semiconductor memory industry, multiple original good memory dies with no defective memory cells in memory chips of semiconductor manufacturing processes were distributed on wafers. However, as the capacity of memory devices gradually increases, it becomes difficult to produce memory devices with no defective memory cells. At present, it is impossible to manufacture such memory devices. As a method to overcome this situation, a method of repairing defective memory cells of memory devices using redundant memory cells is used.

[0005] As another way, an error correction circuit (ECC circuit) that corrects errors in a storage system is used to correct errors associated with storage cells. Errors associated with storage cells include errors that occur in storage cells and errors that occur when data is transferred during read and write processes of the storage system. Summary of the invention

[0006] In an embodiment of the present disclosure, a memory may include: a memory core; an error correction code (ECC) engine, which: reads data and error correction codes from the memory core and uses the data and error correction codes to detect errors in the data; and an error information generation circuit, which: generates error information to be output to the outside of the memory in response to an error detection result of the ECC engine, the error information including a number of errors that is less than the number of errors included in the error detection result.

[0007] In an embodiment of the present disclosure, a memory may include: a memory core; an error correction code (ECC) engine, which: reads data and error correction codes from the memory core and uses the data and error correction codes to detect errors in the data; and an error information generating circuit, which: generates error information indicating that the error is uncorrectable to be output to the outside of the memory when the error detection result of the ECC engine indicates that an uncorrectable error of more than 2 bits is found; generates error information indicating that the error is correctable when the error detection result indicates that a correctable error of 2 bits or a 1-bit error is found; and generates error information indicating that no error is found when the error detection result indicates that no error is found.

[0008] In an embodiment of the present disclosure, a method for operating a memory may include: reading data and error correction codes from a memory core; detecting and correcting N-bit errors in the data by using error correction codes, where N is an integer greater than 2; generating error information, the error information including information indicating that an error less than N bits is found in the data; and sending the error-corrected data and error information to a memory controller.

[0009] In an embodiment of the present disclosure, a storage system may include: a memory controller; and a memory coupled to the memory controller, wherein the memory includes: a memory core; an error correction code (ECC) engine, configured to read data and error correction codes from the memory core, and use the data and the error correction code to detect errors in the data; and an error information generation circuit, configured to generate error information based on an error detection result of the ECC engine, and send the error information to the memory controller, wherein the memory controller is configured to receive the error information, wherein the error information generation circuit is configured to: when the error detection result of the ECC engine indicates that an uncorrectable error of more than 2 bits is found, generate error information indicating that the error is uncorrectable; when the error detection result indicates that a correctable error of 2 bits or a 1-bit error is found, generate error information indicating that the error is correctable; and when the error detection result indicates that no error is found, generate error information indicating that no error is found. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a configuration diagram of a storage system according to an embodiment of the present disclosure.

[0011] Figure 2 yes Figure 1 Configuration diagram of the memory in .

[0012] Figure 3A is a diagram illustrating error information ERR_INF generated by an error information generation circuit in a correction mode according to an embodiment of the present disclosure.

[0013] Figure 3B is a diagram illustrating error information ERR_INF generated by an error information generation circuit in a non-correction mode according to an embodiment of the present disclosure.

[0014] Figure 4 The present invention is a diagram showing an embodiment of the present invention. Figure 2 Figure 2 is a diagram of an error checking operation of a memory in FIG. DETAILED DESCRIPTION

[0015] Various embodiments of the present disclosure are directed to providing a technique for detecting and correcting errors in memory and reporting the detected errors.

[0016] Embodiments of the present disclosure may detect and correct errors in a memory and report the errors to increase the stability of the memory system.

[0017] Hereinafter, embodiments according to the technical essence of the present disclosure are described with reference to the drawings.

[0018] Figure 1 is a configuration diagram of a storage system 100 according to an embodiment of the present disclosure.

[0019] Reference Figure 1 , the memory system 100 may include a memory controller 110 and a memory 120. The memory controller 110 may control the operation of the memory 120 according to a request from a host (HOST). The HOST may include a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP), etc. The memory controller 110 may include a host interface 111, a control block 113, a command generator 115, and a memory interface 117. The memory controller 110 may be included in a CPU, a GPU, or an AP, etc. In this case, the HOST may refer to a configuration other than the memory controller 110 in these configurations. For example, when the memory controller 110 is included in a CPU, the HOST in the figure may represent the remaining components in the CPU except the memory controller 110.

[0020] The host interface 111 may be an interface for communication between the HOST and the memory controller 110 .

[0021] The control block 113 may control the overall operation of the memory controller 110 and schedule operations to be instructed to the memory 120. To improve the performance of the memory 120, the control block 113 may allow the order in which requests are received from the host to be different from the order in which operations are instructed to the memory 120. For example, even if the HOST first requests a read operation of the memory 120 and later requests a write operation, the order may be adjusted so that the write operation is performed before the read operation.

[0022] The command generator 115 may generate a command to be applied to the memory 120 according to the operation sequence determined by the control block 113 .

[0023] The memory interface 117 may be an interface for communication between the memory controller 110 and the memory 120. Commands and addresses CA may be transmitted from the memory controller 110 to the memory 120 through the memory interface 117. Data DATA may be sent and received between the memory controller 110 and the memory 120 through the memory interface 117, that is, from the memory controller 110 to the memory 120 or from the memory 120 to the memory controller 110. The memory interface 117 may receive error information ERR_INF from the memory 120. The memory interface 117 is also referred to as a physical (PHY) interface.

[0024] The memory 120 may perform operations instructed by the memory controller 110. Figure 2 The memory 120 is described in detail.

[0025] Figure 2 yes Figure 1 A configuration diagram of an embodiment of the memory 120 in FIG.

[0026] Reference Figure 2 , the memory 120 may include a command address receiving circuit 201, a data sending / receiving circuit 203, an error information sending circuit 205, a command decoder 210, a row control circuit 220, a column control circuit 230, an address control circuit 240, an error correction code (ECC) engine 250, an error checking operation control circuit 261, an error checking address generating circuit 263, an error log circuit 265, an error information generating circuit 270 and a memory core 280.

[0027] The command address receiving circuit 201 may receive a command and an address CA. According to the type of the memory 120, the command and the address CA may be input through the same input terminal, or the command and the address CA may be input through different input terminals. Figure 2 It is shown that the command and the address CA are input through the same input terminal. The command and the address CA may each have multiple bits.

[0028] The data transmission / reception circuit 203 can be Figure 1 The data transmission / reception circuit 203 receives data DATA from the memory controller 110 or transmits data DATA to the memory controller 110. During a write operation, the data transmission / reception circuit 203 may receive data DATA to be written to the memory core 280 from the memory controller 110. During a read operation, the data transmission / reception circuit 203 may transmit data DATA read from the memory core 280 and having errors corrected by the error correction circuit 251 to the memory controller 110.

[0029] The command decoder 210 may determine the type of operation instructed by the memory controller 110 to the memory 120 by decoding the command and the address CA.

[0030] When a row type operation such as an activation operation and a precharge operation is indicated as a result of decoding of the command decoder 210, the row control circuit 220 may control such operations. For these operations, the activation signal ACT may include a signal indicating the activation operation, and the precharge signal PCG may include a signal indicating the precharge operation.

[0031] When column-based operations such as write operations and read operations are indicated as a result of decoding of the command decoder 210, the column control circuit 230 may control such operations. For these operations, the write signal WR may include a signal indicating a write operation, and the read signal RD may include a signal indicating a read operation.

[0032] When the error check operation mode is indicated as a result of decoding by the command decoder 210 , the memory 120 may operate in the error check operation mode. In the error check operation mode, the memory 120 may operate under the control of the error check operation control circuit 261 .

[0033] The address control circuit 240 may classify the address received from the command decoder 210 into a row address R_ADD and a column address C_ADD, and transmit the row address R_ADD and the column address C_ADD to the memory core 280. When an activation operation is indicated as a result of decoding by the command decoder 210, the address control circuit 240 may classify the received address into the row address R_ADD. When a read / write operation is indicated, the address control circuit 240 may classify the received address into the column address C_ADD.

[0034] The ECC engine 250 may include an error correction circuit 251 and an error correction code generation circuit 253. During a read operation, the error correction circuit 251 may detect an error in the data DATA' read from the memory core 280 by using the error correction code ECC read from the memory core 280, and correct the detected error. When an error in the data DATA' is discovered and corrected, the data DATA' input to the error correction circuit 251 may be different from the data DATA output from the error correction circuit 251. The error correction circuit 251 may transmit an error detection result ERR_DET as a data error detection result to the error log circuit 265 and the error information generation circuit 270.

[0035] The error correction code generation circuit 253 may generate an error correction code by using the data DATA during a write operation. During a write operation, since only the data is used to generate the error correction code and an error in the data DATA is not corrected, the data DATA input to the error correction code generation circuit 253 from the data transmission / reception circuit 203 may be the same as the data DATA′ output from the error correction code generation circuit 253 to the memory core 280.

[0036] The specification of the error correction capability of the ECC engine 250 embedded in the memory 120 may be defined. For example, there is a specification that the ECC engine 250 embedded in the memory 120 needs to be able to correct a 1-bit error in the read data. The ECC engine 250 may also have an error correction capability (hereinafter referred to as a specific or required error correction capability) that exceeds the error correction capability defined in the specification. That is, an ECC engine 250 with the required error correction capability may also be embedded in the memory 120. For example, the memory system 100 may require that the ECC engine 250 embedded in the memory 120 needs to be able to correct a 1-bit error, but the ECC engine 250 embedded in the memory 120 can correct not only a 1-bit error, but also some pattern errors in 2-bit errors. In the following, the error correction capability required for the memory 120 in the memory system 100 is 1-bit error correction, but the ECC engine 250 of the memory 120 may have the ability to correct some pattern errors in errors above 2 bits that even exceed the requirements of the memory system 100.

[0037] The error correction circuit 251 of the ECC engine 250 may be able to set a mode among the correction mode and the non-correction mode. The correction mode may correspond to the ECC mode signal ECC_MODE at a logic "1" level. The non-correction mode may correspond to the ECC mode signal ECC_MODE at a logic "0" level. In the correction mode, the error correction circuit 251 may correct all correctable errors. For example, when a 2-bit correctable error is found, the error correction circuit 251 may correct the error. In the non-correction mode, the error correction circuit 251 may not correct errors that exceed the required error correction capability. For example, when a 1-bit error is found, the error correction circuit 251 may correct the error, but when a 2-bit correctable error is found, the error correction circuit 251 may not correct the error.

[0038] In response to the error detection result ERR_DET of the ECC engine 250, the error information generation circuit 270 may generate error information ERR_INF to be output to the outside of the memory 120. Each time a read operation is performed, the error information ERR_INF may be transmitted to the memory controller 110 through the error information transmission circuit 205. The error information ERR_INF may be output from the memory 120 to the memory controller 110 through an unused pad of the memory 120. For example, a data mask inversion (DMI) pad of the memory 120 is not used during a read operation, and the error information transmission circuit 205 may transmit the error information ERR_INF through the DMI pad.

[0039] In the correction mode, the error information generating circuit 270 may generate the error information ERR_INF so that the number of errors included in the error information ERR_INF is less than the number of errors included in the error detection result ERR_DET. For example, when the error detection result ERR_DET includes information indicating that an error of N bits is found in the data DATA' (where N is an integer greater than 2), the error information ERR_INF may include information indicating that an error of less than N bits is found in the data DATA'.

[0040] Figure 3A 2 is a diagram showing error information ERR_INF generated by the error information generation circuit 270 in the correction mode according to an embodiment of the present disclosure. Figure 3A When the error correction circuit 251 does not find or detect an error (ERR_DET=no error), the error information ERR_INF may be generated as "00" indicating no error (NE). When the error information (ERR_INF='00') is sent to the memory controller 110, the memory controller 110 may recognize that there is no error in the memory 120.

[0041] When the error correction circuit 251 finds or detects a 1-bit error (ERR_DET=1-bit error), the error information ERR_INF may be generated as "01" indicating a correctable error (CE). When the error information (ERR_INF="01") is sent to the memory controller 110, the memory controller 110 may recognize that a 1-bit error has been found in the memory 120 and has been corrected.

[0042] When the error correction circuit 251 finds or detects a 2-bit correctable error (ERR_DET=2-bit correctable error), the error information ERR_INF may be generated as "01" indicating a correctable error (CE). When the error information (ERR_INF="01") is sent to the memory controller 110, the memory controller 110 may recognize that a 1-bit error has been found and corrected in the memory 120. That is, a 2-bit error has been found and corrected in the memory 120, but it may be reported to the memory controller 110 that a 1-bit error has been found and corrected. This is because the ECC engine 250 of the memory 120 has an error correction capability that exceeds the error correction capability required by the specification, and even if a 2-bit error has been found, since the 2-bit error has been corrected, even if the memory controller 110 recognizes that a 1-bit error has been found and corrected, the stability of the system may not be a problem.

[0043] When the error correction circuit 251 finds or detects an uncorrectable error of more than 2 bits (ERR_DET=uncorrectable error of more than 2 bits), the error information ERR_INF may be generated as "11" indicating an uncorrectable error (UE). When the error information (ERR_INF="11") is sent to the memory controller 110, the memory controller 110 may recognize that an error of more than 2 bits has been found in the memory 120 and has not been corrected.

[0044] Figure 3B 2 is a diagram showing error information ERR_INF generated by the error information generation circuit 270 in the non-correction mode according to an embodiment of the present disclosure. Figure 3B When the error correction circuit 251 does not find or detect an error (ERR_DET=no error), the error information ERR_INF may be generated as "00" indicating no error (NE). When the error information (ERR_INF='00') is sent to the memory controller 110, the memory controller 110 may recognize that there is no error in the memory 120.

[0045] When the error correction circuit 251 finds or detects a 1-bit error (ERR_DET=1-bit error), the error information ERR_INF may be generated as "01" indicating a correctable error (CE). When the error information (ERR_INF="01") is sent to the memory controller 110, the memory controller 110 may recognize that a 1-bit error has been found in the memory 120 and has been corrected.

[0046] When the error correction circuit 251 finds or detects a 2-bit correctable error (ERR_DET=2-bit correctable error), the error information ERR_INF may be generated as "11" indicating an uncorrectable error (UE). When the error information (ERR_INF="11") is sent to the memory controller 110, the memory controller 110 may recognize that errors of more than 2 bits have been found in the memory 120 and have not been corrected. In the non-correction mode, even if a 2-bit correctable error is found, since the error correction circuit 251 does not correct the error, the recognition of the memory controller 110 may be OK.

[0047] When the error correction circuit 251 finds or detects an uncorrectable error of more than 2 bits (ERR_DET=uncorrectable error of more than 2 bits), the error information ERR_INF may be generated as "11" indicating an uncorrectable error (UE). When the error information (ERR_INF="11") is sent to the memory controller 110, the memory controller 110 may recognize that an error of more than 2 bits has been found in the memory 120 and has not been corrected.

[0048] Refer again Figure 2 , the error checking operation control circuit 261 can control the error checking operation of the memory 120. The error checking operation is also called an error checking and cleaning (ECS) operation. The error checking operation may include operations of reading data DATA' and error correction code ECC from the memory core 280, checking errors by using the error correction circuit 251, and selecting a specific area (e.g., a cell or a row) including an error among the storage cells in the memory core 280. The data after the error is corrected by the error correction circuit 251 can be written to the memory core 280 again. When the error checking operation mode is set, the error checking operation control circuit 261 can control the error checking operation. Since the error checking operation needs to control the rows and columns of the memory core 280, the error checking operation control circuit 261 can control the row control circuit 220 and the column control circuit 230 during the error checking operation. The error checking operation control circuit 261 can also control the error checking address generation circuit 263 and the error log circuit 265 related to the error checking operation.

[0049] The error check address generation circuit 263 may generate internal addresses R_ADD_INT and C_ADD_INT to be used for the error check operation. The internal address may include an internal row address R_ADD_INT and an internal column address C_ADD_INT. Each time the error check operation is performed, the error check address generation circuit 263 may change the internal addresses R_ADD_INT and C_ADD_INT. Each time the error check operation is performed, the error check address generation circuit 263 may increase the internal addresses R_ADD_INT and C_ADD_INT by one step. When the value of the internal row address R_ADD_INT ranges from 0 to X and the value of the internal column address C_ADD_INT ranges from 0 to Y, the error check address generation circuit 263 may generate the internal addresses R_ADD_INT and C_ADD_INT as (0, 0) during the first error check operation. During the second error checking operation, the error checking address generation circuit 263 can generate the internal addresses R_ADD_INT and C_ADD_INT as (0, 1) by increasing the internal addresses R_ADD_INT and C_ADD_INT by one step. Similarly, during the third error checking operation, the error checking address generation circuit 263 can generate the internal addresses R_ADD_INT and C_ADD_INT as (0, 2) by increasing the internal addresses R_ADD_INT and C_ADD_INT by one step. Each time the error checking operation is performed, the internal addresses R_ADD_INT and C_ADD_INT may be increased by one step, so that the internal addresses (row address, column address) are generated in the following order: (0, 0) -> (0, 1) -> (0, 2) -> ... -> (0, Y-1) -> (0, Y) -> (1, 0) -> (1, 1) -> ... -> (1, Y-1) -> (1, Y) -> (2, 0) -> (2, 1) -> ... -> (X, Y-1) -> (X, Y). Because the error checking address generation circuit 263 changes the internal addresses R_ADD_INT and C_ADD_INT each time the error checking operation is performed, the error checking operation may be performed on all memory cells of the memory core 280 when the error checking operation is repeatedly performed.

[0050] The error log circuit 265 may be a circuit for recording the history of errors found during the error checking operation. The error log circuit 265 may count and store the number of times an error has been found for each region (e.g., each row) of the memory core 280, and classify a region where many errors exceeding a threshold value have been found as a bad region. Because the error log circuit 265 receives the internal addresses R_ADD_INT and C_ADD_INT and the error detection result ERR_DET, the error log circuit 265 may determine the region of the memory core 280 where an error has been found during the error checking operation. When there is a request from the memory controller 110, the bad region information BAD_REGION classified by the error log circuit 265 may be sent to the memory controller 110 through the data transmission / reception circuit 203. In some embodiments, the bad region information BAD_REGION may include the address of the region classified as a bad region in the memory core 280 and information about the number of errors found in the region.

[0051] When a 1-bit error is found in the error detection result ERR_DET, the error log circuit 265 may increase the error count of the corresponding area by a specific value, such as + 1. When an uncorrectable error of more than 2 bits is found, the error log circuit 265 may increase the error count of the corresponding area by a specific value, such as + 2. When a 2-bit correctable error is found, the error count of the corresponding area may be set to a specific value, such as + 1, or the error count of the corresponding area may be set to a specific value, such as + 2.

[0052] The memory core 280 may perform operations indicated by internal command signals ACT, PCG, WR, and RD. The memory core 280 may include a configuration for operations such as activation, precharge, reading, and writing, such as a cell array including memory cells arranged between multiple rows and multiple columns. In addition, the memory core 280 may include a row decoder for activating / deactivating the rows of the cell array, a column decoder for inputting / outputting data from the cell array, and an input / output circuit. When the activation signal ACT is activated, the row selected by the row address R_ADD in the row of the memory core 280 may be activated. When the precharge signal PCG is activated, the activated row may be deactivated. When the write signal WR is activated, the data DATA' and the error correction code ECC may be written to the memory cell of the column selected by the column address C_ADD among the columns of the memory core 280. When the read signal RD is activated, the data DATA' and the error correction code ECC may be read from the memory cell of the column selected by the column address C_ADD among the columns of the memory core 280. During the error checking operation, the internal addresses R_ADD_INT and C_ADD_INT generated by the error checking address generation circuit 263 may be used instead of the addresses R_ADD and C_ADD of the address control circuit 240 .

[0053] Figure 4 The present invention is a diagram showing an embodiment of the present invention. Figure 2 FIG. 1 is a diagram of an error checking operation of the memory 120 in FIG.

[0054] Reference Figure 4 , data DATA′ and error correction code ECC may first be read from a memory cell selected by internal addresses R_ADD_INT and C_ADD_INT in the memory core 280 ( 401 ).

[0055] The error correction circuit 251 of the ECC engine 250 may detect and correct an error in the data DATA′ by using the error correction code ECC ( 403 ).

[0056] When an error is detected ("Yes" in 405), the detected error may be recorded in the error log circuit 265 (407). As described above, the error log circuit 265 may count the number of errors found in each area of ​​the memory core 280. When a 1-bit error is found in the error detection result ERR_DET of the ECC engine 250, the error log circuit 265 may increase the error count of the corresponding area by a specific value, such as +1. When an uncorrectable error of more than 2 bits is found, the error log circuit 265 may increase the error count of the corresponding area by a specific value, such as +2. When a 2-bit correctable error is found, the error count of the corresponding area may be set to a specific value, such as +1, or the error count of the corresponding area may be set to a specific value, such as +2.

[0057] The data DATA′ and the error correction code ECC after the error is corrected by the ECC engine 250 may be rewritten to the memory core 280 again (409). The read operation (401) and the rewrite operation (409) may be performed on the same memory cell of the memory core 480.

[0058] Subsequently, the error check address generation circuit 263 may change the values ​​of the internal addresses R_ADD_INT and C_ADD_INT ( 411 ), and may perform the operations ( 401 to 409 ) again using the changed internal addresses R_ADD_INT and C_ADD_INT.

[0059] Although the embodiments according to the technical concept of the present disclosure have been described above with reference to the accompanying drawings, this is only used to describe the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical concept of the present disclosure defined in the attached claims, technicians in the field to which the present disclosure belongs can make various types of replacements, modifications and changes to the embodiments, and it should be understood that these replacements, modifications and changes all belong to the scope of the present disclosure.

[0060] In the above-described embodiments, all operations may be selectively performed, or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described, but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. In other words, it is obvious to those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0061] Embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only for describing embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and there may be many changes within the scope of the present disclosure. It is apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A memory, comprising: Memory core; An ECC engine that: reads data and an error correction code from the memory core and detects errors in the data using the data and the error correction code, ECC standing for error correction code; and An error information generating circuit generates error information to be output to the outside of the memory in response to an error detection result of the ECC engine, wherein the error number included in the error information is smaller than the error number included in the error detection result.

2. The memory according to claim 1, wherein: When the error detection result indicates that an error of N bits is found in the data, the error information generation circuit generates the error information to include information indicating that an error of less than N bits is found, where N is an integer greater than or equal to 2.

3. The memory according to claim 1, wherein: The ECC engine has error correction capabilities that exceed the specified error correction capabilities, and When the ECC engine corrects an error in the read data that corresponds to an error that exceeds the specific error correction capability and can be corrected by the ECC engine, the error information generation circuit generates the error information so that the number of errors included in the error information is smaller than the number of errors included in the error detection result.

4. A memory comprising: Memory core; An ECC engine that: reads data and an error correction code from the memory core and detects errors in the data using the data and the error correction code, ECC standing for error correction code; and An error information generating circuit, which: generates error information indicating that the error is uncorrectable, to be output to the outside of the memory, when the error detection result of the ECC engine indicates that an uncorrectable error of more than 2 bits is found; generates the error information indicating that the error is correctable, when the error detection result indicates that a correctable error of 2 bits or an error of 1 bit is found; and generates the error information indicating that there is no error, when the error detection result indicates that no error is found.

5. The memory according to claim 4, wherein: The memory controller receives the error information, and when the error information indicates that the error is uncorrectable, determines based on the error information that an error of more than 2 bits is found in the memory, When the error information indicates that the error is correctable, determining that a 1-bit error is found in the memory, and When the error information indicates no error, it is determined that no error is found in the memory.

6. The memory according to claim 4, wherein In the first mode, the error information generating circuit: when the error detection result indicates that an uncorrectable error of more than 2 bits is found, generates the error information indicating that the error is uncorrectable; when the error detection result indicates that a correctable error of 2 bits or an error of 1 bit is found, generates the error information indicating that the error is correctable; and when the error detection result indicates that no error is found, generating the error information indicating that no error is found, and In the second mode, the error information generating circuit: when the error detection result indicates that more than 2 bits of errors are found, generates the error information indicating that the error is uncorrectable; When the error detection result indicates that the 1-bit error is found, the error information indicating that the error is correctable is generated; and when the error detection result indicates that no error is found, the error information indicating that no error is generated.

7. The memory according to claim 6, wherein In the correction mode, when the 2-bit correctable error is found, the ECC engine corrects the error in the read data, and In the non-correction mode, when the 2-bit correctable error is found, the ECC engine does not correct the error in the read data.

8. The memory according to claim 4, further comprising: an error log circuit for recording the error detection history of the ECC engine, Wherein, the error log circuit: when the error detection result indicates that the 2-bit correctable error is found, the error number is counted plus 2; and when the error detection result indicates that the 1-bit error is found, the error number is counted plus 1.

9. The memory according to claim 4, further comprising: an error log circuit for recording the error detection history of the ECC engine, When the error detection result indicates that the 2-bit correctable error and the 1-bit error are found, the error log circuit counts the number of errors by adding 1.

10. A method for operating a memory, the method comprising: Reading data and error correction codes from the memory core; Detecting and correcting N-bit errors in the data by using the error correction code, where N is an integer greater than 2; generating error information, the error information including information indicating that an error less than N bits is found in the data; as well as The error-corrected data and the error information are sent to a memory controller.

11. The operating method according to claim 10, wherein: The memory has an error correction capability that exceeds a specified error correction capability, and Correction of errors in the N bits of the data exceeds the specific error correction capability.

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