Epitaxial growth substrate and method for manufacturing semiconductor device

Abstract

Provided is an epitaxial growth substrate capable of suppressing the occurrence of cracks in a semiconductor layer when the semiconductor layer is separated from the substrate. This epitaxial growth substrate is provided with: a substrate comprising a group III-V compound semiconductor containing Ga or In as a group III element; a sacrificial layer epitaxially grown on the substrate; and a semiconductor layer epitaxially grown on the sacrificial layer. The sacrificial layer includes a layer formed of a mixed crystal semiconductor containing Al or In as a Group III element, the composition ratio of Al or In changes in the thickness direction, and the position where the composition ratio of Al or In is maximum is located inside the sacrificial layer other than the lower surface and the upper surface.

Description

Technical Field

[0001] The present invention relates to an epitaxial growth substrate and a method for manufacturing a semiconductor device. Background Art

[0002] It is well known that a sacrificial layer such as AlGaAs or AlAs is epitaxially grown on a substrate such as GaAs, a semiconductor layer is epitaxially grown thereon, and then the sacrificial layer is etched to separate the semiconductor layer from the substrate (Patent Documents 1 and 2). When etching the sacrificial layer, a groove is formed from the semiconductor layer to the lower surface of the sacrificial layer. After the groove is formed, the sacrificial layer is etched from the side of the groove.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 2658493

[0006] Patent Document 2: Japanese Patent No. 5394091 Summary of the invention

[0007] The etching of the sacrificial layer is performed laterally from the end face exposed in the groove. Due to the dependence of the etching rate on the crystal plane orientation, the etching of the portion of the sacrificial layer in contact with the semiconductor layer is sometimes faster than the portion in contact with the substrate. If etching is continued under this condition, the sacrificial layer and the semiconductor layer are connected in a small area, and the sacrificial layer and the substrate are connected in a relatively wide area. If the substrate and the sacrificial layer fall off from the semiconductor layer in a state where the sacrificial layer and the semiconductor layer are connected in a small area, cracks will occur in the semiconductor layer.

[0008] An object of the present invention is to provide an epitaxial growth substrate which can suppress cracks from being generated in a semiconductor layer when the semiconductor layer is separated from the substrate. Another object of the present invention is to provide a method for manufacturing a semiconductor device using the epitaxial growth substrate.

[0009] According to one aspect of the present invention, there is provided the following epitaxial growth substrate, comprising:

[0010] A substrate formed of a III-V compound semiconductor containing Ga or In as a III-group element, a sacrificial layer epitaxially grown on the substrate, and

[0011] a semiconductor layer epitaxially grown on the sacrificial layer;

[0012] The sacrificial layer includes a layer formed of a mixed crystal semiconductor containing Al or In as a Group III element, and the composition ratio of Al or In changes in the thickness direction. The position where the composition ratio of Al or In reaches a maximum value is located inside the sacrificial layer other than the lower surface and the upper surface.

[0013] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided as follows:

[0014] forming a semiconductor element of at least one of a transistor and a diode in the semiconductor layer of the epitaxial growth substrate;

[0015] Furthermore, the sacrificial layer is removed by etching to separate the substrate from the semiconductor layer.

[0016] At the position where the composition ratio of Al or In in the sacrificial layer is at a maximum value, the etching rate for an acidic etchant or an alkaline etchant is relatively high. Therefore, if the sacrificial layer is etched, the etching is relatively fast at positions other than the lower and upper surfaces of the sacrificial layer, and the portion on the substrate side and the portion on the semiconductor layer side are separated at positions other than the lower and upper surfaces of the sacrificial layer. Since the sacrificial layer on the substrate side and the sacrificial layer on the semiconductor layer side are separated at a position away from the semiconductor layer, cracks are not easily generated in the semiconductor layer during separation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A is a cross-sectional view of an epitaxial growth substrate according to the first embodiment. Figure 1B This is a diagram showing an example of the distribution of the etching rate of each layer of the epitaxial growth substrate.

[0018] Figure 2A , Figure 2B and Figure 2C It is a cross-sectional view of the epitaxial growth substrate, the dummy substrate, and the adhesive layer at an intermediate stage of the step of separating the semiconductor layer from the substrate based on the epitaxial growth substrate of the first embodiment.

[0019] Figure 3A and Figure 3C is a cross-sectional view of an epitaxial growth substrate, a dummy substrate, and an adhesive layer in the middle of a process of separating a semiconductor layer from a substrate based on an epitaxial growth substrate according to the first embodiment, Figure 3B Yes means Figure 3A The top view of the positional relationship between the substrate, semiconductor layer and sacrificial layer at the intermediate stage is shown. Figure 3D is a cross-sectional view of a semiconductor layer, a dummy substrate, and an adhesive layer separated from a substrate.

[0020] Figure 4A and Figure 4B It is a diagram showing a step of separating a substrate and a semiconductor layer in an epitaxial growth substrate according to a comparative example.

[0021] Figure 5A is a diagram showing the distribution of the Al composition ratio in the thickness direction in the sacrificial layer of the epitaxial growth substrate according to the first embodiment. Figure 5B to Figure 5FFIG. 1 is a diagram showing the distribution of the Al composition ratio in the thickness direction in the sacrificial layer of the epitaxial growth substrate according to the modified example of the first embodiment.

[0022] Figure 6A to Figure 6F FIG. 1 is a diagram showing the distribution of the In composition ratio in the thickness direction in the sacrificial layer of the epitaxial growth substrate according to another modified example of the first embodiment.

[0023] Figure 7 This is a cross-sectional view of an epitaxial growth substrate according to the second embodiment.

[0024] Fig. 8A and Figure 8B This is a cross-sectional view of a semiconductor device according to the third embodiment at an intermediate stage in the manufacturing process.

[0025] Fig. 9A and Fig. 9B This is a cross-sectional view of a semiconductor device according to the third embodiment at an intermediate stage in the manufacturing process.

[0026] Explanation of symbols

[0027] 10 substrates

[0028] 20 Sacrificial Layer

[0029] 20A AlGaAs layer

[0030] 20B AlAs layer

[0031] 20C AlGaAs layer

[0032] 20D dot-shaped tiny area

[0033] 20E The substrate side of the sacrificial layer

[0034] 20F The part of the sacrificial layer on the semiconductor layer side

[0035] 30Semiconductor layer

[0036] 30C Crack

[0037] 30D equipment layer

[0038] 30I component separation area

[0039] 30N active area

[0040] 30S barrier layer

[0041] 31 transistors

[0042] 32 diodes

[0043] 33 Insulation film

[0044] 40 epitaxial growth substrate

[0045] 50 pseudo substrate

[0046] 51 Adhesive layer

[0047] 55 separation tank DETAILED DESCRIPTION

[0048] [First embodiment]

[0049] Reference Figure 1A to Figure 4B The epitaxial growth substrate based on the first embodiment is described with reference to FIG.

[0050] Figure 1A This is a cross-sectional view of an epitaxial growth substrate 40 based on the first embodiment. A sacrificial layer 20 and a semiconductor layer 30 are epitaxially grown in this order on a substrate 10 formed of a III-V compound semiconductor containing Ga as a III-group element, such as GaAs. The sacrificial layer 20 includes layers 20A and 20C formed of a III-V mixed crystal semiconductor containing Al as a III-group element, such as AlGaAs. In addition, a layer 20B formed of a compound semiconductor containing Al as a III-group element, such as AlAs, is included between the two. The semiconductor layer 30 includes a layer formed of a compound semiconductor such as GaAs that is lattice-matched with the substrate 10.

[0051] Based on the epitaxial growth substrate 40 of the first embodiment, the sacrificial layer 20 is removed by etching, thereby separating the semiconductor layer 30 from the substrate 10 and using it as a thin semiconductor layer 30. For example, before being separated from the substrate 10, various electronic circuit elements such as transistors, diodes, and other passive elements are formed on the semiconductor layer 30, and then separated from the substrate 10, so that a very thin integrated circuit element can be made.

[0052] Figure 1B This is a diagram showing an example of the distribution of the etching rates of the various layers of the epitaxial growth substrate 40. The horizontal axis represents the position in the thickness direction of the epitaxial growth substrate 40, and the vertical axis represents the etching rate. If the composition ratio of Al becomes larger, the etching rate during wet etching with an acidic etchant or an alkaline etchant becomes faster. Therefore, the etching rate of the layer 20B formed by AlAs is faster than the etching rate of the layers 20A and 20C formed by AlGaAs. The etching rates of the substrate 10 and the semiconductor layer 30 formed by GaAs are much lower than the etching rates of the three layers 20A, 20B, and 20C included in the sacrificial layer 20.

[0053] Next, refer to Figure 2A to Figure 3D , a step of separating the substrate 10 and the semiconductor layer 30 based on the epitaxial growth substrate 40 of the first embodiment is described. Figure 2A , Figure 2B , Figure 2C , Figure 3A as well as Figure 3CIt is a cross-sectional view of the epitaxial growth substrate 40 , the dummy substrate 50 , and the adhesive layer 51 at an intermediate stage of the step of separating the substrate 10 from the semiconductor layer 30 based on the epitaxial growth substrate 40 of the first embodiment. Figure 3B Yes means Figure 3A FIG. 2 is a diagram showing the positional relationship among the substrate 10 , the semiconductor layer 30 , and the sacrificial layer 20 in a plan view at an intermediate stage. Figure 3D 3 is a cross-sectional view of the semiconductor layer 30 , the dummy substrate 50 , and the adhesive layer 51 separated from the substrate 10 .

[0054] like Figure 2A As shown, the semiconductor layer 30 of the epitaxial growth substrate 40 according to the first embodiment is placed opposite to the dummy substrate 50, and the epitaxial growth substrate 40 and the dummy substrate 50 are bonded together by the bonding layer 51. As the dummy substrate 50, for example, a silicon substrate is used, and the bonding layer 51 uses a polyimide-based adhesive.

[0055] like Figure 2B As shown, the epitaxial growth substrate 40 is cut to form separation grooves 55 , thereby separating the epitaxial growth substrate 40 into a plurality of small pieces (chips). The plurality of small pieces of the epitaxial growth substrate 40 are bonded to the dummy substrate 50 and supported by the dummy substrate 50 .

[0056] like Figure 2C As shown, the epitaxial growth substrate 40 separated into small pieces is immersed in an acidic or alkaline etchant to wet-etch the sacrificial layer 20. The sacrificial layer 20 is etched from the exposed end surface in the lateral direction. Figure 1B As shown, the etching rate of the sacrificial layer 20 is high in the central portion in the thickness direction and low near the interface between the substrate 10 and the semiconductor layer 30. Therefore, the lateral etching depth of the central portion in the thickness direction of the sacrificial layer 20 becomes relatively deep compared to other portions.

[0057] If further etching is performed, such as Figure 3A as well as Figure 3B As shown, in the central portion of the thickness direction of the sacrificial layer 20, the substrate 10 side portion of the sacrificial layer 20 and the semiconductor layer 30 side portion are connected in a dot-shaped micro region 20D. Figure 3C As shown, the sacrificial layer 20 is separated into a portion 20E on the substrate 10 side and a portion 20F on the semiconductor layer 30 side.

[0058] After the sacrificial layer 20 is separated into two parts 20E and 20F, further etching is performed, such as Figure 3D As shown, the remaining portion 20F on the semiconductor layer 30 side is completely removed ( Figure 3C In the process up to this point, the semiconductor layer 30 and the substrate 10 ( Figure 3C The semiconductor layer 30 is hardly etched by the etchant.

[0059] Next, with Figure 4A and Figure 4B The excellent effects of the first embodiment will be described by comparison with the comparative examples shown.

[0060] Figure 4A as well as Figure 4B 1 is a diagram showing a step of separating the semiconductor layer 30 from the substrate 10 in the epitaxial growth substrate 40 of the comparative example. In the epitaxial growth substrate 40 of the comparative example, the Al composition ratio of the sacrificial layer 20 is constant in the thickness direction. If the sacrificial layer 20 is etched from the exposed end face, due to the crystal plane orientation dependence of the etching rate, as shown in FIG. Figure 4A As shown, the sacrificial layer 20 is in the shape of a quadrangular pyramid with a crystal plane having a slow etching rate as an inclined surface. The surface (upper surface) of the semiconductor layer 30 connected to the quadrangular pyramid is smaller than the surface (lower surface) connected to the substrate 10.

[0061] If further etching is performed, such as Figure 4B As shown, the upper surface of the quadrangular pyramid sacrificial layer 20 becomes almost dot-shaped, and the sacrificial layer 20 is separated from the semiconductor layer 30. Just before the sacrificial layer 20 is separated from the semiconductor layer 30, the sacrificial layer 20 is supported in a tiny dot-shaped region relative to the semiconductor layer 30. Due to the stress concentration in the tiny dot-shaped region, cracks 30C are easily generated in the semiconductor layer 30.

[0062] In contrast, in the first embodiment, the etching rate varies in the thickness direction of the sacrificial layer 20, and the portion with the highest etching rate is located inside the sacrificial layer 20. Figure 3A and Figure 3B As shown in FIG. 1 , before the substrate 10 is separated from the semiconductor layer 30, the substrate 10 side portion of the sacrificial layer 20 and the semiconductor layer 30 side portion are connected in a tiny dot-shaped area. That is, the sacrificial layer 20 and the semiconductor layer 30 are connected at the position ( Figure 3A , Figure 3C ) does not produce a tiny point-like state. Therefore, an excellent effect of making it difficult for cracks to occur on the semiconductor layer 30 can be obtained. In order to preferentially etch and remove the sacrificial layer 20 relative to the substrate 10 and the semiconductor layer 30, it is preferred that the maximum value of the Al composition ratio in the sacrificial layer 20 is set to be greater than 0.5.

[0063] If the layer 20A formed of AlGaAs is omitted ( Figure 1A), if the layer 20B formed of AlAs is directly epitaxially grown on the substrate 10, the crystal quality of the sacrificial layer 20 is reduced due to the lattice mismatch. As a result, the crystal quality of the semiconductor layer 30 epitaxially grown on the sacrificial layer 20 is also reduced. The layer 20A formed of AlGaAs disposed between the layer 20B formed of AlAs and the substrate 10 formed of GaAs has the function of alleviating the lattice mismatch. Thus, the reduction in the crystallinity of the sacrificial layer 20 and the semiconductor layer 30 can be suppressed.

[0064] Next, a preferred range of the thickness of the sacrificial layer 20 will be described.

[0065] Due to the lattice mismatch between the substrate 10 and the sacrificial layer 20, strain occurs in the sacrificial layer 20. However, if the sacrificial layer 20 is too thick, dislocations occur in the sacrificial layer 20 to relax the strain. The sacrificial layer 20 is preferably thin enough not to relax the strain. Figure 2C In the etching step shown, the etchant is unlikely to penetrate into the space of the removed sacrificial layer 20. The sacrificial layer 20 is preferably thick enough not to hinder the penetration of the etchant.

[0066] Next, a preferred relationship among the thicknesses of the substrate 10 , the sacrificial layer 20 , and the semiconductor layer 30 will be described.

[0067] In a semiconductor process for forming various electronic circuit elements such as transistors, diodes, capacitors, and inductors on a thin semiconductor layer 30, the substrate 10 functions as a supporting substrate for mechanically supporting the semiconductor layer 30. The semiconductor layer 30 is so thin that it cannot maintain a stable shape by itself. In addition, the substrate 10 is separated from the semiconductor layer 30 to achieve thin filmization of the components of the semiconductor layer 30 including the electronic circuit elements. Therefore, it is preferred that the thickness of the semiconductor layer 30 is thinner than that of the substrate 10.

[0068] When a transistor is formed on the semiconductor layer 30 , a material lattice-matched to a compound semiconductor constituting one layer of the transistor is preferably used as the substrate 10 . In other words, the semiconductor layer 30 preferably includes a layer formed of a compound semiconductor lattice-matched to the substrate 10 .

[0069] If the sacrificial layer 20 is made too thick, dislocations are likely to occur in the sacrificial layer 20, and the crystal quality of the semiconductor layer 30 epitaxially grown thereon will be reduced. In order to suppress the reduction in the crystal quality of the semiconductor layer 30, the sacrificial layer 20 is preferably as thin as possible. As an example, the thickness of the sacrificial layer 20 is preferably thinner than the thickness of the semiconductor layer 30. For example, the thickness of the sacrificial layer 20 is 0.01 μm to 0.5 μm, and the thickness of the semiconductor layer 30 is 0.5 μm to 10 μm.

[0070] Next, refer to Figure 5A to Figure 5FThe epitaxial growth substrate based on the first embodiment and the modified example of the first embodiment is described with reference to the figures. Figure 5A is a diagram showing the distribution of the Al composition ratio in the thickness direction in the sacrificial layer 20 of the epitaxial growth substrate 40 according to the first embodiment. Figure 5B to Figure 5F FIG. 1 is a diagram showing the distribution of the Al composition ratio in the thickness direction in the sacrificial layer 20 of the epitaxial growth substrate 40 according to the modified example of the first embodiment. x Ga 1－x As formed. Figure 5A to Figure 5F In the graph shown, the horizontal axis represents the positions in the thickness direction of the substrate 10 , the sacrificial layer 20 , and the semiconductor layer 30 , and the vertical axis represents the Al composition ratio x.

[0071] like Figure 5A As shown, in the first embodiment, the sacrificial layer 20 is composed of three layers, the Al composition ratio x of the central layer 20B is 1, and the Al composition ratios x of the layers 20A and 20C on both sides are the same and less than 1.

[0072] Figure 5B In the variation shown, the Al composition ratio x of the central layer of the sacrificial layer 20 is also 1. However, the Al composition ratio x of the layer on the substrate 10 side is lower than the Al composition ratio of the layer on the semiconductor layer 30 side. By making it such a structure, the lattice mismatch at the interface between the substrate 10 and the sacrificial layer 20 is reduced, and the effect of suppressing the reduction of the crystal quality of the sacrificial layer 20 and the semiconductor layer 30 is improved.

[0073] In addition, since the Al composition ratio x of the layer in contact with the semiconductor layer 30 in the sacrificial layer 20 is higher than the Al composition ratio of the layer in contact with the substrate 10, the etching rate of the layer in contact with the semiconductor layer 30 in the sacrificial layer 20 is faster than the etching rate of the layer in contact with the substrate 10. Figure 3C The portion 20F of the sacrificial layer 20 on the semiconductor layer 30 side is shown to be smaller than the portion 20E on the substrate side. As a result, after the substrate 10 is separated from the semiconductor layer 30, the remaining portion 20F of the sacrificial layer 20 on the semiconductor layer 30 side can be removed in a shorter time.

[0074] Figure 5C In the variation shown, two layers with different Al composition ratios x whose Al composition ratios x are less than 1 are arranged between the layer with an Al composition ratio x of 1 and the substrate 10. The Al composition ratio x of the layer on the substrate 10 side of the two layers is relatively low. By increasing the Al composition ratio stepwise from the substrate 10 toward the layer with an Al composition ratio x of 1, the lattice constant of the portion of the sacrificial layer 20 in contact with the substrate 10 can be made close to the lattice constant of the substrate 10 while suppressing a sharp change in the lattice constant. Thus, the reduction in crystal quality due to lattice mismatch can be further suppressed.

[0075] Figure 5DIn the modification shown, the Al composition ratio x is 1 at two locations in the thickness direction of the sacrificial layer 20 . Figure 5E In the variation shown, the Al composition ratio x is 1 at three locations in the thickness direction of the sacrificial layer 20. In the layer having the Al composition ratio x of 1, which has the largest lattice mismatch with respect to the substrate 10, relatively large strain exists inside due to the lattice mismatch. If the thickness of each layer having the Al composition ratio of 1 is increased, dislocation occurs to relax the strain.

[0076] In the thickness direction of the sacrificial layer 20, by making the Al composition ratio x equal to 1 at multiple locations, the sacrificial layer 20 can be thickened without relieving strain (without causing dislocation) in the sacrificial layer 20. If the sacrificial layer 20 is thickened, Figure 2C In the etching step shown, the etchant easily intrudes between the substrate 10 and the semiconductor layer 30 , and the stability of the etching step of the sacrificial layer 20 can be improved.

[0077] The positions where the Al composition ratio x is 1 may be arranged at not only two positions or three positions in the thickness direction of the sacrificial layer 20 , but also at four or more positions.

[0078] in addition, Figure 5D In the example of changes shown, Figure 5B Similarly to the modification example shown in FIG. 1 , the Al composition ratio x of the layer in contact with the substrate 10 is made lower than the Al composition ratio x of the layer in contact with the semiconductor layer 30. Figure 5B The modified example can also alleviate the lattice mismatch at the interface between the substrate 10 and the sacrificial layer 20. It should be noted that Figure 5E In the modification shown, the Al composition ratio x of the layer in contact with the substrate 10 may be lower than the Al composition ratio x of the layer in contact with the semiconductor layer 30 .

[0079] Fig. 5F In the variation shown in FIG. 1 , the Al composition ratio x in the sacrificial layer 20 changes continuously in the thickness direction. Figure 5D Similarly, the Al composition ratio x is 1 at two positions in the thickness direction of the sacrificial layer 20. If the Al composition ratio x changes discontinuously, stress is easily concentrated on the interface of the layer where the Al composition ratio x is discontinuous. By changing the Al composition ratio x continuously, the localization of stress can be suppressed. As a result, the crystal quality of the sacrificial layer 20 can be improved.

[0080] And, with Figure 5D In the modified example shown, the Al composition ratio x of the sacrificial layer 20 at the interface with the substrate 10 is similarly lower than the Al composition ratio x of the sacrificial layer 20 at the interface with the semiconductor layer 30. This can suppress lattice mismatch and improve the crystal quality of the semiconductor layer 30.

[0081] Figure 5A The first embodiment shown and Figure 5B to Figure 5F In the modification of the first embodiment shown in the figure, the Al composition ratio x at the position where the etching rate is to be relatively fast is set to 1, but the Al composition ratio does not necessarily have to be 1. The Al composition ratio x may be set to be a maximum value at at least one location in the thickness direction of the sacrificial layer 20 other than the interface with the substrate 10 and the interface with the semiconductor layer 30.

[0082] Figure 2C to Figure 3D In the process of etching the sacrificial layer 20, in order to reduce the etching damage to the semiconductor layer 30, it is preferred to make the ratio of the etching rate of the sacrificial layer 20 to the etching rate of the semiconductor layer 30 when the etchant used in the process of etching the sacrificial layer 20 is used (etching selectivity) larger. For example, in the case where the semiconductor layer 30 and the substrate 10 are formed of GaAs, it is preferred to make the Al composition ratio x at the point where the Al composition ratio x in the sacrificial layer 20 is a maximum value be greater than 0.5, and more preferably greater than 0.7. When the Al composition ratio x at the point where the Al composition ratio x in the sacrificial layer 20 is a maximum value is less than 0.5, the time required for etching to separate the semiconductor layer 30 from the substrate 10 becomes longer, and as a result, the damage to the semiconductor layer 30 and the substrate 10 becomes greater.

[0083] Next, refer to Figure 6A to Figure 6F The following describes other variations of the first embodiment with reference to the drawings.

[0084] In the first embodiment, as the substrate 10 ( Figure 1A ) uses a GaAs substrate, but a substrate formed of other III-V compound semiconductors, such as an InP substrate, can be used. When an InP substrate is used, an InP substrate can be used as the sacrificial layer 20. y Ga 1－y As

[0085] Figure 6A to Figure 6F FIG. 1 is a diagram showing the distribution of the In composition ratio y in the thickness direction of the sacrificial layer 20 of the epitaxial growth substrate 40 according to other modified examples of the first embodiment. In all examples, an InP substrate is used as the substrate 10, and the sacrificial layer 20 is composed of In y Ga 1－y As formed. Figure 6A to Figure 6F The distribution of the In composition ratio y in the sacrificial layer 20 shown in the figure is respectively Figure 5A to Figure 5F The distribution of the Al composition ratio x in the sacrificial layer 20 shown in the graph of FIG. 3 is the same. The semiconductor layer 30 includes a layer formed of a semiconductor material such as InP that is lattice-matched to the InP substrate.

[0086] The etching rate of InGaAs with an acidic etchant or an alkaline etchant increases as the In composition ratio y increases. Therefore, by making the distribution of the In composition ratio y in the sacrificial layer 20 Figure 6A to Figure 6F The distribution of the graph is represented by Figure 5A to Figure 5F The same excellent effect is achieved in the first embodiment and the modified example shown in the figure. In order to preferentially etch and remove the sacrificial layer 20 relative to the semiconductor layer 30 and the substrate 10, it is preferred that the In composition ratio y is 0.5 or more. For example, when the semiconductor layer 30 and the substrate 10 are formed of InP, it is preferred that the In composition ratio y at the position where the In composition ratio y in the sacrificial layer 20 has a maximum value is 0.5 or more, and more preferably 0.7 or more.

[0087] As another modification, the sacrificial layer 20 may be made of Al x In y Ga 1－x－y In this case, the substrate 10 may be a GaAs substrate or an InP substrate. The distribution of the total composition ratio x+y of Al and In in the sacrificial layer 20 may be set to be equal to Figure 5A to Figure 5F The distribution of the Al composition ratio x shown in FIG. 1 is similar to that of FIG. 1. Alternatively, an InP substrate or a GaAs substrate may be used as the substrate 10 and InAlP may be used as the sacrificial layer 20.

[0088] [Second embodiment]

[0089] Next, refer to Figure 7 The epitaxial growth substrate of the second embodiment is described. Figure 1A to Figure 3D The following is an explanation of the common structure of the epitaxial growth substrate 40 of the first embodiment already explained in the figure.

[0090] Figure 7 4 is a cross-sectional view of an epitaxial growth substrate 40 according to the second embodiment. In the second embodiment, as in the first embodiment, the epitaxial growth substrate 40 includes a substrate 10, a sacrificial layer 20, and a semiconductor layer 30. In the second embodiment, the semiconductor layer 30 includes a barrier layer 30S epitaxially grown from the sacrificial layer 20 and a device layer 30D epitaxially grown from the barrier layer 30S.

[0091] The device layer 30D includes a layer formed of a compound semiconductor lattice-matched with the substrate 10, for example, a layer formed of the same compound semiconductor as the substrate 10. The barrier layer 30S is formed during the etching process of the sacrificial layer 20 ( Figure 2C , Figure 3A , Figure 3C , Figure 3D ), has the function of protecting the device layer 30D from the etchant. Therefore, in the wet etching using the etchant for etching the sacrificial layer 20, the etching rate of the barrier layer 30S is slower than the etching rate of the layer at the interface of the barrier layer 30S with the device layer 30D.

[0092] As an example, when the sacrificial layer 20 is formed of AlGaAs or AlAs, and the device layer 30D includes an AlGaAs layer, an AlGaInP layer, a GaInP layer, an AlInP layer, a GaInAs layer, etc. can be used as the barrier layer 30S. The lattice constant of the barrier layer 30S can be substantially matched with the lattice constant of the substrate 10 composed of GaAs by adjusting the composition ratio of the III group element of the mixed crystal semiconductor constituting the barrier layer 30S. It should be noted that even in the case where the lattice constant is completely mismatched, the generation of dislocations in the barrier layer 30S can be suppressed by making the barrier layer 30S thin enough not to produce a degree of relaxation strain. In addition, the impurity concentration dependence of the etching rate can be utilized by making the impurity concentration of the barrier layer 30S and the device layer 30D different.

[0093] [Third embodiment]

[0094] Next, refer to Figures 8A to 9B The figure illustrates a method for manufacturing a semiconductor device using an epitaxial growth substrate based on the third embodiment. Figures 8A to 9B FIG. 1 is a cross-sectional view of a semiconductor device of the third embodiment at an intermediate stage in the manufacture of the semiconductor device.

[0095] like Fig. 8A As shown, an epitaxial growth substrate 40 based on the first embodiment is prepared. The epitaxial growth substrate 40 includes a substrate 10, a sacrificial layer 20, and a semiconductor layer 30 composed of n-type GaAs. A portion of the semiconductor layer 30 is made high-impedance to form an element isolation region 30I. The element isolation region 30I is divided into a plurality of active regions 30N composed of n-type GaAs that are electrically isolated from each other.

[0096] Semiconductor elements such as transistors 31 and diodes 32 are formed on each of the plurality of active regions 30N of the semiconductor layer 30. The transistor 31 is, for example, a heterojunction bipolar transistor including a collector layer formed of n-type GaAs, a base layer formed of p-type GaAs, and an emitter layer formed of n-type InGaP. The diode 32 includes, for example, the transistor 31 and a cathode layer formed of n-type GaAs and an anode layer formed of p-type GaAs formed in the same process as the base layer. The active region 30N is used as a current path for supplying carriers to the collector layer of the transistor 31 and the cathode layer of the diode 32.

[0097] An insulating film 33 covering the transistor 31 and the diode 32 is formed on the semiconductor layer 30. The insulating film 33 is made of an inorganic insulating material such as silicon nitride, an insulating resin, or the like.

[0098] like Figure 8BAs shown, the epitaxial growth substrate 40 is bonded to the dummy substrate 50 via the adhesive layer 51 in a state where the surface on which the semiconductor layer 30 is formed faces the dummy substrate 50. More specifically, the insulating film 33 and the dummy substrate 50 are bonded.

[0099] like Fig. 9A As shown, the epitaxial growth substrate 40 and the insulating film 33 are separated into a plurality of small pieces by cutting the epitaxial growth substrate 40 and the insulating film 33 . Fig. 9A Only a small piece is shown. Fig. 9B As shown, the sacrificial layer 20 of the epitaxial growth substrate 40 is removed by etching, thereby separating the substrate 10 from the semiconductor layer 30. Through the steps up to this point, a plurality of thin electronic circuit chips including transistors 31 and diodes 32 can be obtained.

[0100] As an example, by separating these electronic circuit chips from the dummy substrate 50 and bonding the semiconductor layer 30 to another electronic circuit chip including a silicon substrate, electronic circuit elements including silicon-based electronic circuit elements and compound semiconductor-based electronic circuit elements can be manufactured.

[0101] Next, the excellent effects of the third embodiment will be described.

[0102] In the third embodiment, similarly to the first embodiment, Fig. 9B In the step of separating the semiconductor layer 30 from the substrate 10 shown in FIG. 1 , the generation of cracks in the semiconductor layer 30 can be suppressed.

[0103] The heterojunction transistor 31 uses an n-type compound semiconductor as a collector layer. In order to form a current path in the semiconductor layer 30 to supply carriers to the collector layer, the semiconductor layer 30 is preferably an n-type compound semiconductor layer. Fig. 9B In the step of etching the sacrificial layer 20 shown in the figure, the transistor 31 and the diode 32 are covered by the insulating film 33, so the etchant used to etch the sacrificial layer 20 is not exposed. Therefore, the transistor 31 and the diode 32 can include a compound semiconductor layer whose etching selectivity with the sacrificial layer 20 is not very large.

[0104] The above-mentioned embodiments are illustrative, and partial replacement or combination of the structures represented by different embodiments can be performed. The same effect obtained by the same structure of multiple embodiments will not be described in sequence with each embodiment. Moreover, the present invention is not limited to the above-mentioned embodiments. It is obvious to those skilled in the art that various changes, improvements, combinations, etc. can be made.

[0105] Based on the above-described embodiments described in this specification, the following inventions are disclosed.

[0106] <1>

[0107] An epitaxial growth substrate, comprising:

[0108] A substrate formed of a group III-V compound semiconductor containing Ga or In as a group III element,

[0109] a sacrificial layer epitaxially grown on the substrate, and

[0110] A semiconductor layer epitaxially grown on the sacrificial layer;

[0111] The sacrificial layer includes a layer formed of a mixed crystal semiconductor containing Al or In as a Group III element, and the composition ratio of Al or In varies in the thickness direction. The position where the composition ratio of Al or In reaches a maximum value is located inside the sacrificial layer other than the lower and upper surfaces.

[0112] <2>

[0113] According to the epitaxial growth substrate described in <1>, wherein the layer formed by the mixed crystal semiconductor included in the sacrificial layer contains Ga as a group III element in addition to Al or In, and contains at least one of As and P as a group V element, and the maximum value of the composition ratio of Al or In is greater than 0.5.

[0114] <3>

[0115] The epitaxial growth substrate according to <1> or <2>, wherein the composition ratio of Al or In in a portion of the sacrificial layer in contact with the substrate is smaller than the composition ratio of Al or In in a portion in contact with the semiconductor layer.

[0116] <4>

[0117] The epitaxial growth substrate according to any one of <1> to <3>, wherein a composition ratio of Al or In takes a local maximum value at a plurality of locations in a thickness direction of the sacrificial layer.

[0118] <5>

[0119] The epitaxial growth substrate according to any one of <1> to <4>, wherein the semiconductor layer has a thickness thinner than that of the substrate and thicker than that of the sacrificial layer.

[0120] <6>

[0121] The epitaxial growth substrate according to any one of <1> to <5>, wherein the substrate is formed of GaAs or InP, and the semiconductor layer includes a layer formed of a semiconductor lattice-matched to the substrate.

[0122] <7>

[0123] The epitaxial growth substrate according to any one of <1> to <6>, wherein the semiconductor layer includes a barrier layer in contact with the sacrificial layer, and an etching rate of the barrier layer is slower than an etching rate of the sacrificial layer in wet etching using an acidic etchant or an alkaline etchant.

[0124] <8>

[0125] The epitaxial growth substrate according to any one of <1> to <7>, wherein the semiconductor layer includes a layer formed of an N-type semiconductor.

[0126] <9>

[0127] According to any one of <1> to <8>, in the wet etching using an acidic etchant or an alkaline etchant, the portion where the etching rate of the sacrificial layer is the highest is located inside the sacrificial layer other than the lower surface and the upper surface.

[0128] <10>

[0129] A method for manufacturing a semiconductor device, wherein a semiconductor element of at least one of a transistor and a diode is formed in the semiconductor layer of the epitaxial growth substrate according to any one of <1> to <9>,

[0130] The sacrificial layer is removed by etching to separate the substrate from the semiconductor layer.

Claims

1. An epitaxial growth substrate, comprising: A substrate formed of a group III-V compound semiconductor containing Ga or In as a group III element, a sacrificial layer epitaxially grown on the substrate, and A semiconductor layer epitaxially grown on the sacrificial layer; The sacrificial layer includes a layer formed of a mixed crystal semiconductor containing Al or In as a Group III element, and the composition ratio of Al or In varies in the thickness direction. The position where the composition ratio of Al or In reaches a maximum value is located inside the sacrificial layer other than the lower surface and the upper surface.

2. The epitaxial growth substrate according to claim 1, wherein: The layer formed of the mixed crystal semiconductor included in the sacrificial layer contains Ga as a group III element in addition to Al or In, and contains at least one of As and P as a group V element, and the maximum value of the composition ratio of Al or In is greater than or equal to 0.

5.

3. The epitaxial growth substrate according to claim 1 or 2, wherein: In the sacrificial layer, a composition ratio of Al or In in a portion in contact with the substrate is smaller than a composition ratio of Al or In in a portion in contact with the semiconductor layer.

4. The epitaxial growth substrate according to claim 1 or 2, wherein: The composition ratio of Al or In takes a maximum value at a plurality of positions in the thickness direction of the sacrificial layer.

5. The epitaxial growth substrate according to claim 1 or 2, wherein: The thickness of the semiconductor layer is thinner than the thickness of the substrate and thicker than the thickness of the sacrificial layer.

6. The epitaxial growth substrate according to claim 1 or 2, wherein: The substrate is formed of GaAs or InP, and the semiconductor layer includes a layer formed of a semiconductor lattice-matched to the substrate.

7. The epitaxial growth substrate according to claim 1 or 2, wherein: The semiconductor layer includes a barrier layer in contact with the sacrificial layer, and in wet etching using an acidic etchant or an alkaline etchant, an etching rate of the barrier layer is slower than an etching rate of the sacrificial layer.

8. The epitaxial growth substrate according to claim 1 or 2, wherein: The semiconductor layer includes a layer formed of an N-type semiconductor.

9. The epitaxial growth substrate according to claim 1 or 2, wherein: In wet etching using an acidic etchant or an alkaline etchant, a portion where the etching rate of the sacrificial layer is the highest is located inside the sacrificial layer other than the lower surface and the upper surface.

10. A method for manufacturing a semiconductor device, comprising forming a semiconductor element of at least one of a transistor and a diode in the semiconductor layer of the epitaxial growth substrate according to claim 1 or 2, The sacrificial layer is removed by etching to separate the substrate from the semiconductor layer.

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