Semiconductor structure etching method, semiconductor device and electronic equipment

Abstract

The invention provides an etching method of a semiconductor structure, a semiconductor device and electronic equipment, and the etching method comprises the steps: carrying out the etching of an anti-reflection coating and a hard mask layer at an initial etching stage through employing a lower electrode power of 0-400W until an interlayer dielectric layer is exposed; in the main etching stage, the hard mask layer which is not etched is used as a mask, and the interlayer dielectric layer is etched by adopting the lower electrode power of 2500W-3500W until the barrier layer is exposed; and in the over-etching stage, the barrier layer is etched by adopting the lower electrode power of 50-800W until the substrate is exposed, and the contact hole is obtained. Because the power of the lower electrode in the main etching stage is improved, the plasma in the etching process can vertically act on the interlayer dielectric layer without bombarding the side wall of the contact hole, and the generation of the concave morphology of the side wall is avoided, so that the performance of the semiconductor device, especially the BCD device, is improved, and the process window in the main etching stage is widened.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device manufacturing, and in particular to an etching method for a semiconductor structure, a semiconductor device and an electronic device. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a monolithic integration process technology that can produce Bipolar (bipolar transistor), CMOS (complementary metal oxide semiconductor) and DMOS (double diffused metal oxide semiconductor) devices on the same chip, where contact holes are used to connect semiconductor devices at different levels, such as transistors and metal interconnect layers. In some special application scenarios, such as the SRAM (static random access memory) platform, due to application requirements, its exposure rate is smaller than other BCD products, and the critical size of the open area is smaller. When the contact hole is etched with a conventional etching recipe, a concave morphology will be caused in the interlayer dielectric layer, and the presence of the concave morphology will affect the subsequent contact hole filling process, resulting in the presence of voids, which will lead to abnormal electrical parameters of the product.

[0003] In view of the above problems, the prior art reduces the power of the lower electrode during the etching of the interlayer dielectric layer or reduces the concentration of the etching auxiliary gas O2, so that the sidewall is not over-etched to form a concave morphology. However, due to the small etching diameter, the byproducts are difficult to extract, and the reduction of the power of the lower electrode and the concentration of O2 makes the byproducts more likely to accumulate, which will cause the side of the contact hole to become a tapered profile, and even cause the etching to stop. Therefore, an etching method for a semiconductor structure is urgently needed to solve the above problems. Summary of the invention

[0004] In order to solve the above technical problems, the present application proposes an etching method for a semiconductor structure, a semiconductor device and an electronic device, which not only increases the power of the lower electrode during the etching of the interlayer dielectric layer, so that the plasma during the etching process can act vertically on the interlayer dielectric layer without bombarding the side wall of the contact hole, thereby effectively controlling the morphology of the side wall, avoiding the generation of a concave morphology and avoiding the degradation of semiconductor device performance caused by the concave morphology; but also avoids the generation of by-products by using amorphous carbon as a hard mask for etching the interlayer dielectric layer; the power of the lower electrode during the etching of the interlayer dielectric layer of the present application also widens the process window for etching the interlayer dielectric layer.

[0005] On the one hand, an embodiment of the present application provides a method for etching a semiconductor structure, the etching method comprising:

[0006] Providing a semiconductor structure after photolithography; the semiconductor structure after photolithography comprises a substrate, a barrier layer, an interlayer dielectric layer, a hard mask layer and an anti-reflective coating layer stacked in sequence from bottom to top;

[0007] In the initial etching stage, the anti-reflective coating and the hard mask layer are sequentially etched until the interlayer dielectric layer is exposed; the lower electrode power corresponding to the initial etching stage is 0-400W;

[0008] In the main etching stage, the interlayer dielectric layer is etched using the unetched hard mask layer as a mask until the barrier layer is exposed; the lower electrode power corresponding to the main etching stage is 2500W-3500W;

[0009] In the over-etching stage, the barrier layer is etched until the substrate is exposed to obtain a contact hole; the lower electrode power corresponding to the over-etching stage is 50W-800W.

[0010] Furthermore, the critical dimension of the contact hole is less than 90 nm; the thickness of the interlayer dielectric layer is greater than 400 nm; the sum of the thicknesses of the substrate layer and the barrier layer is less than 120 nm; and the aperture ratio of the semiconductor structure after photolithography is less than 3%.

[0011] Further, the hard mask layer is amorphous carbon; in the main etching stage, the interlayer dielectric layer is etched using the unetched hard mask layer as a mask until the barrier layer is exposed, comprising:

[0012] Determining the main etching time based on the etching conditions corresponding to the main etching stage and the thickness of the interlayer dielectric layer;

[0013] According to the etching conditions corresponding to the main etching stage and the main etching time, the interlayer dielectric layer is etched using the amorphous carbon as a mask until the barrier layer is exposed.

[0014] Furthermore, the material of the interlayer dielectric layer includes SiO2; the material of the substrate includes Si;

[0015] The etching conditions corresponding to the main etching stage include: the chamber pressure is 20mt-25mt, the upper electrode power is 200W-800W, the flow ratio of the main etching gas and the auxiliary gas is less than 1.8:1, the flow rate of the main etching gas is ≤25sccm, and the flow rate of the protective gas is 350sccm-450sccm;

[0016] Wherein, the main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar.

[0017] Further, the etching conditions corresponding to the initial etching stage include: the chamber pressure is 10mt-80mt, the upper electrode power is 200W-900W, and the flow ratio of the first main etching gas to the auxiliary gas is>3:1; wherein the flow rate of the first main etching gas is 80sccm-200sccm;

[0018] Wherein, the first main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar.

[0019] Further, the etching conditions corresponding to the over-etching stage include: the chamber pressure is 20mt-70mt, the upper electrode power is 0-300W, the flow ratio of the second main etching gas and the auxiliary gas is less than 1:1, and the flow rate of the second main etching gas is 10sccm-50sccm, and the flow rate of the protective gas is 200sccm-600sccm;

[0020] Wherein, the second main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar.

[0021] Further, the anti-reflective coating comprises a bottom anti-reflective coating, an oxide layer and a top anti-reflective coating stacked in sequence from bottom to top; the photoresist layer after photolithography is arranged on the upper surface of the top anti-reflective coating; the initial etching stage comprises an anti-reflective coating etching stage and a hard mask layer etching stage; in the initial etching stage, the anti-reflective coating and the hard mask layer are sequentially etched until the interlayer dielectric layer is exposed, comprising:

[0022] The sum of the thicknesses of the top anti-reflective coating, the oxide layer and the bottom anti-reflective coating is determined as a first thickness; based on the etching conditions corresponding to the anti-reflective coating etching stage and the first thickness, the anti-reflective coating etching time is determined; and the top anti-reflective coating, the oxide layer and the bottom anti-reflective coating are etched using the photoresist layer after photolithography as a mask according to the etching conditions corresponding to the anti-reflective coating etching stage and the anti-reflective coating etching time, until the surface of the hard mask layer is exposed;

[0023] The hard mask layer etching time is determined based on the etching conditions corresponding to the hard mask layer etching stage and the thickness of the hard mask layer; the hard mask layer is etched according to the etching conditions corresponding to the hard mask layer etching stage and the hard mask layer etching time until the interlayer dielectric layer is exposed.

[0024] Further, the barrier layer includes a silicide barrier layer and a first barrier layer, the silicide barrier layer is arranged on the upper surface of the substrate layer, and the first barrier layer is arranged on the upper surface of the silicide barrier layer; therefore, the over-etching stage includes a silicide barrier layer etching stage and a first barrier layer etching stage;

[0025] The step of etching the barrier layer in the over-etching stage until the substrate is exposed to obtain a contact hole comprises:

[0026] Determining a first barrier layer etching time based on the etching conditions corresponding to the first barrier layer etching stage and the thickness of the first barrier layer; etching the first barrier layer according to the etching conditions corresponding to the first barrier layer etching stage and the first barrier layer etching time until the silicide barrier layer is exposed;

[0027] Determine the silicide barrier layer etching time according to the etching conditions corresponding to the silicide barrier layer etching stage and the thickness of the silicide barrier layer; and etch the silicide barrier layer according to the etching conditions corresponding to the silicide barrier layer etching stage and the silicide barrier layer etching time until the substrate is exposed to obtain the contact hole.

[0028] On the other hand, an embodiment of the present application further provides a semiconductor device, which is prepared by the above-mentioned etching method of the semiconductor structure.

[0029] On the other hand, an embodiment of the present application further provides an electronic device, comprising the above-mentioned semiconductor device.

[0030] The present application provides a semiconductor structure etching method, a semiconductor device and an electronic device. Compared with the prior art, the present invention has the following beneficial technical effects:

[0031] In the etching method of the semiconductor structure provided by the present application, since the power of the lower electrode in the main etching process (i.e., the interlayer dielectric layer etching process) is increased, the plasma in the etching process can act vertically on the interlayer dielectric layer, and does not bombard the side wall of the contact hole, which is beneficial to controlling the morphology of the contact hole. By using amorphous carbon as a hard mask for etching the interlayer dielectric layer, the generation of by-products is avoided, thereby avoiding the generation of a concave morphology on the side wall of the contact hole and avoiding the degradation of semiconductor device performance caused by the concave morphology, improving the electrical parameters of the product, and thus improving the performance of semiconductor devices, especially BCD devices; finally, the present application increases the power of the lower electrode in the interlayer dielectric layer etching process and widens the process window for etching the interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 This is a schematic diagram of the principle of etching a BCD product with a low exposure rate using a conventional etching method provided in an embodiment of the present application;

[0034] Figure 2 It is a schematic flow chart of a semiconductor structure etching method provided in an embodiment of the present application;

[0035] Figure 3 is a cross-sectional view of a semiconductor structure after photolithography provided in an embodiment of the present application;

[0036] Figure 4 This is a schematic diagram of the process structure of the initial etching stage provided in an embodiment of the present application;

[0037] Figure 5 is a cross-sectional view of a semiconductor structure after a main etching stage provided by an embodiment of the present application;

[0038] Figure 6 It is a schematic diagram of etching principle in a main etching stage provided in an embodiment of the present application;

[0039] Figure 7 It is a structural schematic diagram of an etching process in an over-etching stage provided in an embodiment of the present application;

[0040] Figure 8 is a cross-sectional view of another semiconductor structure after photolithography provided in an embodiment of the present application;

[0041] Fig. 9 is a cross-sectional view of an etching process of an anti-reflective coating etching stage provided in an embodiment of the present application;

[0042] Fig.10 It is a structural schematic diagram of an etching process in a hard mask layer etching stage provided in an embodiment of the present application;

[0043] Fig.11 It is a structural schematic diagram of an etching process of a first barrier layer etching stage provided in an embodiment of the present application;

[0044] Fig.12 It is a structural schematic diagram of an etching process in a silicide barrier layer etching stage provided in an embodiment of the present application;

[0045] Fig.13It is a structural schematic diagram of an etching process of a semiconductor structure provided in an embodiment of the present application;

[0046] Fig.14 It is a structural schematic diagram of an etching process of a semiconductor structure in the prior art provided by an embodiment of the present application;

[0047] Fig.15 is a semiconductor structure slice structure diagram obtained in Example 1;

[0048] Fig.16 This is a semiconductor structure slice structure diagram obtained in Example 1.

[0049] The following is an explanation of the reference numerals:

[0050] 10-substrate;

[0051] 20-blocking layer; 201-silicide blocking layer; 202-first blocking layer;

[0052] 30-interlayer dielectric layer;

[0053] 40-hard mask layer;

[0054] 50-anti-reflective coating; 51-bottom anti-reflective coating; 52-top anti-oxidation layer;

[0055] 60- oxide layer;

[0056] 70- photoresist layer;

[0057] 80-contact hole;

[0058] 90- Etched window. DETAILED DESCRIPTION

[0059] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0060] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solution of this party, and the component layout form may also be more complicated.

[0061] In the BCD (Bipolar-CMOS-DMOS) platform, contact holes are used to connect semiconductor devices of different levels, such as transistors and metal interconnect layers. In the prior art, some BCD (Bipolar-CMOS-DMOS) platform products, such as SRAM (static random access memory), have relatively fast storage and reading speeds and are suitable for data caching. During the etching process of the contact holes, the exposure rate and the CD (critical dimension) of the open area are smaller than other standard BCD products or conventional BCD products, resulting in the use of conventional etching recipes to etch the interlayer dielectric layer. Figure 1 As shown, due to the problem of plasma ion bombardment direction, the etching process is prone to produce by-products. Therefore, a bowing profile will be formed on the sidewall of the interlayer dielectric layer. The bowing profile will affect the subsequent filling process of the contact hole, and may cause the formation of holes, thereby causing abnormal electrical parameters. In addition, the methods for improving the bowing profile of the interlayer dielectric layer in the prior art are prone to cause by-products, which can easily lead to tapered contact holes or etching stop.

[0062] Based on this, Figure 2 is a schematic diagram of a semiconductor structure etching method provided in an embodiment of the present application. Figure 2 An etching method for a semiconductor structure provided in an embodiment of the present application is described.

[0063] S10: providing a semiconductor structure after photolithography; the semiconductor structure after photolithography comprises a substrate 10, a barrier layer 20, an interlayer dielectric layer 30, a hard mask layer 40 and an anti-reflective coating 50 which are sequentially stacked from bottom to top.

[0064] As an example, Figure 3 The cross-sectional view of the semiconductor structure after photolithography provided by the embodiment of the present application is shown. Figure 3 As shown, the semiconductor structure after photolithography includes a substrate 10, a barrier layer 20, an interlayer dielectric layer 30, a hard mask layer 40 and an anti-reflective coating 50 which are stacked in sequence from bottom to top.

[0065] The semiconductor structure after photolithography refers to the semiconductor structure having a photoresist layer 70 after photolithography on the upper surface, which is also called a photoresist layer. The photoresist layer 70 after photolithography is a patterned photoresist layer 70, which has been formed into a desired patterned structure through a development step. This patterned photoresist layer plays a protective role in the subsequent etching step, ensuring that only the area not covered by the photoresist is etched, thereby accurately replicating the desired pattern on the substrate. Figure 3As shown, the semiconductor structure after photolithography includes an etching window 90 . The etching window 90 defines the position and size of the contact hole 80 . The etching window 90 exposes the upper surface of the anti-reflective coating 50 .

[0066] The substrate 10 refers to the bottom material on which other material layers are deposited. In the embodiment of the present application, the substrate 10 is an epitaxial substrate 10 having an epitaxial layer function. As an example, the material of the substrate 10 can be silicon, silicon carbide, diamond, gallium nitride, gallium arsenide, zinc oxide, diamond, aluminum oxide, etc., preferably Si.

[0067] The main function of the barrier layer 20 is to prevent metal atoms in the semiconductor device from diffusing from the metal interconnect layer to the interlayer dielectric layer 30 to avoid leakage; and to improve the adhesion between the metal and dielectric layers, reduce contact resistance and stress, protect semiconductor components from damage in subsequent processes, prevent unwanted chemical reactions, and keep the interface clear and stable.

[0068] The interlayer dielectric layer 30 is an insulating material used to isolate different metal layers in the semiconductor structure, and can prevent mutual diffusion between different materials, which is crucial to maintaining the stability and performance of the device. The material of the interlayer dielectric layer 30 may include silicon dioxide (SiO2), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), polymer materials, silicon nitride (Si3N4), aerogels, etc. As an example, SiO2 is preferred.

[0069] The hard mask layer 40 is used as a protective layer during the etching process of the interlayer dielectric layer 30 to prevent the unneeded part of the interlayer dielectric layer 30 from being damaged or contaminated. It is also used as a template in the manufacturing process to define and guide the shape and position of the interlayer dielectric layer 30. As an example, the criteria for selecting the hard mask layer 40 are that it is hard in texture and the process recipe for etching the interlayer dielectric layer 30 has a high selectivity for it, which can reduce the generation of by-products in the main etching stage. Specifically, if the by-products are not controlled, the accumulation of by-products may change the mean free path and kinetic energy of ions in the plasma during the main etching stage, thereby affecting the ion bombardment energy and direction, which will change the etching rate and etching morphology; and the accumulation of by-products may cause a reduction in the number of effective active particles in the plasma, thereby affecting the ion density; the by-products may affect the physical bombardment effect of the ions, for example, the by-products may form a layer of coverage on the surface of the etched material, reducing the direct contact between the ions and the material, affecting the etching efficiency; the accumulation of by-products may also affect the uniformity of the plasma, resulting in uneven distribution of ion density in the etching area, affecting the uniformity of etching. Therefore, the by-products will affect the etching morphology.

[0070] The function of the anti-reflection coating 50 is to reduce the reflection of light in the photoresist layer 70 during the etching process.

[0071] S30: In the initial etching stage, the anti-reflective coating 50 and the hard mask layer 40 are etched in sequence until the interlayer dielectric layer 30 is exposed; the lower electrode power corresponding to the initial etching stage is 0-400W.

[0072] As an example, Figure 4 The schematic diagram of the structure of the etching process in the initial etching stage provided by the embodiment of the present application is shown. The initial etching stage refers to the process of etching the semiconductor film layer above the interlayer dielectric layer 30 (ie, the anti-reflective coating 50 and the hard mask layer 40).

[0073] In the initial etching stage, dry etching is first used, and the photoresist layer 70 after photolithography is used as a mask to etch the anti-reflective coating 50 along the etching window 90 until the hard mask layer 40 is exposed; then, dry etching is used, and the photoresist layer 70 after photolithography is used as a mask to continue etching the hard mask layer 40 along the etching window 90 until the surface of the interlayer dielectric layer 30 is exposed, thereby forming a patterned hard mask layer 40. Figure 4 As shown, the photoresist layer 70 and the anti-reflective layer are gradually consumed during the etching process of the hard mask layer without the need for a separate removal step.

[0074] As an optional implementation method, the etching conditions corresponding to the initial etching stage include: the chamber pressure is 10mt-80mt, the upper electrode power (HF) is 200W-900W, the lower electrode power (LF) is 0-400W, and the flow ratio of the first main etching gas and the auxiliary gas is>3:1; wherein the flow rate of the first main etching gas is 80sccm-200sccm;

[0075] Among them, the first main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar.

[0076] It should be noted that, in the initial etching stage, the etching conditions for etching the anti-reflective coating 50 and the etching conditions for etching the hard mask layer 40 are both within the above ranges, but the specific etching conditions are generally different.

[0077] S50: In the main etching stage, the interlayer dielectric layer 30 is etched using the unetched hard mask layer 40 as a mask until the barrier layer 20 is exposed; the lower electrode power corresponding to the main etching stage is 2500W-3500W;

[0078] As an example, Figure 5The cross-sectional view of the semiconductor structure after the main etching stage is shown, and the etching stage refers to the stage of etching the interlayer dielectric layer 30, and the hard mask layer 40 that is not etched refers to the patterned hard mask layer 40. In the main etching stage, the patterned hard mask layer 40 is used as a mask, dry etching is adopted, and the power of the lower electrode in the dry etching is set to 2500W-3500W, and the area not covered by the hard mask layer 40 is etched along the etching window 90 until the surface of the barrier layer 20 is exposed.

[0079] The principle of dry etching is to use the active substances in the plasma to selectively etch the surface of the material in order to achieve the purpose of precise material removal. In dry etching, the upper electrode and the lower electrode work together to form a plasma for etching. The upper electrode is mainly responsible for generating plasma, while the lower electrode is in contact with the substrate to be etched. The ion bombardment energy is affected by controlling the RF power, that is, the power of the lower electrode affects the bombardment ability during the etching process. During the dry etching process, when the plasma contacts the wall of the dry etching chamber or the electrode, the transition zone formed between the two is called the sheath, and the sheath determines the energy distribution and angle distribution of the semiconductor to be etched during the etching process, directly the etching rate and the etching profile.

[0080] In summary, the main reasons for improving the concave morphology of the interlayer dielectric layer 30 during the etching process by increasing the power of the lower electrode in the main etching stage in the present application are:

[0081] (1) Increasing the power of the lower electrode in the main etching stage increases the mean free path of plasma particles, thereby enhancing the physical intensity of bombarding the interlayer dielectric layer 30.

[0082] (2) Increasing the power of the lower electrode in the main etching stage will not have a significant impact on the particle density in the sheath. When the power of the lower electrode is 2500-3500W, the particle density per unit volume in the sheath is still at a low level (less than 10 20 particles / m 3 ), and the hard mask layer 40 used in the etching process for etching the interlayer dielectric layer 30 is hard and the main process formula for etching the interlayer dielectric layer 30 has a high selectivity for it, so during the etching process, it will not react with the hard mask layer 40 to generate by-products, and because the exposure rate is low and the CD of the etched contact hole 80 is small, the by-products of the interlayer dielectric layer 30 during the etching process are also much lower than other BCD products, so almost no by-products are generated, thereby avoiding the influence of the by-products on the etching process.

[0083] Here, the advantages of controlling the particle density per unit volume in the sheath to a low level are explained:

[0084] (1) Improved etching uniformity: When the particle density per unit volume in the sheath is low, the uniformity of plasma etching can be improved. This is because lower particle density helps reduce the difference in etching rate in local areas, thereby achieving a more uniform etching effect across the entire wafer.

[0085] (2) Improve anisotropy: A lower particle density per unit volume in the sheath helps improve the anisotropy of the etching process. This is because the acceleration and bombardment angle distribution of ions in the sheath have a direct impact on the etching profile, and a lower particle density helps control these distributions, thereby achieving better anisotropic etching.

[0086] (3) Reduce the influence of dust particles: In the plasma sheath, the distribution of dust particles is affected by the particle density in the sheath. When the plasma density is high, the sheath is thinner and the influence of dust particles is relatively small, which helps to reduce the interference of dust on the plasma etching process.

[0087] (4) Reducing the pre-sheath transition zone: A lower sheath particle density can reduce the pre-sheath transition zone, allowing a pure positive ion sheath to form near the electrode, which helps improve the selectivity and directionality of plasma etching.

[0088] In summary, when the power of the lower electrode is increased to 2500-3500W, the particle density per unit volume in the sheath is small, and there is almost no interference from by-products during the etching process, such as Figure 6 As shown, the plasma is not easy to collide and change direction, and can act vertically on the interlayer dielectric layer 30 without bombarding the sidewall, thereby avoiding the generation of concave morphology.

[0089] As an optional implementation, the hard mask layer 40 is amorphous carbon; the specific process of the above main etching stage includes:

[0090] S51 : determining the main etching time based on the etching conditions corresponding to the main etching stage and the thickness of the interlayer dielectric layer 30 .

[0091] As an example, amorphous carbon (APF) is selected as the hard mask layer 40 because: APF is hard and the process formula for etching the interlayer dielectric layer 30 has a high selectivity for it, so during the etching process, it will not react with APF to generate by-products. In addition, because the exposure rate is low and the CD of the etched contact hole 80 is small, the by-products of the interlayer dielectric layer 30 during the etching process are also much lower than those of other BCD products.

[0092] As an example, during the main etching stage, the etching rate is first determined according to the etching conditions corresponding to the main etching stage, and then the main etching time is determined according to the etching rate, the thickness of the interlayer dielectric layer 30 and the etching area.

[0093] S53: etching the interlayer dielectric layer 30 using the amorphous carbon as a mask according to the etching conditions corresponding to the main etching stage and the main etching time, until the barrier layer 20 is exposed.

[0094] As an example, dry etching is used, and according to the etching conditions and main etching time corresponding to the main etching stage, the patterned APF40 is used as a mask to etch the interlayer dielectric layer 30 until the surface of the barrier layer 20 is exposed, wherein the main etching time is precisely controlled to prevent excessive etching. The dry etching process is an anisotropic etching process, which has good etching profile control, reduces damage to other film layer structures, and is conducive to making the morphology of the contact hole 80 meet the process requirements and improve the formation efficiency of the contact hole 80.

[0095] As an optional implementation, the material of the interlayer dielectric layer 30 includes SiO2; the material of the substrate 10 includes Si;

[0096] The etching conditions corresponding to the main etching stage include: the chamber pressure is 20mt-25mt, the upper electrode power is 200W-800W, the flow ratio of the main etching gas and the auxiliary gas is less than 1.8:1, the flow rate of the main etching gas is ≤25sccm, and the flow rate of the protective gas is 350sccm-450sccm;

[0097] The main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar. As an example, the main etching gas is preferably C4F8.

[0098] The embodiment of the present application increases the lower electrode power in the main etching stage and selects the hard mask layer 40 with amorphous carbon texture, which can not only strictly control the morphology of the contact hole 80 and prevent the formation of a concave morphology, but also improves the production efficiency and widens the process window for etching the interlayer dielectric layer 30 by increasing the lower electrode power.

[0099] S70: etching the barrier layer 20 in an over-etching stage until the substrate 10 is exposed to obtain a contact hole 80; the lower electrode power corresponding to the over-etching stage is 50W-800W.

[0100] As an example, Figure 7 A structural schematic diagram of the etching process in the over-etching stage is shown. In this step, the patterned hard mask layer 40 continues to be used as a mask to dry-etch the barrier layer 20, and the power of the lower electrode is reduced to 50W-800W. The etching time is precisely controlled and the etching is stopped when the surface of the substrate 10 is exposed, thereby obtaining a contact hole 80 that penetrates the hard mask layer 40, the interlayer dielectric layer 30 and the barrier layer 20 and exposes the surface of the substrate 10 layer.

[0101] Optionally, in order to subsequently fill the metal contact hole 80 and form a contact area in the substrate 10 layer, the etching time can be controlled in the over-etching stage so that part of the substrate 10 is etched along the contact hole 80, for example, the substrate layer is etched away by 10 nm.

[0102] As an optional implementation, the etching conditions corresponding to the over-etching stage include: the chamber pressure is 20mt-70mt, the upper electrode power (HF) is 0-300W, the flow ratio of the second main etching gas and the auxiliary gas is <1:1, and the flow rate of the second main etching gas is 10sccm-50sccm, and the flow rate of the protective gas is 200sccm-600sccm;

[0103] Wherein, the second main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar.

[0104] In the etching method of the semiconductor structure provided by the present application, since the power of the lower electrode in the main etching process (i.e., the etching process of the interlayer dielectric layer 30) is increased, the plasma in the etching process can act vertically on the interlayer dielectric layer 30, and does not bombard the side wall of the contact hole 80, which is beneficial to controlling the morphology of the contact hole 80, thereby avoiding the generation of a concave morphology on the side wall of the contact hole 80, and avoiding the degradation of the performance of the semiconductor device caused by the concave morphology, improving the electrical parameters of the semiconductor device, and thus improving the performance of the semiconductor device, especially the BCD device; in addition, by using amorphous carbon as a hard mask for etching the interlayer dielectric layer 30, the generation of by-products is avoided; finally, the present application increases the power of the lower electrode in the etching process of the interlayer dielectric layer 30, and also widens the process window for etching the interlayer dielectric layer 30.

[0105] The etching method provided in the embodiment of the present application is applicable to the etching process of the contact hole 80 of the BCD platform product, and is applicable to the critical dimension of the contact hole 80 being less than 90nm; the thickness of the interlayer dielectric layer 30 being greater than 400nm; the sum of the thickness of the substrate 10 layer and the barrier layer 20 being less than 120nm; and the aperture ratio of the semiconductor structure after photolithography being less than 3%.

[0106] As an example, the open ratio refers to the ratio of the actual light-transmitting area to the total area of ​​the pattern formed during the photolithography process. Specifically, the open ratio refers to the percentage of the opening (i.e., the etching window 90) formed on the photoresist layer to the entire photoresist layer area. The open ratio of the semiconductor structure after photolithography is less than <3% means that the area of ​​the etching window 90 on the photoresist layer 70 accounts for less than 3% of the area of ​​the photoresist layer 70.

[0107] As an optional implementation, Figure 8A cross-sectional view of another semiconductor structure after photolithography provided by an embodiment of the present application is shown; the anti-reflective coating comprises a bottom anti-reflective coating, an oxide layer and a top anti-reflective coating stacked in sequence from bottom to top; the photoresist layer after photolithography is arranged on the upper surface of the top anti-reflective coating; the top anti-reflective coating 51 bottom anti-reflective coating 52 bottom anti-reflective coating 52 top anti-reflective coating 51 barrier layer 20 comprises a silicide barrier layer 201 and a first barrier layer 202, the silicide barrier layer 201 is arranged on the upper surface of the substrate 10 layer, and the first barrier layer 202 is arranged on the upper surface of the silicide barrier layer 201.

[0108] As an example, a top anti-reflective coating 51 (BARC) is located on the upper surface of the oxide layer 60 and the lower surface of the photoresist layer 70 after photolithography. Its main function is to reduce the reflection of light inside the photoresist, thereby reducing the standing waves formed inside the photoresist layer 70.

[0109] The bottom anti-reflective coating 52 (DARC) is located on the upper surface of the hard mask layer 40 and the lower surface of the oxide layer 60 . Its function is to reduce the reflection of light inside the hard mask layer 40 during the etching process, thereby reducing the standing waves formed inside the hard mask layer 40 .

[0110] The oxide layer 60 is mainly used as a sacrificial layer and is etched away in the subsequent process to achieve a specific structure or pattern, that is, to achieve the etching of the contact hole 80. The silicide blocking layer 201 is also called a self-aligned silicide block layer 201 (SAB for short), and its main function is to prevent the formation of silicide in the area where metal silicide is not required to be formed. The self-aligned silicide blocking layer 201 can be made of a variety of materials, including silicon-rich oxide (SRO), tetraethyl orthosilicate (TEOS), silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or an oxide-nitride-oxide (ONO) structure including silicon oxide, silicon nitride and silicon oxide.

[0111] The first barrier layer 202 is a silicon nitride layer, and its main functions include blocking impurity diffusion, providing insulation, enhancing mechanical strength, improving corrosion resistance and oxidation resistance, maintaining insulation performance at high temperatures, blocking oxygen diffusion, and serving as an etching barrier layer 20.

[0112] The initial etching stage includes an anti-reflective coating etching stage (BARC STEP) and a hard mask layer etching stage (APF STEP); in the initial etching stage, the anti-reflective coating 50 and the hard mask layer 40 are etched in sequence until the interlayer dielectric layer 30 is exposed, including:

[0113] S31: Determine the sum of the thicknesses of the top anti-reflective coating 51, the oxide layer 60 and the bottom anti-reflective coating 52 as a first thickness; determine the anti-reflective coating etching time based on the etching conditions corresponding to the etching stage of the oxide layer 60 and the first thickness; and perform etching on the top anti-reflective coating 51, the oxide layer 60 and the bottom anti-reflective coating 52 according to the etching conditions and the anti-reflective coating etching time corresponding to the etching stage of the anti-reflective coating until the surface of the hard mask layer 40 is exposed.

[0114] Fig. 9 The cross-sectional view of the etching process of the anti-reflective coating etching stage of the embodiment of the present application is shown, please refer to Fig. 9 , the top anti-reflective coating 51 , the oxide layer 60 and the bottom anti-reflective coating 52 are etched along the etching window 90 to expose the surface of the hard mask layer 40 .

[0115] In this step, the anti-reflective coating etching time is first determined according to the sum of the thicknesses of the top anti-reflective coating 51, the oxide layer 60 and the bottom anti-reflective coating 52, i.e., the first thickness, and then according to the first thickness and the etching conditions and etching area corresponding to the oxide layer etching stage. According to the etching conditions and the anti-reflective coating etching time corresponding to the anti-reflective coating etching stage, the top anti-reflective coating 51, the oxide layer 60 and the bottom anti-reflective coating 52 are etched until the surface of the hard mask layer 40 is exposed.

[0116] As an example, the conditions corresponding to the anti-reflective coating etching stage are: the chamber pressure is 60mt-80mt, the upper electrode power is 300W-900W, the lower electrode power is 100W-300W, and the flow ratio of the main etching gas and the auxiliary gas is >3:1; wherein the flow rate of the main etching gas is 80sccm-160sccm; the main etching gas is preferably CF4, and the auxiliary gas is O2.

[0117] S33: Determine the hard mask layer etching time based on the etching conditions corresponding to the hard mask layer etching stage and the thickness of the hard mask layer 40; etch the hard mask layer 40 according to the etching conditions corresponding to the hard mask layer etching stage and the hard mask layer etching time until the top anti-reflective coating 51 and the bottom anti-reflective coating 52 of the interlayer dielectric layer 30 are exposed.

[0118] Fig.10 FIG. 4 is a cross-sectional view showing the etching process of the hard mask layer 40 according to an embodiment of the present application. Fig.10 , the hard mask layer 40 is etched along the etching window 90 to expose the surface of the interlayer dielectric layer 30 .

[0119] In the present application embodiment, Fig.10As shown, the photoresist layer 70, the top anti-reflective coating layer 51, the oxide layer 30 and the bottom anti-reflective coating layer 52 are consumed in the etching of the hard mask layer, thereby simplifying the process flow without adding a removal step.

[0120] As an example, the etching conditions corresponding to the etching stage of the hard mask layer 40 are: the chamber pressure is 10mt-30mt, the upper electrode power is 200W-400W, the lower electrode power is 0-100W, and the flow ratio of the main etching gas and the auxiliary gas is >3:1; wherein the flow rate of the main etching gas is 100sccm-200sccm; the main etching gas is preferably CO2, and the auxiliary gas is O2.

[0121] In an optional embodiment, the over-etching stage includes a silicide barrier layer 201 etching stage and a first barrier layer etching stage; in the above steps, the barrier layer 20 is etched in the over-etching stage until the substrate 10 is exposed to obtain the contact hole 80, including:

[0122] S71: Determine the first barrier layer etching time based on the etching conditions corresponding to the first barrier layer etching stage and the thickness of the first barrier layer 202; etch the first barrier layer 202 according to the etching conditions corresponding to the first barrier layer etching stage and the first barrier layer etching time until the silicide barrier layer 201 is exposed.

[0123] Fig.11 FIG. 2 is a cross-sectional view showing the etching process of the first barrier layer 202 in the embodiment of the present application, please refer to FIG. Fig.12 , the first barrier layer 202 is etched along the etching window 90 to expose the surface of the silicide barrier layer 201 .

[0124] In this step, dry etching is adopted, and the patterned APF 40 is used as a mask, and the first barrier layer 202 is etched according to the etching conditions corresponding to the first barrier layer etching stage and the first barrier layer etching time.

[0125] As an example, the etching conditions corresponding to the first barrier layer etching stage are: the chamber pressure is 30mt-70mt, the upper electrode power is 100W-300W, the lower electrode power is 50W-300W, the flow ratio of the main etching gas and the auxiliary gas is <1:1, and the flow rate of the protective gas is 200sccm-600sccm; among them, the flow rate of the main etching gas is 10sccm-50sccm; the main etching gas is preferably CH2F2, the auxiliary gas is O2, and the protective gas is Ar.

[0126] S73: Determine the silicide barrier layer etching time according to the etching conditions corresponding to the silicide barrier layer etching stage and the thickness of the silicide barrier layer 201; etch the silicide barrier layer 201 according to the etching conditions corresponding to the silicide barrier layer etching stage and the silicide barrier layer etching time until the substrate 10 is exposed to obtain the contact hole 80.

[0127] Fig.12 FIG. 2 is a cross-sectional view showing the etching process of the silicide barrier layer 201 according to an embodiment of the present application. Fig.13 The silicide barrier layer 201 is etched along the etching window 90 to expose the surface of the substrate 10 , thereby obtaining a contact hole 80 penetrating the APF, the interlayer dielectric layer 30 , the first barrier layer 202 and the silicide barrier layer 201 .

[0128] In this step, dry etching is adopted, and the silicide blocking layer 201 is etched using the patterned APF 40 as a mask.

[0129] As an example, the etching conditions corresponding to the silicide barrier layer etching stage are: the chamber pressure is 20mt-60mt, the upper electrode power is 0-100W, the lower electrode power is 300W-800W, the flow ratio of the main etching gas and the auxiliary gas is <1:1, and the flow rate of the protective gas is 800sccm-1500sccm; among them, the flow rate of the main etching gas is 5sccm-100sccm; among them, the main etching gas is preferably C4F6, the auxiliary gas is O2, and the protective gas is Ar.

[0130] The present application also provides a specific embodiment to further verify the effect of the embodiment of a semiconductor structure etching method in the technical solution of the present application. The implementation effect of the technical solution of the present application is described in detail below in combination with the specific embodiment.

[0131] Embodiment 1:

[0132] This embodiment 1 discloses a method for etching a semiconductor structure. The structural schematic diagram of the etching process is shown in FIG. Fig.13 shown.

[0133] Step 1:

[0134] A semiconductor structure after photolithography is provided, wherein the semiconductor structure comprises, from top to bottom: a thickness of PR (photoresist layer 70), with a thickness of BARC (top anti-reflective coating 51) with a thickness of Oxide (oxide layer 60), thickness is DARC (bottom anti-reflective coating 52) with a thickness of APF (amorphous carbon) with a thickness of The silicon dioxide layer (interlayer dielectric layer 30) has a thickness of The SIN layer (silicon nitride layer) has a thickness of SAB Oxide (silicide barrier layer 201), EPI (Epitaxy, epitaxial layer, made of Si). Representative Amy ), is a commonly used unit of length in crystallography, atomic physics, ultramicrostructure, etc. The photoresist layer 70 is a patterned photoresist, which limits the CD of the contact hole 80 to 75 nm.

[0135] Step 2:

[0136] Anti-reflective coating etching stage (BARC STEP): using the photoresist layer 70 after photolithography as a mask, dry etching is adopted, and the dry etching conditions are set to: pressure 70mt, HF is 600W, LF is 200W, CF4 (main etching gas) flow rate is 120sccm, O2 (auxiliary gas) flow rate is 4sccm, etching time is 85s, BARC (top anti-reflective coating 51), Oxide (oxide layer 60), and DARC (bottom anti-reflective coating 52) are etched in turn to expose the surface of the hard mask layer 40.

[0137] Step 3:

[0138] Hard mask layer 40 etching stage (APF STEP): using the photoresist layer 70 after photolithography as a mask, dry etching is adopted, and the dry etching conditions are set to: pressure 20mt, HF is 300W, LF is 0W, CO2 (main etching gas) flow rate is 150sccm, O2 (auxiliary gas) flow rate is 50sccm, etching time is 98s, the amorphous carbon is etched to expose the surface of the interlayer dielectric layer 30, and a patterned APF40 is obtained; after the etching of the hard mask layer 40 is completed, the photoresist layer 70 after photolithography, BARC (top anti-reflective coating 51), Oxide (oxide layer 60) and DARC (bottom anti-reflective coating 52) are gradually etched in this step.

[0139] Step 4:

[0140] Main etching stage (ME step): Using the patterned APF40 as a mask, dry etching is used to etch the silicon dioxide layer, and the dry etching conditions are set as follows: pressure 25mt, HF is 500W, LF is 2500W, C4F8 (main etching gas) flow rate is 25sccm, O2 (auxiliary gas) flow rate is 14sccm, Ar (protective gas) flow rate is 400sccm, and etching time is 95s, until the surface of the SIN layer is exposed.

[0141] Step 5:

[0142] Silicon nitride layer etching stage (LRM STEP): Using the patterned APF40 as a mask, dry etching is used to etch the silicon nitride layer, and the dry etching conditions are set to: pressure 50mt, HF 200W, LF 100W, CH2F2 (main etching gas) flow rate 25sccm, O2 (auxiliary gas) flow rate 8sccm, Ar (protective gas) flow rate 300sccm, etching time 15s, until the surface of the SAB Oxide layer is exposed.

[0143] Step 6:

[0144] Over-etching stage (OE STEP): With the patterned APF40 as a mask, dry etching is used to etch the SABOxide, and the dry etching conditions are set to: pressure of 35mt, HF of 0W, LF of 500W, C4F6 (main etching gas) flow rate of 12sccm, O2 (auxiliary gas) flow rate of 15sccm, Ar (protective gas) flow rate of 1200sccm, etching time of 95s. After etching the SAB oxide in this step, the surface of the Si epitaxial layer is exposed, and about 100A of the Si epitaxial layer is etched (not shown in the figure). This is a specific choice when setting the etching conditions, because part of the Si epitaxial layer is etched to form the contact area filled with the subsequent metal contact hole 80. After the etching is completed, the patterned APF40 is removed (the removal process is not shown in the figure).

[0145] Comparative Example 1:

[0146] This embodiment 1 discloses a method for etching a semiconductor structure. The structural schematic diagram of the etching process is shown in FIG. Fig.14 Show.

[0147] Step 1:

[0148] A semiconductor structure after photolithography is provided, wherein the semiconductor structure comprises, from top to bottom: a thickness of PR (photoresist layer 70), with a thickness of BARC (top anti-reflective coating 51) with a thickness of The silicon dioxide layer (interlayer dielectric layer 30) has a thickness of The SIN layer (silicon nitride layer) has a thickness of SAB Oxide (silicide barrier layer 201), EPI (Epitaxy, epitaxial layer, made of Si). Representative Amy ), is a commonly used unit of length in crystallography, atomic physics, ultramicrostructure, etc. The photoresist layer 70 is a patterned photoresist, which limits the CD of the contact hole 80 to 75 nm.

[0149] Step 2:

[0150] Anti-reflective coating 50 etching stage (BARC STEP): using the photoresist layer 70 after photolithography as a mask, dry etching is adopted, and the dry etching conditions are set to: pressure 70mt, HF is 600W, LF is 200W, CF4 (main etching gas) flow rate is 120sccm, O2 (auxiliary gas) flow rate is 4sccm, etching time is 85s, BARC (top anti-reflective coating 51) is etched to expose the surface of the silicon dioxide layer.

[0151] Step 3:

[0152] Main etching stage (ME step): using the photoresist layer 70 after photolithography as a mask, dry etching is used to etch the silicon dioxide layer, and the dry etching conditions are set to: pressure 25mt, HF is 500W, LF is 2000W, C4F8 (main etching gas) flow rate is 25sccm, O2 (auxiliary gas) flow rate is 14sccm, Ar (protective gas) flow rate is 400sccm, and etching time is 95s, until the surface of the SIN layer is exposed.

[0153] Step 4:

[0154] The silicon nitride layer etching stage (LRM STEP) is different from step 5 of embodiment 1 in that the photoresist layer 70 after photolithography is used as a mask, and the rest is consistent with step 5 of embodiment 1.

[0155] Step 5:

[0156] The over-etching stage (OE STEP) is different from step 6 of embodiment 1 in that the photoresist layer 70 after photolithography is used as a mask, and the rest is consistent with step 6 of embodiment 1.

[0157] The main differences between Comparative Example 1 and Example 1 are: (1) it does not contain an APF layer, and (2) the power of the lower electrode is smaller than that of Example 1.

[0158] The semiconductor structures obtained in Example 1 and Comparative Example 1 were sliced ​​and analyzed. The slice results of the semiconductor structure prepared in Example 1 are as follows: Fig.15 The sliced ​​structure of the semiconductor structure prepared in Comparative Example 1 is as follows: Fig.16 , by comparison Fig.15 and Fig.16 , indicating that by increasing the power of the lower electrode in the main etching stage and using the APF as a mask, the interlayer dielectric layer 30 will not produce a concave morphology during the etching process of the contact hole 80 .

[0159] The electrical parameter tests were performed on the semiconductor structures obtained in Example 1 and Comparative Example 1. The results are shown in Tables 1 and 2.

[0160] Table 1 Electrical parameters of the semiconductor structure prepared in Example 1

[0161]

[0162]

[0163] Table 2 Electrical parameters of the semiconductor structure prepared in Comparative Example 1

[0164] -2 -1 0 1 2 3 4 5 6 7 8 0 115.05 113.87 114.14 111.65 111.79 110.15 113.96 1 115.32 115.06 111.2 110.86 112.94 111.77 110.3 109.66 112.38 2 112.69 114.99 114.61 112.63 110.64 109.14 109.63 108.27 109.71 108.62 110.88 3 114.63 114.95 110.82 109.03 109.03 108.95 109.31 107.34 110.85 108.03 111.88 4 111.32 116.51 111.29 111.12 111.22 107.62 108.24 108.39 109.34 109.24 112.45 5 115.33 116.53 109.08 110.07 107.69 107.79 107.61 108.47 114.39 6 115.69 115.76 110.76 111.34 113.44 113.18 114.67

[0165] It should be noted that Table 1 and Table 2 are resistance test data. The data in each table represent resistance test data of multiple points on the semiconductor structure, and each point corresponds to a single semiconductor device manufactured subsequently, wherein row headers -2 to 8 represent the specific positions of the semiconductor device in the x direction on the semiconductor structure, and column headers 0 to 6 represent the specific positions of the semiconductor device in the y direction on the semiconductor structure. The vacant position is because the semiconductor structure is circular and no semiconductor device is detected at this position.

[0166] By analyzing Table 1 and Table 2, we can obtain the resistance parameter comparison between Example 1 and Comparative Example 1, as shown in Table 3:

[0167] Table 3 Comparison of resistance parameters of Example 1 and Comparative Example 1

[0168] Maximum resistance / Ω Minimum resistance / Ω Average resistance / Ω Range / Ω Example 1 103.09 91.36 95.63 11.74 Comparative Example 1 116.53 107.34 111.47 9.79

[0169] According to the comparison of the resistance parameters of Example 1 and Comparative Example 1, it can be known that after increasing the power of the lower electrode, the resistance value drops from 111.47Ω to 95.63Ω. The larger the resistance, the weaker the conductivity of the semiconductor structure and the greater the resistance to the passage of current. Therefore, after increasing the power of the lower electrode, the resistance value of the semiconductor structure drops to about 15Ω. The reduction in resistance means that the energy consumed when the current passes through is reduced, which directly leads to a reduction in overall energy consumption and helps to improve energy efficiency; reducing resistance can improve the operating speed and performance of semiconductor devices, because current can pass through the device more quickly and reduce signal delays; reducing resistance can reduce the heat generated by the device during operation, which helps to improve the stability and reliability of the device, and also reduces the need for a cooling system; reducing resistance helps to achieve device miniaturization, because the same performance can be achieved in a smaller device; reducing resistance allows more power handling capabilities to be integrated in the same volume. In summary, the reduction in resistance of semiconductor structures is of great significance for improving energy efficiency, performance and reliability, and also helps to achieve device miniaturization and overall optimization of the system.

[0170] Therefore, by using the above method to etch the small critical size contact hole 80 on the BCD platform, since the power of the lower electrode in the main etching process (i.e., the etching process of the interlayer dielectric layer 30) is increased, the plasma in the etching process can act vertically on the interlayer dielectric layer 30, and does not bombard the side wall of the contact hole 80, which is beneficial to controlling the morphology of the contact hole 80. By using amorphous carbon as a hard mask for etching the interlayer dielectric layer 30, the generation of by-products is avoided, thereby avoiding the generation of a concave morphology on the side wall of the contact hole 80 and avoiding the performance degradation of the semiconductor device caused by the concave morphology, thereby improving the electrical parameters of the product; finally, the present application increases the power of the lower electrode in the etching process of the interlayer dielectric layer 30, and also widens the process window for etching the interlayer dielectric layer 30.

[0171] On the other hand, an embodiment of the present application further provides a semiconductor device, which is prepared by the above-mentioned etching method of the semiconductor structure.

[0172] On the other hand, an embodiment of the present application further provides an electronic device, comprising the above-mentioned semiconductor device.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the scope of protection of the present invention. Although the present invention is described in detail with reference to the preferred embodiments, it is not limited to those listed in the embodiments. Those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A method for etching a semiconductor structure, characterized in that: The etching method comprises: Providing a semiconductor structure after photolithography; the semiconductor structure after photolithography comprises a substrate, a barrier layer, an interlayer dielectric layer, a hard mask layer and an anti-reflective coating layer stacked in sequence from bottom to top; In the initial etching stage, the anti-reflective coating and the hard mask layer are sequentially etched until the interlayer dielectric layer is exposed; the lower electrode power corresponding to the initial etching stage is 0-400W; In the main etching stage, the interlayer dielectric layer is etched using the unetched hard mask layer as a mask until the barrier layer is exposed; the lower electrode power corresponding to the main etching stage is 2500W-3500W; In the over-etching stage, the barrier layer is etched until the substrate is exposed to obtain a contact hole; the lower electrode power corresponding to the over-etching stage is 50W-800W.

2. The etching method according to claim 1, characterized in that: The critical dimension of the contact hole is less than 90nm; the thickness of the interlayer dielectric layer is greater than 400nm; the sum of the thicknesses of the substrate layer and the barrier layer is less than 120nm; and the aperture ratio of the semiconductor structure after photolithography is less than 3%.

3. The etching method according to claim 1, characterized in that: The hard mask layer is amorphous carbon; In the main etching stage, the interlayer dielectric layer is etched using the unetched hard mask layer as a mask until the barrier layer is exposed, comprising: Determining the main etching time based on the etching conditions corresponding to the main etching stage and the thickness of the interlayer dielectric layer; According to the etching conditions corresponding to the main etching stage and the main etching time, the interlayer dielectric layer is etched using the unetched amorphous carbon as a mask until the barrier layer is exposed.

4. The etching method according to claim 3, characterized in that: The material of the interlayer dielectric layer includes SiO2; the material of the substrate includes Si; The etching conditions corresponding to the main etching stage include: the chamber pressure is 20mt-25mt, the upper electrode power is 200W-800W, the flow ratio of the main etching gas and the auxiliary gas is less than 1.8:1, the flow rate of the main etching gas is ≤25sccm, and the flow rate of the protective gas is 350sccm-450sccm; Wherein, the main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar.

5. The etching method according to claim 1, characterized in that: The etching conditions corresponding to the initial etching stage include: the chamber pressure is 10mt-80mt, the upper electrode power is 200W-900W, and the flow ratio of the first main etching gas to the auxiliary gas is greater than 3:1; wherein the flow rate of the first main etching gas is 80sccm-200sccm; Wherein, the first main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar.

6. The etching method according to claim 1, characterized in that: The etching conditions corresponding to the over-etching stage include: the chamber pressure is 20mt-70mt, the upper electrode power is 0-300W, the flow ratio of the second main etching gas and the auxiliary gas is less than 1:1, and the flow rate of the second main etching gas is 10sccm-50sccm, and the flow rate of the protective gas is 200sccm-600sccm; Wherein, the second main etching gas is at least one of C4F6, C4F8, CH2F2, CO2, and CF4; the auxiliary gas is O2, and the protective gas is Ar.

7. The etching method according to claim 5, characterized in that: The anti-reflection coating comprises a bottom anti-reflection coating, an oxide layer and a top anti-reflection coating stacked in sequence from bottom to top; the photoresist layer after photolithography is arranged on the upper surface of the top anti-reflection coating; The initial etching stage includes an anti-reflective coating etching stage and a hard mask layer etching stage; In the initial etching stage, the anti-reflective coating layer and the hard mask layer are sequentially etched until the interlayer dielectric layer is exposed, comprising: The sum of the thicknesses of the top anti-reflective coating, the oxide layer and the bottom anti-reflective coating is determined as a first thickness; based on the etching conditions corresponding to the anti-reflective coating etching stage and the first thickness, an anti-reflective coating etching time is determined; and the top anti-reflective coating, the oxide layer and the bottom anti-reflective coating are etched according to the etching conditions corresponding to the anti-reflective coating etching stage and the anti-reflective coating etching time until the surface of the hard mask layer is exposed; The hard mask layer etching time is determined based on the etching conditions corresponding to the hard mask layer etching stage and the thickness of the hard mask layer; the hard mask layer is etched according to the etching conditions corresponding to the hard mask layer etching stage and the hard mask layer etching time until the interlayer dielectric layer is exposed.

8. The etching method according to claim 6, characterized in that: The barrier layer comprises a silicide barrier layer and a first barrier layer, the silicide barrier layer is arranged on the upper surface of the substrate layer, and the first barrier layer is arranged on the upper surface of the silicide barrier layer; Therefore, the over-etching stage includes the silicide barrier layer etching stage and the first barrier layer etching stage; The step of etching the barrier layer in the over-etching stage until the substrate is exposed to obtain a contact hole comprises: Determining a first barrier layer etching time based on the etching conditions corresponding to the first barrier layer etching stage and the thickness of the first barrier layer; etching the first barrier layer according to the etching conditions corresponding to the first barrier layer etching stage and the first barrier layer etching time until the silicide barrier layer is exposed; Determine the silicide barrier layer etching time according to the etching conditions corresponding to the silicide barrier layer etching stage and the thickness of the silicide barrier layer; and etch the silicide barrier layer according to the etching conditions corresponding to the silicide barrier layer etching stage and the silicide barrier layer etching time until the substrate is exposed to obtain the contact hole.

9. A semiconductor device, characterized in that: The semiconductor structure is prepared by the etching method of any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the semiconductor device as claimed in claim 9.

Images