Method and system for judging and controlling tripping fault and starting timeout fault of motor

Abstract

The invention provides a judgment control method and system for a tripping fault and a starting timeout fault of a motor. Wherein a control program is written in a control system to which the motor belongs, so that the distinguishing judgment of a tripping fault and a starting overtime fault is realized. The accurate fault type judgment is beneficial to reducing the troubleshooting time, so that the time for solving the fault is saved, the equipment can be put into production more quickly, and the deserved value of the equipment is exerted; and the tripping fault is different from the starting overtime fault, and particularly, the tripping fault instead of the starting overtime fault is needed in the automatic switching process of the standby equipment, so that the system can conveniently and quickly realize the automatic switching control of the standby equipment by accurately judging the tripping fault.

Description

Technical Field

[0001] The present application relates to a method and system for judging and controlling a motor tripping fault and a starting timeout fault, and belongs to the technical field of automatic control. Background Art

[0002] Motor-driven devices are ubiquitous in modern industrial production, and the control and protection of motors are particularly important in the process of industrial automatic control. However, the commonly used motor startup protection program logic usually only judges the startup timeout fault. The startup timeout fault refers to: during the motor startup phase, the control system does not receive the motor's running signal within the specified time after the control system (PLC or DCS) to which it belongs issues the start command. However, it does not judge the fault (referred to as a trip fault in this article) in which the equipment stops for no reason and the running signal is lost during the operation process after the motor is started without issuing a stop command, that is, when the start command always exists, or the program logic of the startup timeout fault is used to judge, and the trip fault is generally summarized as a startup timeout fault.

[0003] This makes it difficult for operation and maintenance personnel to accurately determine the fault type, which affects the efficiency of fault handling. In addition, the start-up timeout fault cannot replace the role of the trip fault in the automatic input of the backup equipment. Summary of the invention

[0004] The present application provides a method and system for determining and controlling a motor tripping fault and a starting timeout fault, so as to solve the current problem that a tripping fault cannot be accurately determined.

[0005] In a first aspect, an embodiment of the present application provides a method for determining and controlling a motor trip fault and a start-up timeout fault, comprising: When the motor meets the starting conditions, a starting command is issued to the motor; Acquire an operation feedback signal returned by the motor based on the start instruction, and acquire a trip judgment validity period signal; If the trip judgment validity period signal is an invalid signal, and the duration of the operation feedback signal being an invalid signal reaches a first time threshold, it is determined that there is a start timeout fault, and a start timeout fault prompt is issued; wherein, when the motor meets the start condition and the duration of receiving the start command is greater than the second time threshold, the trip judgment validity period signal is a valid signal, otherwise the trip judgment validity period signal is an invalid signal; when the motor operates normally, the operation feedback signal is a valid signal, otherwise the operation feedback signal is an invalid signal; the first time threshold is less than the second time threshold; If the trip judgment validity period signal is a valid signal, and the duration of the operation feedback signal being an invalid signal reaches a third time threshold, it is determined that a trip fault exists, and a trip fault prompt is issued.

[0006] Based on the above method, optionally, it also includes: After the reset signal is obtained, the start timeout fault signal and the trip fault signal are reset to the default value.

[0007] In a second aspect, an embodiment of the present application further provides a motor trip fault and a start timeout fault judgment control system, which is used to implement the method as described in the first aspect, wherein the control system stores a control program, and the control program is configured with: A first AND gate is used to access the start condition signal, the start command signal, the motor operation feedback signal and the trip judgment validity period signal, and output a first output signal; A first on-delay timer, used for receiving the first output signal and a first time variable, and outputting a start timeout latch signal; A second AND gate is used to access the start condition signal and the start command signal, and output a second output signal; A second on-delay timer, used for receiving the second output signal and a second time variable, and outputting the trip judgment validity period signal; The third AND gate is used to access the start condition signal, the start command signal, the motor operation feedback signal and the trip judgment validity period signal, and output a third output signal; The third on-delay timer is used to access the third output signal and the third time variable, and output a trip fault latch signal.

[0008] Based on the above system, optionally, the start condition signal is connected to the first input terminal of the first AND gate, the start command signal is connected to the second input terminal of the first AND gate, the operation feedback signal is connected to the third input terminal of the first AND gate after being inverted by the first NOT gate, and the trip judgment validity period signal is connected to the fourth input terminal of the first AND gate after being inverted by the second NOT gate; the output terminal of the first AND gate is connected to the first input terminal of the first on-delay timer, and the first time variable is connected to the second input terminal of the first on-delay timer; the output terminal of the first delay on-timer sets the start timeout latch signal.

[0009] Based on the above system, optionally, the start condition signal is connected to the first input terminal of the second AND gate, and the start command signal is connected to the second input terminal of the second AND gate; the output terminal of the second AND gate is connected to the first input terminal of the second on-delay timer, and the second time variable is connected to the second input terminal of the second on-delay timer; the output terminal of the second delay on-timer outputs a trip judgment validity period signal.

[0010] Based on the above system, optionally, the start condition signal is connected to the first input terminal of the third AND gate, the start command signal is connected to the second input terminal of the third AND gate, the operation feedback signal is connected to the third input terminal of the third AND gate after being inverted by the second NOT gate, and the trip judgment validity period signal is connected to the fourth input terminal of the third AND gate; the output terminal of the third AND gate is connected to the first input terminal of the third on-delay timer, and the third time variable is connected to the second input terminal of the third on-delay timer; the output terminal of the third delay on-timer sets the trip fault latch signal.

[0011] Based on the above system, optionally, the control program is further configured to: When the reset button triggers the reset signal, the rising edge of the reset button signal is taken to reset the start timeout latch signal and the trip fault latch signal.

[0012] Based on the above system, optionally, the system is a PLC or a DCS.

[0013] In the judgment control method and system for the motor trip fault and the start timeout fault provided by the present application, the control program is written in the control system to which the motor belongs, so as to realize the distinction judgment between the trip fault and the start timeout fault. Accurate fault type judgment is conducive to reducing the time of troubleshooting, thereby saving the time of solving the fault, making the equipment put into production faster, and giving full play to the due value of the equipment; and because the trip fault is different from the start timeout fault, especially in the process of automatic start of the standby equipment, what is needed is the trip fault rather than the start timeout fault, so by accurately judging the trip fault, it is convenient for the system to quickly realize the automatic start control of the standby equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. In addition, these drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application for those skilled in the art by referring to specific embodiments.

[0015] Figure 1 A flow chart of a method for determining and controlling a motor tripping fault and a starting timeout fault provided by an embodiment of the present application; Figure 2 A schematic diagram of the overall packaging of a control system for judging a motor tripping fault and a starting timeout fault provided by an embodiment of the present application; Figure 3 A logic diagram for starting timeout judgment provided by an embodiment of the present application; Figure 4 A logic diagram of a trip determination validity period signal provided by one embodiment of the present application; Figure 5 A logic diagram for tripping fault judgment provided by an embodiment of the present application; Figure 6 A logic diagram of a reset fault latch signal provided by one embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0017] In order to accurately perform fault judgment, the present application realizes the distinction between tripping fault and starting timeout fault by writing a control program in the control system to which the motor belongs.

[0018] Reference Figure 1 , Figure 1 The flowchart of the method for judging and controlling the motor tripping fault and the starting timeout fault provided by one embodiment of the present application is shown in FIG. The method of the present embodiment can be executed by the control system of the motor, and the control system can be a DCS system or a PLC system. Based on this, Figure 1 As shown, the method comprises at least the following steps: Step S101: When the motor meets the starting conditions, a starting instruction is issued to the motor.

[0019] Specifically, when the motor needs to be started, it is first detected whether the motor meets the starting conditions. If the starting conditions are met, the control system sends a starting instruction to the motor to control the motor to start.

[0020] Step S102: obtaining an operation feedback signal returned by the motor based on the start-up instruction, and obtaining a trip judgment validity period signal.

[0021] In practice, after the motor receives the start command, it starts to try to start and returns an operation feedback signal to the control system. When the motor is running normally, the operation feedback signal is a valid signal, otherwise the operation feedback signal is an invalid signal. The control system can determine whether the motor is running normally based on the operation feedback signal.

[0022] In addition, the trip judgment validity period signal is a newly added signal in this embodiment, which is determined based on the duration of the motor meeting the starting condition and receiving the starting instruction. When the duration of the motor meeting the starting condition and receiving the starting instruction is greater than the second time threshold, the trip judgment validity period signal is a valid signal, otherwise the trip judgment validity period signal is an invalid signal.

[0023] When the duration of the motor meeting the starting conditions and receiving the start command is greater than the second time threshold, it indicates that a long time has passed since the motor started, and it has entered a stable operation state under normal circumstances, so the trip judgment validity period signal is a valid signal, and when the motor meets the starting conditions and receives the start command for a duration less than the second time threshold, the motor has not yet entered a stable operation state, so the trip judgment validity period signal is an invalid signal. If the trip judgment validity period signal is a valid signal, then the motor meets the prerequisite for judging a trip fault at this time, and if the trip judgment validity period signal is an invalid signal, then the motor does not meet the prerequisite for judging a trip fault at this time, and no trip fault judgment is required.

[0024] Step S103: If the trip judgment validity period signal is an invalid signal, and the duration of the operation feedback signal being an invalid signal reaches a first time threshold, it is determined that there is a start timeout fault, and a start timeout fault prompt is issued; wherein the first time threshold is less than the second time threshold.

[0025] Specifically, when the trip judgment validity period signal is an invalid signal, and the duration of the operation feedback signal being an invalid signal at this time reaches the first time threshold, it indicates that the motor cannot operate normally for a long time, so it can be determined that there is a start timeout fault. If the operation feedback signal is a valid signal, or the duration of the invalid signal does not reach the first time threshold, it can be determined that the motor has completed normal startup, so there is no start timeout fault. Among them, the first time threshold is less than the second time threshold to ensure that the motor has completed normal startup before the trip fault judgment is performed.

[0026] Step S104: If the trip judgment validity period signal is a valid signal, and the duration of the operation feedback signal being an invalid signal reaches a third time threshold, it is determined that a trip fault exists, and a trip fault prompt is issued.

[0027] Specifically, when the trip judgment validity period signal is a valid signal, and the duration of the operation feedback signal being an invalid signal reaches a third time threshold, it indicates that the motor is in a state of non-operating operation during the stage when it should be operating normally, so it can be determined that a trip fault exists.

[0028] Based on the above scheme, by writing a control program in the control system to which the motor belongs, the distinction between tripping fault and starting timeout fault can be realized. Accurate fault type judgment is conducive to reducing the time of troubleshooting, thereby saving time to solve the fault, allowing the equipment to be put into production faster and giving full play to the value of the equipment; and because the tripping fault is different from the starting timeout fault, especially in the automatic start-up process of the standby equipment, what is needed is the tripping fault rather than the starting timeout fault, so by accurately judging the tripping fault, it is convenient for the system to quickly realize the automatic start-up control of the standby equipment.

[0029] In addition, in some embodiments, the above method may further include: After the reset signal is obtained, the start timeout fault signal and the trip fault signal are reset to the default value.

[0030] Specifically, in practice, when the control system reports a fault, the motor will be prohibited from running. In addition, after the relevant personnel perform fault detection and maintenance, if the corresponding fault is eliminated, they can press the reset button to trigger the reset signal to reset the start timeout fault signal and the trip fault signal to the default value. Only then is it allowed to start the motor again.

[0031] In addition, the embodiment of the present application provides a motor tripping fault and start-up timeout fault judgment control system, the control system is used to implement the method described in any of the above embodiments, the control system stores a control program, the overall packaging schematic diagram of the control system is as shown in Figure 2 .

[0032] Among them, Figure 3-5 As shown, the control program is configured with: The first AND gate 101 is used to access the start condition signal, the start command signal, the motor operation feedback signal and the trip judgment validity period signal, and output a first output signal; A first on-delay timer 104 is used to access the first output signal and the first time variable (i.e. the first time threshold mentioned above), and output a start timeout latch signal; The second AND gate 201 is used to access the start condition signal and the start instruction signal, and output a second output signal; A second on-delay timer 203, used to access the second output signal and the second time variable, and output the trip judgment validity period signal; The third AND gate 301 is used to access the start condition signal, the start command signal, the motor operation feedback signal and the trip judgment validity period signal, and output a third output signal; The third on-delay timer 303 is used to access the third output signal and the third time variable, and output a trip fault latch signal.

[0033] The specific judgment logic is as follows: like Figure 3 As shown, the logic of starting timeout judgment is: The start condition signal is connected to the first input terminal of the first AND gate 101, the start command signal is connected to the second input terminal of the first AND gate 101, the operation feedback signal is connected to the third input terminal of the first AND gate after being inverted by the first NOT gate 102, and the trip judgment validity period signal is connected to the fourth input terminal of the first AND gate 101 after being inverted by the second NOT gate 103; the output terminal of the first AND gate 101 is connected to the first input terminal of the first on-delay timer 104, and the first time variable 105 is connected to the second input terminal of the first on-delay timer 104; the output terminal of the first delay on-timer 105 sets the start timeout latch signal. Through the above logic, it can be determined whether the motor has a start timeout fault.

[0034] like Figure 4 As shown in the figure, the logic of the trip judgment validity period signal is: The start condition signal is connected to the first input terminal of the second AND gate 201, and the start command signal is connected to the second input terminal of the second AND gate 201; the output terminal of the second AND gate 201 is connected to the first input terminal of the second on-delay timer 203, and the second time variable 202 is connected to the second input terminal of the second on-delay timer 203; the output terminal of the second delay on-timer 203 outputs the trip judgment validity period signal. The logic value (0 or 1) of the trip judgment validity period signal is obtained through the above logic.

[0035] like Figure 5 As shown in the figure, the logic of tripping fault judgment is: The start condition signal is connected to the first input terminal of the third AND gate 301, the start command signal is connected to the second input terminal of the third AND gate 301, the operation feedback signal is connected to the third input terminal of the third AND gate 301 after being inverted by the second NOT gate 302, and the trip judgment validity period signal is connected to the fourth input terminal of the third AND gate 301; the output terminal of the third AND gate 301 is connected to the first input terminal of the third on-delay timer 303, and the third time variable 304 is connected to the second input terminal of the third on-delay timer 303; the output terminal of the third delay on-timer 303 sets the trip fault latch signal. Through the above logic, it can be judged whether the motor has a trip fault.

[0036] In addition, in some embodiments, the control program is further configured to: When the reset button triggers the reset signal, the rising edge 401 of the reset button signal is taken to reset the start timeout latch signal and the trip fault latch signal.

[0037] like Figure 6 As shown, the logic of resetting the fault latch signal is: The reset button on the operation screen is connected to the first rising edge, and the rising edge of the device reset button signal is taken to reset the two fault latch signals. The purpose of this operation is that the motor can only be started again after the operator confirms and eliminates the fault of the motor and manually resets the fault latch signal.

[0038] For a better understanding, please refer to the attached Figure 3-6 Let's take an example: At the initial stage of equipment startup, if the motor meets the startup condition, that is, the startup condition is 1, the control system (PLC or DCS) to which the motor belongs issues a startup instruction, that is, the startup instruction is 1, the trip judgment validity period signal defaults to 0, and is 1 after being inverted by the second NOT gate 103, and the operation feedback signal defaults to 0, and is 1 after being inverted by the first NOT gate 102; the above four signals are connected to the first AND gate 101, and the four signals are logically ANDed to the first connection delay timer 104; the prerequisite for judging the startup timeout fault is that the startup condition is 1 and the startup instruction is 1 and the trip judgment validity period is 1 after being inverted; at this time, if the equipment starts normally, the operation feedback signal is 1, and is 0 after being inverted by the first NOT gate 102, then the first AND gate 101 outputs a logic value of 0, the first connection delay timer 104 does not work, and will not trigger the first setting instruction 105, and the startup timeout latch signal will not appear. At this time, if the device cannot start normally, the operation feedback signal is 0, which is 1 after being inverted by the first NOT gate 102, then the first AND gate 101 outputs a logic value of 1, and the first on-delay timer 104 starts to work. If the time when the operation feedback signal is 0 reaches the set value of the first time variable 105, the first on-delay timer 104 outputs a signal of 1, and the start timeout latch signal is set by the first setting instruction 106, proving that the motor has a start timeout fault. After the control system to which the motor belongs determines that the start timeout fault has occurred, the start instruction is cancelled.

[0039] If the motor meets the starting condition, that is, the starting condition is 1, the control system to which the motor belongs issues a starting instruction, that is, the starting instruction is 1, and the above two signals are connected to the second AND gate 201, and the two signals are logically ANDed and connected to the second on-delay timer 203. As long as the time when the starting condition and the starting instruction are both 1 reaches the set value of the second time variable 202, the second on-delay timer 203 outputs signal 1, that is, the trip judgment validity period signal is 1. When the trip judgment validity period is 1, the start timeout prerequisite is not met, and the start timeout fault will not occur.

[0040] After the motor equipment is started, it enters the normal operation state. At this time, the motor meets the starting condition, that is, the starting condition is 1; the starting command of the control system to which the motor belongs is 1; when the motor is operating normally, the running signal is 1, and the running feedback signal is 0 after being inverted by the third NOT gate 302; the trip judgment validity period is based on Figure 4The logic judgment is 1 or 0; the above four signals are connected to the third AND gate 301, and the four signals are logically ANDed to the third on-delay timer 303. When the trip judgment validity period is 0, the output of the third AND gate 301 is 0, the third on-delay timer 303 does not work, and the second setting instruction 305 will not be triggered, and the trip fault latch signal will not appear. When the trip judgment validity period signal is 1, if the operation feedback signal is 0, and it is 1 after being inverted by the third NOT gate 302, the output of the third AND gate 301 is 1, and the third on-delay timer 303 starts to work. If the time when the operation feedback signal is 0 reaches the set value of the third time variable 304, the third on-delay timer 303 outputs a signal 1, and the trip fault latch signal is set through the second setting instruction 305.

[0041] like Figure 6 As shown, when the reset button of the operation screen is connected to the first rising edge 401, the rising edge of the device reset button signal is taken to reset the two fault latch signals 402 and 403.

[0042] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0043] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0044] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0045] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0046] A person skilled in the art may understand that all or part of the steps of the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0047] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0048] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0049] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A method for judging and controlling motor tripping fault and starting timeout fault, characterized in that: include: When the motor meets the starting conditions, a starting command is issued to the motor; Acquire an operation feedback signal returned by the motor based on the start instruction, and acquire a trip judgment validity period signal; If the trip judgment validity period signal is an invalid signal, and the duration of the operation feedback signal being an invalid signal reaches a first time threshold, it is determined that there is a start timeout fault, and a start timeout fault prompt is issued; wherein, when the motor meets the start condition and the duration of receiving the start command is greater than the second time threshold, the trip judgment validity period signal is a valid signal, otherwise the trip judgment validity period signal is an invalid signal; when the motor operates normally, the operation feedback signal is a valid signal, otherwise the operation feedback signal is an invalid signal; the first time threshold is less than the second time threshold; If the trip judgment validity period signal is a valid signal, and the duration of the operation feedback signal being an invalid signal reaches a third time threshold, it is determined that a trip fault exists, and a trip fault prompt is issued.

2. The method according to claim 1, characterized in that Also includes: After the reset signal is obtained, the start timeout fault signal and the trip fault signal are reset to the default value.

3. A judgment and control system for motor tripping fault and starting timeout fault, characterized in that: For implementing the method according to claim 1 or 2, the control system stores a control program, and the control program is configured with: A first AND gate is used to access the start condition signal, the start command signal, the motor operation feedback signal and the trip judgment validity period signal, and output a first output signal; A first on-delay timer, used for receiving the first output signal and a first time variable, and outputting a start timeout latch signal; A second AND gate is used to access the start condition signal and the start command signal, and output a second output signal; A second on-delay timer, used for receiving the second output signal and a second time variable, and outputting the trip judgment validity period signal; The third AND gate is used to access the start condition signal, the start command signal, the motor operation feedback signal and the trip judgment validity period signal, and output a third output signal; The third on-delay timer is used to access the third output signal and the third time variable, and output a trip fault latch signal.

4. The system according to claim 3, characterized in that The start condition signal is connected to the first input terminal of the first AND gate, the start command signal is connected to the second input terminal of the first AND gate, the operation feedback signal is inverted by the first NOT gate and connected to the third input terminal of the first AND gate, and the trip judgment validity period signal is inverted by the second NOT gate and connected to the fourth input terminal of the first AND gate; the output terminal of the first AND gate is connected to the first input terminal of the first on-delay timer, and the first time variable is connected to the second input terminal of the first on-delay timer; the output terminal of the first delay on-timer sets the start timeout latch signal.

5. The system according to claim 3, characterized in that The start condition signal is connected to the first input terminal of the second AND gate, and the start command signal is connected to the second input terminal of the second AND gate; the output terminal of the second AND gate is connected to the first input terminal of the second on-delay timer, and the second time variable is connected to the second input terminal of the second on-delay timer; the output terminal of the second delay on-timer outputs a trip judgment validity period signal.

6. The system according to claim 3, characterized in that The start condition signal is connected to the first input terminal of the third AND gate, the start command signal is connected to the second input terminal of the third AND gate, the operation feedback signal is connected to the third input terminal of the third AND gate after being inverted by the second NOT gate, and the trip judgment validity period signal is connected to the fourth input terminal of the third AND gate; the output terminal of the third AND gate is connected to the first input terminal of the third on-delay timer, and the third time variable is connected to the second input terminal of the third on-delay timer; the output terminal of the third delay on-timer sets the trip fault latch signal.

7. The system according to claim 3, characterized in that The control program is also configured to: When the reset button triggers the reset signal, the rising edge of the reset button signal is taken to reset the start timeout latch signal and the trip fault latch signal.

8. The system according to claim 3, characterized in that The system is a PLC or a DCS.

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