Clock-controlled self-turn-off slew rate enhancement circuit

Abstract

The invention relates to a clock-controlled self-turn-off slew rate enhancement circuit, and belongs to the technical field of analog integrated circuits. The two slew rate enhancing modules are respectively used for enhancing the bidirectional slew rate of the positive end and the negative end of the fully differential operational amplifier; each slew rate enhancement module comprises a self-turn-off comparison amplifier and a current output unit; the self-turn-off comparator is used for detecting the polarity of an input large signal, generating a positive and negative slew rate enhancement control signal, and automatically turning off after comparing for one time without influencing the response of a small signal; the current output unit is used for generating pulling current and is used for realizing bidirectional slew rate enhancement; the whole slew rate enhancement circuit can be controlled by a clock to be opened or closed. Under the conditions that static power consumption is not generated and small signal frequency characteristics are not affected, the two-way slew rate enhancing circuit is used in parallel with a fully differential operational amplifier, the two-way slew rate can be improved, it is guaranteed that a main circuit is not affected by a slew rate enhancing circuit, and overcharge and oscillation are prevented.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a clock-controlled self-shutdown slew rate enhancement circuit, which can be used to assist in improving the slew rate of a fully differential operational amplifier. Background Art

[0002] Operational amplifiers are widely used in the field of analog integrated circuits. They are key modules in mixed analog and digital circuits and determine the final performance of the overall circuit. In the switched capacitor circuit of the analog-to-digital converter chip, the operational amplifier is usually required to drive a large capacitive load. This requires the operational amplifier to provide sufficient slew rate to complete the transfer of charge on the capacitor within the specified time.

[0003] The slew rate (SR) is the conversion rate of the output voltage of the operational amplifier. It reflects the speed index of the operational amplifier, indicating the response speed of the operational amplifier to large signal input, which is limited by the maximum pull-out current that the operational amplifier can provide.

[0004] In order to obtain a highly linear response, the circuit system usually uses a Class A operational amplifier, which can provide a maximum current draw that does not exceed its output stage current. For applications that require a large slew rate, such as large capacitive loads and high-speed analog-to-digital conversion, the output stage is often required to work under a large bias current, resulting in excessive power consumption or even difficulty in achieving it. Therefore, it is necessary to add an auxiliary circuit to the operational amplifier to significantly improve its slew rate without significantly increasing power consumption. Traditional slew rate enhancement auxiliary circuits are usually always in operation and cannot be shut down autonomously, and there is no clock signal control. This results in the slew rate enhancement auxiliary circuit possibly over-drawing current when a large signal is input, causing an overshoot of the input voltage, which in turn slows down the response speed of the overall circuit. Summary of the invention

[0005] In view of the above technical problems, the present invention provides a clock-controlled self-shutdown slew rate enhancement circuit. The present invention can realize clock-controlled self-shutdown and significantly improve the bidirectional slew rate of a fully differential operational amplifier without significantly increasing power consumption or affecting the small signal frequency response of the operational amplifier.

[0006] The technical solution adopted by the present invention is:

[0007] A clock-controlled self-shutdown slew rate enhancement circuit is applied to a fully differential switched capacitor circuit, comprising a first slew rate enhancement module and a second slew rate enhancement module; the first slew rate enhancement module comprises a first comparator and a first current output unit, and the second slew rate enhancement module comprises a second comparator and a second current output unit;

[0008] The first comparator includes a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-second transistor M22, a twenty-third transistor M23, a twentieth transistor M20, a twenty-first transistor M21, an eighteenth transistor M18, a nineteenth transistor M19, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a twenty-ninth transistor M29, and a thirtieth transistor M30; wherein the sources of the eighteenth transistor M18 and the nineteenth transistor M19 are connected to the ground, the gates of the eighteenth transistor M18 and the nineteenth transistor M19 are connected together to the drain of the eighteenth transistor M18, and the drain of the eighteenth transistor M18 is connected to the second The source of the tenth transistor M20 is connected to the source of the twenty-first transistor M21, the drain of the nineteenth transistor M19 is connected to the source of the twenty-first transistor M21, the gates of the twentieth transistor M20 and the twenty-first transistor M21 are connected to the input clock signal CK, the sources of the twenty-second transistor M22 and the twenty-third transistor M23 are connected to the drain of the twenty-first transistor M21, the gate of the twenty-second transistor M22 is connected to the first input signal VP of the fully differential switched capacitor circuit, the gate of the twenty-third transistor M23 is connected to the second input signal VM of the fully differential switched capacitor circuit, the drain of the twenty-second transistor M22 is connected to the drain of the twenty-fifth transistor M25, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are connected to the drain of the twenty-third transistor M26. The source of the twenty-fifth transistor M26 is connected to the power supply, the gates of the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are connected together to the drain of the twenty-fifth transistor M25, the drain of the twenty-third transistor M23 and the drain of the twenty-sixth transistor M26 are connected together as the first output VPP of the first comparator, the drain of the twenty-fourth transistor M24 is connected to the drain of the twentieth transistor M20, the source of the twenty-fourth transistor M24 is connected to the power supply, the gate of the twenty-fourth transistor M24 is connected to the first output VPP of the first comparator, the source of the twenty-seventh transistor M27 is connected to the first output VPP of the first comparator, and the gate of the twenty-seventh transistor M27 is connected to the input clock signal CK. The drain of the twenty-seventh transistor M27 is connected to the ground, the source of the twenty-eighth transistor M28 is connected to the power supply, the gate of the twenty-eighth transistor M28 is connected to the first output VPP of the first comparator, the drain of the twenty-eighth transistor M28, the drain of the twenty-ninth transistor M29 and the gate of the thirtieth transistor M30 are connected together as the second output VP1 of the first comparator, the gate of the twenty-ninth transistor M29 is connected to the input clock signal CK, the source of the twenty-ninth transistor M29 is connected to the drain of the thirtieth transistor M30, the source of the thirtieth transistor M30 is connected to the ground, and the width-to-length ratio of the twenty-second transistor M22 is greater than that of the twenty-third transistor M23, so as to achieve a preset input deviation voltage;

[0009] The second comparator includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a fifth transistor M5, a sixth transistor M6, a fourth transistor M4, a third transistor M3, a first transistor M1, a second transistor M2, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; wherein the sources of the first transistor M1 and the second transistor M2 are connected to the ground, the gates of the first transistor M1 and the second transistor M2 are connected together to the drain of the first transistor M1, the drain of the first transistor M1 is connected to the source of the fourth transistor M4, The drain of the second transistor M2 is connected to the source of the third transistor M3, the gates of the fourth transistor M4 and the third transistor M3 are connected to the input clock signal CK, the source of the fifth transistor M5 and the sixth transistor M6 are connected to the drain of the third transistor M3, the gate of the fifth transistor M5 is connected to the second input signal VM of the fully differential switch capacitor circuit, the gate of the sixth transistor M6 is connected to the first input signal VP of the fully differential switch capacitor circuit, the drain of the fifth transistor M5 is connected to the drain of the eighth transistor M8, the sources of the eighth transistor M8 and the ninth transistor M9 are connected to the power supply, and the eighth transistor The gates of the ninth transistor M8 and the ninth transistor M9 are connected together to the drain of the eighth transistor M8, the drain of the sixth transistor M6 and the drain of the ninth transistor M9 are connected together as the first output VMM of the second comparator, the drain of the seventh transistor M7 is connected to the drain of the fourth transistor M4, the source of the seventh transistor M7 is connected to the power supply, the gate of the seventh transistor M7 is connected to the first output VMM of the second comparator, the source of the tenth transistor M10 is connected to the first output VMM of the second comparator, the gate of the tenth transistor M10 is connected to the input clock signal CK, the drain of the tenth transistor M10 is connected to the ground, and the tenth transistor M10 is connected to the input clock signal CK. The source of the first transistor M11 is connected to the power supply, the gate of the eleventh transistor M11 is connected to the first output VMM of the second comparator, the drain of the eleventh transistor M11, the drain of the twelfth transistor M12 and the gate of the thirteenth transistor M13 are connected together as the second output VM1 of the second comparator, the gate of the twelfth transistor M12 is connected to the input clock signal CK, the source of the twelfth transistor M12 is connected to the drain of the thirteenth transistor M13, the source of the thirteenth transistor M13 is connected to the ground, and the width-to-length ratio of the fifth transistor M5 is greater than that of the sixth transistor M6, so as to achieve a preset input deviation voltage;

[0010] The first current output unit includes a thirty-first transistor M31, a thirty-second transistor M32, a thirty-third transistor M33, a thirty-fourth transistor M34, a first NAND gate X11, and a first AND gate X01; wherein the source of the thirty-first transistor M31 is connected to the ground, the gate of the thirty-first transistor M31 is connected to the second output VP1 of the first comparator, the drain of the thirty-first transistor M31 is connected to the source of the thirty-second transistor M32, the source of the thirty-fourth transistor M34 is connected to the power supply, the gate of the thirty-fourth transistor M34 is connected to the first output VMM of the second comparator, and the thirty-fourth transistor The drain of M34 is connected to the source of the thirty-third transistor M33, the drain of the thirty-third transistor M33 and the drain of the thirty-second transistor M32 are connected together as the output terminal VOP of the first current output unit, the two inputs of the first NAND gate X11 are the input clock signal CK and the second output VM1 of the second comparator respectively, the output of the first NAND gate X11 is connected to the gate of the thirty-third transistor M33, the two inputs of the first AND gate X01 are the input clock signal CK and the second output VP1 of the first comparator respectively, and the output of the first AND gate X01 is connected to the gate of the thirty-second transistor M32;

[0011] The second current output unit includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, a second NAND gate X12, and a second AND gate X02; wherein the source of the fourteenth transistor M14 is connected to the ground, the gate of the fourteenth transistor M14 is connected to the second output VM1 of the second comparator, the drain of the fourteenth transistor M14 is connected to the source of the fifteenth transistor M15, the source of the seventeenth transistor M17 is connected to the power supply, the gate of the seventeenth transistor M17 is connected to the first output VPP of the first comparator, and the seventeenth transistor M17 is connected to the first output VPP of the first comparator. The drain of the sixteenth transistor M16 is connected to the source of the sixteenth transistor M16, the drain of the sixteenth transistor M16 and the drain of the fifteenth transistor M15 are connected together as the output terminal VOM of the second current output unit, the two inputs of the second NAND gate X12 are the input clock signal CK and the second output VP1 of the first comparator, the output of the second NAND gate X12 is connected to the gate of the sixteenth transistor M16, the two inputs of the second AND gate X02 are the input clock signal CK and the second output VM1 of the second comparator, and the output of the second AND gate X02 is connected to the gate of the fifteenth transistor M15.

[0012] The beneficial effects of the present invention are:

[0013] 1. The present invention utilizes the intermittent working characteristics of the switched capacitor circuit, has clock control and automatic shutdown functions, can realize automatic shutdown controlled by the clock, and can significantly improve the bidirectional slew rate of the fully differential operational amplifier without significantly increasing power consumption and affecting the small signal frequency response of the operational amplifier.

[0014] 2. The present invention avoids output voltage overshoot and possible oscillation, and ensures that the small signal response of the overall circuit is not affected by the slew rate enhancement circuit.

[0015] 3. The slew rate enhancement circuit proposed in the present invention is very suitable for use in a clock-controlled switched capacitor circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure is a schematic diagram of the circuit principle of a clock-controlled self-shutdown slew rate enhancement circuit in an embodiment of the present invention.

[0017] Figure 2 for Figure 1 The schematic diagram of the slew rate enhancement circuit shown is applied in the switched capacitor circuit. DETAILED DESCRIPTION

[0018] In order to further illustrate the technical solution disclosed in the present invention, the following is a detailed description in conjunction with the accompanying drawings and specific embodiments. Those skilled in the art should know that the optimized design and improved method made without violating the spirit of the invention all fall within the protection scope of the present invention, and the conventional technology in the field will not be described in detail in this specific embodiment.

[0019] A clock-controlled self-shutdown slew rate enhancement circuit, such as Figure 2 As shown, it can be used in a switched capacitor circuit in conjunction with a fully differential operational amplifier. Figure 2 In the figure, CK1 and CK2 are two-phase non-overlapping clocks. When CK1 is high, the switched capacitor circuit is in the sampling phase; when CK2 is high, the switched capacitor circuit is in the integration phase. CK2s is part of the CK2 clock. The rising edge of CK2s is aligned with CK2, but it changes to 0 earlier than CK2. When CK2s is low, the slew rate enhancement circuit does not work, and does not push or pull current into the VOP and VOM ports. When CK2s changes from low to high, the switched capacitor circuit enters the integration phase. The slew rate enhancement circuit compares VP and VM, determines whether VOP and VOM push or pull current, quickly changes the voltage of VOP and VOM, completes the transfer of charges on capacitors C1 and C2 to capacitors C3 and C4, and brings the voltage of VP and VM closer. When VP is close to VM, the fully differential operational amplifier has entered the small signal working area, and the slew rate enhancement circuit automatically stops working to prevent output voltage overshoot and slew rate enhancement circuit oscillation. Afterwards, to further prevent the slew rate enhancement circuit from affecting the main operational amplifier, CK2s is changed to 0 to completely shut it down. Finally, the switched capacitor circuit uses a fully differential operational amplifier to complete the small signal response and achieve high linearity operation.

[0020] like Figure 1As shown, the slew rate enhancement circuit includes a first slew rate enhancement module and a second slew rate enhancement module, which respectively provide push-out or pull-in currents for the positive and negative output terminals VOP and VOM of the fully differential operational amplifier. Both slew rate enhancement modules are composed of a comparator and a current output unit, and they are both controlled by a clock signal. The comparator is used to detect the difference between the VP and VM voltages, generate a signal to control the current output, determine the push-out or pull-in currents of VOP and VOM, and has an automatic shutdown function. The width-to-length ratios of the differential input pairs of the two comparators are different, the width-to-length ratio of M22 is greater than that of M23, and the width-to-length ratio of M5 is greater than that of M6. The current output unit generates a sufficiently large push-out or pull-in dynamic current to enhance the bidirectional slew rate of the fully differential operational amplifier.

[0021] When CK is at a low level, M3, M4, M20, and M21 are turned off, the two comparators are turned off, and no current is consumed; M10 and M27 are turned on, pulling the voltages of nodes VPP and VMM to a lower voltage; M12 and M29 are turned on, raising the voltages of nodes VP1 and VM1 to a higher voltage; M15, M16, M32, and M33 are turned off, and no current is pushed out or pulled into VOP and VOM, which does not affect the small signal frequency response of the fully differential operational amplifier.

[0022] When CK becomes high, M20, M21, M29, M4, M3, and M12 are turned on. Since VPP and VMM still maintain a low voltage, current flows through M7 and M24, providing bias current for the two comparators, and the two comparators work normally. If VP is much larger than VM, VPP rises to a high level quickly, VP1 drops to a low level quickly, VMM remains low, and VM1 remains high: VPP is high to turn off M24, the first comparator automatically stops working, no longer compares VP and VM, and automatically turns off, while M7 remains on, and the second comparator works normally; VPP is high to turn off M17, VP1 is low to turn off M31, M32, and M16, VMM is low to turn on M34, and VM1 is high to turn on M33, M14, and M15. At this time, the slew rate enhancement circuit pushes current from the VOP end and pulls current from the VOM end, forming a large dynamic current to help improve the slew rate. When VM is close to VP but not greater than VP, since the width-to-length ratio of M5 is greater than that of M6, VMM is raised to a high level, VM1 is reduced to a low level, the bias current of the second comparator is turned off, and VP and VM are no longer compared. All transistors of the first current output unit and the second current output unit are turned off, and the current pushed out of the VOP terminal and the current pulled in of the VOM terminal are turned off. At this time, the slew rate enhancement circuit completely stops working when VM is close to VP, and neither pushes out current nor pulls in current. Since both comparators have turned off the bias current, no matter how the values ​​of VM and VP change, the slew rate enhancement circuit will not push out or pull in current, thus avoiding output voltage overshoot and possible oscillation. If VM is much larger than VP, VMM rises to a high level quickly, VM1 drops to a low level quickly, VPP remains at a low level, and VP1 remains at a high level: VMM is at a high level to turn off M7, and the second comparator automatically stops working and no longer compares VP and VM, achieving automatic shutdown, while M24 remains on and the first comparator works normally; VMM is at a high level to turn off M34, VM1 is at a low level to turn off M14, M15 and M33, VPP is at a low level to turn on M17, and VP1 is at a high level to turn on M31, M32 and M16. At this time, the slew rate enhancement circuit pulls in current from the VOP end and pushes out current from the VOM end, forming a large dynamic current to help improve the slew rate. When VP is close to VM but not greater than VM, since the width-to-length ratio of M22 is greater than that of M23, VPP is raised to a high level, VP1 is reduced to a low level, the bias current of the first comparator is turned off, VP and VM are no longer compared, all transistors of the first current output unit and the second current output unit are turned off, and the VOP terminal pull-in current and the VOM terminal push-out current are turned off. At this time, the slew rate enhancement circuit completely stops working when VM is close to VP, and neither pushes out current nor pulls in current.Since both comparators shut off the bias current, no matter how the values ​​of VM and VP change, the slew rate enhancement circuit will not push or pull in current, avoiding output voltage overshoot and possible oscillation. If VP is close to VM, since the width-to-length ratio of M22 is greater than that of M23 and the width-to-length ratio of M5 is greater than that of M6, both VPP and VMM are quickly raised to a high level, and both VP1 and VM1 are quickly reduced to a low level, and the slew rate enhancement circuit is quickly turned off without affecting the outside.

[0023] Here is a more specific example:

[0024] A clock-controlled self-shutdown slew rate enhancement circuit, such as Figure 1 As shown, it includes two slew rate enhancement modules with similar structures, which are respectively used for slew rate enhancement at both ends of the full differential circuit, and each slew rate enhancement module includes a comparator and a current output unit.

[0025] In the first comparator in the first slew rate enhancement module, a first-stage single-ended output differential amplifier plays a comparison role. The width-to-length ratio of the in-phase input tube in the input pair is greater than that of the inverting input tube, so there is a preset input deviation voltage Vd, that is, when the in-phase input terminal VP is greater than the inverting input terminal VM minus the preset deviation voltage Vd, the first comparator output signal VPP is high level, otherwise it is low level; in addition, its bias current is controlled by the first comparator output signal VPP. When CK just changes from low level to high level, VPP is low level, and bias current flows through the first comparator. When VP is close to VM, VPP becomes high level, the bias current of the first comparator is turned off, VP and VM are no longer compared, and the VPP level remains high level; in addition, the first comparator output signals are VPP and VP1, which are controlled by the input clock signal CK. When CK is low or high level, VPP is low level and VP1 is high level, so as to prepare for the next comparator operation.

[0026] Specifically, the first comparator includes a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-second transistor M22, a twenty-third transistor M23, a twentieth transistor M20, a twenty-first transistor M21, an eighteenth transistor M18, a nineteenth transistor M19, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a twenty-ninth transistor M29, and a thirtieth transistor M30. The circuit connection relationship is as follows: the sources of the eighteenth transistor M18 and the nineteenth transistor M19 are connected to the ground, the gates of the eighteenth transistor M18 and the nineteenth transistor M19 are connected to the drain of the eighteenth transistor M18, the drain of the eighteenth transistor M18 is connected to the source of the twentieth transistor M20, the drain of the nineteenth transistor M19 is connected to the source of the twenty-first transistor M21, the gates of the twentieth transistor M20 and the twenty-first transistor M21 are connected to the input clock signal CK, the sources of the twenty-second transistor M22 and the twenty-third transistor M23 are connected to the drain of the twenty-first transistor M21, the gate of the twenty-second transistor M22 is connected to the input signal VP, the gate of the twenty-third transistor M23 is connected to the input signal VM, the drain of the twenty-second transistor M22 is connected to the drain of the twenty-fifth transistor M25, the sources of the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are connected to the power supply, the gates of the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are connected to the drain of the twenty-fifth transistor M25, and the gates of the twenty-third transistor M23 are connected to the drain of the twenty-fifth transistor M25. The drain of the transistor M23 is connected with the drain of the twenty-sixth transistor M26 as the output VPP of the first comparator, the drain of the twenty-fourth transistor M24 is connected to the drain of the twentieth transistor M20, the source of the twenty-fourth transistor M24 is connected to the power supply, the gate of the twenty-fourth transistor M24 is connected to the output signal VPP of the first comparator, the source of the twenty-seventh transistor M27 is connected to the first comparator output signal VPP, the gate of the twenty-seventh transistor M27 is connected to the input clock signal CK, the drain of the twenty-seventh transistor M27 is connected to the ground, the source of the twenty-eighth transistor M28 is connected to the power supply, the gate of the twenty-eighth transistor M28 is connected to the output signal VPP of the first comparator, the drain of the twenty-eighth transistor M28, the drain of the twenty-ninth transistor M29 and the gate of the thirtieth transistor M30 are connected together as the output VP1 of the first comparator, the gate of the twenty-ninth transistor M29 is connected to the input clock signal CK, the source of the twenty-ninth transistor M29 is connected to the drain of the thirtieth transistor M30, and the source of the thirtieth transistor M30 is connected to the ground. The width-to-length ratio of the twenty-second transistor M22 is greater than that of the twenty-third transistor M23 to achieve a preset input deviation voltage Vd.

[0027] In the second comparator in the second slew rate enhancement module, a first-stage single-ended output differential amplifier plays a comparison role. The width-to-length ratio of the in-phase input tube in the input pair is greater than that of the inverting input tube, so there is a preset input deviation voltage Vd, that is, when the in-phase input terminal VM is greater than the inverting input terminal VP minus the preset deviation voltage Vd, the second comparator output signal VMM is high level, otherwise it is low level; in addition, its bias current is controlled by the second comparator output signal VMM. When CK just changes from low level to high level, VMM is low level, and the second comparator has a bias current flowing through it. When VP and VM are close, VMM becomes high level, the bias current of the second comparator is turned off, and VP and VM are no longer compared, and the VMM level remains high level; in addition, the second comparator output signals are VMM and VM1, which are controlled by the input clock signal CK. When CK is low or high level, VMM is low level and VM1 is high level, ready for the next comparator operation.

[0028] Specifically, the second comparator includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a fifth transistor M5, a sixth transistor M6, a fourth transistor M4, a third transistor M3, a first transistor M1, a second transistor M2, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The circuit connection relationship is as follows: the sources of the first transistor M1 and the second transistor M2 are connected to the ground, the gates of the first transistor M1 and the second transistor M2 are connected to the drain of the first transistor M1, the drain of the first transistor M1 is connected to the source of the fourth transistor M4, the drain of the second transistor M2 is connected to the source of the third transistor M3, the gates of the fourth transistor M4 and the third transistor M3 are connected to the input clock signal CK, the sources of the fifth transistor M5 and the sixth transistor M6 are connected to the drain of the third transistor M3, the gate of the fifth transistor M5 is connected to the input signal VM, the gate of the sixth transistor M6 is connected to the input signal VP, the drain of the fifth transistor M5 is connected to the drain of the eighth transistor M8, the sources of the eighth transistor M8 and the ninth transistor M9 are connected to the power supply, the gates of the eighth transistor M8 and the ninth transistor M9 are connected to the drain of the eighth transistor M8, the drain of the sixth transistor M6 and the drain of the ninth transistor M9 are connected to the drain of the eighth transistor M8, The drain of the seventh transistor M7 is connected to the drain of the fourth transistor M4, the source of the seventh transistor M7 is connected to the power supply, the gate of the seventh transistor M7 is connected to the output signal VMM of the second comparator, the source of the tenth transistor M10 is connected to the output signal VMM of the second comparator, the gate of the tenth transistor M10 is connected to the input clock signal CK, the drain of the tenth transistor M10 is connected to the ground, the source of the eleventh transistor M11 is connected to the power supply, the gate of the eleventh transistor M11 is connected to the output signal VMM of the second comparator, the drain of the eleventh transistor M11, the drain of the twelfth transistor M12 and the gate of the thirteenth transistor M13 are connected together as the output VM1 of the second comparator, the gate of the twelfth transistor M12 is connected to the input clock signal CK, the source of the twelfth transistor M12 is connected to the drain of the thirteenth transistor M13, and the source of the thirteenth transistor M13 is connected to the ground. The width-to-length ratio of the fifth transistor M5 is greater than that of the sixth transistor M6 to achieve the preset input deviation voltage Vd.

[0029] The first current output unit in the first slew rate enhancement module is controlled by the first comparator output signals VPP and VP1, the second comparator output signals VMM and VM1, and the clock signal CK, and pushes or pulls current to the differential output terminal VOP to enhance the slew rate of the overall circuit.

[0030] Specifically, the first current output unit includes a thirty-first transistor M31, a thirty-second transistor M32, a thirty-third transistor M33, a thirty-fourth transistor M34, a first NAND gate X11, and a first AND gate X01. The circuit connection relationship is as follows: the source of the thirty-first transistor M31 is connected to the ground, the gate of the thirty-first transistor M31 is connected to the first comparator output signal VP1, the drain of the thirty-first transistor M31 is connected to the source of the thirty-second transistor M32, the source of the thirty-fourth transistor M34 is connected to the power supply, the gate of the thirty-fourth transistor M34 is connected to the second comparator output signal VMM, the drain of the thirty-fourth transistor M34 is connected to the source of the thirty-third transistor M33, the drain of the thirty-third transistor M33 and the drain of the thirty-second transistor M32 are connected together as the output terminal VOP of the first current output unit, the two inputs of the first NAND gate X11 are respectively the input clock signal CK and the output signal VM1 of the second comparator, the output of the first NAND gate X11 is connected to the gate of the thirty-third transistor M33, the two inputs of the first AND gate X01 are respectively the input clock signal CK and the output signal VP1 of the first comparator, and the output of the first AND gate X01 is connected to the gate of the thirty-second transistor M32.

[0031] The second current output unit in the second slew rate enhancement module is controlled by the first comparator output signals VPP and VP1, the second comparator output signals VMM and VM1, and the clock signal CK, and pushes or pulls current to the differential output terminal VOM to enhance the slew rate of the overall circuit.

[0032] Specifically, the second current output unit includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, a second NAND gate X12, and a second AND gate X02. The circuit connection relationship is as follows: the source of the fourteenth transistor M14 is connected to the ground, the gate of the fourteenth transistor M14 is connected to the second comparator output signal VM1, the drain of the fourteenth transistor M14 is connected to the source of the fifteenth transistor M15, the source of the seventeenth transistor M17 is connected to the power supply, the gate of the seventeenth transistor M17 is connected to the first comparator output signal VPP, the drain of the seventeenth transistor M17 is connected to the source of the sixteenth transistor M16, the drain of the sixteenth transistor M16 and the drain of the fifteenth transistor M15 are connected together as the output terminal VOM of the second current output unit, the two inputs of the second NAND gate X12 are respectively the input clock signal CK and the output signal VP1 of the first comparator, the output of the second NAND gate X12 is connected to the gate of the sixteenth transistor M16, the two inputs of the second AND gate X02 are respectively the input clock signal CK and the output signal VM1 of the second comparator, and the output of the second AND gate X02 is connected to the gate of the fifteenth transistor M15.

[0033] In summary, the present invention uses two slew rate enhancement modules to enhance the bidirectional slew rate at the positive and negative ends of the fully differential operational amplifier respectively; each slew rate enhancement module includes a self-shutdown comparator amplifier and a current output unit; the self-shutdown comparator is used to detect the polarity of the input large signal, generate positive and negative slew rate enhancement control signals, and automatically shut down after one comparison without affecting the small signal response; the current output unit is used to generate a pull-out current to achieve bidirectional slew rate enhancement; the entire slew rate enhancement circuit can be turned on or off by clock control.

[0034] The present invention can be used in parallel with a fully differential operational amplifier to improve its bidirectional slew rate without generating static power consumption and affecting the small signal frequency characteristics. The present invention has clock control and self-shutdown functions, which can better ensure that the main circuit is not affected by the slew rate enhancement circuit and prevent overcharging and oscillation.

[0035] The above description of the embodiments in combination with the accompanying drawings is intended to facilitate understanding of the innovative essence of the present invention, but is not intended to limit the diverse implementation methods of the present invention and the scope of protection of the claims. Any design that understands the present invention and performs equivalent structural changes or component replacements based on the above embodiments and can achieve the same purpose and effect shall be deemed to infringe the protection content of this patent application.

Claims

1. A clock-controlled self-shutdown slew rate enhancement circuit, characterized in that: Applied in a fully differential switched capacitor circuit, comprising a first slew rate enhancement module and a second slew rate enhancement module; the first slew rate enhancement module comprises a first comparator and a first current output unit, and the second slew rate enhancement module comprises a second comparator and a second current output unit; The first comparator includes a twenty-fourth transistor (M24), a twenty-fifth transistor (M25), a twenty-sixth transistor (M26), a twenty-second transistor (M22), a twenty-third transistor (M23), a twentieth transistor (M20), a twenty-first transistor (M21), an eighteenth transistor (M18), a nineteenth transistor (M19), a twenty-seventh transistor (M27), a twenty-eighth transistor (M28), a twenty-ninth transistor (M29), and a thirtieth transistor (M30);The sources of the eighteenth transistor (M18) and the nineteenth transistor (M19) are connected to the ground, the gates of the eighteenth transistor (M18) and the nineteenth transistor (M19) are connected to the drain of the eighteenth transistor (M18), the drain of the eighteenth transistor (M18) is connected to the source of the twentieth transistor (M20), the drain of the nineteenth transistor (M19) is connected to the source of the twenty-first transistor (M21), the gates of the twentieth transistor (M20) and the twenty-first transistor (M21) are connected to the input clock signal (CK), the sources of the twenty-second transistor (M22) and the twenty-third transistor (M23) are connected to the source of the twenty-first transistor (M21). The drain of the twenty-second transistor (M21) is connected to the first input signal (VP) of the fully differential switched capacitor circuit, the gate of the twenty-third transistor (M23) is connected to the second input signal (VM) of the fully differential switched capacitor circuit, the drain of the twenty-second transistor (M22) is connected to the drain of the twenty-fifth transistor (M25), the sources of the twenty-fifth transistor (M25) and the twenty-sixth transistor (M26) are connected to the power supply, the gates of the twenty-fifth transistor (M25) and the twenty-sixth transistor (M26) are connected together to the drain of the twenty-fifth transistor (M25), and the drain of the twenty-third transistor (M23) is connected to the drain of the twenty-sixth transistor (M26). The drains of the transistors (M26) are connected together as the first output (VPP) of the first comparator, the drain of the twenty-fourth transistor (M24) is connected to the drain of the twentieth transistor (M20), the source of the twenty-fourth transistor (M24) is connected to the power supply, the gate of the twenty-fourth transistor (M24) is connected to the first output (VPP) of the first comparator, the source of the twenty-seventh transistor (M27) is connected to the first output (VPP) of the first comparator, the gate of the twenty-seventh transistor (M27) is connected to the input clock signal (CK), the drain of the twenty-seventh transistor (M27) is connected to the ground, the source of the twenty-eighth transistor (M28) is connected to the power supply, and the second The gate of the eighteenth transistor (M28) is connected to the first output (VPP) of the first comparator, the drain of the twenty-eighth transistor (M28), the drain of the twenty-ninth transistor (M29) and the gate of the thirtieth transistor (M30) are connected together as the second output (VP1) of the first comparator, the gate of the twenty-ninth transistor (M29) is connected to the input clock signal (CK), the source of the twenty-ninth transistor (M29) is connected to the drain of the thirtieth transistor (M30), the source of the thirtieth transistor (M30) is connected to the ground, and the width-to-length ratio of the twenty-second transistor (M22) is greater than that of the twenty-third transistor (M23) to achieve a preset input deviation voltage; The second comparator comprises a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a fifth transistor (M5), a sixth transistor (M6), a fourth transistor (M4), a third transistor (M3), a first transistor (M1), a second transistor (M2), a tenth transistor (M10), an eleventh transistor (M11), a twelfth transistor (M12), and a thirteenth transistor (M13); wherein the sources of the first transistor (M1) and the second transistor (M2) are connected to the ground, the gates of the first transistor (M1) and the second transistor (M2) are connected together to the drain of the first transistor (M1), and the drain of the first transistor (M1) is connected to the fourth transistor ( The source of the second transistor (M4) is connected to the source of the third transistor (M3), the drain of the second transistor (M2) is connected to the source of the third transistor (M3), the gate of the fourth transistor (M4) and the gate of the third transistor (M3) are connected to the input clock signal (CK), the source of the fifth transistor (M5) and the sixth transistor (M6) are connected to the drain of the third transistor (M3), the gate of the fifth transistor (M5) is connected to the second input signal (VM) of the fully differential switched capacitor circuit, the gate of the sixth transistor (M6) is connected to the first input signal (VP) of the fully differential switched capacitor circuit, the drain of the fifth transistor (M5) is connected to the drain of the eighth transistor (M8), and the sources of the eighth transistor (M8) and the ninth transistor (M9) are connected to the power supply The gates of the eighth transistor (M8) and the ninth transistor (M9) are connected together to the drain of the eighth transistor (M8), the drain of the sixth transistor (M6) and the drain of the ninth transistor (M9) are connected together as the first output (VMM) of the second comparator, the drain of the seventh transistor (M7) is connected to the drain of the fourth transistor (M4), the source of the seventh transistor (M7) is connected to the power supply, the gate of the seventh transistor (M7) is connected to the first output (VMM) of the second comparator, the source of the tenth transistor (M10) is connected to the first output (VMM) of the second comparator, the gate of the tenth transistor (M10) is connected to the input clock signal (CK), and the drain of the tenth transistor (M10) is connected to the input clock signal (CK). grounded, the source of the eleventh transistor (M11) is connected to the power supply, the gate of the eleventh transistor (M11) is connected to the first output (VMM) of the second comparator, the drain of the eleventh transistor (M11), the drain of the twelfth transistor (M12) and the gate of the thirteenth transistor (M13) are connected together as the second output (VM1) of the second comparator, the gate of the twelfth transistor (M12) is connected to the input clock signal (CK), the source of the twelfth transistor (M12) is connected to the drain of the thirteenth transistor (M13), the source of the thirteenth transistor (M13) is connected to the ground, and the width-to-length ratio of the fifth transistor (M5) is greater than that of the sixth transistor (M6) to achieve a preset input deviation voltage; The first current output unit comprises a thirty-first transistor (M31), a thirty-second transistor (M32), a thirty-third transistor (M33), a thirty-fourth transistor (M34), a first NAND gate (X11), and a first AND gate (X01); wherein the source of the thirty-first transistor (M31) is connected to the ground, the gate of the thirty-first transistor (M31) is connected to the second output (VP1) of the first comparator, the drain of the thirty-first transistor (M31) is connected to the source of the thirty-second transistor (M32), the source of the thirty-fourth transistor (M34) is connected to the power supply, the gate of the thirty-fourth transistor (M34) is connected to the first output (VMM) of the second comparator, and the thirty-fourth transistor ( The drain of the first transistor (M34) is connected to the source of the third transistor (M33), the drain of the third transistor (M33) and the drain of the third transistor (M32) are connected together as the output end (VOP) of the first current output unit, the two inputs of the first NAND gate (X11) are the input clock signal (CK) and the second output (VM1) of the second comparator, the output of the first NAND gate (X11) is connected to the gate of the third transistor (M33), the two inputs of the first AND gate (X01) are the input clock signal (CK) and the second output (VP1) of the first comparator, and the output of the first AND gate (X01) is connected to the gate of the third transistor (M32); The second current output unit comprises a fourteenth transistor (M14), a fifteenth transistor (M15), a sixteenth transistor (M16), a seventeenth transistor (M17), a second NAND gate (X12), and a second AND gate (X02); wherein the source of the fourteenth transistor (M14) is connected to the ground, the gate of the fourteenth transistor (M14) is connected to the second output (VM1) of the second comparator, the drain of the fourteenth transistor (M14) is connected to the source of the fifteenth transistor (M15), the source of the seventeenth transistor (M17) is connected to the power supply, the gate of the seventeenth transistor (M17) is connected to the first output (VPP) of the first comparator, and the seventeenth transistor (M17) is connected to the first output (VPP) of the first comparator. ) is connected to the source of the sixteenth transistor (M16), the drain of the sixteenth transistor (M16) and the drain of the fifteenth transistor (M15) are connected together as the output end (VOM) of the second current output unit, the two inputs of the second NAND gate (X12) are the input clock signal (CK) and the second output (VP1) of the first comparator, the output of the second NAND gate (X12) is connected to the gate of the sixteenth transistor (M16), the two inputs of the second AND gate (X02) are the input clock signal (CK) and the second output (VM1) of the second comparator, and the output of the second AND gate (X02) is connected to the gate of the fifteenth transistor (M15).

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