Rapid reset circuit suitable for flight control system

Abstract

The invention provides a quick reset circuit suitable for a flight control system, and belongs to the technical field of airborne computers, the quick reset circuit specifically comprises a line and circuit, an RC circuit and an anti-shake circuit which are connected in sequence, the line and circuit comprises a power input end, a reset signal source end, a first resistor, a second resistor and a first diode, the RC circuit comprises a third resistor and a second capacitor, and the anti-shake circuit comprises a second resistor and a third capacitor. The reset signal source end comprises an output voltage good indication signal end and a power failure reset signal end; the reset time can be configured by controlling the resistance value of the third resistor and the capacitance value of the second capacitor, and the output signal is generated when the change edge of the input signal reaches the minimum value through the anti-shake circuit. Through the processing scheme provided by the invention, the application requirements of quick start and reset of the flight control system are met, the reset time is configurable, and the over-high cost caused by using a special chip is avoided; and a jitter-removing circuit is adopted, so that serious hidden dangers of repeated resetting are avoided, and the circuit reliability is improved.

Description

Technical Field

[0001] The present application relates to the technical field of airborne computers, and in particular to a fast reset circuit suitable for a flight control system. Background Art

[0002] In digital circuit systems, reset is a very important and basic function. It is often the first function executed after the circuit is powered on. In the reset circuit design of the flight control system, there are often very strict requirements on the power-on startup time of the system. Due to the special application scenarios of the flight control system, most products need to have fast power-on startup and reset time. Once the reset time required by the system is within 200ms, the commonly used reset chips (MAX791, MAX706, etc.) will inevitably fail to meet the requirements of fast startup due to the internal fixed reset time of 200ms. For this type of application scenario, there is currently no low-cost and high-reliability mature design. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a fast reset circuit suitable for a flight control system, which is used in application scenarios where the flight control system requires a fast startup and fast reset time for the product, to solve the problem of long reset time of a traditional reset chip.

[0004] The embodiment of the present application provides a fast reset circuit suitable for a flight control system, the circuit comprising a line and circuit, an RC circuit and an anti-shake circuit connected in sequence, the line and circuit comprising a power input terminal, a reset signal source terminal, a first resistor, a second resistor and a first diode, the RC circuit comprising a third resistor and a second capacitor, the reset signal source terminal comprising an output voltage good indication signal terminal and a power-off reset signal terminal, the output voltage good indication signal terminal is connected in series with a diode and is respectively connected to one end of the first resistor and the cathode of the first diode, the other end of the first resistor is connected to the input power terminal, the power-off reset signal terminal is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the anode of the first diode; one end of the third resistor is connected to the power input terminal, the other end of the third resistor is connected to one end of the second capacitor, the other end of the second capacitor is grounded, and the midpoint of the third resistor and the second capacitor is respectively connected to the anode of the first diode, the other end of the second resistor and the anti-shake circuit; by controlling the resistance value of the third resistor and the capacitance value of the second capacitor, the reset time is configurable, and the anti-shake circuit is used to generate an output signal when the input signal change edge reaches the minimum value.

[0005] According to a specific implementation method of an embodiment of the present application, the line and circuit also includes a second diode, the cathode of the second diode is connected to the power input terminal, and the anode of the second diode is respectively connected to the anode of the first diode, the other end of the second resistor, and the midpoint of the third resistor and the second capacitor.

[0006] According to a specific implementation of the embodiment of the present application, the anti-shake circuit includes a Schmitt trigger.

[0007] According to a specific implementation of the embodiment of the present application, the anti-shake circuit further includes a first capacitor, which is connected in parallel between the power supply and the ground.

[0008] According to a specific implementation of the embodiment of the present application, the Schmitt trigger is configured as a six-channel Schmitt trigger, and each channel provides a NOT gate operation function.

[0009] According to a specific implementation of the embodiment of the present application, the reset time is within 200ms.

[0010] According to a specific implementation method of an embodiment of the present application, the output voltage good indication signal is generated by the power supply system of the external circuit. When its output voltage reaches within the error range of ±10% of the rated value, the output voltage good indication signal is high level; when its output voltage exceeds the error range of ±10% of the rated value, the output voltage good indication signal is low level.

[0011] According to a specific implementation method of an embodiment of the present application, the power-off reset signal is generated by a control logic circuit of an external module. When the power-off reset signal is at a high level, it represents that the external circuit is working normally and the reset function is invalid; when the power-off reset signal is at a low level, it represents that the external circuit is abnormal or the power is off normally, and the reset function is valid.

[0012] Beneficial effects:

[0013] The fast reset circuit suitable for the flight control system in the embodiment of the present application can realize the functional requirements of fast startup and reset of the flight control system, and the reset time is configurable. It is functionally divided into three levels of processing: line and circuit, RC circuit, and anti-shake circuit; the function "AND" of multiple reset sources is realized in the line and circuit to ensure that all reset sources can effectively reset the product; the RC circuit realizes the slow climb of the signal from a low level to a high level, and the climb time is determined by the configuration of the resistor and the capacitor to ensure that the startup time is configurable; it is equipped with an anti-shake circuit to generate an output signal when the input signal changes along the minimum value, and has a wider tolerance threshold for signal noise, which can achieve a certain noise reduction and de-shake effect; it can support a reset time of less than 200ms, and has high portability, and only needs to adaptively modify the circuit parameters to be applied to various fast startup and reset circuit designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 is a structural diagram of a fast reset circuit applicable to a flight control system according to an embodiment of the present invention;

[0016] Figure 2 A schematic diagram of a power-on reset signal waveform according to an embodiment of the present invention;

[0017] Figure 3 FIG. 4 is a diagram showing fast reset simulation results according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0019] The following describes the implementation methods of the present application through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0020] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0021] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0022] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0023] In digital circuit systems, reset is a very important and basic function. It is often the first function executed after the circuit is powered on. Common reset methods are:

[0024] (1) Power-on reset / power-off reset: Power-on reset ensures that the system is in a certain initial state, allowing the processor to start the software program from a pre-set address, ultimately ensuring that the entire processor enters a normal working state. In addition, when the chip encounters a low power supply voltage during the power-on process or during operation, a reset signal is also required to prevent the chip from operating in an abnormal and unstable state;

[0025] (2) Watchdog reset: To prevent the program from looping or running away, after the system is powered on and the program starts running, the processor timing circuit starts counting automatically. The program design has a "feed the dog" function that resets the timing circuit at regular intervals. If the program loops or runs away, the code in the program that resets the timing circuit will not be executed, and the watchdog reset circuit will be started to output a system reset signal to reset the system;

[0026] (3) Manual reset: This method uses the hardware button / switch in the circuit to generate a reset signal, thereby resetting the circuit. It is often used to restart the system from an abnormal state during debugging.

[0027] The circuit described in this application is a "power-on reset" working mode. Figures 1 to 3 The fast reset circuit applicable to the flight control system of the present application is described in detail.

[0028] In one embodiment, a fast reset circuit suitable for a flight control system includes a line and circuit, an RC circuit and an anti-shake circuit connected in sequence, wherein the line and circuit includes a power input terminal, a reset signal source terminal, a first resistor R5, a second resistor R6 and a first diode V1, the RC circuit includes a third resistor R7 and a second capacitor C2, and the reset signal source terminal includes an output voltage good indication signal terminal ( Figure 1The output voltage good indication signal terminal is connected in series with a diode and is respectively connected to one end of the first resistor R5 and the cathode of the first diode V1, the other end of the first resistor R5 is connected to the input power supply terminal, the power-off reset signal terminal is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the anode of the first diode V1; one end of the third resistor R7 is connected to the power input terminal, the other end of the third resistor R7 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, and the midpoint of the third resistor R7 and the second capacitor C2 is respectively connected to the anode of the first diode V1, the other end of the second resistor R6 and the anti-shake circuit; by controlling the resistance value of the third resistor R7 and the capacitance value of the second capacitor C2, the reset time is configurable, and the anti-shake circuit is used to generate an output signal when the input signal changes along the minimum value.

[0029] In this embodiment, the function of "AND" of multiple reset sources is implemented in the online AND circuit to ensure that all reset sources can effectively reset the product. The reset sources mainly include normal voltage indication, power-off indication, and FPGA loading completion signal; the RC circuit realizes a slow climb of the signal from 0 to 1, and the climb time is determined by the configuration of the resistor and the capacitor, which is the start-up time of the circuit; the signal can also be quickly discharged from 1 to 0, and the power-off time is determined by the configuration of the resistor and the capacitor, which is the power-off time of the circuit; the anti-shake circuit realizes the generation of an output signal when the input signal changes along the minimum value, and has a wider tolerance threshold for signal noise, which can achieve a certain noise reduction and de-shake effect.

[0030] Furthermore, the line and circuit also includes a second diode V2, the cathode of the second diode V2 is connected to the power input terminal, and the anode of the second diode V2 is respectively connected to the anode of the first diode V1, the other end of the second resistor R6, and the midpoint of the third resistor R7 and the second capacitor C2. The circuit is designed with a fast discharge reverse diode (the second diode V2) to ensure that it can discharge quickly when the system is powered off, so as to avoid the phenomenon of being unable to reset due to frequent power-on, and further improve the circuit stability and reliability.

[0031] Furthermore, the anti-shake circuit includes a Schmitt trigger. Preferably, the Schmitt trigger is configured as a six-channel Schmitt trigger, each channel providing a NOT gate operation function, such as a JC54AC14F chip.

[0032] Furthermore, the anti-shake circuit further includes a first capacitor C1, and the first capacitor C1 is connected in parallel between the power supply and the ground.

[0033] In one embodiment, the reset time is within 200 ms.

[0034] In one embodiment, the output voltage good indication signal is generated by the power supply system of the external circuit. When its output voltage reaches within the error range of ±10% of the rated value, the output voltage good indication signal is high level; when its output voltage exceeds the error range of ±10% of the rated value, the output voltage good indication signal is low level.

[0035] In one embodiment, the power-off reset signal is generated by a control logic circuit of an external module. When the power-off reset signal is at a high level, it indicates that the external circuit is operating normally and the reset function is invalid. When the power-off reset signal is at a low level, it indicates that the external circuit is abnormal or the power is off normally and the reset function is valid.

[0036] The present application provides a high-reliability fast reset circuit suitable for a flight control system, wherein the reset time is configurable, and is divided into three levels of processing in hardware: line and circuit, RC circuit, and anti-shake circuit, so that the system can ultimately support fast startup and reset with configurable time. By designing three-layer processing of line and circuit, RC circuit, and anti-shake circuit, the application requirements of fast startup and reset of the flight control system are realized, and the reset time is configurable, avoiding the high cost caused by the use of dedicated chips. At the same time, the design adopts a de-shaking circuit to prevent jitter near the threshold voltage threshold and avoid the serious hidden dangers of repeated reset. The circuit has high reliability and provides a solution to the demand for fast startup of the flight control system. The circuit of the present application has high portability and can be applied to various monitoring system circuits. It has certain promotion and use value for application scenarios with time requirements for the startup and reset of the flight control system.

[0037] In specific implementation, the reset signal sources of this circuit are divided into two categories, namely:

[0038] a. Output voltage good indication signal: It comes from the power supply system of the external circuit. This type of signal is generally generated by the power conversion chip. When its output voltage reaches the ±10% error range of the rated value (for example: the +2.5V output signal is between +2.25V and +2.75V), the good indication signal is "high level" (pulled up to +3.3V); when the output voltage exceeds the error range, the good indication signal is "low level" (about 0V); the output signal of this embodiment also includes 3.3V output signal, 1.5V output signal and 1.8V output signal;

[0039] b. Power-off reset signal: It comes from the control logic circuit of the external module, generally generated by the FPGA chip. When the signal is "high level", it means that the external circuit is working normally and the reset function is invalid; when the signal is "low level", it means that the external circuit has encountered an abnormal / normal power failure and the reset function is valid.

[0040] The above two types of reset signal sources can be valid at the same time (such as: complete product), or only the first type of signal source can be valid (such as: module product).

[0041] exist Figure 1 In the figure, the voltage VA at point A is determined by the output voltage good indication signal, that is: when any output voltage good indication signal is "low level" at a certain moment, due to the pull-up resistor R5, the current will flow to the indication signal at "low level", and VA will be approximately equal to 0V; when all output voltage good indication signals are "high level" at a certain moment, due to the no voltage difference across the pull-up resistor R5, VA will be +3.3V.

[0042] According to the different states of the power-down reset signal, Figure 1 The voltage VB at point B will have the following results:

[0043] (1) The voltage VA at point A is approximately equal to 0V:

[0044] The reset signal PW_DOWN_RST_I N# is +3.3V: Since VA is approximately equal to 0V, under the action of the pull-up resistor R7, the diode V1 will be turned on, and its forward voltage drop is about 0.41V, that is, the voltage VB at point B is also about 0.41V, which is less than the minimum forward threshold voltage of the JC54AC14F chip 0.8V. Therefore, the power-on reset output PW_RST obtained by the RST_I N signal after two NOT gate operations is still 0V;

[0045] The reset signal PW_DOWN_RST_I N# is 0V: Since VA is approximately equal to 0V, and the resistance of the series resistor R6 is much larger than the on-resistance of the diode V1, the diode V1 will be turned on under the action of the pull-up resistor R7, and the current flowing through the series resistor R6 can be ignored. Since the forward voltage drop of the diode V1 is about 0.41V at this time, that is, the voltage VB at point B is also about 0.41V, which is less than the minimum forward threshold voltage of the JC54AC14F chip of 0.8V, the power-on reset PW_RST of RST_I N is still 0V after passing through two NOT gates;

[0046] The reset signal PW_DOWN_RST_I N# is open or "high impedance": Since VA is approximately equal to 0V and the current will not flow through the series resistor R6, under the action of the pull-up resistor R7, the diode V1 will be turned on, and its forward voltage drop is approximately 0V, that is, the voltage VB at point B is also approximately 0V, which is less than the minimum forward threshold voltage of the JC54AC14F chip 0.8V, and the power-on reset PW_RST is still 0V after RST_I N passes through two NOT gates;

[0047] (2) The voltage VA at point A is approximately equal to +3.3V:

[0048] The reset signal PW_DOWN_RST_I N# is +3.3V: Since the voltage values ​​of VA and VB are equal at this time, both are +3.3V, the diode V1 will be cut off. At this time, the pull-up resistor R7 and the capacitor C2 will form an RC circuit, and the +3.3V power supply will charge the capacitor C2. The voltage value of the RST_I N signal will gradually rise from 0V, and the charging time t required to reach the instantaneous voltage value Vt can be calculated by formula (1). When Vt rises above the minimum positive threshold voltage of 0.8V of the JC54AC14F chip, the power-on reset output PW_RST obtained by the RST_I N signal after two NOT gate operations will also gradually rise from 0V. When the RST_I N signal rises to +3.3V due to the completion of the charging of the capacitor C2, the power-on reset output PW_RST will also reach +3.3V;

[0049]

[0050] Where, t is the charging time required to reach the instantaneous voltage Vt, s;

[0051] R——Resistance in RC circuit, Ω;

[0052] C——capacitance in RC circuit, F;

[0053] V1——the voltage value reached when the capacitor is fully charged, V;

[0054] V0——The initial voltage value when the capacitor starts charging, V;

[0055] V t ——The instantaneous voltage value reached when the capacitor is charged, V.

[0056] Let R=470kΩ, C=0.1uF, V1=3.3V, V0=0V, V t =0.8V, then according to formula (1), it can be obtained that the time required for capacitor C2 to be charged to +0.8V is about 13ms;

[0057] The reset signal PW_DOWN_RST_I N# is 0V: Since the diode V1 is cut off, under the combined effect of the pull-up resistor R7 and the series resistor R6, the current will flow to the reset signal PW_DOWN_RST_I N#. Since the resistance of R7 is much greater than that of R6, the voltage VB at point B will drop to about 3mV, and the power-on reset output PW_RST obtained after the RST_I N signal undergoes two NOT gate operations will also drop to 0V;

[0058] The reset signal PW_DOWN_RST_I N# is open or "high impedance state": since the current will not flow through the series resistor R6 and the diode V1 is cut off, the voltage VB at point B is also stabilized at +3.3V under the action of the pull-up resistor R7, and the power-on reset output PW_RST obtained by the RST_I N signal after two NOT gate operations is still +3.3V.

[0059] In summary, starting from the +3.3V DC power supply, the working principle of the reset output signal is as follows: Figure 2 The time parameters are shown in Table 1.

[0060] Table 1 Power-on reset signal time parameters

[0061]

[0062] In the de-jitter circuit, a six-channel Schmitt trigger chip (D1) is used, and each channel can provide a NOT gate operation function. This chip can generate an output signal when the input signal changes along the minimum value, and has a wider tolerance threshold for signal noise, which can achieve a certain noise reduction and de-jitter effect. For example: when the input signal is raised, there are multiple noise jitters in the range of +0.8V to +2.2V, and the JC54AC14F chip can still stably output a "high level", which is equivalent to removing the influence of signal noise.

[0063] Figure 1 In the figure, a diode V2 is connected from the RST_IN signal to the +3.3V power supply signal. Its function is to allow the capacitor C2 to quickly discharge into the power supply system when the entire system is powered off, to prevent the capacitor C2 from being completely discharged when it is powered on again quickly after power off. From formula (1), it can be seen that at this time, there is an initial voltage on the capacitor C2, which will affect the duration of the reset signal, and ultimately lead to insufficient system power-on reset time, causing system operation disorder.

[0064] The embodiment provided by the present invention can realize the functional requirements of fast startup and reset of the flight control system, and the reset time is configurable. It is functionally divided into three levels of processing: line and circuit, RC circuit, and anti-shake circuit;

[0065] The present invention implements the function "AND" of multiple reset sources in an online AND circuit to ensure that all reset sources can effectively reset the product. The reset sources mainly include a normal voltage indication, a power-off indication, an FPGA loading completion signal, etc.

[0066] The RC circuit of the present invention realizes the slow rise of the signal from a low level to a high level, and the rise time is determined by the configuration of the resistor and the capacitor, ensuring that the start-up time is configurable;

[0067] The present invention is equipped with an anti-shake circuit, which can realize generating an output signal when the input signal changes and reaches the minimum value, and has a wider tolerance threshold for signal noise, thereby achieving a certain noise reduction and de-shaking effect;

[0068] The present invention can support a reset time within 200ms and has high portability. It can be applied to various quick start and reset circuit designs by only adaptively modifying circuit parameters.

[0069] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A fast reset circuit suitable for a flight control system, characterized in that: The circuit includes a line-and-circuit, an RC circuit and an anti-shake circuit connected in sequence. The line-and-circuit includes a power input terminal, a reset signal source terminal, a first resistor, a second resistor and a first diode. The RC circuit includes a third resistor and a second capacitor. The reset signal source terminal includes an output voltage good indication signal terminal and a power-off reset signal terminal. The output voltage good indication signal terminal is connected in series with a diode and is respectively connected to one end of the first resistor and the cathode of the first diode. The other end of the first resistor is connected to the input power terminal, the power-off reset signal terminal is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the anode of the first diode; one end of the third resistor is connected to the power input terminal, the other end of the third resistor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded. The midpoint of the third resistor and the second capacitor is respectively connected to the anode of the first diode, the other end of the second resistor and the anti-shake circuit; by controlling the resistance value of the third resistor and the capacitance value of the second capacitor, the reset time is configurable, and the anti-shake circuit is used to generate an output signal when the input signal change edge reaches the minimum value.

2. The fast reset circuit suitable for a flight control system according to claim 1, characterized in that: The line and circuit also includes a second diode, the cathode of the second diode is connected to the power input terminal, and the anode of the second diode is respectively connected to the anode of the first diode, the other end of the second resistor, and the midpoint of the third resistor and the second capacitor.

3. The fast reset circuit suitable for a flight control system according to claim 1, characterized in that: The anti-shake circuit includes a Schmitt trigger.

4. The fast reset circuit suitable for a flight control system according to claim 3, characterized in that: The anti-shake circuit also includes a first capacitor connected in parallel between the power supply and the ground.

5. The fast reset circuit suitable for a flight control system according to claim 3, characterized in that: The Schmitt trigger is configured as a six-channel Schmitt trigger, and each channel provides a NOT gate operation function.

6. The fast reset circuit suitable for a flight control system according to claim 1, characterized in that: The reset time is within 200ms.

7. The fast reset circuit suitable for a flight control system according to claim 1, characterized in that: The output voltage good indication signal is generated by the power supply system of the external circuit. When its output voltage reaches the error range of ±10% of the rated value, the output voltage good indication signal is high level. When its output voltage exceeds the error range of ±10% of the rated value, the output voltage good indication signal is low level.

8. The fast reset circuit suitable for a flight control system according to claim 1, characterized in that: The power-off reset signal is generated by the control logic circuit of the external module. When the power-off reset signal is at a high level, it means that the external circuit is working normally and the reset function is invalid; when the power-off reset signal is at a low level, it means that the external circuit is abnormal or the power is off normally, and the reset function is valid.

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