Clock circuit phase drift compensation circuit, clock chip, array and system

Abstract

The embodiment of the invention provides a clock circuit phase drift compensation circuit, a clock chip, an array and a system, and the clock circuit phase drift compensation circuit comprises a phase frequency detector which obtains a reference clock signal and a feedback clock signal, and determines an error voltage signal based on the reference clock signal and the feedback clock signal; the filter is used for filtering the transmitted error voltage signal; the voltage-controlled oscillator receives the filtered error voltage signal and adjusts the frequency of the current clock signal according to the error voltage signal; the buffer is connected with the output end of the voltage-controlled oscillator; feedback branches connected with the multiplexer are respectively arranged behind the multiplexer, the voltage-controlled oscillator and the buffer; and the frequency divider is connected between the multiplexers and the phase frequency detectors, carries out frequency division on the signals of the feedback branches selected by the multiplexers to obtain feedback clock signals, and sends the feedback clock signals to the phase frequency detectors.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a clock circuit phase drift compensation circuit, a clock chip, a clock array and a digital beamforming system. Background Art

[0002] In digital beamforming systems, in addition to frequency synchronization of multiple clocks, the system also requires phase synchronization accuracy. Amplifiers, buffers and other components in the clock circuit are easily affected by temperature fluctuations, resulting in phase drift, which can lead to poor clock phase synchronization or even failure to synchronize, and large deviations in data information.

[0003] The current compensation method to solve the phase drift problem of clock circuits is usually the acquisition + correction method: first, the main control unit controls the analog-to-digital converter (ADC) to collect various clock signals, and the phase drift of each clock signal relative to the main clock signal is calculated by comparison, and then the main control unit sends and corrects the phase drift to achieve the purpose of meeting the clock phase synchronization accuracy. However, this method requires additional hardware components and logic resources, and is a static calculation process that cannot achieve dynamic synchronization, resulting in disadvantages such as high cost and lack of real-time performance. Summary of the invention

[0004] In order to solve the existing technical problems, the present application provides a clock circuit phase drift compensation circuit, clock chip, clock array and digital beamforming system with low cost, which can dynamically adjust the clock circuit phase drift in real time to improve the clock phase synchronization accuracy.

[0005] In a first aspect, an embodiment of the present application provides a clock circuit phase drift compensation circuit, comprising:

[0006] A frequency detector and a phase detector, which obtains a reference clock signal and a feedback clock signal, and determines an error voltage signal based on the reference clock signal and the feedback clock signal;

[0007] A filter is used to filter the error voltage signal transmitted therethrough;

[0008] A voltage-controlled oscillator receives the filtered error voltage signal and adjusts the frequency of a current clock signal according to the error voltage signal;

[0009] A buffer connected to the output end of the voltage controlled oscillator;

[0010] A multiplexer, wherein the voltage-controlled oscillator and the buffer are respectively provided with feedback branches connected to the multiplexer;

[0011] The frequency divider is connected between the multiplexer and the phase frequency detector, and obtains the feedback clock signal after frequency division of the signal of the feedback branch selected by the multiplexer, and sends the feedback clock signal to the phase frequency detector.

[0012] In a second aspect, a clock chip is provided, comprising the clock circuit phase drift compensation circuit described in any embodiment of the present application.

[0013] In a third aspect, a clock array is provided, comprising a master clock chip and a slave clock chip connected to an output end of the master clock chip;

[0014] The master clock chip includes the clock circuit phase drift compensation circuit described in any embodiment of the present application. In the master clock chip, the clock circuit phase drift compensation circuit includes a buffer and a multi-channel amplifier connected to the buffer, and each amplifier is connected to a corresponding slave clock chip;

[0015] The slave clock chip includes the clock circuit phase drift compensation circuit described in any embodiment of the present application.

[0016] In a fourth aspect, a digital beamforming system is provided, comprising the clock array described in any embodiment of the present application.

[0017] The clock circuit phase drift compensation circuit provided in the above embodiment has feedback branches connected to the multiplexer after the voltage-controlled oscillator and the buffer, respectively. The frequency divider divides the signal of the feedback branch selected by the multiplexer to obtain a feedback clock signal, and sends the feedback clock signal to the frequency detector. In this way, when the filter, voltage-controlled oscillator, buffer, etc. in the clock circuit are affected by temperature fluctuations and form phase drift, they can be fed back to the frequency detector in the form of an error voltage signal through the signal feedback branch, thereby eliminating the need to add additional hardware components and logic resources. The setting of the feedback branch after the buffer can include the phase drift introduced by the temperature fluctuation factor of all devices including the buffer into the loop, and use the adaptive adjustment capability of the negative feedback system to compensate for the clock phase, thereby maintaining the stability and synchronization of the clock phase while reducing costs.

[0018] The clock chip, clock array and digital beamforming system provided in the above embodiments belong to the same concept as the corresponding clock circuit phase drift compensation circuit embodiments, and thus have the same technical effects as the corresponding clock circuit phase drift compensation circuit embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 4 is a schematic diagram of a clock circuit phase drift compensation circuit in an embodiment.

[0020] Figure 2for Figure 1 The circuit diagram of the clock circuit phase drift compensation circuit shown is as follows.

[0021] Figure 3 FIG. 4 is a circuit diagram of a clock circuit phase drift compensation circuit in another embodiment.

[0022] Figure 4 FIG. 4 is a circuit diagram of a clock array in an embodiment. DETAILED DESCRIPTION

[0023] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0024] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0025] In the following description, the expression "some embodiments" is involved, which describes a subset of all possible embodiments. It should be noted that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0026] In the following description, the terms "first, second, third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first, second, third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0027] See also Figure 1 and Figure 2 , a clock circuit phase drift compensation circuit provided by an embodiment of the present application, includes: a frequency detector 11, which obtains a reference clock signal CLKref and a feedback clock signal, and determines an error voltage signal based on the reference clock signal CLKref and the feedback clock signal; a filter 13, which filters the error voltage signal transmitted; a voltage-controlled oscillator 14, which receives the filtered error voltage signal and adjusts the frequency of the current clock signal according to the error voltage signal; a buffer 191, which is connected to the output end of the voltage-controlled oscillator 14; a multiplexer 15, wherein the voltage-controlled oscillator 14 and the buffer 191 are respectively provided with feedback branches connected to the multiplexer 15; a frequency divider 16, which is connected between the multiplexer 15 and the frequency detector 11, divides the signal of the feedback branch selected by the multiplexer 15 to obtain a feedback clock signal, and sends the feedback clock signal to the frequency detector 11.

[0028] The phase frequency detector 11 (PFD) is an electronic circuit used to measure the frequency and phase relationship between two signals. It is widely used in phase-locked loops (PLLs), frequency synthesizers and other high-frequency applications. The phase frequency detector 11 obtains a reference clock signal CLKref and a feedback clock signal to compare the phase and frequency differences of the two input signals, and reflects these differences through the output signal, thereby adjusting the output signal to synchronize it with the reference signal.

[0029] In an optional example, the filter 13 is a loop filter (LPF), which compares the output signal of the filter 13 with the input signal, and then feeds the difference signal back to the input end to filter the input signal, thereby achieving filtering of the input signal. This is a circuit that uses the feedback principle to achieve filtering.

[0030] A voltage controlled oscillator 14 (VCO) is an oscillator circuit whose output frequency corresponds to an input control voltage. The working state of the oscillator or the component parameters of the oscillation circuit are controlled by the input control voltage, thereby forming a voltage controlled oscillator 14. The working principle of the voltage controlled oscillator 14 is to control the frequency of the oscillator by the input control voltage, and it has a wide range of applications in adjustable communications, radio, radar, sensing and measurement systems.

[0031] The buffer 191 (buffer) is used to amplify and isolate the output signal of the voltage-controlled oscillator 14 and is usually used as a signal output device of the clock circuit.

[0032] The multiplexer 15 (MUX) is a logic circuit, which usually has multiple inputs and one output. The multiplexer 15 can select one of the multiple input signals and send it to the output end according to different states of the selection signal.

[0033] The frequency divider (N Divider) is used to perform frequency division processing on the feedback signal selected and output by the multiplexer 15, and restore the signal in the feedback branch to a feedback clock signal with the same multiple as the reference clock signal CLKref, which is used for feedback adjustment of the phase offset compensation of the clock circuit.

[0034] In the clock circuit phase drift compensation circuit provided in the above embodiment, feedback branches connected to the multiplexer 15 are respectively provided after the voltage-controlled oscillator 14 and the buffer 191, and the frequency divider 16 obtains a feedback clock signal after dividing the signal of the feedback branch selected by the multiplexer 15, and sends the feedback clock signal to the frequency detector 11. In this way, when the filter 13, the voltage-controlled oscillator 14, the buffer 191, etc. in the clock circuit are affected by temperature fluctuations and form a phase drift, the error voltage signal can be fed back to the frequency detector 11 in the form of an error voltage signal through the signal feedback branch, thereby eliminating the need to add additional hardware components and logic resources. The setting of the feedback branch after the buffer 191 can include all phase drifts introduced by temperature fluctuations in all devices including the buffer 191 into the loop, and use the adaptive adjustment capability of the negative feedback system to compensate for the clock phase, thereby maintaining the stability and synchronization of the clock phase while reducing costs.

[0035] The inventors of the present application have found in their research on solutions to the phase drift of the clock circuit that the traditional clock circuit usually uses a phase-locked loop (PLL) architecture to generate the required frequency clock, and the core components of the phase-locked loop architecture of the traditional clock circuit include a frequency detector 11, a filter 13, and a voltage-controlled oscillator 14. The frequency signal output by the voltage-controlled oscillator 14 is directly fed back to the frequency detector 11 through a feedback branch. In the embodiment of the present application, in order to effectively improve the function and performance of the clock circuit, a buffer 191 is further provided at the output end of the voltage-controlled oscillator 14 to amplify the output signal and match it with the requirements of the subsequent load, so as to provide a driving capability that meets the requirements of the subsequent load.

[0036] In some embodiments, the clock circuit phase drift compensation circuit further includes an amplifier 192 connected to the buffer 191 ; a feedback branch after the buffer 191 is connected between the output end of the amplifier 192 and the multiplexer 15 .

[0037] It should be noted that the buffer 191 and the amplifier 192 are usually used as the signal output device 19 of the clock circuit, wherein the buffer 191 is used to amplify the signal and isolate the load, and the signal transmission path between the frequency detector 11 and the buffer 191 forms a phase-locked loop circuit. The amplifier (AMP) is arranged outside the clock chip, and can usually be selectively added according to the power load of the subsequent load (such as ADC, etc.) to meet the signal input requirements of the subsequent load. The signal output device 19 refers to a circuit device in the clock circuit that outputs the clock signal to drive the load, and usually has the function of signal amplification and shaping, which can increase the load-carrying capacity of the clock circuit. The clock circuit can be designed according to different application requirements. The signal output device 19 includes one or more different circuit devices. For example, the signal output device 19 can only include a buffer 191, which is connected to the output end of the voltage-controlled oscillator 14 to amplify the current clock signal output by the voltage-controlled oscillator 14 to provide a stronger driving capability for the load; or the signal output device 19 can be multiple, which are sequentially connected to the output end of the voltage-controlled oscillator 14. For example, the clock circuit further includes an amplifier 192 connected to the rear of the buffer 191, and the multiple signal output devices respectively perform signal amplification and power amplification to further meet the signal input requirements of the subsequent load. In the case where the signal output device 19 includes multiple devices, the feedback branch located after the buffer 191 can refer to the last signal output device 19 connected to the output end of the voltage-controlled oscillator 14, that is, the signal feedback branch formed between the output end of the final signal output device 19 and the frequency detector 11.

[0038] It is understandable that the clock circuit is not limited to the structure shown in the embodiment of the present application. Figure 2 As shown, before the buffer 191 or before the final amplifier 192, the clock circuit may include more circuit devices. When any device in the clock circuit, such as the filter 13 and the voltage-controlled oscillator 14, is affected by temperature fluctuations and forms a phase drift, it can be fed back to the frequency detector 11 in the form of an error voltage signal through the signal feedback branch at the output end of the final signal output device 19, so that the phase drift introduced by the temperature fluctuation factor of all devices including the signal output device 19 is included in the clock circuit loop. In an optional example, taking the signal output device 19 as an example including both the buffer 191 and the amplifier 192, the feedback branch provided after the buffer 191 may refer to a feedback branch provided between the output end of the final amplifier 192 and the multiplexer 15. By providing a feedback branch connected to the multiplexer 15 after the buffer 191, the phase drift introduced by the temperature fluctuation factor of all devices including the signal output device 19 in the clock circuit is included in the clock circuit loop.

[0039] Optionally, the clock circuit phase drift compensation circuit further includes a charge pump 12 connected between the phase frequency detector 11 and the filter 13; the charge pump 12 is used to convert the error voltage signal output by the phase frequency detector 11 to match the input voltage requirement of the voltage controlled oscillator 14. At this time, the signal transmission path between the phase frequency detector 11 and the buffer 191 includes the phase frequency detector 11, the charge pump 12, the loop filter and the voltage controlled oscillator 14, and the phase frequency detector 11, the charge pump 12, the loop filter and the voltage controlled oscillator 14 are connected in sequence to form a phase-locked loop circuit.

[0040] Optionally, when the clock circuit includes multiple signal output devices 19, the feedback branch after the buffer 191 can also be provided at the output end of the buffer 191 and the output end of the rear signal output device 19. Still taking the clock circuit phase drift compensation circuit also including an amplifier 192 connected to the buffer 191 as an example, a first feedback branch Feedback line1 is provided between the output end of the voltage-controlled oscillator 14 and the multiplexer 15, and a second feedback branch Feedback line2 is provided between the output end of the buffer 191 and the multiplexer 15. A third feedback branch Feedback line3 is provided between the output end of the amplifier 192 and the multiplexer 15.

[0041] In the above embodiment, the output ends of the voltage-controlled oscillator 14, the buffer 191, and the amplifier 192 are respectively connected to the frequency detector 11 through the first feedback branch Feedback line1, the second feedback branch Feedback line2, and the third feedback branch Feedback line3 via the multiplexer 15 and the frequency divider 16. The multiplexer 15 can select one of the first feedback branch Feedback line1, the second feedback branch Feedback line2, and the third feedback branch Feedback line3 to output to the frequency divider 16, and then the frequency divider 16 performs frequency division processing and then feeds back to the frequency detector 11. It should be noted that the second feedback branch Feedback line2 set at the output end of the buffer 191 can include the phase offset of all circuit devices in the phase-locked loop circuit, including itself, into the loop, and send it to the frequency detector 11 after frequency division. After comparing with the reference clock signal CLKref, the frequency detector 11 generates a corresponding error voltage signal. When the frequencies of the two are equal, the voltage signal remains constant, and after filtering, it drives the voltage-controlled oscillator 14 to lock the current clock signal frequency. When the signal frequency drifts, the phase-locked loop circuit causes the error voltage signal to change accordingly through the feedback clock signal fed back from the output end of the final buffer 191, further driving the output frequency of the voltage-controlled oscillator 14 to change and approach the reference clock signal CLKref. Amplifier 192 is used to further amplify the output power of the phase-locked loop circuit. The third feedback branch Feedback line3 set at the output end of the amplifier 192 can include the phase offset of all circuit devices in the phase-locked loop circuit, including the amplifier 192 itself, into the loop. When the signal frequency drifts, the phase-locked loop circuit causes the error voltage signal to change accordingly through the feedback clock signal fed back from the output end of the final amplifier, further driving the output frequency of the voltage-controlled oscillator 14 to change and approach the reference clock signal CLKref.

[0042] For scenarios where the clock power requirements of the subsequent load are not high and no external amplifier is required, the signal output device 19 may only include the buffer 191, and the multiplexer 15 selects the path of the second feedback branch, and the frequency signal of the current clock signal generated by the voltage-controlled oscillator 14 and passed through the buffer 191 is fed back to the frequency divider 16, and finally sent to the frequency detector 11, and the phase drift amount of the components including the buffer 191 itself in the phase-locked loop circuit due to temperature fluctuation factors is fully included in the loop for compensation through negative feedback adaptive compensation. For scenarios where the clock circuit needs to add an amplifier 192, the multiplexer 15 can select the path of the third feedback branch, and the frequency signal of the current clock signal generated by the voltage-controlled oscillator 14 and passed through the buffer 191 and the amplifier 192 is fed back to the frequency divider 16, and finally sent to the frequency detector 11, and the phase drift amount of all components including the buffer 191 and the amplifier 192 in the phase-locked loop circuit due to temperature fluctuation factors is fully included in the loop for compensation through negative feedback adaptive compensation.

[0043] In this way, when the buffer 191 and the amplifier 192 produce phase drift (such as phase enlargement) due to temperature fluctuation factors, the feedback signal can transmit the phase offset error to the frequency detector 11 through the corresponding second feedback branch Feedback line2 or the third feedback branch Feedback line3. Since the frequency is the differential form of the phase function, the frequency detector 11 converts the frequency error introduced by the phase drift into a voltage error signal, and the voltage error signal is transmitted to the output end of the voltage-controlled oscillator 14 after passing through the charge pump 12 and the loop filter. The voltage-controlled oscillator 14 pulls the phase of the current clock signal output inversely transformed, and then feeds back to the frequency detector 11 for comparison. This is repeated for multiple cycles, and the clock phase is continuously and adaptively adjusted to finally pull it back to the locked state, and finally achieve the purpose of clock phase synchronization. It can be seen that the clock circuit phase drift compensation circuit provided in the above embodiment has a simple structure on the one hand, and realizes adaptive compensation of phase drift through only a small number of hardware units, completes real-time dynamic adjustment, and has low cost; on the other hand, due to the use of negative feedback technology, it has good real-time performance, saving hardware acquisition resources such as ADC and logic resources required for correcting phase information.

[0044] In some embodiments, see Figure 3, the signal output device 19 also includes a multi-channel amplifier connected to the buffer 191; the feedback branch after the buffer 191 may refer to a third feedback branch Feedback line3 connected between the output end of one of the amplifiers and the multiplexer 15. Among them, the multi-channel amplifier is connected in parallel to the output end of the buffer 191, and can form a multi-channel output channel of a single clock chip, such as the output channels CLK1, CLK2...CLKn-1, CLKn corresponding to the n-channel amplifier, to meet the needs of the system with multiple clock channels. When the multi-channel amplifiers are placed together, since the temperature changes of the amplifiers are basically the same and have similar phase drift characteristics, one of the clock channels, such as the CLKn output channel, can be fed back to the frequency detector 11 through the third feedback branch Feedback line3 for phase offset adaptive compensation, while the output channels CLK1, CLK2...CLKn-1 corresponding to other clock channels normally output clock signals and maintain clock phase synchronization.

[0045] It should be noted that, in an embodiment in which the signal output device 19 includes a buffer 191 and an amplifier 192 sequentially connected to the output end of the voltage-controlled oscillator 14, the output ends of the voltage-controlled oscillator 14, the buffer 191 and the amplifier 192 are respectively connected to the multiplexer 15 through the first feedback branch Feedback line1, the second feedback branch Feedback line2 and the third feedback branch Feedback line3. Optionally, the multiplexer 15 selects multiple feedback signals and selects one of the feedback signals to be fed back to the frequency detector 11 through the frequency divider 16 according to the set requirements. For example, the multiplexer 15 can select one of the first feedback branch Feedback line1, the second feedback branch Feedback line2 and the third feedback branch Feedback line3 at different times to output to the frequency divider 16. Optionally, the multiplexer 15 selects the feedback signals corresponding to the multiple feedback branches, selects the signal output device 19 of the current final stage, that is, the feedback branch corresponding to the last amplifier 192 connected in sequence after the buffer 191 is fed back to the frequency detector 11 through the divider 16.

[0046] Clock phase synchronization is mainly used in digital beamforming systems that require a multi-channel clock system. A single-chip single-channel clock chip may include a clock circuit phase drift compensation circuit as shown in 2, and a single-chip multi-channel clock chip may include a clock circuit phase drift compensation circuit as shown in 2. Figure 3 The clock circuit phase drift compensation circuit shown in the figure, on the other hand, the present application provides a monolithic clock chip, including the clock circuit phase drift compensation circuit of any embodiment of the present application.

[0047] For large-scale digital beamforming systems, a single clock chip often cannot meet the number of clock channels required. In this case, multiple clock chips are needed to form a clock array. Figure 4 On the other hand, the present application provides a clock array, including a master clock chip 10 and a slave clock chip 20 connected to the output end of the master clock chip 10; the master clock chip 10 includes the clock circuit phase drift compensation circuit in the embodiment of the present application, and in the master clock chip 10, the clock circuit phase drift compensation circuit includes a multi-channel amplifier connected to the buffer 191, and each amplifier is connected to a corresponding slave clock chip 20; the slave clock chip 20 may include the clock circuit phase drift compensation circuit of any embodiment of the present application. In the clock array, the phase drift problem of multiple multi-channel clock chips is involved. Figure 4 As shown in the figure, the first-level clock chip PLL0 is used as the master clock chip 10 to drive the slave clock chips 20PLL1~PLLm as the second-level clock chips, and each slave clock chip 20 outputs n clock signals. Due to the large array scale, the second-level clock chips are often distributed at different positions on the circuit board (PCB) and are far away, so the temperature fluctuations received by different clock chips may not be consistent, and therefore have different phase drift characteristics. In this embodiment, each slave clock chip 20 is phase-adaptively adjusted to adapt to the phase synchronization of all clock channels in the system. Specifically, the master clock chip 10 selects a clock signal to be fed back to the frequency detector 11 of the master clock chip 10 through the third feedback branch for phase-adaptive adjustment to achieve the first-level clock phase synchronization; the second-level clock chips each select a clock signal, and feed it back to the frequency detector 11 of their own chip through the path of the second feedback branch or the third feedback branch external to each chip for phase-adaptive adjustment to achieve the second-level clock phase synchronization. In this way, the clock array can achieve the phase synchronization of all clock channels in the system.

[0048] In another aspect, the present application further provides a digital beamforming system, comprising the clock array of the aforementioned embodiment.

[0049] The clock circuit phase drift compensation circuit and related products provided in the above embodiments have at least the following characteristics:

[0050] First, in the clock circuit phase drift compensation circuit, the signal feedback branch arranged after the buffer 191 can feed back the phase offset caused by temperature fluctuations of all devices in the clock circuit, including the buffer 191 and other signal output devices 19 behind it, to the frequency detector 11 in the form of an error voltage signal, thereby avoiding the addition of additional hardware components and logic resources, and realizing dynamic phase synchronization through only a small number of hardware units, with a simple circuit structure and low cost.

[0051] Second, the use of negative feedback technology has better real-time performance.

[0052] Third, it can be better applied to the field of digital beamforming, and based on the application scenarios of digital beamforming arrays of different sizes, a specific implementation method of the phase compensation device of a single-chip single-channel clock chip, a single-chip multi-channel clock chip, and multiple multi-channel clock chips composed of a clock array is designed, which has good practicality.

[0053] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0054] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A clock circuit phase drift compensation circuit, characterized in that: include: A frequency detector and a phase detector, which obtains a reference clock signal and a feedback clock signal, and determines an error voltage signal based on the reference clock signal and the feedback clock signal; A filter is used to filter the error voltage signal transmitted therethrough; A voltage-controlled oscillator receives the filtered error voltage signal and adjusts the frequency of a current clock signal according to the error voltage signal; A buffer connected to the output end of the voltage controlled oscillator; A multiplexer, wherein the voltage-controlled oscillator and the buffer are respectively provided with feedback branches connected to the multiplexer; The frequency divider is connected between the multiplexer and the phase frequency detector, divides the frequency of the signal of the feedback branch selected by the multiplexer to obtain the feedback clock signal, and sends the feedback clock signal to the phase frequency detector.

2. The clock circuit phase drift compensation circuit according to claim 1, characterized in that: It also includes an amplifier connected to the buffer, and a feedback branch after the buffer is connected between the output end of the amplifier and the multiplexer.

3. The clock circuit phase drift compensation circuit according to claim 2, characterized in that: Also included is an amplifier connected to the buffer; The feedback branch after the voltage-controlled oscillator includes a first feedback branch connected between the output end of the voltage-controlled oscillator and the multiplexer, and the feedback branch after the buffer includes a second feedback branch connected between the output end of the buffer and the multiplexer respectively and a third feedback branch connected between the output end of the amplifier and the multiplexer.

4. The clock circuit phase drift compensation circuit according to claim 2, characterized in that: The signal output device also includes a multi-channel amplifier connected to the buffer; The feedback branch after the buffer is connected between the output end of one of the amplifiers and the multiplexer.

5. The clock circuit phase drift compensation circuit according to claim 4, characterized in that: The multiplexer selects multiple feedback signals corresponding to multiple feedback branches, and selects one of the feedback signals according to the set requirements to be fed back to the frequency detector and phase detector through the frequency divider.

6. The clock circuit phase drift compensation circuit according to claim 4, characterized in that: The multiplexer selects multiple feedback signals corresponding to multiple feedback branches, and selects the feedback signal corresponding to the feedback branch connected to the output end of the amplifier to be fed back to the frequency detector and phase detector through the frequency divider.

7. The clock circuit phase drift compensation circuit according to claim 1, characterized in that: A charge pump connected between the phase frequency detector and the filter is also included.

8. A clock chip, characterized in that: The invention comprises a clock circuit phase drift compensation circuit as claimed in any one of claims 1 to 7.

9. A clock array, characterized in that: It includes a master clock chip and a slave clock chip connected to the output end of the master clock chip; The master clock chip comprises a clock circuit phase drift compensation circuit as claimed in any one of claims 1 to 7, wherein in the master clock chip, the clock circuit phase drift compensation circuit comprises a multi-channel amplifier connected to the buffer, and each of the amplifiers is connected to one of the slave clock chips; The slave clock chip comprises the clock circuit phase drift compensation circuit as claimed in any one of claims 1 to 7.

10. A digital beamforming system, characterized in that: Comprising the clock array as claimed in claim 9.

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