High-precision clock generation method of passive BLE tag without crystal oscillator

Abstract

The invention relates to a high-precision clock generation method for a passive BLE tag without a crystal oscillator, and the method comprises the following steps: generating a low-frequency oscillation clock through a relaxation oscillator circuit according to an input current; according to the low-frequency oscillation clock, generating a frequency multiplication oscillation clock by using a phase-locked loop circuit; judging whether a high-frequency carrier signal exists or not; if so, demodulating the high-frequency carrier signal by using a demodulation circuit to obtain a calibration pulse signal; according to the calibration pulse signal, in a single period of the calibration pulse signal, the current calibration circuit is used for quantifying the frequency multiplication oscillation clock to obtain frequency error information of the frequency multiplication oscillation clock, the frequency error information is used as a calibration parameter to calibrate output current, and the calibrated output current is fed back to the relaxation oscillator circuit; in this way, the input current of the relaxation oscillator circuit is changed. According to the method, a relaxation oscillator circuit is used for generating a low-frequency oscillation clock, current calibration is carried out to change the clock frequency, an external crystal oscillator is not needed, and application of a passive BLE tag is met.

Description

Technical Field

[0001] The present invention belongs to the technical field of passive BLE tag communication, and in particular relates to a high-precision clock generation method for a passive BLE tag without a crystal oscillator. Background Art

[0002] The advantages of traditional radio frequency identification (RFID) tags include high integration, low power consumption, passive operation, and relatively long communication distance. However, dedicated and expensive readers are required to read RFID tag information, which limits its large-scale deployment and application. On the other hand, near field communication (NFC) is widely used, but its communication range is limited to less than 10 cm. In contrast, passive Bluetooth low energy (BLE) tags based on backscatter communication have greatly improved access performance. Compared with RFID, passive BLE tags are compatible with today's commercial mobile smart devices, provide additional "zero cost" for wearable receivers, and greatly expand access coverage. Compared with NFC, the access range of passive BLE tags is extended by two orders of magnitude. Compared with active BLE devices, the cost of passive BLE tags is reduced by one to two orders of magnitude. Passive BLE tags based on backscatter technology have advantages in compatibility, access range and cost, so they are promising in IoT applications.

[0003] To ensure compatibility with existing BLE receivers, the baseband data rate tolerance of passive BLE tags is set to 1000ppm (actual measurements have shown that frequency deviations within 4‰ are acceptable), which is much higher than the clock accuracy requirements of passive RFID tags (maximum deviation is 22%). Traditional battery-powered active BLE systems use crystal oscillators to generate high-precision reference clock signals. However, crystal oscillators are large in size and high in power consumption, which can be ignored in active BLE systems. Currently, some experimental prototype passive BLE tags still use this method as a clock solution. However, considering the inherent application characteristics of passive tags, it is crucial to achieve small size, low power consumption, high energy efficiency and high integration without external components. Therefore, it is crucial and challenging to generate high-precision clock frequencies for passive BLE tags without relying on crystal oscillators.

[0004] In order to solve the problem of high-precision clock system without crystal oscillator, the prior art proposes the following two on-chip clock solutions. The first solution uses two external carriers as the local oscillator (LO) of the PCB passive tag, relying on the extraction of the second-order intermodulation components of two wireless power transfer (WPT) RF waves as the reference clock. However, to obtain basically stable results, this method must use an additional auxiliary carrier generator, which is more expensive and requires that the power of the two RF waves received by the tag receiving antenna end is roughly equal; in addition, this method is also easily interfered by other air RF (RF) signals or noise signals, resulting in many limitations such as clock recovery failure. The second solution is to use current calibration to recover the intermediate frequency clock from the wireless power transfer (WPT) RF signal of Gaussian frequency shift keying modulation (GFSK). Although this method avoids the use of crystal oscillators, its milliwatt power consumption is still not affordable in the field of passive tag communication. In addition, an external carrier source is required to continuously transmit GFSK signals. Both of the above on-chip clock solutions cannot meet the application in passive BLE tags. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a high-precision clock generation method for a passive BLE tag without a crystal oscillator. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The present invention provides a high-precision clock generation method for a passive BLE tag without a crystal oscillator, which is applied to a passive BLE tag including a demodulation circuit, a current calibration circuit, a relaxation oscillator circuit and a phase-locked loop circuit. The method comprises the following steps:

[0007] generating a low-frequency oscillation clock using the relaxation oscillator circuit according to the input current;

[0008] According to the low-frequency oscillation clock, the phase-locked loop circuit is used to generate a frequency-multiplied oscillation clock;

[0009] Determine whether there is a high-frequency carrier signal; if so, use the demodulation circuit to demodulate the high-frequency carrier signal to obtain a calibration pulse signal; if not, output the frequency-multiplied oscillation clock;

[0010] According to the calibration pulse signal, within a single cycle of the calibration pulse signal, the current calibration circuit is used to quantize the frequency doubled oscillation clock to obtain frequency error information of the frequency doubled oscillation clock, the frequency error information is used as a calibration parameter to calibrate the output current, and the calibrated output current is fed back to the relaxation oscillator circuit to change the input current of the relaxation oscillator circuit.

[0011] In one achievable manner, the frequency of the low-frequency oscillation clock generated by the relaxation oscillator circuit is proportional to the magnitude of the input current of the relaxation oscillator circuit;

[0012] The input current of the relaxation oscillator circuit is the sum of the constant current source current and the output current calibrated by the current calibration circuit.

[0013] In one achievable manner, the current calibration circuit is used to quantize the frequency-multiplied oscillation clock, including:

[0014] The current calibration circuit is used to count rising edges of the frequency-doubled oscillation clock to obtain a first counting result.

[0015] In an achievable manner, obtaining frequency error information of the frequency-multiplied oscillation clock, and using the frequency error information as a calibration parameter to calibrate the output current includes:

[0016] When the first counting result is less than a pre-designed value, an additive difference is output according to the difference between the first counting result and the pre-designed value, and the output current is increased according to the additive difference; when the first counting result is greater than the pre-designed value, a subtractive difference is output according to the difference between the first counting result and the pre-designed value, and the output current is reduced according to the subtractive difference.

[0017] In one achievable manner, the preset count value is the product of a frequency of a preset clock and a pulse width of the preset clock.

[0018] In an implementable manner, the current calibration circuit includes: a counter A, a counter B, a counter C and a current control array, wherein:

[0019] The counter C is used to count the frequency-multiplied oscillation clock to obtain a first counting result;

[0020] The counter A is used to count the frequency-multiplied oscillation clock when the first counting result is less than a pre-designed value, and output an addition difference value according to the difference between the counting result and the pre-designed value;

[0021] The counter B is used to count the frequency-multiplied oscillation clock when the first counting result is greater than a pre-designed value, and output a subtraction difference value according to the difference between the counting result and the pre-designed value;

[0022] The current control array is used to increase the output current according to the addition difference, or to reduce the output current according to the subtraction difference.

[0023] In one achievable manner, the current control array includes: an addition current mirror array and a subtraction current mirror array, wherein:

[0024] The adding current mirror array opens a corresponding number of current mirrors according to the added difference to increase the output current;

[0025] The subtraction current mirror array turns off a corresponding number of current mirrors according to the subtraction difference to reduce the output current.

[0026] In an implementable manner, the demodulation circuit includes: an envelope detection subcircuit, a low-pass filter, a peak hold subcircuit, a hysteresis comparator, and a D flip-flop;

[0027] The envelope detection subcircuit is used to extract an envelope signal from the high-frequency carrier signal;

[0028] The low-pass filter is used to eliminate noise from the envelope signal and generate V x Signal;

[0029] The peak holding subcircuit is used to x Signal generation V y Signal;

[0030] The hysteresis comparator is used to x signal and the V y The signal generates a calibration pulse signal represented by a falling edge;

[0031] The D flip-flop is used to convert the calibration pulse signal represented by a falling edge into a calibration pulse signal represented by a rising edge.

[0032] In an achievable manner, the relaxation oscillator circuit comprises: a two-phase charge and discharge electronic circuit, a comparator, a Schmitt trigger and a logic gate subcircuit, wherein:

[0033] The comparator is used to output a low-frequency oscillation clock through the Schmitt trigger according to the output current of the two-phase charge and discharge electronic circuit; the comparator uses the reference voltage generated by the reference circuit as the flip threshold voltage;

[0034] The logic gate subcircuit is used to generate a control signal for controlling the two-phase charging and discharging electronic circuit according to the low-frequency oscillation clock.

[0035] In an achievable manner, the phase-locked loop circuit comprises: a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider connected in sequence, wherein:

[0036] The reference frequency input terminal of the frequency detector is input with the low frequency oscillation clock, and the feedback frequency input terminal of the frequency detector is connected with the output terminal of the frequency divider;

[0037] The output end of the voltage-controlled oscillator outputs the frequency-multiplied oscillation clock;

[0038] The output frequency f of the voltage controlled oscillator VCO The formula is:

[0039]

[0040] Among them, f 0 is the oscillation frequency provided by the initial current, k is the proportional factor, V ctrl is the control voltage of the voltage controlled oscillator, C 0 is the value of the capacitor in the voltage controlled oscillator, and VDD is the supply voltage of the voltage controlled oscillator.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] The invention provides a high-precision clock generation method for a passive BLE tag without a crystal oscillator. According to the calibration pulse signal, current calibration is performed to change the input current of the relaxation oscillator circuit, thereby changing the clock frequency. No external crystal oscillator is required, and major technical obstacles are overcome to realize a BLE tag-type passive Internet of Things chip that meets the requirements of miniaturization, high integration, low cost, and easy deployment. The clock generation method has high precision and low power consumption, which meets the application of passive BLE tags. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic diagram of the circuit structure of a passive BLE tag provided in an embodiment of the present invention;

[0044] Figure 2 It is a step diagram of a high-precision clock generation method for a passive BLE tag without a crystal oscillator provided by an embodiment of the present invention;

[0045] Figure 3 is a circuit structure diagram of a relaxation oscillator circuit provided in an embodiment of the present invention;

[0046] Figure 4 It is a schematic diagram of the circuit structure of a traditional relaxation oscillator;

[0047] Figure 5 is a circuit structure diagram of a phase-locked loop circuit provided in an embodiment of the present invention;

[0048] Figure 6 is a schematic diagram of the circuit structure of a voltage-controlled oscillator provided in an embodiment of the present invention;

[0049] Figure 7 is a schematic diagram of the circuit structure of a demodulation circuit provided by an embodiment of the present invention;

[0050] Figure 8 is a calibration logic diagram of a current calibration circuit provided by an embodiment of the present invention;

[0051] Fig. 9 is a circuit structure schematic diagram of a current calibration circuit provided by an embodiment of the present invention;

[0052] Fig.10 is a schematic diagram of the connection relationship between the current calibration circuit and the relaxation oscillator circuit provided in an embodiment of the present invention;

[0053] Fig.11 is a schematic diagram of the circuit structure of a decision module provided in an embodiment of the present invention;

[0054] Fig.12 is a signal flow diagram of a decision circuit provided by an embodiment of the present invention;

[0055] Fig.13 4 is a frequency variation diagram of a low-frequency oscillation clock output by a relaxation oscillator circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0057] Embodiment 1

[0058] This embodiment provides a high-precision clock generation method for a passive BLE tag without a crystal oscillator, which is applied to a passive BLE tag including a demodulation circuit, a current calibration circuit, a relaxation oscillator circuit and a phase-locked loop circuit. The circuit structure of the passive BLE tag is as follows: Figure 1 As shown, the demodulation circuit, the current calibration circuit, the relaxation oscillator circuit and the phase-locked loop circuit are connected in sequence, the input end of the demodulation circuit is connected to the external high-frequency carrier signal source, and the output end of the phase-locked loop circuit outputs the clock signal CLK REF , and connect the current calibration circuit.

[0059] See also Figure 2 , Figure 2 1 is a step diagram of a high-precision clock generation method for a passive BLE tag without a crystal oscillator provided by an embodiment of the present invention. The high-precision clock generation method for a passive BLE tag without a crystal oscillator provided by this embodiment includes the following steps:

[0060] S1: Based on the input current, a relaxation oscillator circuit is used to generate a low-frequency oscillation clock f 1 .

[0061] In this embodiment, the low-frequency oscillation clock f generated by the relaxation oscillator circuit is 1 The frequency is proportional to the input current of the relaxation oscillator circuit. The input current of the relaxation oscillator circuit is the sum of the constant current source current and the output current calibrated by the current calibration circuit.

[0062] See also Figure 3 , Figure 3 is a circuit structure diagram of a relaxation oscillator circuit provided in an embodiment of the present invention. In this embodiment, the relaxation oscillator circuit includes: a two-phase charge-discharge electronic circuit, a comparator, a Schmitt trigger, and a logic gate subcircuit. The comparator is used to output a low-frequency oscillation clock f through a Schmitt trigger according to the output current of the two-phase charge-discharge electronic circuit. 1 The comparator uses the reference voltage V generated by the reference circuit bias As the flip threshold voltage. The logic gate subcircuit is used to generate a low frequency oscillation clock f 1 Generates control signals for controlling two-phase charging and discharging electronic circuits.

[0063] For further information, see Figure 4 , Figure 4 This is a schematic diagram of the circuit structure of a traditional relaxation oscillator. The traditional relaxation oscillator uses capacitor charging and discharging to generate a rectangular wave. However, the traditional relaxation oscillator has the following disadvantages: (1) The oscillation period of the traditional relaxation oscillator is only composed of the charging and discharging time of a single capacitor, and the output waveform is a narrow pulse with a small duty cycle; (2) The comparator is offset and fluctuates with the influence of PVT; (3) The output frequency is related to RC, the process fluctuation is large, and it is difficult to calibrate linearly. Therefore, this embodiment adopts a relaxation oscillator with a new chopper structure current control, such as Figure 3 As shown, the constant current source I 1 and I 2 For capacitor C 1 and C 2 Charge and discharge to form a two-phase charge and discharge electronic circuit, and are connected to the comparator's non-inverting input and inverting input respectively. The comparator outputs a low-frequency oscillation clock f through a Schmitt trigger. 1 , the logic gate subcircuit is based on the low frequency oscillation clock f 1 Output control signal S for controlling two-phase charging and discharging electronic circuit 1 and S 2 In this embodiment, the reference voltage V generated by the reference circuit is bias Replace the resistor R in the traditional relaxation oscillator with V bias As the flip threshold voltage of the comparator, the oscillation frequency of the comparator output is proportional to the current of the two-phase charge and discharge electronic circuit. 1 and C 2 ) and the flip threshold voltage to achieve offset elimination of the comparator. In addition, since the temperature-sensitive unit of the resistor in the traditional relaxation oscillator is eliminated, the relaxation oscillator provided by this embodiment also has good temperature characteristics. In an achievable manner, the final output frequency of the relaxation oscillator provided by this embodiment is 125KHz, the power consumption is 468nW, and the temperature drift coefficient is only 20ppm.

[0064] S2: According to the low frequency oscillation clock f 1 , using the phase-locked loop circuit to generate a frequency-multiplied oscillation clock N*f 1 .

[0065] See also Figure 5 , Figure 5 Schematic diagram of the circuit structure of the phase-locked loop circuit provided by the embodiment of the present invention. The phase-locked loop circuit of this embodiment adopts the traditional second-order third-class charge pump phase-locked loop architecture to 1 Perform N-time frequency multiplication to generate a frequency multiplied oscillation clock N*f 1 The phase-locked loop circuit includes: a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider (DIV) connected in sequence. The reference frequency input terminal of the phase frequency detector inputs a low-frequency oscillation clock f 1 The feedback frequency input end of the frequency detector is connected to the output end of the frequency divider. The output end of the voltage controlled oscillator outputs the multiplied frequency oscillation clock N*f 1 . Frequency multiplication clock N*f 1 That is the clock signal CLK REF For further information, see Figure 6 , Figure 6 : is a schematic diagram of a circuit structure provided by an embodiment of the present invention. The voltage-controlled oscillator in this embodiment includes a voltage-controlled current bias and a current-starved VCO. The input end of the voltage-controlled current bias inputs an initial current I bias , the voltage-controlled current biases through the current mirror tube M ctrl Control, M ctrl The control voltage V is applied to the gate terminal ctrl , M ctrl The source end is connected to the negative feedback resistor R s The output frequency f of the voltage controlled oscillator in this embodiment is VCO The formula is:

[0066]

[0067] Among them, f 0 is the initial current I bias The oscillation frequency provided, k is the scale factor, V ctrl is the control voltage of the voltage controlled oscillator, C 0 is the value of the capacitor in the voltage controlled oscillator, and VDD is the supply voltage of the voltage controlled oscillator.

[0068] This embodiment introduces a fixed bias at the input of the current-starved VCO so that the voltage-controlled oscillator ctrl When it is 0V, there is still frequency output (initial current I bias Provides oscillation frequency f 0), speeding up the loop locking. And, the negative feedback resistor R s It can improve the linearity of the voltage control curve. ctrl When the voltage is 620mV, the output frequency of the voltage-controlled oscillator is 2MHz, and the power consumption is only 0.53μA. The overall power consumption of the phase-locked loop circuit is 1.07μW, and the overall power consumption of the relaxation oscillator and the phase-locked loop can be controlled at 1.6μW. The output frequency is 2MHz, which can meet the application of passive BLE tags. Compared with the traditional solution of using crystal oscillators as clock sources, the tag size is reduced, and the tag integration and application range are greatly improved.

[0069] S3: Determine whether there is a high-frequency carrier signal; if so, use the demodulation circuit to demodulate the high-frequency carrier signal to obtain a calibration pulse signal; if not, output the frequency-multiplied oscillation clock N*f 1 (CLK REF ).

[0070] See also Figure 7 , Figure 7 : is a schematic diagram of the circuit structure of the demodulation circuit provided in an embodiment of the present invention. The function of the demodulation circuit is to demodulate the high-frequency carrier signal into the calibration pulse signal required by the current calibration circuit. In this embodiment, the demodulation circuit includes: an envelope detection subcircuit, a low-pass filter, a peak holding subcircuit, a hysteresis comparator and a D flip-flop. Among them, the envelope detection subcircuit is used to extract the envelope signal from the high-frequency carrier signal. The low-pass filter is used to eliminate noise from the envelope signal and generate V x signal. The peak hold subcircuit is used to x Signal generation V y signal. The hysteresis comparator is used to x Signal and V y The signal generates a calibration pulse signal represented by a falling edge. The D flip-flop is used to convert the calibration pulse signal represented by a falling edge into a calibration pulse signal represented by a rising edge.

[0071] Specifically, since the passive BLE tag chip obtains energy from a high-frequency carrier, if the pulse is directly AM-modulated on the high-frequency carrier, the carrier source maintains a low level and does not transmit the carrier between pulses, which greatly reduces the efficiency of energy acquisition, and the D flip-flop can detect two adjacent falling edges to generate a pulse of fixed width. Therefore, this embodiment modulates the calibration pulse signal represented by the falling edge onto the carrier in the 860MHz~960MHz frequency band, restores the calibration pulse signal represented by the falling edge through the hysteresis comparator, and converts it into the calibration pulse signal represented by the rising edge required by the current calibration circuit through the D flip-flop, so that the carrier source can continue to send the high-frequency carrier between two adjacent falling edges, and the carrier source can also transmit the high-frequency carrier between pulses, which can greatly improve the efficiency of energy acquisition.

[0072] S4: According to the calibration pulse signal, within a single cycle of the calibration pulse signal, the current calibration circuit is used to calibrate the frequency-multiplied oscillation clock N*f 1 Quantify and obtain the frequency-multiplied oscillation clock N*f 1 The frequency error information is used as the calibration parameter to calibrate the output current, and the calibrated output current is fed back to the relaxation oscillator circuit to change the input current of the relaxation oscillator circuit.

[0073] Specifically, the current calibration circuit is used to calibrate the frequency-multiplied oscillation clock N*f 1 The rising edge is counted to obtain the first counting result D 1 When the first counting result is less than the pre-set value, according to the first counting result D 1 Compared with the pre-designed value D 0 The difference between the output and the addition difference is output, and the output current is increased according to the addition difference; in the first counting result D 1 Greater than the pre-designed value D 0 When, according to the first counting result D 1 Compared with the pre-designed value D 0 The difference between the output and the output current is reduced according to the subtraction difference. 0 The product of the frequency of the preset clock and the pulse width of the preset clock. For example, the frequency of the preset clock is 2 MHz and the pulse width is 125 μs, then the pre-designed value D 0 is 250.

[0074] Furthermore, considering the overall circuit coordination, avoiding the circuit structure being too large due to the calibration range being too large, and considering that the clock deviation caused by the process deviation is basically within the range of ±20%, the calibration range of the current calibration circuit only needs to be 80% to 120%, and does not need to be 0% to 200%. This embodiment introduces a preset threshold D. When the first counting result is greater than or equal to the preset threshold and less than the pre-designed value (D≤D 1 <D 0 ), according to the first counting result D 1 Compared with the pre-designed value D 0 The difference output adds the difference, thereby controlling the calibration range of the current calibration circuit to 2*(D 0 -D), the larger D is, the smaller the calibrated frequency range is.

[0075] See also Figure 8 and Fig. 9 , Figure 8 is a calibration logic diagram of a current calibration circuit provided in an embodiment of the present invention, Fig. 9It is a circuit structure diagram of the current calibration circuit provided by an embodiment of the present invention. In this embodiment, the current calibration circuit includes: counter A, counter B, counter C and a current control array. Among them, counter C is used to count the frequency-doubled oscillation clock to obtain a first counting result. Counter A is used to count the frequency-doubled oscillation clock when the first counting result is less than the pre-designed value, and output the addition difference according to the difference between the counting result and the pre-designed value. Counter B is used to count the frequency-doubled oscillation clock when the first counting result is greater than the pre-designed value, and output the subtraction difference according to the difference between the counting result and the pre-designed value. The current control array is used to increase the output current according to the addition difference, or to reduce the output current according to the subtraction difference.

[0076] Specifically, after the tag is powered on or initialized, if the current calibration circuit does not receive the calibration pulse signal, it means that the tag is working normally and the current calibration circuit does not need to work. If the current calibration circuit receives the calibration pulse signal, the counter C is turned on to oscillate the frequency-multiplied oscillation clock N*f output by the phase-locked loop circuit. 1 Count the frequency and get D 1 , in D 1 ≥D, turn on the adder counter (counter A), and when the falling edge of the calibration pulse signal arrives, D 1 <D 0 , the count value is small at this time, which theoretically means that the frequency-multiplied oscillation clock N*f output by the phase-locked loop circuit 1 The frequency is low and the output frequency needs to be increased, so counter A will 1 With D 0 Compare and get the current clock offset ΔD 1 (additive difference), and then use the offset ΔD 1 Control current control array to increase charge and discharge current ΔI 1 , thereby increasing the output frequency of the relaxation oscillator circuit. 1 =D 0 , it proves that the output frequency of the phase-locked loop is the same as the ideal output frequency during design, and the current calibration is completed. The current calibration circuit waits for the next calibration pulse signal. If within a single cycle of the calibration pulse signal, that is, before the falling edge of the calibration pulse signal arrives, D 1 Already greater than D 0 , which represents the frequency-multiplied oscillation clock N*f output by the phase-locked loop circuit 1 The frequency is higher than the preset clock frequency and needs to be reduced. 1 >D 0 When the adder counter is turned off, the subtractor counter (counter B) is turned on to multiply the frequency oscillation clock N*f 1 The frequency continues to count until the falling edge of the calibration pulse signal arrives, ending the counting and setting D1 With D 0 Comparison results in the offset ΔD 2 (subtraction difference), control the current control array to reduce the charge and discharge current ΔI 2 , thereby reducing the output frequency of the relaxation oscillator circuit. For example, the preset clock frequency is 2 MHz, the pulse width is 125 μs, and the pre-designed value D 0 is 250. If the output frequency of the phase-locked loop is 2.4MHz at this time, after the count value of the adder counter reaches 250, the adder counter is turned off, and the subtraction counter is turned on to continue counting 50 numbers. The subtraction difference is 50, and then the current control array is controlled to reduce the current value corresponding to the 50 count values. The current value corresponds to the output frequency of the relaxation oscillator circuit. The reduced current value is fed back to the relaxation oscillator circuit, reducing the output frequency of the relaxation oscillator circuit, thereby controlling the N*f output of the phase-locked loop circuit. 1 The frequency is reduced.

[0077] In this embodiment, the current control array includes: an addition current mirror array and a subtraction current mirror array. The addition current mirror array turns on a corresponding number of current mirrors according to the addition difference to increase the output current. The subtraction current mirror array turns off a corresponding number of current mirrors according to the subtraction difference to reduce the output current. The addition current mirror array is connected to the output end of counter A through register A, and the subtraction current mirror array is connected to the output end of counter B through register B. See Fig.10 , Fig.10 1 is a schematic diagram of the connection relationship between the current calibration circuit and the relaxation oscillator circuit provided by an embodiment of the present invention. The output end of the addition current mirror array and the output end of the subtraction current mirror array are both connected to the nodes VN and VP in the relaxation oscillator circuit. 1 Composition C 1 The charging current, the addition current mirror array, the subtraction current mirror array and I 2 Composition C 2 The charging current. 1 and I 2 The size of is constant, switch S controls the subtraction current mirror array, switch F controls the addition current mirror array, switch S is fully open by default, and switch F is fully closed by default. For example, Fig.10 The switches S and F are 7-bit binary control switches. S[0:6] defaults to all low levels, i.e., fully open by default, and F[0:6] defaults to all high levels, i.e., fully closed by default. 1 Below D 0 , then we get the offset ΔD 1 Controlling the Adding Current Mirror Array to Open ΔD 1 A current mirror is used to increase the current ΔI 1 , thereby increasing the frequency Δf 1; When the count value D 1 Higher than D 0 , then we get the offset ΔD 2 Controlling the subtraction current mirror array to turn off ΔD 2 A current mirror is used to reduce the current ΔI 2 , thereby reducing the frequency Δf 2 .

[0078] In this embodiment, the frequency multiplier oscillation clock N*f 1 The frequency count gives D 1, convert the counting result into error information ΔD, use the error information ΔD as a calibration parameter to change the output current ΔI, and then change the frequency Δf, so as to calibrate the clock frequency with current. During the calibration process, there is an error in the absolute value of the unit current and the frequency corresponding to the unit current. Therefore, when the unit current corresponding to the difference between the actual count value and the ideal value is applied to the relaxation oscillator circuit, the error will be superimposed and eventually cause a large frequency deviation. In order to eliminate this error, the current calibration circuit of this embodiment is designed as a reusable structure, which can perform multiple calibrations. When a calibration pulse is received, a calibration is performed once, and the binary value of the previous calibration cycle will not be set during each calibration cycle, so as to achieve a fast approximation calibration of the frequency. In order to achieve multiple calibrations, counter C will be reset to 0 before the arrival of each calibration pulse high level, while counter A and counter B will never be reset. Since counter A has been working before and after counter B is turned on, a judgment module should be added to stop sending the clock signal to the addition counter at the moment when the subtraction counter is turned on. In this way, counter A counts N times, that is, maintains the value of the previous calibration cycle. However, when counter B is turned on for the first time, since register A is initially reset to all 1s, and counter A is initially reset to all 0s, if N counts are made at this time, the addition current mirror array will be fully connected, causing the logic to fail. Therefore, this embodiment uses a judgment module to ensure that when the subtraction counter is first detected to be turned on, the addition counter only counts N-1 times, and when the subtraction counter is subsequently calibrated to be turned on, the addition counter is guaranteed to count N times, ensuring that the multiple calibration logics are correct. Exemplarily, assuming that the addition counter is a 6-bit counter, then theoretically, the maximum number of numbers that can be counted when the count is full is from 000000 to 111111, which is a total of 63 numbers. If one more number is counted, it will become 000000 again and will be cleared, which will cause the addition current array to be fully connected, resulting in an increase in the clock frequency (if the addition counter can count fully, it means that the clock frequency is already high enough, and the frequency should not be increased), resulting in calibration failure. Therefore, before the subtraction counter is turned on for the first time, the addition counter counts a maximum of 63 numbers, corresponding to N-1. Since the addition counter is only reset once when the tag starts working, it will not be reset before the subsequent calibration pulse. If the subtraction counter is turned on for the first time, the value of the addition counter will definitely be 111111. Then, if there is another pulse, 64 numbers must be counted before the addition counter can count to 111111 again.

[0079] like Fig.11 As shown, Fig.11The circuit structure diagram of the judgment module provided by the embodiment of the present invention is shown in FIG. The judgment module is composed of a trigger A, a trigger B, a trigger C and a selector. The input ends of trigger A and trigger C are connected to the calibration pulse, VDD and node E. The input end of trigger B is connected to the reset signal, VDD and node E. The output end of trigger A outputs a comparison signal Q. A The inverted signal Q A N, the output terminal of trigger B outputs comparison signal Q B The output terminal of trigger C outputs comparison signal Q C The inverted signal Q C N, trigger A is rising edge triggered, trigger B and trigger C are falling edge triggered. The output terminals of trigger A, trigger B and trigger C are connected to the I0, S and I1 terminals of the selector respectively, and the selector outputs the shutdown signal Z to counter A. For further information, please refer to Fig.12 , Fig.12 The first calibration pulse is at a high level, indicating that it is in the calibration stage. The transition of the signal at point E from low to high indicates that the adder counter has counted N-1 times. The trigger A is triggered by the rising edge, so Q A N flips when E jumps on the rising edge, from high level to low level, so I0 jumps from high to low. Trigger C is triggered by the falling edge, so I1 flips when E falls. Trigger B is also triggered by the falling edge, so the S signal flips from low to high. When S is low, Z selects I0 output, and when S is high, Z selects I1 output. Therefore, the signal of Z is as follows Fig.12 As shown, it is equivalent to the Z signal flipping at the rising edge of the E signal. The Z signal indicates whether to cut off the continued counting of the adder counter. When the Z signal is at a low level, it means that the count of the adder counter is cut off. At this time, the adder counter only counts N-1 numbers. When the calibration pulse signal flips from high to low, it means that the first calibration is over, trigger A and trigger C are reset, and trigger B is not reset, so I0 and I1 are reset but S is not reset. The ellipsis is followed by the start of the second calibration. The calibration pulse is at a high level. After the adder counter counts N-1 numbers, the E signal flips to a high level. Similarly, the I0 signal flips on the rising edge and the I1 signal flips on the falling edge. However, since the S signal is always at a high level, the output Z signal of the selector always selects the I1 signal output, so Z only changes when the E signal falls. Comparing the E and Z signals during the two calibrations, in the second calibration, the Z signal is delayed by one signal cycle before flipping. At this time, the adder counter will count one more number, that is, N numbers.

[0080] See also Fig.13 , Fig.13 4 is a frequency variation diagram of a low-frequency oscillation clock output by a relaxation oscillator circuit provided in an embodiment of the present invention. Fig.13 The horizontal axis is time, and the vertical axis is frequency. Fig.13 The curve shows the output signal frequency of the relaxation oscillator circuit under the FF, SF, FS and SS process feet. It can be seen that in the case of uncalibrated, the output signal frequency of the FF process foot is 147.2kHz, and the output signal frequency of the SS process foot is 108.5kHz, with a deviation of about 20%. Since the current calibration ends when the number of clock cycles reaches the target value during the calibration pulse signal enable period, there will be a rounding error, which is the calibration accuracy. After one current calibration, the output signal frequency of the FF process foot is 121.0kHz, and the output signal frequency of the SS process foot is 120.7kHz, and the deviation is significantly reduced. After 4 current calibrations, the frequency deviation under all process feet is within 4‰, and the calibration accuracy meets the BLE protocol requirements for clock accuracy. Furthermore, if the tag chip integrates on-chip memory, the calibration result can be saved in the memory, so that the calibration result is not lost after the tag is powered off, and the previous calibration result can be read after the tag chip is powered on next time without repeating the calibration.

[0081] The present embodiment provides a high-precision clock generation method for a passive BLE tag without a crystal oscillator. According to the calibration pulse signal, current calibration is performed to change the input current of the relaxation oscillator circuit, thereby changing the clock frequency. No external crystal oscillator is required, which overcomes major technical obstacles for realizing a miniaturized, highly integrated, low-cost, and easy-to-deploy BLE tag-type passive Internet of Things chip that meets the requirements. After initialization, the passive BLE tag using the high-precision clock generation method provided by the present embodiment only needs to send a few calibration pulses for calibration. After the calibration is completed, a normal carrier signal can be sent, thereby improving the energy acquisition efficiency and thereby increasing the tag communication range. And no additional carrier source is required, reducing system costs. The high-precision clock generation method provided by the present embodiment has high calibration accuracy, and the frequency deviation of the clock signal can be calibrated to within 4‰, meeting the BLE protocol communication requirements. Moreover, this embodiment relies on a low-temperature drift relaxation oscillator to generate a low-frequency oscillation clock, and uses a low-power phase-locked loop circuit to multiply the frequency to generate a multiplied oscillation clock, and uses extremely low power consumption (about 1.6μW) to achieve a higher frequency (2MHz) clock output, and the energy efficiency ratio reaches 0.79nW / KHz, which fully realizes low temperature drift and low power consumption. Moreover, compared with the traditional trimming calibration, this embodiment adopts a current calibration method, which is simpler and more convenient to operate, and can be batched for high-precision calibration, that is, a carrier source is used to calibrate several BLE tags at the same time. During the calibration process, the carrier source only needs to transmit signals without communicating, so there is no need to worry about interference between multiple tags during calibration, which improves the calibration efficiency. Moreover, the current calibration circuit no longer consumes additional power after the calibration is completed, maintaining low power consumption and high precision. The current calibration circuit provided in this embodiment is designed as a reusable structure, which avoids the cumulative error of multiple calibrations that causes calibration failure.

[0082] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-precision clock generation method for a passive BLE tag without a crystal oscillator, characterized in that: Applied to a passive BLE tag including a demodulation circuit, a current calibration circuit, a relaxation oscillator circuit and a phase-locked loop circuit, the method comprises the following steps: generating a low-frequency oscillation clock using the relaxation oscillator circuit according to the input current; According to the low-frequency oscillation clock, the phase-locked loop circuit is used to generate a frequency-multiplied oscillation clock; Determine whether there is a high-frequency carrier signal; if so, use the demodulation circuit to demodulate the high-frequency carrier signal to obtain a calibration pulse signal; if not, output the frequency-multiplied oscillation clock; According to the calibration pulse signal, within a single cycle of the calibration pulse signal, the current calibration circuit is used to quantize the frequency doubled oscillation clock to obtain frequency error information of the frequency doubled oscillation clock, the frequency error information is used as a calibration parameter to calibrate the output current, and the calibrated output current is fed back to the relaxation oscillator circuit to change the input current of the relaxation oscillator circuit.

2. According to claim 1, a high-precision clock generation method for a passive BLE tag without a crystal oscillator is characterized in that: The frequency of the low-frequency oscillation clock generated by the relaxation oscillator circuit is proportional to the magnitude of the input current of the relaxation oscillator circuit; The input current of the relaxation oscillator circuit is the sum of the constant current source current and the output current calibrated by the current calibration circuit.

3. The high-precision clock generation method for a passive BLE tag without a crystal oscillator according to claim 1 is characterized in that: Quantizing the frequency-multiplied oscillation clock using the current calibration circuit includes: The current calibration circuit is used to count rising edges of the frequency-doubled oscillation clock to obtain a first counting result.

4. According to claim 3, a high-precision clock generation method for a passive BLE tag without a crystal oscillator is characterized in that: Acquiring frequency error information of the frequency-multiplied oscillation clock, and using the frequency error information as a calibration parameter to calibrate the output current, including: When the first counting result is less than a pre-designed value, an additive difference is output according to the difference between the first counting result and the pre-designed value, and the output current is increased according to the additive difference; when the first counting result is greater than the pre-designed value, a subtractive difference is output according to the difference between the first counting result and the pre-designed value, and the output current is reduced according to the subtractive difference.

5. The high-precision clock generation method for a passive BLE tag without a crystal oscillator according to claim 4 is characterized in that: The preset count value is the product of the frequency of the preset clock and the pulse width of the preset clock.

6. The high-precision clock generation method for a passive BLE tag without a crystal oscillator according to claim 1 is characterized in that: The current calibration circuit includes: a counter A, a counter B, a counter C and a current control array, wherein: The counter C is used to count the frequency-multiplied oscillation clock to obtain a first counting result; The counter A is used to count the frequency-multiplied oscillation clock when the first counting result is less than a pre-designed value, and output an addition difference value according to the difference between the counting result and the pre-designed value; The counter B is used to count the frequency-multiplied oscillation clock when the first counting result is greater than a pre-designed value, and output a subtraction difference value according to the difference between the counting result and the pre-designed value; The current control array is used to increase the output current according to the addition difference, or to reduce the output current according to the subtraction difference.

7. The high-precision clock generation method for a passive BLE tag without a crystal oscillator according to claim 6 is characterized in that: The current control array includes: an addition current mirror array and a subtraction current mirror array, wherein: The adding current mirror array opens a corresponding number of current mirrors according to the added difference to increase the output current; The subtraction current mirror array turns off a corresponding number of current mirrors according to the subtraction difference to reduce the output current.

8. The high-precision clock generation method for a passive BLE tag without a crystal oscillator according to claim 1, characterized in that: The demodulation circuit comprises: an envelope detection subcircuit, a low-pass filter, a peak holding subcircuit, a hysteresis comparator and a D flip-flop; The envelope detection subcircuit is used to extract an envelope signal from the high-frequency carrier signal; The low-pass filter is used to eliminate noise from the envelope signal and generate V x Signal; The peak holding subcircuit is used to x Signal generation V y Signal; The hysteresis comparator is used to x signal and the V y The signal generates a calibration pulse signal represented by a falling edge; The D flip-flop is used to convert the calibration pulse signal represented by a falling edge into a calibration pulse signal represented by a rising edge.

9. The high-precision clock generation method for a passive BLE tag without a crystal oscillator according to claim 1, characterized in that: The relaxation oscillator circuit includes: a two-phase charge and discharge electronic circuit, a comparator, a Schmitt trigger and a logic gate circuit, wherein: The comparator is used to output a low-frequency oscillation clock through the Schmitt trigger according to the output current of the two-phase charge and discharge electronic circuit; the comparator uses the reference voltage generated by the reference circuit as the flip threshold voltage; The logic gate subcircuit is used to generate a control signal for controlling the two-phase charging and discharging electronic circuit according to the low-frequency oscillation clock.

10. The high-precision clock generation method for a passive BLE tag without a crystal oscillator according to claim 1, characterized in that: The phase-locked loop circuit comprises: a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider connected in sequence, wherein: The reference frequency input terminal of the frequency detector is input with the low frequency oscillation clock, and the feedback frequency input terminal of the frequency detector is connected with the output terminal of the frequency divider; The output end of the voltage-controlled oscillator outputs the frequency-multiplied oscillation clock; The output frequency f of the voltage controlled oscillator VCO The formula is: Where f0 is the oscillation frequency provided by the initial current, k is the proportional factor, V ctrl is the control voltage of the voltage controlled oscillator, C0 is the value of the capacitor in the voltage controlled oscillator, and VDD is the supply voltage of the voltage controlled oscillator.

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