Bootstrap switch circuit and analog-to-digital converter thereof
By designing a bootstrap switching circuit in the sampling module of the analog-to-digital converter, and using the switching state to switch the switching unit to bootstrap the sampling capacitor several times, it solves the problem that traditional technology cannot reduce power consumption by reducing the power supply voltage, and achieves signal acquisition and power consumption reduction in a wider dynamic range.
Patent Information
- Application Number
- CN202411980755.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-22
AI Technical Summary
Traditional bootstrap switching technology cannot reduce power consumption by reducing the power supply voltage at the same dynamic range of signal input.
A bootstrap switching circuit is designed. By introducing the first and second switching units into the sampling module, switching the switching states in the non-sampled phase and the sampling phase respectively, so that the sampling capacitor can boot several times at a lower power supply voltage, increasing the dynamic range of the collected signal.
It realizes the acquisition of a wider dynamic range input signal at a lower power supply voltage, reducing the power consumption of the analog-to-digital converter while ensuring high linearity signal acquisition.
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Figure CN119865172A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a bootstrap switch circuit and an analog-to-digital converter thereof. Background Art
[0002] In the design and application of analog-to-digital converters (ADCs), the analog front end of the ADC chip is a sample-and-hold circuit, which samples and holds the input signal on the input capacitor through a sampling switch and a sampling capacitor. In order to obtain a high-linearity sampling switch, a relatively constant sampling switch resistance is required; in order to enable the analog-to-digital converter to work at a higher bandwidth, the sampling resistance needs to be as small as possible.
[0003] Traditional sampling switches use bootstrap switching technology, such as Figure 1 As shown, M1 is a sampling switch MOS tube. In the non-sampling phase, switches S1, S2, and S5 are closed, S3 and S4 are disconnected, the MOS tube M1 is disconnected, and the capacitor C1 is charged to the power supply voltage VDD; in the sampling phase, switches S1, S2, and S5 are disconnected, and S3 and S4 are closed, so that the voltage difference between the gate and the source of the MOS tube M1 is always the power supply voltage VDD, which is independent of the input signal, ensuring the consistency of the on-resistance and improving the linearity of signal acquisition.
[0004] However, Figure 1 The circuit shown can only collect signals with an input dynamic range less than VDD. If the collected signal is to be greater than VDD, a MOS tube with a higher withstand voltage is required, and the MOS tube is often longer. If the VDD voltage is still used to drive the switch tube, the switch on resistance will be too large, and the linearity can only be guaranteed by reducing the sampling frequency of the system. In other words, the traditional bootstrap switch technology cannot guarantee the reduction of power consumption by reducing the power supply voltage under the same input dynamic range. Summary of the invention
[0005] The technical problem to be solved by the present invention is that the conventional bootstrap switch cannot guarantee the reduction of power consumption by reducing the power supply voltage under the same signal input dynamic range.
[0006] In a first aspect of the present invention, in order to solve the above technical problem, a bootstrap switch circuit is provided, which is applied to a sampling module of a low-power and high-precision analog-to-digital converter. The bootstrap switch circuit comprises: Sampling switch; The sampling capacitor is configured with a first switch unit, and the sampling capacitors are connected in series through a second switch unit; the bootstrap switch circuit includes two working states: a non-sampling phase and a sampling phase, wherein: In the non-sampling phase, the first switch unit is closed, the second switch unit is opened, and the sampling switch is opened, so that both ends of the sampling capacitor are charged to the power supply voltage; In the sampling phase, the first switch unit is disconnected, the second switch unit is closed, and the sampling switch is turned on, so as to bootstrap the power supply voltage several times and then add it to the sampling switch, so that the sampling module can collect inputs with a wider dynamic range under the power supply voltage.
[0007] Furthermore, the sampling switch is a MOS tube M1, wherein: The gate of the MOS tube M1 is grounded; The source of the MOS tube M1 is connected to the input signal port; The drain of the MOS tube M1 is connected to the output signal port.
[0008] Further, the sampling capacitor includes a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, wherein: The capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2, twice the capacitance value of the third capacitor C3, and twice the capacitance value of the fourth capacitor C4.
[0009] Further, the first switch unit includes a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6 and a switch S10; the second switch unit includes a switch S7, a switch S8, a switch S9 and a switch S11, wherein: The switch S1, the first capacitor C1, and the switch S2 are sequentially connected in series between the power supply voltage and the ground; The switch S3, the second capacitor C2, and the switch S4 are sequentially connected in series between the power supply voltage and the ground; The switch S5, the third capacitor C3, and the switch S6 are sequentially connected in series between the power supply voltage and the ground; The upper end of the first capacitor C1 and the lower end of the second capacitor C2 are connected via the switch S7; The lower end of the first capacitor C1 is connected to the source of the MOS transistor M1 through the switch S11; The gate of the MOS tube M1 is grounded through the switch S10; The upper end of the second capacitor C2 is connected to the lower end of the third capacitor C3 via the switch S8; The third capacitor C3 and the fourth capacitor C4 are connected in parallel via the switch S9.
[0010] Further: In the non-sampling phase, the first switch unit is closed, the second switch unit is opened, the gate of the MOS tube M1 is grounded, and the MOS tube M1 is opened, then the power supply voltage charges the first capacitor C1, the second capacitor C2, and the third capacitor C3, and the voltage values of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are charged to the power supply voltage; In the sampling phase, the first switch unit is opened and the second switch unit is closed, then the voltage value across the third capacitor C3 and the fourth capacitor C4 is 1 / 2 of the power supply voltage, and the voltage value of the MOS tube M1 is the sum of the voltage values of the first capacitor C1, the second capacitor C2 and the third capacitor C3.
[0011] Furthermore, in the sampling phase, the sampling capacitor can bootstrap the power supply voltage by 2.5 times and then add it to the sampling switch.
[0012] A second aspect of the present invention provides an analog-to-digital converter, comprising a sampling module, wherein the sampling module comprises the bootstrap switch circuit.
[0013] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: The present invention can bootstrap the power supply voltage by 2.5 times through a bootstrap switch circuit and then add it to the sampling switch, so that the sampling module of the analog-to-digital converter can collect inputs with a higher dynamic range under the power supply of a lower power supply voltage, thereby reducing the power consumption of the analog-to-digital converter while also ensuring its input dynamic range. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.
[0015] Figure 1 It is the schematic diagram of the traditional bootstrap switch circuit; Figure 2 A simplified schematic diagram of the bootstrap switch circuit disclosed in the present invention; Figure 3 The present invention is a circuit diagram for a specific implementation of the bootstrap switch circuit disclosed in the present invention. DETAILED DESCRIPTION
[0016] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0017] The input dynamic range of the signal collected by the traditional bootstrap switch circuit is smaller than the power supply voltage. If the collected signal is to be greater than the power supply voltage, a MOS tube with a higher withstand voltage is required, and the MOS tube is often longer. If the power supply voltage is still used to drive the switch MOS tube, the on-resistance of the switch MOS tube will be too large. In this case, the linearity can only be ensured by reducing the sampling frequency of the system. In view of this, the present invention provides a bootstrap switch circuit, which is applied to the sampling module of a low-power and high-precision analog-to-digital converter.
[0018] The bootstrap switch circuit of the present invention comprises a sampling switch and a sampling capacitor, wherein the sampling capacitor is configured with a first switch unit, and the sampling capacitors are connected in series via a second switch unit.
[0019] The bootstrap switch circuit includes two working states: non-sampling phase and sampling phase, where: In the non-sampling phase, the first switch unit is closed, the second switch unit is opened, and the sampling switch is opened, so that both ends of the sampling capacitor are charged to the power supply voltage.
[0020] In the sampling phase, the first switch unit is disconnected, the second switch unit is closed, and the sampling switch is turned on. The power supply voltage can be bootstrapped several times and then added to the sampling switch, so that the sampling module can collect inputs with a wider dynamic range under the power supply voltage.
[0021] In a further embodiment of the present invention, see Figure 2 The sampling capacitor includes a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.
[0022] The capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2, twice the capacitance value of the third capacitor C3, and twice the capacitance value of the fourth capacitor C4.
[0023] The sampling switch is a MOS tube M1, wherein the gate of the MOS tube M1 is grounded; the source of the MOS tube M1 is connected to the input signal port; and the drain of the MOS tube M1 is connected to the output signal port.
[0024] The first switch unit includes a switch S1 , a switch S2 , a switch S3 , a switch S4 , a switch S5 , a switch S6 and a switch S10 ; the second switch unit includes a switch S7 , a switch S8 , a switch S9 and a switch S11 .
[0025] in: The switch S1, the first capacitor C1, and the switch S2 are sequentially connected in series between the power supply voltage and the ground.
[0026] The switch S3, the second capacitor C2, and the switch S4 are sequentially connected in series between the power supply voltage and the ground.
[0027] The switch S5, the third capacitor C3, and the switch S6 are sequentially connected in series between the power supply voltage and the ground.
[0028] The upper end of the first capacitor C1 and the lower end of the second capacitor C2 are connected via a switch S7.
[0029] The lower end of the first capacitor C1 is connected to the source of the MOS transistor M1 through the switch S11.
[0030] The gate of the MOS tube M1 is grounded through the switch S10.
[0031] The upper end of the second capacitor C2 and the lower end of the third capacitor C3 are connected via a switch S8.
[0032] The third capacitor C3 and the fourth capacitor C4 are connected in parallel via the switch S9.
[0033] Specifically: In the non-sampling phase, switches S1, S2, S3, S4, S5, S6 and S10 are closed, switches S7, S8, S9 and S11 are opened, the gate of the MOS tube M1 is grounded, and the MOS tube M1 is opened. At this time, the power supply voltage VDD charges the first capacitor C1, the second capacitor C2 and the third capacitor C3 respectively, and charges both ends of the first capacitor C1, the second capacitor C2 and the third capacitor C3 to the power supply voltage VDD, that is, 1.8V.
[0034] In the sampling phase, switches S1, S2, S3, S4, S5, S6 and S10 are disconnected, and switches S7, S8, S9 and S11 are closed. Since the capacitance value of the third capacitor C3 is equal to the capacitance value of the fourth capacitor C4, and both ends of the fourth capacitor C4 are grounded in the non-sampling phase, that is, there is no charge on the fourth capacitor C4. When switch S9 is closed, the charge on the third capacitor C3 will be divided by half by the fourth capacitor C4. At this time, the voltages across the third capacitor C3 and the fourth capacitor C4 are both half of the power supply voltage VDD, that is, 0.9V. At this time, the first capacitor C1 is connected in series with the second capacitor C2 through the switch S7, the second capacitor C2 is connected in parallel with the third capacitor C3 and the fourth capacitor C4 through the switch S8, and then connected in series, and then connected in parallel with the gate and source of the MOS tube M1 through the switch S11 and the switch S9. Then, the voltage value at both ends of the MOS tube M1 is the sum of the voltage values of the first capacitor C1, the second capacitor C2 and the third capacitor C3, that is, 1.8+1.8+0.9=4.5V.
[0035] When the dynamic range of the signal input to be collected is 5V, the sampling module uses a 5V withstand voltage MOS tube M1 to ensure that the sampling module will not be damaged by overvoltage. However, 4.5V can drive the 5V withstand voltage MOS tube M1 well, so that the on-resistance of the MOS tube M1 can be kept at a small value and relatively constant, and can support high linearity and a certain rate of sampling.
[0036] Example Please refer to Figure 3 The specific implementation circuit of the bootstrap switch circuit provided by the present invention, wherein the sampling switch is a MOS tube M1, CK is an input clock signal, VIN is an input signal interface, VOUT is an output signal interface, and VDD is a power supply voltage of 1.8V.
[0037] In a further solution of this embodiment, the circuit composed of the capacitor C1, the capacitor C2, the MOS transistor M2, the MOS transistor M3 and the inverter I1 is a charge pump circuit.
[0038] When CK is at a high level or when CKn is at a high level, the upper end of capacitor C1 or capacitor C2 can be raised to twice the power supply voltage to drive MOS tubes M4, M5, and M6 to turn on and increase the output voltage of inverter I2 to drive MOS tubes M8 and M9 to turn on.
[0039] The bootstrap switch is divided into two states when working: sampling phase and non-sampling phase, where: When the input clock signal CK is at a low level, the bootstrap switch circuit is in a non-sampling phase, the MOS tube M7 is turned on, and the MOS tubes M10, M11, and M12 are turned off.
[0040] After the input clock signal CK passes through the inverter I1, CKn is at a high level, so that the MOS tubes M13, M14, M15, M17, and M18 are turned on. At the same time, the voltage at the upper end of the capacitor C2 is twice the power supply voltage VDD, so that the MOS tubes M4, M5, and M6 are turned on, and the capacitors C3, C4, and C5 are charged to the power supply voltage VDD, and both ends of the capacitor C6 are grounded and discharged.
[0041] After CKn passes through the inverter I2, CKh is at a low level, so that the MOS tubes M8, M9, and M16 are disconnected, and the gate of the MOS tube M1 is grounded, so the MOS tube M1 is in a disconnected state.
[0042] When the input clock signal CK is at a high level, the bootstrap switch circuit is in a sampling phase, and the MOS tube M7 is disconnected.
[0043] After the input clock signal CK passes through the inverter I1, CKn is at a low level, so that MOS transistors M13, M14, M15, M17, and M18 are disconnected. At the same time, the voltage at the upper end of the capacitor C2 is the power supply voltage VDD, so that MOS transistors M4, M5, and M6 are disconnected.
[0044] After CKn passes through the inverter I2, CKh is at a high level twice VDD, so that MOS tubes M8, MOS tubes M9, and MOS tubes M16 are turned on. The sources of MOS tubes M10, MOS tubes M11, and MOS tubes M12 are higher than the gates by VDD, so they are in the turned-on state. Capacitors C5 and C6 are connected in parallel, and are connected in series with capacitors C3 and C4. After completing 2.5 times voltage bootstrapping, they are connected in parallel to the gate and source of MOS tube M1, so that MOS tube M1 is turned on.
[0045] The present invention further provides an analog-to-digital converter, comprising a sampling module, wherein the sampling module comprises the above-mentioned bootstrap switch circuit.
[0046] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A bootstrap switch circuit, characterized in that: A sampling module applied to a low-power and high-precision analog-to-digital converter, the bootstrap switch circuit comprises: Sampling switch; The sampling capacitor is configured with a first switch unit, and the sampling capacitors are connected in series through a second switch unit; the bootstrap switch circuit includes two working states: a non-sampling phase and a sampling phase, wherein: In the non-sampling phase, the first switch unit is closed, the second switch unit is opened, and the sampling switch is opened, so that both ends of the sampling capacitor are charged to the power supply voltage; In the sampling phase, the first switch unit is disconnected, the second switch unit is closed, and the sampling switch is turned on, so as to bootstrap the power supply voltage several times and then add it to the sampling switch, so that the sampling module can collect inputs with a wider dynamic range under the power supply voltage.
2. The bootstrap switch circuit according to claim 1, characterized in that: The sampling switch is a MOS tube M1, wherein: The gate of the MOS tube M1 is grounded; The source of the MOS tube M1 is connected to the input signal port; The drain of the MOS tube M1 is connected to the output signal port.
3. The bootstrap switch circuit according to claim 2, characterized in that: The sampling capacitor includes a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, wherein: The capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2, twice the capacitance value of the third capacitor C3, and twice the capacitance value of the fourth capacitor C4.
4. The bootstrap switch circuit according to claim 3, characterized in that: The first switch unit includes a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6 and a switch S10; the second switch unit includes a switch S7, a switch S8, a switch S9 and a switch S11, wherein: The switch S1, the first capacitor C1, and the switch S2 are sequentially connected in series between the power supply voltage and the ground; The switch S3, the second capacitor C2, and the switch S4 are sequentially connected in series between the power supply voltage and the ground; The switch S5, the third capacitor C3, and the switch S6 are sequentially connected in series between the power supply voltage and the ground; The upper end of the first capacitor C1 and the lower end of the second capacitor C2 are connected via the switch S7; The lower end of the first capacitor C1 is connected to the source of the MOS transistor M1 through the switch S11; The gate of the MOS tube M1 is grounded through the switch S10; The upper end of the second capacitor C2 is connected to the lower end of the third capacitor C3 via the switch S8; The third capacitor C3 and the fourth capacitor C4 are connected in parallel via the switch S9.
5. The bootstrap switch circuit according to claim 4, characterized in that: In the non-sampling phase, the first switch unit is closed, the second switch unit is opened, the gate of the MOS tube M1 is grounded, and the MOS tube M1 is opened, then the power supply voltage charges the first capacitor C1, the second capacitor C2, and the third capacitor C3, and the voltage values of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are charged to the power supply voltage; In the sampling phase, the first switch unit is opened and the second switch unit is closed, then the voltage value across the third capacitor C3 and the fourth capacitor C4 is 1 / 2 of the power supply voltage, and the voltage value of the MOS tube M1 is the sum of the voltage values of the first capacitor C1, the second capacitor C2 and the third capacitor C3.
6. The bootstrap switch circuit according to claim 1, characterized in that: In the sampling phase, the sampling capacitor can bootstrap the power supply voltage by 2.5 times and then add it to the sampling switch.
7. An analog-to-digital converter, comprising a sampling module, characterized in that: The sampling module comprises the bootstrap switch circuit according to any one of claims 1-6.