Comparator, analog-to-digital converter, image sensor, and electronic device

Abstract

The invention provides a comparator, an analog-to-digital converter, an image sensor and electronic equipment. The comparator comprises a differential amplifier, a first capacitor and N second capacitors, the first input end of the comparator is used for acquiring electric signals output by one or more columns of sensors in the sensor array; the second input end of the comparator is used for acquiring the reference level generated by the reference level generator; a first port of the first capacitor is coupled with a reverse input end of the differential amplifier, and a second port of the first capacitor is coupled with a first input end of the comparator; the first port of the ith second capacitor in the N second capacitors is coupled with the reverse input end of the differential amplifier, and the second port of the ith second capacitor is coupled with the output end of the differential amplifier. According to the technical scheme, the gain of the comparator is adjusted by setting the first capacitor and the second capacitor, so that the peak value of the recoil signal is reduced. Therefore, the image quality can be improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and more specifically, to a comparator, an analog-to-digital converter, an image sensor, and an electronic device. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensors are the mainstream image sensors currently. CMOS image sensors (CIS) are widely used in various electronic devices, such as mobile phones, tablet computers, laptops, digital cameras, digital video cameras, and so on.

[0003] Column-parallel output is the mainstream output mode of CMOS image sensors. CMOS image sensors with column-parallel output can read data by row at a time, which can reduce data reading events and achieve high-speed, high-frame-rate image acquisition. When reading data by row, data of all columns in the same row in the sensor array are read out. CMOS image sensors include analog to digital converters (ADCs). Each comparator in the ADC corresponds to one or more columns of sensors in the sensor array. The comparator converts the acquired analog signal into a digital signal based on the reference level.

[0004] The comparator in the ADC may generate a kick back signal under the influence of cross-talk capacitance. The kick back signal will affect other comparators, thereby affecting the image quality of the output image. Therefore, how to weaken the kick back signal to reduce or avoid the image quality degradation caused by the kick back signal is an urgent problem to be solved in the art. Summary of the invention

[0005] The present application provides a comparator, an analog-to-digital converter, an image sensor, and an electronic device. The comparator can reduce the peak value of a kickback signal, thereby improving image quality.

[0006] In a first aspect, an embodiment of the present application provides a comparator, which includes: a differential amplifier, a first capacitor and N second capacitors, N is a positive integer greater than or equal to 1; the first input terminal of the comparator is used to obtain the electrical signal output from one or more columns of sensors in the sensor array; the second input terminal of the comparator is used to obtain the reference level generated by a reference level generator; the first port of the first capacitor is coupled to the reverse input terminal of the differential amplifier, and the second port of the first capacitor is coupled to the first input terminal of the comparator; the first port of the i-th second capacitor among the N second capacitors is coupled to the reverse input terminal of the differential amplifier, and the second port of the i-th second capacitor is coupled to the output terminal of the differential amplifier, i=1,…,N.

[0007] In the above technical solution, the first capacitor and the second capacitor are the main factors affecting the gain of the comparator. In this way, the gain of the comparator can be adjusted by setting the first capacitor and the second capacitor. The gain of the comparator determines the fall time of the output signal of the differential amplifier of the comparator. The peak value of the kickback signal is proportional to the inverse of the fall time of the output signal of the differential amplifier of the comparator. Therefore, selecting the appropriate first capacitor and the second capacitor can increase the fall time of the output signal of the differential amplifier, thereby reducing the peak value of the kickback signal. In this way, the image quality can be improved.

[0008] In combination with the first aspect, in a possible implementation of the first aspect, the comparator also includes a third capacitor and M fourth capacitors, M is a positive integer greater than or equal to 1, wherein a first port of the third capacitor is coupled to the positive input terminal of the differential amplifier, and a second port of the third capacitor is coupled to the second input terminal of the comparator; the jth fourth capacitor among the M fourth capacitors is connected in parallel with the third capacitor, j=1,…,M.

[0009] In combination with the first aspect, in a possible implementation manner of the first aspect, the first capacitor matches the third capacitor, and the N second capacitors match the M fourth capacitors.

[0010] The above technical solution achieves capacitance matching through the third capacitor and the fourth capacitor, thereby improving the performance, stability and reliability of the circuit.

[0011] In combination with the first aspect, in a possible implementation of the first aspect, the comparator further includes a switching circuit, which is used to control the second ports of the N second capacitors to be coupled with the output end of the differential amplifier or the first input end of the comparator.

[0012] The operating mode of the comparator can be selected by the switch circuit, so that the comparator can operate in different operating modes. For example, the kickback signal in the low-gain operating mode has a greater impact on image quality, while the kickback signal has a relatively small impact on high-resolution operation compared to the low-gain operating mode. Therefore, the comparator can support different operating modes by the switch circuit.

[0013] In combination with the first aspect, in a possible implementation of the first aspect, the switching circuit includes N first switches, a moving end of an i-th first switch among the N first switches is coupled to the second port of the i-th second capacitor, a first contact of the i-th first switch is coupled to the first input end of the comparator, and a second contact of the i-th first switch is coupled to the output end of the differential amplifier.

[0014] In combination with the first aspect, in a possible implementation of the first aspect, the switch circuit includes a second switch and N third switches, the moving end of the i-th third switch among the N third switches is coupled to the second port of the i-th second capacitor, the first contact of the i-th third switch is coupled to the first input end of the comparator, the second contact of the i-th third switch is coupled to the moving end of the second switch, the first contact of the second switch is coupled to the output end of the differential amplifier, and the second contact of the second switch is grounded.

[0015] In combination with the first aspect, in a possible implementation of the first aspect, the gain of the comparator satisfies the following formula: A0=-(C INN / C FBN ), where A0 is the gain of the comparator, C INN is the capacitance value of the first capacitor, C FBN is the equivalent capacitance value of the N second capacitors.

[0016] In a second aspect, an embodiment of the present application provides an analog-to-digital converter ADC, which includes: a reference level generator and at least one comparator as in the first aspect or any possible implementation of the first aspect, wherein the output end of the reference level generator is coupled to the second input end of each comparator of the at least one comparator, and the first input end of each comparator is used to couple to the output port of the sensor.

[0017] In combination with the second aspect, in a possible implementation of the second aspect, the ADC also includes: at least one counter and at least one latch, the at least one counter corresponds one-to-one to the at least one comparator, the output end of each comparator in the at least one comparator is coupled to the input end of the corresponding counter, the at least one counter corresponds one-to-one to the at least one latch, and the output end of each counter in the at least one counter is coupled to the input end of the corresponding latch.

[0018] In a third aspect, an embodiment of the present application provides an image sensor, comprising: a sensor array, an ADC such as the second aspect or a possible implementation of the second aspect, each comparator in the ADC corresponds to one or more columns of sensors in the sensor array, and a first input terminal of each comparator is coupled to an output port of the corresponding one or more columns of sensors.

[0019] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes the image sensor provided in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural diagram of an electronic device.

[0021] Figure 2 It is a schematic structural block diagram of a CMOS image sensor.

[0022] Figure 3 is a schematic diagram of a ramp signal.

[0023] Figure 4 It is a schematic diagram of an ADC provided according to an embodiment of the present application.

[0024] Figure 5 is a schematic diagram of a comparator.

[0025] Figure 6 It is a schematic structural block diagram of a comparator provided according to an embodiment of the present application.

[0026] Figure 7 It is a schematic structural block diagram of another comparator provided according to an embodiment of the present application.

[0027] Figure 8 is a schematic diagram of another comparator provided according to an embodiment of the present application.

[0028] Fig. 9 is a schematic diagram of another comparator provided according to an embodiment of the present application.

[0029] Fig.10 is a schematic diagram of another comparator provided according to an embodiment of the present application.

[0030] Fig.11 is a schematic diagram of another comparator provided according to an embodiment of the present application.

[0031] Fig.12 is a schematic diagram of another comparator provided according to an embodiment of the present application.

[0032] Fig.13 is a structural diagram of another comparator provided according to an embodiment of the present application.

[0033] Fig.14 is a schematic diagram of a comparator provided according to an embodiment of the present application.

[0034] Fig.15 is a schematic diagram of a comparator provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0036] In the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0037] In the embodiments of the present application, "corresponding (corresponding, relevant)" and "corresponding (corresponding)" can sometimes be used interchangeably. It should be pointed out that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0038] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0039] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0040] For example, Figure 1 1 shows a schematic diagram of the structure of an electronic device 100. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, a camera 150, a display screen 160, and the like.

[0041] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0042] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a memory, a video codec, and / or a digital signal processor (DSP), etc. Different processing units may be independent devices or integrated into one or more processors.

[0043] The controller may be the nerve center and command center of the electronic device 100. The controller may generate an operation control signal according to the instruction operation code and the timing signal to complete the control of fetching and executing instructions.

[0044] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0045] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general- / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0046] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple groups of I2C buses. The processor 110 can charge the charger, flash, camera 150, etc. through different I2C bus interfaces. For example, the processor 110 can couple the touch sensor through the I2C interface, so that the processor 110 communicates with the touch sensor through the I2C bus interface to realize the touch function of the electronic device 100.

[0047] The MIPI interface can be used to connect the processor 110 with devices such as the camera 150 and the display screen 160. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), etc. In some embodiments, the processor 110 and the camera 150 communicate via the CSI interface to implement the shooting function of the electronic device 100. The processor 110 and the display screen 160 communicate via the DSI interface to implement the display function of the electronic device 100.

[0048] The GPIO interface can be configured by software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 with the camera 150, the display screen 160, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0049] The USB interface 130 is an interface that complies with the USB standard specification, and can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 130 can be used to connect a charger to charge the electronic device 100, and can also be used to transfer data between the electronic device 100 and other electronic devices (such as a laptop, a tablet computer, a mobile phone, etc.). It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices, etc.

[0050] It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present application is only a schematic illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0051] The charging management module 140 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100. While the charging management module 140 is charging the battery 142, it may also power the electronic device through the power management module 141.

[0052] The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the external memory, the camera 150, the display screen 160, etc. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0053] The electronic device 100 implements the display function through a GPU, a display screen 160, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 160 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0054] The display screen 160 is used to display images, videos, etc. The display screen 160 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), MiniLED, MicroLED, Micro-OLED, quantum dot light-emitting diodes (QLED), etc. In some embodiments, the electronic device 100 may include one display screen 160. In other embodiments, the electronic device 100 may include two or more display screens 160.

[0055] The electronic device 100 can realize the shooting function through the ISP, the camera 150, the video codec, the GPU, the display screen 160 and the application processor.

[0056] The ISP is used to process the data fed back by the camera 150. For example, when taking a photo, the shutter is opened and light is transmitted to the image sensor of the camera through the lens. The image sensor converts the light signal into an electrical signal, which is then transmitted to the ISP for processing and converted into an image visible to the naked eye. The ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image. The ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, the ISP can be set in the camera 150.

[0057] The camera 150 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the image sensor. The image sensor may be a complementary metal-oxide-semiconductor (CMOS) image sensor. The image sensor converts the optical signal into an electrical signal, and then transmits the electrical signal to the ISP for conversion into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include one camera 150. In other embodiments, the electronic device 100 may include two or more cameras 150, where N is a positive integer greater than 1.

[0058] The digital signal processor is used to process digital signals, and can process not only digital image signals but also other digital signals. For example, when the electronic device 100 is selecting a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0059] Video codecs are used to compress or decompress digital videos. The electronic device 100 may support one or more video codecs. Thus, the electronic device 100 may play or record videos in a variety of coding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0060] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function, such as storing images, videos, and other files in the external memory card.

[0061] The internal memory 121 can be used to store computer executable program codes, which include instructions. The processor 110 executes various functional applications and data processing of the electronic device 100 by running the instructions stored in the internal memory 121. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0062] Figure 2 This is a schematic block diagram of a CMOS image sensor. Figure 2 The CMOS image sensor 200 shown can be applied to Figure 1 The electronic device 100 shown. For example, Figure 1 The camera 150 of the electronic device 100 shown may include: Figure 2 A CMOS image sensor 200 is shown.

[0063] like Figure 2 As shown, the CMOS image sensor 200 includes a sensor array 210 , a vertical scanning circuit 220 , and an ADC 230 .

[0064] The sensor array 210 includes a plurality of photoelectric sensors 211. The photoelectric sensors 211 are used to acquire light signals and perform photoelectric conversion on the light signals to obtain electrical signals.

[0065] like Figure 2 As shown, the ADC 230 includes a reference level generator 231 and a plurality of comparators 232 .

[0066] The reference level generator 231 is used to generate a reference level. The reference level can be a continuous signal that rises or falls (can be called a ramp signal). For example, the reference level can be monotonically or linearly increased from a minimum level (e.g., 0 volts) to a maximum level (e.g., a power supply voltage). In some embodiments, the reference level generator can also be called a reference digital to analog converter (DAC).

[0067] In some embodiments, the reference level generator 231 may generate a reference level.

[0068] In some other embodiments, the reference level generator 231 may generate a plurality of reference levels. In this case, the comparator 232 may be coupled to the reference level generator 230 via a switch circuit. The switch circuit may be used to select the reference level input to the comparator 232.

[0069] Figure 3 is a schematic diagram of a ramp signal.

[0070] like Figure 3 As shown, the ramp signal includes two falling ramps. The two falling ramps correspond to two sampling moments respectively. The first falling ramp relatively quickly drops the pixel signal from the photosensor from a high level to a level close to the baseline level for the first sampling. Then, after a time interval, the second falling ramp starts, dropping the pixel signal from a high level to a level close to the baseline level again for the second sampling. By calculating the difference between the two sampled values, the result of eliminating the fixed analog voltage offset and certain types of noise can be obtained.

[0071] By changing the amplitude of the ramp signal, resolution control can be achieved, that is, changing the correspondence between the analog voltage and the digital value (DN). The resolution is defined by the maximum output code value of the ADC and the pixel signal. The ADC converts the pixel signal into a digital signal and represents it with a fixed-bit binary code. When the ADC full code (that is, the maximum output code value that the ADC can achieve) corresponds to the maximum signal of the pixel, it is defined as 1 times (that is, x1) or the gain is 0 decibels (decibel, dB); when the amplitude of the ramp signal is halved and reduced by one quarter, the resolution becomes twice and four times, respectively, that is, x2 (also known as a gain of 6dB) and x4 (also known as a gain of 12dB).

[0072] like Figure 2 Each of the multiple comparators 232 shown corresponds to a column of photosensors 211. The comparator 232 obtains an analog signal (which may be referred to as a pixel signal) from a corresponding column of photosensors 211, and converts the obtained pixel signal into a digital signal according to a reference signal from the reference level generator 231.

[0073] exist Figure 2 In the CMOS image sensor 200 shown, each comparator corresponds to a column of photosensors in the sensor array. In other embodiments, one comparator may correspond to two or more columns of photosensors. In other embodiments, one column of photosensors may also correspond to two or more comparators.

[0074] In some embodiments, the ADC 230 may also include a counter and a latch (not shown). Each comparator 232 in the ADC 230 has a corresponding counter and latch. The comparator 232 compares the reference level with the pixel and measures the time of the cross point. The counter records the time as the result of the ADC. In this way, the pixel signal from the photosensor 211 can be converted into a digital signal. The digital signal is stored by the latch. The digital signal stored by the latch can be sent to a subsequent signal processing circuit, and the signal processing circuit can generate a corresponding image based on the acquired digital signal.

[0075] As described above, each comparator in the ADC may have a corresponding latch and a counter. For ease of description, the ADC may be divided into a plurality of ADC units, wherein each of the plurality of ADC units includes a comparator and a counter and latch corresponding to the comparator. In other words, the ADC may include a reference level generator and a plurality of ADC units.

[0076] Figure 4It is a schematic diagram of an ADC provided according to an embodiment of the present application. Figure 4 The reference level generator 410 in the ADC 400 shown in FIG. 4 includes two ADC units, ADC unit 420 and ADC unit 430. Figure 4 As shown, the ADC unit 420 includes a comparator 421, a counter 422 and a latch 423; the ADC unit 430 includes a comparator 431, a counter 432 and a latch 433. The comparators 421 and 431 are coupled to the reference level generator 410 to obtain the reference level from the reference level generator 412, and the comparators 421 and 431 also obtain pixel signals from the corresponding one or more columns of photosensors.

[0077] Figure 5 is a schematic diagram of a comparator. Figure 5 The illustrated comparator 510 includes a first comparator section 511 and a second comparator section 512 .

[0078] The first comparator section 511 includes a differential amplifier 519 , a capacitor 517 , and a capacitor 518 .

[0079] One end of the capacitor 517 is coupled to the positive input (INP) end of the differential amplifier 519, and the other end of the capacitor 517 is coupled to the first input end 513 of the first comparator section 511. The first input end 513 of the first comparator section 511 is coupled to the reference level generator 520 to obtain the reference level from the reference level generator 520. Therefore, the first input end 513 of the first comparator section 511 can also be considered as an input end of the comparator 510.

[0080] One end of the capacitor 518 is coupled to the inverting input (input negative, INN) end of the differential amplifier 519, and the other end of the capacitor 518 is coupled to the second input end 514 of the first comparator unit 511. The second input end 514 of the first comparator unit 511 is coupled to the corresponding one or more columns of sensors in the sensor array to obtain pixel signals. Therefore, the second input end 514 of the first comparator unit 511 can also be considered as another input end of the comparator 510.

[0081] The capacitor 517 and the capacitor 518 are used for the auto-zero process. Therefore, the first comparator unit 511 may also be called an auto-zero comparator.

[0082] The first comparator section 511 outputs the comparison result of the received reference level and the pixel signal as a differential signal to the second comparator section 512. The second comparator section 512 is a buffer for buffering the differential output so as to input the output of the first comparator section 511 to a subsequent circuit (such as a counter) at an appropriate level.

[0083] like Figure 5 As shown, there is a cross-talk capacitance 515 between the output terminal (i.e., node 516) and the positive input terminal of the first comparator unit 511. Figure 5 The reference level generator 520 shown may include an inherent reference level generator 521 and a buffer comparator 522. The inherent reference level generator 521 is used to output an initial reference level, and the buffer comparator 522 is used to buffer and amplify the initial reference level output by the inherent reference level generator to obtain a reference level that is finally output to the comparator 510. There is an output resistor in the buffer comparator 522. This output resistor and the crosstalk capacitor 515 can form a high-pass filter. Due to the high-pass filter, the output of the first comparator unit 511 (i.e., the first-stage output) will form a truncated pulse waveform. This truncated pulse waveform will cause a kickback signal. Since the reference level generator 520 is also coupled to other comparators in the ADC, the kickback signal may be transmitted to other comparators. In this way, the kickback signal may affect the output signal of the ADC, thereby causing the quality of the output image to deteriorate, for example, stripes may be generated in the output image.

[0084] It is understandable that if Figure 5 The auto-zero comparator (i.e., the first comparator section 511) shown in FIG. 1 is only an example of a comparator that can be applied to an ADC. Other types of comparators can also be used in the ADC. For example, the first comparator section of the comparator can also only use Figure 5 The differential amplifier 519 in the first comparator section 511 is shown.

[0085] Optionally, in some embodiments, the comparator in the ADC may include only the first comparator section. In other words, the output of the first comparator section may be used as the input of a subsequent circuit (eg, a counter).

[0086] Understandably, Figure 5 The differential amplifier 519 shown is only a schematic diagram of a differential amplifier, and the differential amplifier in the comparator may also be other common differential amplifiers.

[0087] Figures 6 to 15 The differential amplifier in can be Figure 5 The differential amplifier 519 shown is a common differential amplifier.

[0088] Figure 6 is a schematic structural block diagram of a comparator provided according to an embodiment of the present application. Figure 6 The illustrated comparator 600 includes a differential amplifier 610, a capacitor 621, and a capacitor 622. A crosstalk capacitor 631 exists between the output terminal and the non-inverting input terminal of the differential amplifier 610.

[0089] The comparator 600 corresponds to one or more columns of sensors in the sensor array. Figure 6 As shown, the input terminal 641 of the comparator 600 is used to obtain the electrical signal (ie, pixel signal) output by one or more columns of sensors corresponding to the comparator 600, and the input terminal 642 of the comparator 600 is used to obtain the ramp signal (reference level) from the reference level generator.

[0090] For example, Figure 6 The comparator 600 shown can be applied to Figure 4 and Figure 6 In the column parallel ADC shown in Figure 1, Figure 4 For example, the comparator 600 may be Figure 4 In this case, the input terminal 641 is coupled to the output terminal of the corresponding one or more columns of sensors to obtain the pixel signal from the one or more columns of sensors; the input terminal 642 is coupled to the reference level generator 410 to obtain the ramp signal from the reference level generator 410.

[0091] like Figure 6 As shown, one end of capacitor 621 is coupled to the output end of differential amplifier 610, and the other end of capacitor 621 is coupled to the inverting input end of differential amplifier 610. One end of capacitor 622 is coupled to the inverting input end of differential amplifier 610, and the other end of capacitor 622 is coupled to input end 641. The positive input end of differential amplifier 610 is coupled to input end 642.

[0092] The output terminal of the differential amplifier 610 can be coupled to the input terminal of the subsequent circuit. In some embodiments, the comparator 600 can include a first comparator section and a second comparator section. The first comparator section includes Figure 6 The differential amplifier 610, capacitor 621 and capacitor 622 are shown. The output end of the differential amplifier 610 is the output end of the first comparator unit. The subsequent circuit can be the second comparator unit. For example, in some embodiments, the second comparator unit can be as follows: Figure 5 In some other embodiments, the comparator 600 may include only one comparator section, which includes Figure 6 The differential amplifier 610, capacitor 621 and capacitor 622 are shown. In this case, the subsequent circuit is a counter coupled to the comparator 600. Similarly, Figures 7 to 15 The illustrated comparator may also include a first comparator section and a second comparator section, or may include only one comparator section. Figures 7 to 15 The specific implementation of the comparator shown includes two comparator parts or one comparator part. Figure 6The implementation of the comparator shown is similar and will not be described again for brevity.

[0093] Figure 7 is a schematic structural block diagram of another comparator provided according to an embodiment of the present application. Figure 7 The illustrated comparator 700 includes a differential amplifier 710, a capacitor 721, a capacitor 722, and a switch 751. A crosstalk capacitor 731 exists between the output terminal and the non-inverting input terminal of the differential amplifier 710. The comparator 700 also includes an input terminal 741 and an input terminal 742.

[0094] It can be seen that the comparator 700 has only one additional switch 751 compared to the comparator 600. In addition to the switch 751, the connection relationship and functions of the other components in the comparator 700 are the same as those in the comparator 600. Figure 6 The connection relationship and functions of the corresponding components in the illustrated comparator 600 are the same, and for the sake of brevity, they are not described again here.

[0095] like Figure 7 As shown, one end of the switch 751 is coupled to the inverting input terminal of the differential amplifier 710, and the other end of the switch 751 is coupled to the output terminal of the differential amplifier 710. Before the comparator 700 works as a comparator, the switch 751 is closed (i.e., in an ON state) to determine the operating point of the input terminal of the differential amplifier 710; when the comparator 700 works as a comparator (i.e., during analog (A) / digital (D) conversion), the switch 751 is opened (i.e., in an OFF state).

[0096] exist Figure 6 and Figure 7 In the embodiment shown, there is only one capacitor between the inverting input terminal and the output terminal of the differential amplifier. In other embodiments, a plurality of capacitors connected in parallel may be included between the inverting input terminal and the output terminal of the differential amplifier.

[0097] Figure 8 is a schematic diagram of another comparator provided according to an embodiment of the present application.

[0098] It can be seen that Figure 7 compared to, Figure 8 The comparator 800 shown in FIG. 8 uses five capacitors connected in parallel (i.e., capacitors 821-1 to 821-5) to replace the capacitors 821-1 to 821-5. Figure 7 In addition to capacitors 821-1 to 821-5, Figure 8 The connection relationship and function between other components in Figure 7 The connection relationship and functions of the corresponding components in the illustrated comparator 700 are the same, and are not described again for the sake of brevity.

[0099] Understandably, Figure 8 This is just a possible implementation provided by the embodiment of the present application. The number of capacitors connected in parallel between the inverting input terminal and the output terminal of the differential amplifier may also be other positive integers, for example, 2, 3, 4, 6, etc. In other words, one capacitor may be coupled between the inverting input terminal and the output terminal of the differential amplifier, or two or more capacitors connected in parallel may be coupled.

[0100] Fig. 9 is a schematic diagram of another comparator provided according to an embodiment of the present application. Fig. 9 The comparator 900 shown includes: a differential amplifier 910 , a capacitor 921 , a capacitor 922 , a switch 951 , an input terminal 941 , and an input terminal 942 . In addition, the comparator 900 also includes: a capacitor 961 and a switch 952 .

[0101] It can be seen that Fig. 9 The connection relationship and function between the differential amplifier 910, capacitor 921, capacitor 922, switch 951 and input terminal 941 are similar to Figure 7 The connection relationship and function of the differential amplifier 710, capacitor 721, capacitor 722, switch 751 and input terminal 741 in FIG. 7 are the same, and for the sake of brevity, they are not repeated here. Similarly, a crosstalk capacitor, namely capacitor 931, is also included between the output terminal and the positive input terminal of the differential amplifier 910.

[0102] like Fig. 9 As shown, one end of the capacitor 961 is coupled to the positive input terminal of the differential amplifier 910 , and the other end of the capacitor 961 is coupled to the input terminal 942 .

[0103] Capacitor 961 is a matching capacitor of capacitor 922. In other words, the capacitance value of capacitor 961 is the same as the capacitance value of capacitor 922.

[0104] One end of the switch 952 is coupled to the positive input terminal of the differential amplifier 910, and the other end of the switch 952 is coupled to the node 971. The voltage at the node 971 is the reference voltage. Figure 5 The differential amplifier 519 shown, then the reference voltage is the power supply voltage V DD The difference in forward voltage of a P-type metal-oxide-semiconductor (PMOS) connected to a diode. The diode-connected PMOS is Figure 5 The forward voltage of PMOS 531 can be equal to the source-gate voltage V of PMOS 531. GS In other words, the reference voltage is equal to V DD -V GSIf PMOS 531 and PMOS 532 match, then the drain voltage of PMOS 531 is equal to V DD -V GS In other words, if the differential amplifier 910 is Figure 5 For the differential amplifier 519 shown, the node 971 is the drain of the PMOS 531 .

[0105] Before the comparator 900 works as a comparator, the switch 952 is closed (i.e., in the ON state) to determine the operating point of the input terminal of the differential amplifier 910; when the comparator 900 works as a comparator (i.e., during analog (A) / digital (D) conversion), the switch 952 is opened (i.e., in the OFF state).

[0106] exist Fig. 9 In the illustrated comparator 900, only one capacitor is connected in parallel with the capacitor 962. In other embodiments, multiple capacitors may be connected in parallel with the capacitor 962. Fig. 9 In the illustrated comparator 900, only one capacitor 921 is located between the output terminal and the reverse input terminal of the differential amplifier 910. In other embodiments, one or more capacitors may be connected in parallel with the capacitor 921. In other words, the capacitor 921 may be replaced by a plurality of capacitors connected in parallel. As described above, in the case where only one capacitor 961 is connected in parallel with the capacitor 962 and only one capacitor 921 is located between the output terminal and the reverse input terminal of the differential amplifier 910, the capacitance value of the capacitor 961 is the same as the capacitance value of the capacitor 921. If it is assumed that the capacitor 921 is replaced with X capacitors and the capacitor 961 is replaced with Y capacitors, then in some embodiments, the parallel capacitance value of the X capacitors is the same as the parallel capacitance value of the Y capacitors, where X and Y are positive integers greater than or equal to 1.

[0107] It can be seen that Figures 6 to 9 In the comparator shown in FIG. 1 , one end of a capacitor may be coupled to an input end of the comparator and the other end may be coupled to the inverting input end of the differential amplifier in the comparator. For ease of description, the capacitor may be referred to as a first capacitor, and the input end of the comparator coupled with the capacitor may be referred to as a first input end of the comparator. Figures 6 to 9In the comparator shown, one end of one or more capacitors may be coupled to the inverting input terminal of the differential amplifier in the comparator and the other end may be coupled to the output terminal of the differential amplifier. For ease of description, such capacitors may be referred to as second capacitors. In other words, the comparator may include N second capacitors, where N may be equal to 1 or a positive integer greater than or equal to 2. One port of each of the N second capacitors is coupled to the inverting input terminal of the differential amplifier of the comparator, and the other port is coupled to the output terminal of the differential amplifier of the comparator. For ease of description, C INN Indicates the capacitance value of the first capacitor, for C FBN represents the equivalent capacitance value of the N second capacitors. In other words, if N is equal to 1, then C FBN This is the capacitance value of the second capacitor. If N is greater than or equal to 2, then C FBN It is the capacitance value of the at least two second capacitors connected in parallel.

[0108] Figures 6 to 9 The gain of the comparator, C INN and C FBN The following relationship can be satisfied:

[0109] A0=-(C INN / C FBN )×{1+(1+C INN / C FBN ) / A}-1, (Equation 1)

[0110] Where A0 represents the gain of the comparator, and A represents the gain of the differential amplifier in the comparator. When the gain of the differential amplifier is much greater than C INN / C FBN (For example, the comparator gain is C INN / C FBN K times, where K can be a preset value, such as 20, 30 or 80, etc.), 1+(1+C INN / C FBN ) / A is approximately equal to 1. In this case, the comparator gain A0 is only affected by C INN and C FBN In this way, by setting C INN and C FBN To adjust the gain of the comparator.

[0111] The peak value of the kickback signal output from the comparator is determined by the gain and reference level of the comparator. The kickback signal is output from the reference level input node of the comparator (e.g. Figure 5The gain and reference level of the comparator can determine the fall time of the output signal of the differential amplifier of the comparator. In some embodiments, the gain, reference level and fall time of the comparator satisfy the following relationship:

[0112] T∝1 / {A0×(dV RAMP / dt)}, (Equation 2),

[0113] Where T represents the fall time of the output signal of the differential amplifier of the comparator, A0 represents the gain of the comparator, V RAMP represents the voltage value of the reference level, t represents time, and d is the differential sign.

[0114] As long as the same step amplitude is applied to the output of the comparator, the peak value of the kickback signal is proportional to the inverse of the fall time of the output signal of the differential amplifier of the comparator. In other words, the greater the fall time of the output signal of the first comparator part of the comparator, the smaller the peak value of the kickback signal. The smaller the peak value of the kickback signal, the smaller the impact on the image quality. Combining the above equations 1 and 2, it can be seen that the gain A0 of the comparator can be calculated by C INN and C FBN The gain A0 of the comparator determines the fall time of the output signal of the differential amplifier of the comparator. Therefore, selecting the appropriate first capacitor and second capacitor can increase the fall time of the output signal of the differential amplifier, thereby reducing the peak value of the kickback signal. In this way, the impact of the kickback signal can be reduced, thereby improving the image quality.

[0115] For ease of description, the two ports of the second capacitor may be referred to as the first port of the second capacitor and the second port of the second capacitor, respectively. Figures 6 to 9 In the comparator shown, the first port of the second capacitor is used to couple with the inverting input terminal of the differential amplifier in the comparator, and the second port of the second capacitor is used to couple with the output terminal of the differential amplifier.

[0116] In some embodiments, the comparator may further include a switch circuit, which is used to control the second port of the second capacitor to couple with the output end of the differential amplifier, or to control the second port of the second capacitor to couple with the first input end of the comparator. The first input end of the comparator is an input end for obtaining an electrical signal from a sensor, that is, Figures 6 to 9 Input terminal 641, input terminal 741, input terminal 841 and input terminal 941.

[0117] Fig.10 is a schematic diagram of another comparator provided according to an embodiment of the present application. Fig.10The comparator 1000 in the embodiment includes a differential amplifier 1010, a capacitor 1021, a capacitor 1022, an input terminal 1041, an input terminal 1042, and a switch 1051. Similarly, a crosstalk capacitor 1031 is further included between the output terminal and the positive input terminal of the differential amplifier 1010. Fig.10 The illustrated comparator 1000 further includes a switch circuit, which includes a switch 1023. The capacitor 1021 is the first capacitor mentioned above, and the capacitor 1022 is the second capacitor mentioned above.

[0118] like Fig.10 As shown, one port of the capacitor 1021 is coupled to the inverting input terminal of the differential amplifier 1010, and the other port of the capacitor 1021 is coupled to the switch 1023. For ease of description, the port of the capacitor 1021 coupled to the inverting input terminal of the differential amplifier 1010 may be referred to as the first port of the capacitor 1021, and the port of the capacitor 1021 coupled to the switch 1023 may be referred to as the second port of the capacitor 1021.

[0119] like Fig.10 The switch 1023 shown includes two contacts, contact 1 and contact 2. Contact 1 is coupled to the output of the differential amplifier 1010, and contact 2 is coupled to the input 1041 of the comparator 1000. The switch 1023 also includes two moving terminals, moving terminal a and moving terminal b. When the moving terminal a and contact 1 are closed, and the moving terminal b and contact 2 are disconnected, the second port of the capacitor 1021 is coupled to the output of the differential amplifier 1010; when the moving terminal b and contact 2 are closed, and the moving terminal a and contact 2 are disconnected, the second port of the capacitor 1021 is coupled to the input 1041.

[0120] For the sake of convenience of description, the state in which the moving terminal a and contact 1 are closed and the moving terminal b and contact 2 are disconnected can be called the first state of the comparator, and the state in which the moving terminal b and contact 2 are closed and the moving terminal a and contact 2 are disconnected can be called the second state of the comparator.

[0121] CIS can have two different operating modes, low gain operation and high resolution operation. Low gain operation means that the CIS uses a lower gain setting to capture images. For example, Figure 3In the ramp signal shown, when the gain is less than 12dB, it can be considered as low gain operation. Take the ramp signal with a gain of 0dB as an example. Compared with the ramp signal with a gain of 12dB, the ramp signal with a gain of 0dB has a larger fluctuation range and a larger slope. The slope of the ramp signal affects the brightness level (also known as 1-digital number (1-DN)). The larger the slope of the ramp signal, the larger the change amplitude of the ramp signal corresponding to the value of each brightness level, making the brightness level difference more obvious. When the CIS works in the low gain operation mode, the slope and fluctuation range of the ramp signal are relatively large, which will cause the fluctuation range of the comparator output signal to be larger, thereby generating a larger kickback signal. Therefore, the kickback signal of the low gain operation mode has a greater impact on the image quality. When the gain is greater than or equal to 12dB, it can be considered as a high-resolution operation. It can be seen that as the gain increases, the fluctuation range and slope of the ramp signal become smaller. The smaller the slope of the ramp signal, the smaller the variation of the ramp signal corresponding to the value of each brightness level, so that the brightness level difference is more subtle. Therefore, high-resolution operation can provide more details and more accurate image information. High-resolution operation is easily affected by noise. As mentioned above, a larger slope and fluctuation range of the ramp signal will cause a larger fluctuation range of the comparator output signal, which will produce a larger kickback signal. Correspondingly, a smaller slope and fluctuation range will cause a smaller fluctuation range of the comparator output signal, thereby generating a smaller kickback signal. Therefore, relative to the low-gain operation mode, the impact of the kickback signal on the high-resolution operation is relatively small. Therefore, when the CIS operates in the low-gain operation mode, the comparator can operate in the first state; when the CIS operates in the high-resolution operation, the comparator can operate in the second state.

[0122] The connection relationship and functions among the differential amplifier 1010, the capacitor 1021, the input terminal 1041, the input terminal 1042 and the switch 1051 are the same as those of the corresponding devices in the above embodiments, and are not described again for the sake of brevity.

[0123] The number of the second capacitor and the corresponding switch included in the comparator obtained according to the technical solution disclosed in the present application can also be other values. In other words, the comparator obtained according to the technical solution disclosed in the present application can include N second capacitors and N switches, where N is a positive integer greater than or equal to 1. The N second capacitors correspond to the N switches one by one, and each of the N switches is used to control the second port of the corresponding second capacitor to couple with the output end of the differential amplifier or with the input end of the comparator.

[0124] Fig.11 is a schematic diagram of another comparator provided according to an embodiment of the present application. Fig.11The comparator 1100 in the embodiment includes three second capacitors and three switches. The three second capacitors are capacitor 1121-1, capacitor 1121-2 and capacitor 1121-3; the three switches are switch 1123-1, switch 1123-2 and switch 1123-3.

[0125] Capacitor 1121 - 1 corresponds to switch 1123 - 1 , active end a and active end b of switch 1123 - 1 are coupled to the second port of switch 1121 - 1 , contact 1 of switch 1123 - 1 is coupled to the output end of differential amplifier 1110 , and contact 2 of switch 1123 - 1 is coupled to input end 1141 .

[0126] Capacitor 1121 - 2 corresponds to switch 1123 - 2 , active end a and active end b of switch 1123 - 2 are coupled to the second port of switch 1121 - 2 , contact 1 of switch 1123 - 2 is coupled to the output end of differential amplifier 1110 , and contact 2 of switch 1123 - 2 is coupled to input end 1141 .

[0127] Capacitor 1121 - 3 corresponds to switch 1123 - 3 , active end a and active end b of switch 1123 - 3 are coupled to the second port of switch 1121 - 3 , contact 1 of switch 1123 - 3 is coupled to the output end of differential amplifier 1110 , and contact 2 of switch 1123 - 3 is coupled to input end 1141 .

[0128] When the moving terminal a and contact 1 of the switch 1123-1, the switch 1123-2 and the switch 1123-3 are closed, and the moving terminal b and contact 2 are opened, the comparator 1100 operates in the first state; when the moving terminal b and contact 2 of the switch 1123-1, the switch 1123-2 and the switch 1123-3 are closed, and the moving terminal a and contact 1 are opened, the comparator 1100 operates in the second state. In other words, if the CIS including the comparator 1100 operates in the low gain operation mode, the moving terminal a and contact 1 of the switch 1123-1, the switch 1123-2 and the switch 1123-3 are closed, and the moving terminal b and contact 2 are opened; if the CIS including the comparator 1100 operates in the high resolution operation mode, the moving terminal b and contact 2 of the switch 1123-1, the switch 1123-2 and the switch 1123-3 are closed, and the moving terminal a and contact 1 are opened.

[0129] Fig.11 The comparator 1100 includes a differential amplifier 1110, a capacitor 1122, an input terminal 1141, and the connection mode and function between the input terminal 1142 and the switch 1151 are similar to the connection mode and function of the corresponding devices mentioned above, and for the sake of brevity, they are not repeated here. Similarly, a crosstalk capacitor 1131 is also included between the output terminal and the positive input terminal of the differential amplifier 1110. The capacitor 1122 is the first capacitor mentioned above.

[0130] Fig.12 is a schematic diagram of another comparator provided according to an embodiment of the present application. Fig.12 The comparator 1200 shown includes a differential amplifier 1210, a capacitor 1221, a capacitor 1222, a switch 1223, a capacitor 1224, a capacitor 1225, an input terminal 1241, an input terminal 1242, a switch 1251, and a switch 1252. Similarly, the capacitor 1231 is a crosstalk capacitor between the output terminal and the positive input terminal of the differential amplifier 1210.

[0131] like Fig.12 The connection mode and function of the differential amplifier 1210, the capacitor 1221, the capacitor 1222, the switch 1223, and the switch 1251 in the comparator 1200 shown in FIG. Fig.10 The connection method and function of the differential amplifier 1010, capacitor 1021, capacitor 1022, switch 1023, and switch 1051 in the comparator 1000 are the same, and for the sake of brevity, they are not repeated here.

[0132] It can be seen that Fig.10 The comparator 1000 is compared to Fig.12 The illustrated comparator 1200 has capacitor 1224 , capacitor 1225 , and switch 1252 added.

[0133] Capacitor 1224 is a matching capacitor of capacitor 1222. In other words, the capacitance value of capacitor 1224 is the same as the capacitance value of capacitor 1222.

[0134] Capacitor 1225 is a matching capacitor of capacitor 1221. In other words, the capacitance value of capacitor 1225 is the same as the capacitance value of capacitor 1221.

[0135] One end of the switch 1252 is coupled to the positive input terminal of the differential amplifier 1210, and the other end of the switch 1252 is coupled to the node 1261. The voltage at the node 1261 is the reference voltage. Figure 5 The reference voltage is the difference between the power supply voltage VDD and the forward voltage of a diode-connected P-type metal-oxide-semiconductor (PMOS). Figure 5 The PMOS 531 shown in FIG. 1 can have a forward voltage equal to the source-gate voltage VGS of the PMOS 531. In other words, the reference voltage is equal to VDD-VGS. If the PMOS 531 and the PMOS 532 are matched, then the drain voltage of the PMOS 531 is equal to VDD-VGS. In other words, if the differential amplifier 1210 is as Figure 5For the differential amplifier 519 shown, the node 1261 is the drain of the PMOS 531 .

[0136] Before the comparator 1200 works as a comparator, the switch 1252 is closed (i.e., in the ON state) to determine the operating point of the input terminal of the differential amplifier 1210; when the comparator 1200 works as a comparator (i.e., during analog (A) / digital (D) conversion), the switch 1252 is opened (i.e., in the OFF state).

[0137] Fig.13 is a structural diagram of another comparator provided according to an embodiment of the present application. Fig.13 The comparator 1300 shown includes a differential amplifier 1310, a capacitor 1321-1, a capacitor 1321-2, a capacitor 1321-3, a capacitor 1322, a capacitor 1324, a capacitor 1325-1, a capacitor 1325-2, a capacitor 1325-3, a switch 1323-1, a switch 1323-2, a switch 1323-3, a switch 1351, a switch 1352, an input terminal 1341, and an input terminal 1342. Similarly, a crosstalk capacitor 1331 is included between the output terminal and the positive input terminal of the differential amplifier 1310.

[0138] Capacitor 1322 is the first capacitor mentioned above. Capacitor 1321-1, capacitor 1321-2 and capacitor 1321-3 are the second capacitors mentioned above. Switch 1325-1 is a switch corresponding to capacitor 1321-1, used to control the second port of capacitor 1321-1 to couple with the output end of differential amplifier 1310 or with input end 1341; switch 1325-2 is a switch corresponding to capacitor 1321-2, used to control the second port of capacitor 1321-2 to couple with the output end of differential amplifier 1310 or with input end 1341; switch 1325-3 is a switch corresponding to capacitor 1321-3, which can be used to control the second port of capacitor 1321-3 to couple with the output end of differential amplifier 1310 or with input end 1341. The specific working methods of switches 1321-1, 1321-2 and 1321-3 are as follows. Fig.11 The switches 1123 - 1 , 1123 - 2 and 1123 - 3 in the illustrated comparator 1100 operate in the same manner, and are not described again for brevity.

[0139] and Fig.11 The comparator 1100 shown compares Fig.13The illustrated comparator 1300 adds a matching capacitor of capacitor 1322 (ie, capacitor 1324), a matching capacitor of capacitor 1321-1 (ie, capacitor 1325-1), a matching capacitor of capacitor 1321-2 (ie, capacitor 1325-2), and a matching capacitor of capacitor 1321-3 (ie, 1325-3).

[0140] For ease of description, the capacitance (eg, Fig.12 The capacitor 1224 and Fig.13 The capacitor 1324 in FIG. 1 is called the third capacitor, and the capacitor connected in parallel with the third capacitor (eg Fig.12 The capacitor 1225, Fig.13 The capacitor 1325-1, the capacitor 1325-2 and the capacitor 1325-3) are called the fourth capacitor.

[0141] Fig.12 and Fig.13 The comparators shown are just two embodiments including the third capacitor and the fourth capacitor. According to the content disclosed in this application, those skilled in the art can also obtain other comparators including the third capacitor and the fourth capacitor.

[0142] In some embodiments, the number of second capacitors and the number of fourth capacitors in the comparator may be the same. In other words, the comparator may include N second capacitors and N fourth capacitors, the N second capacitors correspond one-to-one to the N fourth capacitors, and N is a positive integer greater than or equal to 1. Each of the N fourth capacitors is a matching capacitor of the corresponding second capacitor, and the capacitance value of each fourth capacitor is the same as the capacitance value of the corresponding second capacitor. For example, Fig.12 The comparator 1200 shown includes a second capacitor (ie, capacitor 1221) and a fourth capacitor (ie, capacitor 1225), and the capacitance value of the capacitor 1221 is the same as the capacitance value of the capacitor 1225. For example, Fig.13 The comparator 1300 shown includes three second capacitors (i.e., capacitors 1321-1 to 1321-3) and three fourth capacitors (i.e., capacitors 1325-1 to 1325-3), wherein capacitor 1321-1 corresponds to capacitor 1325-1, and the capacitance value of capacitor 1321-1 is the same as the capacitance value of capacitor 1325-1; capacitor 1321-2 corresponds to capacitor 1325-2, and the capacitance value of capacitor 1321-2 is the same as the capacitance value of capacitor 1325-2; capacitor 1321-3 corresponds to capacitor 1325-3, and the capacitance value of capacitor 1321-3 is the same as the capacitance value of capacitor 1325-3.

[0143] In other embodiments, the number of second capacitors and the number of fourth capacitors in the comparator may be different. In other words, the comparator may include N1 second capacitors and N2 fourth capacitors, where N1 and N2 are both positive integers greater than or equal to 1 and N1 is not equal to N2. In this case, the capacitance value of the equivalent capacitance after the N1 second capacitors are connected in parallel is the same as the capacitance value of the equivalent capacitance after the N2 fourth capacitors are connected in parallel.

[0144] In some other embodiments, the number of second capacitors and fourth capacitors in the comparator is the same, but the capacitance value of each second capacitor and the capacitance value of the fourth capacitor corresponding to the second capacitor may be different, but the capacitance value of the equivalent capacitor after all the second capacitors are connected in parallel is the same as the capacitance value of the equivalent capacitor after all the fourth capacitors are connected in parallel. Fig.13 In the comparator 1300 shown, the capacitance value of capacitor 1231-1 is different from the capacitance value of capacitor 1325-1, the capacitance value of capacitor 1321-2 is different from the capacitance value of capacitor 1325-2, and the capacitance value of capacitor 1321-3 is different from the capacitance value of capacitor 1325-3. Assume that the capacitance value of the equivalent capacitance after capacitors 1321-1, 1321-2 and 1321-3 are connected in parallel is C FBN1 The equivalent capacitance of capacitors 1325-1, 1325-2 and 1325-3 connected in parallel is C FBN2 , then C FBN1 Equal to C FBN2 .

[0145] To summarize, in some embodiments, the comparator may include N second capacitors and M fourth capacitors, where N is a positive integer greater than or equal to 1, and M is a positive integer greater than or equal to 1. The values ​​of N and M may be equal or unequal.

[0146] Figures 9 to 13 The switch circuit for controlling the coupling object of the second port of the second capacitor in the shown comparator is implemented by a switch including two moving ends and two contacts. Those skilled in the art will appreciate that the switch circuit may also be implemented by other types of switches. For example, the switch circuit may be implemented by a switch including a moving end and two contacts. For another example, the switch circuit may be implemented by a plurality of switches.

[0147] Fig.14 is a schematic diagram of a comparator provided according to an embodiment of the present application. Fig.14 The comparator 1400 shown includes a differential amplifier 1410 , a capacitor 1421 , a capacitor 1422 , a capacitor 1424 , a capacitor 1425 , a switch 1451 , a switch 1452 , an input terminal 1441 , and an input terminal 1442 . Fig.14The connection relationship and functions between the differential amplifier 1410, the capacitor 1421, the capacitor 1422, the capacitor 1424, the capacitor 1425, the switch 1451, the switch 1452, the input terminal 1441 and the input terminal 1442 in the comparator 1400 shown in FIG. Fig.12 The connection relationship and function between the differential amplifier 1210, capacitor 1221, capacitor 1222, capacitor 1224, capacitor 1225, switch 1251, switch 1252, input terminal 1241 and input terminal 1242 in the comparator 1200 shown are the same. For the sake of brevity, they are not described here. Capacitor 1431 is a crosstalk capacitor, and capacitor 1432 is a parasitic capacitor.

[0148] Fig.12 The switch circuit in the comparator 1200 shown includes only one switch 1223. The switch 1223 is used to control the second port of the capacitor 1221 to be coupled to the input terminal 1241 or the output terminal of the differential amplifier 1210. Fig.14 The switch circuit in the illustrated comparator 1400 includes two switches, namely switch 1423 - 1 and switch 1423 - 2 . Switch 1423 - 1 and switch 1423 - 2 jointly control the coupling of the second port of the capacitor 1421 with the input terminal 1441 or the output terminal of the differential amplifier 1410 .

[0149] like Fig.14 As shown, both the switch 1431-1 and the switch 1431-2 include a moving terminal a, a moving terminal b, a contact 1, and a contact 2. When the moving terminal a and the contact 1 of the switch 1431-1 are closed, the moving terminal b and the contact 2 of the switch 1431-1 are disconnected, the moving terminal a and the contact 1 of the switch 1431-2 are closed, and the moving terminal b and the contact 2 of the switch 1431-2 are disconnected, the second port of the capacitor 1421 is coupled to the output terminal of the differential amplifier 1410 (i.e., the comparator 1400 is in the first state). When the moving terminal b and the contact 2 of the switch 1431-1 are closed, the moving terminal a and the contact 1 of the switch 1431-1 are disconnected, the moving terminal b and the contact 2 of the switch 1431-2 are closed, and the moving terminal a and the contact 1 of the switch 1431-2 are disconnected, the second port of the capacitor 1421 is coupled to the input terminal 1441 (i.e., the comparator 1400 is in the second state).

[0150] like Fig.14 The switching circuit shown can also be applied to Figures 10 to 13 In any of the comparators in . For example, Fig.15 is a schematic diagram of another comparator provided according to an embodiment of the present application. Fig.15 The comparator 1500 shown is in Fig.13A switch 1523-4 is added to the comparator shown. The switch 1523-4 cooperates with the switches 1523-1 to 1523-3 to control the coupling object of the second port of the second capacitor (i.e., the capacitor 1521-1 to the capacitor 1521-3). When the moving end b and the contact 2 of each switch in the switches 1521-1 to 1521-4 are disconnected and the moving end a and the contact 1 are closed, the second ports of the capacitors 1521-1 to 1521-3 are coupled to the output end of the differential amplifier 1510. In this case, the state of the comparator 1500 is the first state. When the moving end b and the contact 2 of each switch in the switches 1521-1 to 1521-4 are closed and the moving end a and the contact 1 are disconnected, the second ports of the capacitors 1521-1 to 1521-3 are coupled to the input end 1541. In this case, the state of the comparator 1500 is the second state.

[0151] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0152] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0153] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0154] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0155] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0156] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0157] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A comparator, characterized in that: The comparator comprises: a differential amplifier, a first capacitor and N second capacitors, where N is a positive integer greater than or equal to 1; The first input terminal of the comparator is used to obtain the electrical signal output from one or more columns of sensors in the sensor array; The second input terminal of the comparator is used to obtain the reference level generated by the reference level generator; The first port of the first capacitor is coupled to the inverting input terminal of the differential amplifier, and the second port of the first capacitor is coupled to the first input terminal of the comparator; A first port of the i-th second capacitor among the N second capacitors is coupled to the inverting input terminal of the differential amplifier, and a second port of the i-th second capacitor is coupled to the output terminal of the differential amplifier, i=1, ..., N.

2. The comparator according to claim 1, characterized in that: The comparator further includes a third capacitor and M fourth capacitors, where M is a positive integer greater than or equal to 1, wherein: The first port of the third capacitor is coupled to the positive input terminal of the differential amplifier, and the second port of the third capacitor is coupled to the second input terminal of the comparator; The j-th fourth capacitor among the M fourth capacitors is connected in parallel with the third capacitor, where j=1, ..., M.

3. The comparator according to claim 2, characterized in that The first capacitor matches the third capacitor, and the N second capacitors match the M fourth capacitors.

4. The comparator according to any one of claims 1 to 3, characterized in that: The comparator further includes a switch circuit, and the switch circuit is used to control the second ports of the N second capacitors to be coupled with the output end of the differential amplifier or the first input end of the comparator.

5. The comparator according to claim 4, characterized in that: The switch circuit includes N first switches, wherein a moving end of an i-th first switch among the N first switches is coupled to a second port of the i-th second capacitor, The first contact of the i-th first switch is coupled to the first input terminal of the comparator, The second contact of the i-th first switch is coupled to the output terminal of the differential amplifier.

6. The comparator according to claim 4, characterized in that: The switch circuit includes a second switch and N third switches, The moving end of the i-th third switch among the N third switches is coupled to the second port of the i-th second capacitor, The first contact of the i-th third switch is coupled to the first input terminal of the comparator, The second contact of the i-th third switch is coupled to the moving end of the second switch, The first contact of the second switch is coupled to the output terminal of the differential amplifier. A second contact point of the second switch is grounded.

7. The comparator according to any one of claims 1 to 6, characterized in that: The gain of the comparator satisfies the following formula: A0=-(C INN / C FBN ), Where A0 is the gain of the comparator, C INN is the capacitance value of the first capacitor, C FBN is the equivalent capacitance value of the N second capacitors.

8. An analog-to-digital converter ADC, characterized in that: The ADC comprises: a reference level generator and at least one comparator as claimed in any one of claims 1 to 7, The output terminal of the reference level generator is coupled to the second input terminal of each comparator of the at least one comparator, and the first input terminal of each comparator is used to be coupled to the output port of the sensor.

9. The ADC according to claim 8, characterized in that The ADC further comprises: at least one counter and at least one latch, The at least one counter corresponds to the at least one comparator one by one, and an output terminal of each comparator in the at least one comparator is coupled to an input terminal of a corresponding counter. The at least one counter corresponds to the at least one latch in a one-to-one manner, and an output terminal of each counter in the at least one counter is coupled to an input terminal of a corresponding latch.

10. An image sensor, characterized in that: include: A sensor array, an ADC as claimed in claim 8 or 9, wherein each comparator in the ADC corresponds to one or more columns of sensors in the sensor array, and a first input terminal of each comparator is coupled to an output port of the corresponding one or more columns of sensors.

11. An electronic device, characterized in that: The electronic device comprises the image sensor as claimed in claim 9.

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