Method of manufacturing a semiconductor structure, semiconductor structure and device

Abstract

This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and a device. The method includes: forming an active structure on a substrate; sequentially forming a stacked first front-side transistor, a second front-side transistor, and a front-side back-end transistor based on the front-side active structure; connecting a first front-side source / drain metal in the first front-side transistor, a second front-side source / drain metal in the second front-side transistor, and a third front-side source / drain metal in the front-side back-end transistor; performing back-end processing on the front-side back-end transistor to form a front-side metal interconnect layer; flipping and thinning the substrate; sequentially forming a stacked first back-side transistor, a second back-side transistor, and a back-side back-end transistor based on the back-side active structure; connecting a first back-side source / drain metal in the first back-side transistor, a second back-side source / drain metal in the second back-side transistor, and a third back-side source / drain metal in the back-side back-end transistor; and performing back-end processing on the back-side back-end transistor to form a back-side metal interconnect layer.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a method for preparing a semiconductor structure, a semiconductor structure, and a device. Background Technology

[0002] A basic SRAM cell typically consists of six transistors, a structure known as 6T SRAM. These transistors include two P-channel (PMOS) and four N-channel (NMOS) transistors. Each SRAM cell usually requires more transistors to maintain the stored data state. This results in a relatively low storage density for SRAM, thus requiring a larger area and consequently a larger design layout. Summary of the Invention

[0003] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, a device, and an apparatus to reduce the layout area of ​​the semiconductor structure.

[0004] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, wherein the semiconductor structure is a static random access memory cell. The method includes: forming an active structure on a substrate; the active structure includes a front active structure, a sacrificial structure, and a back active structure sequentially stacked in a first direction; based on the front active structure, sequentially forming a first front transistor, a second front transistor, and a front back transistor along the first direction; connecting a first front source / drain metal in the first front transistor, a second front source / drain metal in the second front transistor, and a third front source / drain metal in the front back transistor; performing back-end processing on the front back transistor to form a front metal interconnect layer; flipping and thinning the substrate until the back active structure is exposed; and sequentially forming a first back transistor, a second back transistor, and a back back transistor along the first direction based on the back active structure. The method includes: a body transistor; a first back-side source / drain metal in a first back-side transistor, a second back-side source / drain metal in a second back-side transistor, and a third back-side source / drain metal in a back-side back-end transistor connected together; performing back-end processing on the back-side back-end transistor to form a back-side metal interconnect layer; the method further includes: removing a sacrificial structure to form a first gap, and filling the first gap with insulating material to form an intermediate isolation dielectric layer; the intermediate isolation dielectric layer is used to isolate the front active structure and the back active structure; symmetrically distributed first signal lines and second signal lines are embedded on both sides of the intermediate isolation dielectric layer; the extension directions of the first signal lines and the second signal lines are consistent with the extension direction of the intermediate isolation dielectric layer; wherein the first signal lines are respectively connected to the first front gate structure and the first back-side source / drain metal in the first front transistor, and the second signal lines are respectively connected to the first back gate structure and the first front source / drain metal in the first back-side transistor.

[0005] In some possible implementations, a first front-side transistor, a second front-side transistor, and a front-side back-end transistor constitute a front-side semiconductor structure. Based on the front-side active structure, the first front-side transistor, the second front-side transistor, and the front-side back-end transistor are sequentially stacked along a first direction, including: performing source-drain epitaxial growth in the front-side source-drain region of the front-side semiconductor structure to form a first front-side source-drain structure of the first front-side transistor; forming a first front-side source-drain metal and a first front-side insulating isolation layer on the first front-side source-drain structure; the first front-side insulating isolation layer is used to isolate the first front-side transistor and the second front-side transistor in the front-side source-drain region; and the first front-side insulating isolation layer is used to isolate the first front-side transistor and the second front-side transistor in the front-side source-drain region. Epitaxial growth of source and drain is performed on the layer to form the second front-side source and drain structure of the second front-side transistor; metal material is deposited in the front-side gate region of the front-side semiconductor structure to form the first front-side gate structure; metal material is deposited in the front-side gate region and on the first front-side gate structure to form the second front-side gate structure of the second front-side transistor; the second front-side source and drain metal of the second front-side transistor and the second front-side insulating isolation layer are formed on the second front-side source and drain structure; the second front-side insulating isolation layer is used to isolate the second front-side transistor and the front-side back-end transistor; the front-side back-end transistor is formed on the second front-side insulating isolation layer; back-end processing is performed on the front-side back-end transistor to form the front-side metal interconnect layer.

[0006] In some possible implementations, forming a front-side back-end transistor on the second front-side insulating isolation layer includes: depositing an insulating material on the second front-side insulating isolation layer to form a front-side channel dielectric layer; forming a third front-side source / drain structure and a third front-side gate structure on the front-side channel dielectric layer; forming a third source / drain metal and a front-side gate lead-out structure on the third front-side source / drain structure and the third front-side gate structure, respectively; and using the front-side gate lead-out structure to connect the third front-side gate structure and the front-side metal interconnect layer.

[0007] In some possible implementations, a first back-side transistor, a second back-side transistor, and a back-side back-channel transistor constitute a back-side semiconductor structure; based on the back-side active structure, the first back-side transistor, the second back-side transistor, and the back-side back-channel transistor are sequentially stacked along a first direction, including: performing source-drain epitaxial growth in the back-side source-drain region of the back-side semiconductor structure to form a first back-side source-drain structure of the first back-side transistor; forming a first back-side source-drain metal and a first back-side insulating isolation layer on the first back-side source-drain structure; the first back-side insulating isolation layer is used to isolate the first back-side transistor and the second back-side transistor in the back-side source-drain region; the first back-side insulating isolation layer is used to isolate the first back-side transistor and the second back-side transistor in the back-side source-drain region. Epitaxial growth of source and drain is performed on the layer to form the second back-side source and drain structure of the second back-side transistor; metal material is deposited in the back-side gate region of the back-side semiconductor structure to form the first back-side gate structure; metal material is deposited in the back-side gate region and on the first back-side gate structure to form the second back-side gate structure of the second back-side transistor; the second back-side source and drain metal of the second back-side transistor and the second back-side insulating isolation layer are formed on the second back-side source and drain structure; the second back-side insulating isolation layer is used to isolate the second back-side transistor and the back-side back-end transistor; the back-side back-end transistor is formed on the second back-side insulating isolation layer; back-end processing is performed on the back-side back-end transistor to form the back-side metal interconnect layer.

[0008] In some possible implementations, forming a back-side back-channel transistor on a second back-side insulating isolation layer includes: depositing an insulating material on the second back-side insulating isolation layer to form a back-side channel dielectric layer; forming a third back-side source / drain structure and a third back-side gate structure on the back-side channel dielectric layer; forming a third back-side source / drain metal and a back-side gate lead-out structure on the third back-side source / drain structure and the third back-side gate structure, respectively; and using the back-side gate lead-out structure to connect the third back-side gate structure and the back-side metal interconnect layer.

[0009] In some possible implementations, the first front-facing transistor is a first-type transistor; the second front-facing transistor is a second-type transistor; the first back-facing transistor is a first-type transistor; and the second back-facing transistor is a second-type transistor; wherein the first-type transistor and the second-type transistor are complementary transistors.

[0010] In some possible implementations, the first front transistor, the second front transistor, the first back transistor, and the second back transistor are any of the following: fin field-effect transistors and gate-all-around field-effect transistors.

[0011] In some possible implementations, the front-side back-end transistor and the back-side back-end transistor are any of the following: oxide thin-film transistors, planar field-effect transistors, fin field-effect transistors, and gate-all-around field-effect transistors.

[0012] In a second aspect, embodiments of this application provide a semiconductor structure, which is prepared by the method described in the first aspect. The semiconductor structure is a static random access memory (SRAM) cell, and the semiconductor structure includes: a front semiconductor structure; the front semiconductor structure includes a first front transistor, a second front transistor, and a front back-end transistor stacked in a first direction; a first front source / drain metal in the first front transistor, a second front source / drain metal in the second front transistor, and a third front source / drain metal in the front back-end transistor are connected; a back semiconductor structure; the front semiconductor structure and the back semiconductor structure are stacked in a first direction; the back semiconductor structure includes a first back transistor, a second back transistor, and a back back-end transistor stacked in the first direction; the first... The first back-side source / drain metal in the back-side transistor, the second back-side source / drain metal in the second back-side transistor, and the third back-side source / drain metal in the back-side back-end transistor are connected; wherein, an intermediate isolation dielectric layer is disposed between the front-side active structure of the front semiconductor structure and the back-side active structure of the back semiconductor structure; the intermediate isolation dielectric layer is used to isolate the front-side active structure and the back-side active structure; a first signal line and a second signal line are symmetrically distributed on both sides of the intermediate isolation dielectric layer; the extension direction of the first signal line and the second signal line is consistent with the extension direction of the intermediate isolation dielectric layer; the first signal line is connected to the first front-side gate structure and the first back-side source / drain metal in the first front-side transistor, and the second signal line is connected to the first back-side gate structure and the first front-side source / drain metal in the first back-side transistor.

[0013] Thirdly, embodiments of this application provide a semiconductor device, which includes a semiconductor structure as described in the above embodiments.

[0014] Fourthly, embodiments of this application provide an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board.

[0015] In this application, the semiconductor structure includes six transistors stacked in a first direction, namely a back-side transistor, a second back-side transistor, a first back-side transistor, a first front-side transistor, a second front-side transistor, and a front-side back-side transistor. Inside the semiconductor structure, by introducing buried metal wiring technology, namely a first signal line and a second signal line, and by connecting the first signal line to the first front-side gate structure and the first back-side source / drain metal, and the second signal line to the first back-side gate structure and the first front-side source / drain metal, the semiconductor structure achieves internal interconnection while its vertical projected area is only the size of one transistor, which can greatly reduce the layout area.

[0016] Furthermore, the reduction in layout area allows for better integration of the semiconductor structure and saves on manufacturing costs; it can also be used in the manufacturing process of next-generation integrated circuits, representing a novel SRAM design solution with great application potential.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] Figure 1 This is a schematic diagram of an implementation process of the semiconductor structure fabrication method in this application.

[0020] Figure 2 This is a design layout of the semiconductor structure in the embodiments of this application;

[0021] Figure 3 This is a schematic diagram of the semiconductor structure in an embodiment of this application;

[0022] Figures 4A to 4I This is a schematic diagram of a semiconductor structure fabrication process in an embodiment of this application.

[0023] The above images:

[0024] 10. Semiconductor structure; 11. Front-side semiconductor structure; 111. First front-side transistor; 1111. First front-side source / drain structure; 1112. First front-side source / drain metal; 1113. First front-side interlayer dielectric layer; 1114. First front-side gate structure; 112. Second front-side transistor; 1121. Second front-side source / drain structure; 1122. Second front-side source / drain metal; 1123. Second front-side interlayer dielectric layer; 1124. Second front-side gate structure; 113. Front-side back-end transistor; 1131. Third front-side source / drain structure; 1132. Third front-side source / drain metal; 1134. Third front-side... 12. Front-side gate structure; 12. Back-side semiconductor structure; 121. First back-side transistor; 1211. First back-side source / drain structure; 1212. First back-side source / drain metal; 1213. First back-side interlayer dielectric layer; 1214. First back-side gate structure; 122. Second back-side transistor; 1221. Second back-side source / drain structure; 1222. Second back-side source / drain metal; 1223. Second back-side interlayer dielectric layer; 1224. Second back-side gate structure; 123. Back-side back-channel transistor; 1231. Third back-side source / drain structure; 1232. Third back-side source / drain metal; 1234. Third back-side gate Structure; 13. Insulating layer; 14. Carrier wafer; 21. Substrate; 211. Bottom substrate; 212. First stack; 213. Sacrificial layer; 214. Second stack; 22. Active structure; 221. Front active structure; 222. Back active structure; 23. Shallow trench isolation structure; 231. Shallow trench isolation layer; 241. First signal line; 242. Second signal line; 251. Front pseudo-gate structure; 26. First gap; 27. Intermediate isolation dielectric layer; 281. Front spacer wall; 282. Back spacer wall; 291. Front source / drain sidewall; 292. Back source / drain sidewall; 311. Front 321. Front-side insulating isolation layer; 322. First back-side insulating isolation layer; 331. Front-side gate dielectric layer; 332. Back-side gate dielectric layer; 341. Second front-side insulating isolation layer; 342. Second back-side insulating isolation layer; 351. Front-side channel dielectric layer; 352. Back-side channel dielectric layer; 361. Front-side gate lead-out structure; 362. Back-side gate lead-out structure; 371. Front-side metal interconnect layer; 372. Back-side metal interconnect layer; 381. Front-side gate cut-off structure; 382. Back-side gate cut-off structure; 391. Front-side isolation strip; 392. Back-side isolation strip. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0026] With Moore's Law continuously evolving, and beyond the technology node of gate-all-around FETs (GAA), further miniaturizing transistor size is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. This technology is considered one of the key technologies for continuing the miniaturization of integrated circuits.

[0027] In one embodiment, there are two methods for fabricating stacked transistors: the first is a monolithic stacking method, and the second is a sequential method.

[0028] The first approach fabricates N-channel field-effect transistors (NFETs) and P-channel field-effect transistors (PFETs) on the same substrate without using wafer bonding technology. This dictates that transistors in the same layer must be of the same type, i.e., NFETs or PFETs. Furthermore, the upper and lower transistor layers must be strictly on the same plane, with no alignment deviations. The advantage of this approach is its higher integration density. The disadvantages of this approach include the following two points: (1) the process is complex, requiring extensive development and optimization of process technologies; (2) the polarity of each transistor layer is fixed, necessitating two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0029] The second approach is based on wafer bonding and layer-by-layer fabrication. Specifically, the upper transistor is fabricated by bonding a wafer to the top of a pre-fabricated lower transistor, stacking the two transistors vertically. However, this approach requires strict temperature control during the thermal processing of the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this approach is that, thanks to wafer bonding, the device structure, channel orientation, and even channel materials used in the upper and lower transistors can be optimized to achieve better and more compatible device performance. This approach currently faces the following technical challenges: (1) fabrication of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonding wafer; and (3) alignment errors between the upper and lower transistors, requiring extremely high photolithography precision.

[0030] Static random-access memory (SRAM) helps improve the performance of computer systems and occupies a considerable chip area in many computing chips. Researchers have proposed many high-density SRAMs with smaller bit cell areas and stronger driving capabilities based on various new structures and wiring ideas, such as backside power delivery network (BSPDN) SRAM designs and complementary field-effect transistor (CFET) SRAM designs. BSPDN connects the front-side source and drain to the bottom buried power rail through backside vias (BS-Via), which can free up some front-side wiring resources and reduce the layout area. A 6T SRAM structure designed using vertical GAA CFETs and CAA IGZO pass gates reduces the area through single-sided vertical stacking.

[0031] However, for complex standard cells like SRAM, the above-described design still requires a large area to accommodate more than two transistors and interconnects in a horizontal plane, which is not conducive to scaling up the SRAM layout area.

[0032] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor structure to reduce the layout area of ​​the semiconductor structure.

[0033] In this embodiment, the semiconductor structure is an SRAM cell. The SRAM cell includes six transistors: a first front-side transistor, a second front-side transistor, a front-side back-end transistor, a first back-side transistor, a second back-side transistor, and a back-side back-end transistor.

[0034] In some embodiments, the semiconductor structure can be divided into two parts: a front semiconductor structure and a back semiconductor structure. The front semiconductor structure includes a first front transistor, a second front transistor, and a front back-end transistor, while the back semiconductor structure includes a first back transistor, a second back transistor, and a back back-end transistor.

[0035] In some embodiments, the front semiconductor structure and the back semiconductor structure are stacked back-to-back. During the fabrication process, the front semiconductor structure is fabricated first, and then the fabricated front semiconductor structure is flipped, and the back semiconductor structure is fabricated on the flipped structure.

[0036] In some embodiments, in the front-side semiconductor structure, a first front-side transistor, a second front-side transistor, and a front-side back-end transistor are stacked. The first front-side source / drain metal in the first front-side transistor, the second front-side source / drain metal in the second front-side transistor, and the third front-side source / drain metal in the front-side back-end transistor are connected.

[0037] Understandably, in a front-side semiconductor structure, the three transistors stacked together (i.e., the first front-side transistor, the second front-side transistor, and the front-side back-end transistor) achieve source-drain interconnection between the three transistors through the connection of source-drain metal.

[0038] In some embodiments, in the back-side semiconductor structure, a first back-side transistor, a second back-side transistor, and a back-side back-end transistor are stacked. The first back-side source / drain metal in the first back-side transistor, the second back-side source / drain metal in the second back-side transistor, and the third back-side source / drain metal in the back-side back-end transistor are connected.

[0039] Understandably, in a back-side semiconductor structure, the three transistors stacked together (i.e., the first back-side transistor, the second back-side transistor, and the back-side back-channel transistor) achieve source-drain interconnection between the three transistors through the connection of source-drain metal.

[0040] In some embodiments, an intermediate isolation dielectric layer is disposed between the front active structure of the front semiconductor structure and the back active structure of the back semiconductor structure; the intermediate isolation dielectric layer is used to isolate the front active structure and the back active structure.

[0041] In some embodiments, a first signal line and a second signal line are symmetrically distributed on both sides of the intermediate isolation dielectric layer; the extension directions of the first signal line and the second signal line are consistent with the extension direction of the intermediate isolation dielectric layer; the first signal line is connected to the first front gate structure and the first back source / drain metal in the first front transistor, and the second signal line is connected to the first back gate structure and the first front source / drain metal in the first back transistor.

[0042] Understandably, in the first signal line, the surface closest to the front semiconductor structure is connected to the first front gate structure via a gate via, and the surface closest to the back semiconductor structure is connected to the first back source / drain metal via a source / drain via. Similarly, in the second signal line, the surface closest to the front semiconductor structure is connected to the first front source / drain metal via a source / drain via, and the surface closest to the back semiconductor structure is connected to the first back gate structure via a gate via. These first and second signal lines achieve the electrical interconnection between the front and back semiconductor structures within the semiconductor structure.

[0043] In some embodiments, the first front transistor, the second front transistor, the first back transistor, and the second back transistor can be any of the following: a fin field-effect transistor (FinFET) or a gate-all-around field-effect transistor (GAAFET). It should be noted that the first front transistor, the second front transistor, the first back transistor, and the second back transistor can also be designed as other types of transistors according to actual needs; this application does not specifically limit these types.

[0044] In some embodiments, the front-side back-end transistor and the back-side back-end transistor can be any of the following: indium gallium zinc oxide thin film transistor (IGZO transistor), planar metal-oxide-semiconductor field-effect transistor (FET), fin field-effect transistor, or gate-all-around field-effect transistor. It should be noted that the front-side back-end transistor and the back-side back-end transistor can also be designed as other types of transistors according to actual needs, and this application embodiment does not specifically limit them.

[0045] In some embodiments, the first front transistor is a first type transistor; the second front transistor is a second type transistor; the first back transistor is a first type transistor; and the second back transistor is a second type transistor; wherein the first type transistor and the second type transistor are complementary transistors.

[0046] Understandably, the first type of transistor can be an N-type transistor or a P-type transistor, and the second type of transistor can be a P-type transistor or an N-type transistor. In the front-side semiconductor structure, the first and second front-side transistors are complementary transistors. In the back-side semiconductor structure, the first and second back-side transistors are complementary transistors.

[0047] In some embodiments, the front-side back-end transistor and the back-side back-end transistor are N-type transistors.

[0048] In some embodiments, the transistor type in the front semiconductor structure may be different from the transistor type in the back semiconductor structure. For example, the first front transistor and the second front transistor may be gate-all-around field-effect transistors, and the first back transistor and the second back transistor may be fin field-effect transistors. This application does not specifically limit the transistor type in the front semiconductor structure and the transistor type in the back semiconductor structure.

[0049] Figure 3 The semiconductor structure consists of a gate-all-around field-effect transistor and an oxide thin-film transistor, which will be discussed below. Figure 3 The schematic diagram of the semiconductor structure shown illustrates the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0050] Figure 1 This is a schematic diagram illustrating one implementation process of the semiconductor structure fabrication method in this application. See also... Figure 1 As shown, the method for fabricating the above-mentioned semiconductor structure may include:

[0051] S101, an active structure is formed on the substrate. The active structure includes a front active structure, a sacrificial structure, and a back active structure that are stacked sequentially in a first direction.

[0052] In some embodiments, where the first front transistor, the second front transistor, the first back transistor, and the second back transistor are gate-all-around field-effect transistors, the fabrication method prior to S101 may include: providing a raw silicon (Si) substrate, and alternately stacking silicon-germanium (SiGe) material and Si material on the raw Si substrate to form a stack. The stack and the raw Si substrate together constitute the substrate.

[0053] In some embodiments, to achieve isolation between the front and back semiconductor structures during subsequent fabrication, a layer of semiconductor material can be stacked in the middle of the stack to form a sacrificial layer. During the fabrication of the semiconductor structure, the sacrificial layer can serve to delineate the areas occupied by the front semiconductor structure and the areas occupied by the back semiconductor structure.

[0054] In some embodiments, the sacrificial layer can be formed using SiGe material. To distinguish it from the SiGe material in the stack during subsequent etching, a SiGe material with a higher Ge concentration can be used to prepare the sacrificial layer. That is, the stack uses SiGe1 material, and the sacrificial layer uses SiGe2 material, with the Ge concentration of SiGe2 material being higher than that of SiGe1 material.

[0055] In some embodiments, step S101 may include: patterning an active structure on a substrate and etching the substrate to form an active structure. The active structure located above the sacrificial layer is a front active structure, and the active structure located below the sacrificial layer is a back active structure.

[0056] In some embodiments, when the first front transistor, the second front transistor, the first back transistor, and the second back transistor are fin field-effect transistors, the substrate is a Si substrate, excluding the stacked layers; the active structure is a fin structure.

[0057] S102, based on the front-side active structure, a first front-side transistor, a second front-side transistor, and a front-side back-end transistor are sequentially stacked along the first direction. The first front-side source / drain metal of the first front-side transistor, the second front-side source / drain metal of the second front-side transistor, and the third front-side source / drain metal of the front-side back-end transistor are connected.

[0058] Understandably, during the fabrication of the front-side semiconductor structure, a first front-side transistor, a second front-side transistor, and a front-side back-end transistor are formed sequentially. The source-drain metals between the first front-side transistor, the second front-side transistor, and the front-side back-end transistor achieve source-drain interconnection of the front-side semiconductor structure through source-drain vias.

[0059] In some embodiments, the source-drain interconnection scheme between the first front-side transistor, the second front-side transistor, and the front-side back-end transistor can be as follows: the first front-side source-drain metal and the second front-side source-drain metal are connected through a source-drain via, and the second front-side source-drain metal and the third front-side source-drain metal are connected through a source-drain via. The source-drain via is made of a metallic material.

[0060] In some embodiments, the source-drain interconnect scheme between the first front-side transistor, the second front-side transistor, and the front-side back-end transistor can be: the first front-side source-drain metal and the third front-side source-drain metal are connected through a source-drain via, and the second front-side source-drain metal and the third front-side source-drain metal are connected through a source-drain via.

[0061] In some embodiments, the source-drain interconnect scheme between the first front-side transistor, the second front-side transistor, and the front-side back-end transistor can be: the first front-side source-drain metal and the third front-side source-drain metal are connected through a source-drain via, and the second front-side source-drain metal and the first front-side source-drain metal are connected through a source-drain via.

[0062] S103 performs back-end processing on the front-side back-end transistor to form the front-side metal interconnect layer.

[0063] Understandably, by performing processes such as inter-interconnect dielectric deposition, metal line formation, and lead-out pad formation above the front-side back-end transistors, a front-side metal interconnect layer can be formed in the front-side semiconductor structure. The metal lines in the front-side metal interconnect layer can be connected to the third front-side gate structure, the first front-side source / drain metal, the second front-side source / drain metal, and the third front-side source / drain metal.

[0064] S104, the substrate is flipped and thinned until the back-side active structure is exposed.

[0065] Understandably, after forming the front semiconductor structure, it can be flipped so that the substrate faces upwards. Then, the substrate is thinned until the back active structure is exposed.

[0066] In some embodiments, prior to S104, the preparation method may further include: depositing an insulating material (such as silicon oxide) on the front semiconductor structure to form an insulating layer, and bonding the insulating layer to a carrier wafer.

[0067] In the embodiments of this application, the bonded carrier wafer can provide physical support for the flipped front semiconductor structure after the wafer is flipped, effectively avoiding the situation where the front semiconductor structure is broken by external force during the fabrication of the back semiconductor structure.

[0068] S105, based on the back-side active structure, a first back-side transistor, a second back-side transistor, and a back-side back-channel transistor are sequentially stacked along the first direction. The first back-side source / drain metal of the first back-side transistor, the second back-side source / drain metal of the second back-side transistor, and the third back-side source / drain metal of the back-side back-channel transistor are connected.

[0069] Understandably, similar to the process flow for fabricating the front semiconductor structure, the fabrication of the back semiconductor structure involves sequentially forming a first back transistor, a second back transistor, and a back-end transistor. The source-drain interconnects between the first back transistor, the second back transistor, and the back-end transistor are achieved through source-drain vias.

[0070] In some embodiments, the source-drain interconnection scheme between the first back-side transistor, the second back-side transistor, and the back-side back-channel transistor can be as follows: the first back-side source-drain metal and the second back-side source-drain metal are connected through a source-drain via, and the second back-side source-drain metal and the third back-side source-drain metal are connected through a source-drain via. The source-drain via is made of a metallic material.

[0071] In some embodiments, the source-drain interconnect scheme between the first back-side transistor, the second back-side transistor, and the back-side back-channel transistor can be: the first back-side source-drain metal and the third back-side source-drain metal are connected through a source-drain via, and the second back-side source-drain metal and the third back-side source-drain metal are connected through a source-drain via.

[0072] In some embodiments, the source-drain interconnect scheme between the first back-side transistor, the second back-side transistor, and the back-side back-channel transistor can be: the first back-side source-drain metal and the third back-side source-drain metal are connected through a source-drain via, and the second back-side source-drain metal and the first back-side source-drain metal are connected through a source-drain via.

[0073] S106, performs back-end processing on the back-end transistor to form a back-end metal interconnect layer.

[0074] Understandably, performing processes such as inter-interconnect dielectric deposition, metal line formation, and lead-out pad formation above the back-side back-end transistors can form a back-side metal interconnect layer in the back-side semiconductor structure. The metal lines in the back-side metal interconnect layer can be connected to the third back-side gate structure, the first back-side source / drain metal, the second back-side source / drain metal, and the third back-side source / drain metal.

[0075] In some possible implementations, S102 may include: performing source drain epitaxial growth in the front source drain region of the front semiconductor structure to form a first front source drain structure of the first front transistor; forming a first front source drain metal and a first front insulating isolation layer on the first front source drain structure; the first front insulating isolation layer is used to isolate the first front transistor and the second front transistor in the front source drain region; performing source drain epitaxial growth in the front source drain region and on the first front insulating isolation layer to form a second front source drain structure of the second front transistor; depositing metal material in the front gate region of the front semiconductor structure to form a first front gate structure; depositing metal material in the front gate region and on the first front gate structure to form a second front gate structure of the second front transistor; forming a second front source drain metal and a second front insulating isolation layer on the second front source drain structure; the second front insulating isolation layer is used to isolate the second front transistor and the front back-end transistor; forming a front back-end transistor on the second front insulating isolation layer; and performing back-end processing on the front back-end transistor to form a front metal interconnect layer.

[0076] Understandably, the first and second front-side source / drain structures are formed sequentially in the front-side source / drain region of the front-side semiconductor structure. Etching the front-side active structure exposes the space occupied by the front-side source / drain region. Similarly, the first and second front-side gate structures are formed sequentially in the front-side gate region of the front-side semiconductor structure, and the front-side gate region is opened by photolithography.

[0077] It should be noted that, for ease of explanation, the first front-side source / drain structure mentioned in the embodiments of this application is an abbreviation, specifically referring to the first front-side source structure and / or the first front-side drain structure. Furthermore, the second front-side source / drain structure, the third front-side source / drain metal, the first back-side source / drain structure, etc., are all similar to the first front-side source / drain structure, where "source / drain" is an abbreviation for "source and / or drain".

[0078] In some embodiments, after photolithography opens the front gate region, an insulating material (such as polysilicon) is first filled in the front gate region to form a front dummy gate structure; then, the front dummy gate structure is removed by selective etching to expose the front gate region, and different metal materials are sequentially deposited in the front gate region to form a first front gate structure and a second front gate structure.

[0079] In some possible implementations, forming a front-side back-end transistor on the second front-side insulating isolation layer may include: depositing an insulating material on the second front-side insulating isolation layer to form a front-side channel dielectric layer; forming a third front-side source / drain structure and a third front-side gate structure on the front-side channel dielectric layer; forming a third source / drain metal and a front-side gate lead-out structure on the third front-side source / drain structure and the third front-side gate structure, respectively; and using the front-side gate lead-out structure to connect the third front-side gate structure and the front-side metal interconnect layer.

[0080] Understandably, unlike the first and second front-side transistors which are based on a front-side active structure, the front-side back-end transistor is formed by stacking multiple layers above the second front-side transistor. Isolation between the front-side back-end transistor and the second front-side transistor is achieved through a front-side channel dielectric layer.

[0081] In some possible implementations, S105 may include: performing source drain epitaxial growth in the back source drain region of the back semiconductor structure to form a first back source drain structure of the first back transistor; forming a first back source drain metal and a first back insulating isolation layer on the first back source drain structure; the first back insulating isolation layer is used to isolate the first back transistor and the second back transistor in the back source drain region; performing source drain epitaxial growth in the back source drain region and on the first back insulating isolation layer to form a second back source drain structure of the second back transistor; depositing metal material in the back gate region of the back semiconductor structure to form a first back gate structure; depositing metal material in the back gate region and on the first back gate structure to form a second back gate structure of the second back transistor; forming a second back source drain metal and a second back insulating isolation layer on the second back source drain structure; the second back insulating isolation layer is used to isolate the second back transistor and the back back-end transistor; forming a back-end transistor on the second back insulating isolation layer; and performing back-end processing on the back-end transistor to form a back metal interconnect layer.

[0082] Understandably, the first and second back-side source / drain structures are formed sequentially in the back-side source / drain region of the back-side semiconductor structure, and the space occupied by the back-side source / drain region can be exposed by etching the back-side active structure. The first and second back-side gate structures are formed sequentially in the back-side gate region of the back-side semiconductor structure, and the back-side gate region is opened by photolithography.

[0083] In some embodiments, after photolithography opens the back gate region, an insulating material (such as polysilicon) is first filled in the back gate region to form a back dummy gate structure; then, the back dummy gate structure is removed by selective etching to expose the back gate region, and different metal materials are sequentially deposited in the back gate region to form a first back gate structure and a second back gate structure.

[0084] In some possible implementations, forming a back-side back-channel transistor on the second back-side insulating isolation layer may include: depositing an insulating material on the second back-side insulating isolation layer to form a back-side channel dielectric layer; forming a third back-side source / drain structure and a third back-side gate structure on the back-side channel dielectric layer; forming a third source / drain metal and a back-side gate lead-out structure on the third back-side source / drain structure and the third back-side gate structure, respectively; and using the back-side gate lead-out structure to connect the third back-side gate structure and the back-side metal interconnect layer.

[0085] Understandably, unlike the first and second back-side transistors which are based on a back-side active structure, the back-side back-side transistor is formed by stacking multiple layers above the second back-side transistor. Isolation between the back-side back-side transistor and the second back-side transistor is achieved through a back-side channel dielectric layer.

[0086] In some embodiments, the front semiconductor structure and the back semiconductor structure in the semiconductor structure can be fabricated using a monolithic stacking scheme or a sequential scheme. This application does not specifically limit this.

[0087] The following describes the semiconductor structure provided in the embodiments of this application, taking the first front transistor, the second front transistor, the first back transistor, and the second back transistor as fin field-effect transistors, and the front back transistor and the back back transistor as oxide thin film transistors. Figure 2 This is a design layout of the semiconductor structure in an embodiment of this application, wherein, Figure 2 (a) in the diagram is a design layout of transistors (i.e., first front-side transistor, second front-side transistor, first back-side transistor and second back-side transistor) in a semiconductor structure; Figure 2 (b) in the diagram is the design layout of the front-side metal interconnect layer in the semiconductor structure; Figure 2 (c) in the diagram represents the design layout of the back metal interconnect layer in the semiconductor structure. Figure 3 This is a schematic diagram of the semiconductor structure in an embodiment of this application. Figure 3 (a) in the diagram is a cross-sectional view of the semiconductor structure along the AA' direction in the design layout; Figure 3 (b) in the diagram is a cross-sectional view of the semiconductor structure along the BB' direction in the design layout; Figure 3(c) in the diagram is a cross-sectional view of the semiconductor structure along the CC' direction in the design layout; Figure 3 (d) in the diagram is a cross-sectional view of the semiconductor structure along the DD' direction in the design layout.

[0088] In some embodiments, see Figure 2 As shown, the area within the dashed box represents an SRAM cell, with the first metal interconnect layer (M0) and the second metal interconnect layer (M1) arranged in layers. The drain-to-drain (VDD) and source-to-source (VSS) voltage structures are symmetrically arranged. The positions of the word line (WL), bit line (BL), and base-to-emitter voltage (BLB) structures are shown in the figure.

[0089] The following section, in conjunction with the above preparation method, discusses... Figure 3 The fabrication process of the semiconductor structure 10 shown will be explained. Figure 3 The semiconductor structure 10 shown can be used to... Figures 4A to 4I The process shown is used for preparation. Figures 4A to 4I This is a schematic diagram of a semiconductor structure fabrication process in an embodiment of this application.

[0090] Step 1: Provide a substrate 21. The substrate 21 includes a bottom substrate 211, a first stack 212, a sacrificial layer 213, and a second stack 214 (see...). Figure 4A (a)). The first stack 212 and the second stack 214 are both formed by sequentially stacking Si material and SiGe1 material, and the sacrificial layer 213 is made of SiGe2 material.

[0091] in, Figure 4A The AA', BB', and CC' cross-sectional diagrams have the same structure; only one diagram is shown as an example.

[0092] Step 2: Etch substrate 21 to form active structure 22. Active structure 22 includes front active structure 221 and back active structure 222. The etched sacrificial layer 213 is located between front active structure 221 and back active structure 222 (see [link]). Figure 4A (b) in the middle.

[0093] Step 3: Deposit insulating material on the bottom substrate 211 and the active structure 22 to form a shallow trench isolation structure 23. The shallow trench isolation structure 23 encloses the active structure 22 and covers the bottom substrate 211; at this time, the height of the shallow trench isolation structure 23 in the horizontal direction is greater than the height of the active structure 22. Next, by etching, a portion of the shallow trench isolation structure 23 is removed until the front active structure 221 is exposed; at this time, the sacrificial layer 213 and the back active structure 222 are still enclosed by the shallow trench isolation structure 23 (see...). Figure 4A (b) in the middle.

[0094] In some embodiments, after forming the shallow trench isolation structure 23, the shallow trench isolation structure 23 can be subjected to chemical-mechanical planarization (CMP) treatment. This ensures that when the shallow trench isolation structure 23 is subsequently etched, the etching depth of different regions of the shallow trench isolation structure 23 is the same, thereby making the height of the exposed active structure the same.

[0095] Step 4: Embed the first signal line 241 and the second signal line 242 on both sides of the sacrificial layer 213 in the shallow trench isolation structure 23 (see...). Figure 4B (a)). The first signal line 241 and the second signal line 242 are made of metallic material.

[0096] In some embodiments, the method for fabricating the first signal line 241 and the second signal line 242 includes: coating a shallow trench isolation structure 23 with photoresist to form a photomask with a preset photolithographic pattern; etching the shallow trench isolation structure 23 under the masking action of the photomask to form two grooves, the two grooves being located on both sides of the sacrificial layer 213, and the extension direction of the grooves being consistent with the extension direction of the active structure (i.e., the DD' direction); removing the photomask; depositing a metal material of a preset height in the grooves to form the first signal line 241 and the second signal line 242; and depositing an insulating material above the first signal line 241 and the second signal line 242 until the two grooves are filled.

[0097] It should be noted that the first signal line 241 and the second signal line 242 can be formed during the fabrication of the front semiconductor structure 11 or during the fabrication of the back semiconductor structure 12. The above-mentioned formation of the first signal line 241 and the second signal line 242 during the fabrication of the front semiconductor structure 11 is only one example and does not limit the timing of the fabrication of the first signal line 241 and the second signal line 242 in the embodiments of this application.

[0098] Step 5: Photolithography opens the front gate region, and polysilicon is deposited in the front gate region to form the front dummy gate structure 251 (see...). Figure 4B (b) in the middle.

[0099] Step 6: Etch the shallow trench isolation structure 23 downwards to a predetermined height until a portion of the sacrificial layer 213 is exposed (see...). Figure 4B (c)). It should be noted that during the etching process, it is necessary to ensure that the first signal line 241 and the second signal line 242 are not exposed.

[0100] It should be noted that, in Figure 4B In (b) and (c), the structures of the BB' and CC' cross-sectional diagrams are the same, and only one structural diagram is shown as an example.

[0101] Step 7: Remove the sacrificial layer 213 to form the first gap 26 (see...) Figure 4C (a) in the middle.

[0102] Step 8: Deposit insulating material (such as low-K material) in the first gap 26 to form an intermediate insulating dielectric layer 27; simultaneously, form front gap walls 281 on both sides of the front pseudo-gate structure 251 (see...). Figure 4C (b) in the middle.

[0103] It should be noted that the intermediate insulating dielectric layer 27 and the frontal spacer wall 281 can be formed in the same deposition process. In the process of forming the intermediate insulating dielectric layer 27 and the frontal spacer wall 281, insulating material is first deposited in the first gap 26 and on the shallow trench isolation structure 23, the frontal active structure 221 and the frontal dummy gate structure 251; then, the insulating material on the shallow trench isolation structure 23, the frontal active structure 221 and the upper surface of the frontal dummy gate structure 251 is removed, and the remaining insulating material forms the intermediate insulating dielectric layer 27 and the frontal spacer wall 281.

[0104] It should be noted that the intermediate isolation dielectric layer 27 can be formed during the fabrication of the front semiconductor structure 11 or during the fabrication of the back semiconductor structure 12. The above-described formation of the intermediate isolation dielectric layer 27 during the fabrication of the front semiconductor structure 11 is merely one example and does not limit the timing of the fabrication of the intermediate isolation dielectric layer 27 in the embodiments of this application.

[0105] Step 9: Etch a portion of the front-side active structure 221 to form the front-side source / drain region; fill the sidewalls of the front-side source / drain region with an insulating material (such as silicon nitride (SiN)) to form the front-side source / drain sidewalls 291 (see...). Figure 4C (c) in the middle.

[0106] Step 10: An isotropic layer of insulating material is deposited on the sidewalls of the front source / drain sidewall 291 and the front gap wall 281 to form the front source / drain protection layer 311 (see...). Figure 4D(a)). The front source / drain protection layer 311 can protect the front active structure 221 during the growth of the source / drain epitaxy.

[0107] Step 11: Continue etching downwards a portion of the front-side active structure 221 to increase the height of the front-side source / drain region, stopping the etching at the Si layer above the intermediate isolation dielectric layer 27; fill the sidewalls of the newly formed front-side source / drain region with insulating material (such as silicon nitride) to form new front-side source / drain sidewalls 291 (see...). Figure 4D (b) in the middle.

[0108] It should be noted that the Si layers located on the upper and lower surfaces of the intermediate isolation dielectric layer 27 serve to protect the intermediate isolation dielectric layer 27 during the etching process, but they do not limit the specific structure of the first stack 212 and the second stack 214 in this embodiment. Alternatively, the Si layers may not be provided on the upper and lower surfaces of the intermediate isolation dielectric layer 27 in this embodiment; that is, both the upper and lower surfaces of the intermediate isolation dielectric layer 27 may be made of SiGe1 material.

[0109] Step 12: Grow source-drain epitaxy in the front-side source-drain region to form the first front-side source-drain structure 1111 in the first front-side transistor 111 (see...) Figure 4D (c)). The first positive source / drain structure 1111 is a P-type source / drain structure.

[0110] Step 13: Remove the front-side source / drain protection layer 311 by selective etching (see...) Figure 4E (a) in the middle.

[0111] Step 14: Form a first front-side source / drain metal 1112 on the first front-side source / drain structure 1111. The first front-side source / drain metal 1112 is connected to the second signal line 242 through a first source / drain via. Deposit an interlayer dielectric in the corresponding front-side source / drain region of the first front-side transistor 111 to form a first front-side interlayer dielectric layer 1113 (see [link]). Figure 4E (b) in the middle.

[0112] It should be noted that the source and drain metals can be formed before or after the gate structure is formed; this application does not specifically limit this.

[0113] Step 15: Deposit insulating material on the first front source / drain metal 1112 in the front source / drain region to form the first front insulating isolation layer 321 (see...). Figure 4E (c)). The first front insulating isolation layer 321 is used to isolate the first front transistor 111 and the second front transistor 112 in the front source-drain region.

[0114] Step 16: Grow source / drain epitaxy on the first front insulating layer 321 in the front source / drain region to form the second front source / drain structure 1121 in the second front transistor 112 (see...). Figure 4F (a)). The second positive source / drain structure 1121 is an N-type source / drain structure.

[0115] Step 17: Deposit an interlayer dielectric in the corresponding front source / drain region of the second front transistor 112 to form a second front interlayer dielectric layer 1123; remove the front dummy gate structure 251 to expose the front gate region, and deposit an insulating material to form a front gate dielectric layer 331; deposit a metal material in the corresponding front gate region of the first front transistor 111 to form a first front gate structure 1114; deposit a metal material on the first front gate structure 1114 and in the corresponding front gate region of the second front transistor 112 to form a second front gate structure 1124 (see...). Figure 4F (b)). The first front gate structure 1114 is connected to the first signal line 241 through the first gate via.

[0116] Step 18: Form a second front-side source / drain metal 1122 on the second front-side source / drain structure 1121; deposit insulating material on the second front-side gate structure 1124 and on both sides of the second front-side source / drain metal 1122 to form a second front-side insulating isolation layer 341 (see...). Figure 4F (c)). In this case, the second front source / drain metal 1122 is connected to the first front source / drain metal 1112 through the second source / drain via.

[0117] Step 19: Deposit insulating material on the second front insulating isolation layer 341 to form the front channel dielectric layer 351; form the third front source / drain structure 1131 and the third front gate structure 1134 of the front back-channel transistor 113 on the front channel dielectric layer 351 (see...). Figure 4G (a) in the middle.

[0118] Step 20: Form a third front-side source / drain metal 1132 on the third front-side source / drain structure 1131; and form a front-side gate lead-out structure 361 on the third front-side gate structure 1134 (see...). Figure 4G (b)). The third front source / drain metal 1132 is connected to the second front source / drain metal 1122 through the third source / drain via.

[0119] Step 21: Perform subsequent processes on the third front-side source / drain metal 1132 and the front-side gate lead-out structure 361 to form the front-side metal interconnect layer 371 (see...). Figure 4G(c)). Among them, the metal lines in the front metal interconnect layer 371 are respectively connected to the first front source / drain metal 1112, the second front source / drain metal 1122, the third front source / drain metal 1132 and the front gate lead-out structure 361.

[0120] Step 22: Deposit insulating material on the front-side metal interconnect layer 371 to form insulating layer 13; bond insulating layer 13 to carrier wafer 14; then, perform a flipping process on the front-side semiconductor structure 11 so that the bottom substrate 211 faces upward (see...). Figure 4H (a) in the middle.

[0121] Step 23: Thin the bottom substrate 211 until the shallow trench isolation structure 23 and the surface of the back active structure 222 away from the front active structure 221 are exposed (see...). Figure 4H (b) in the middle.

[0122] Step 24: Thin the shallow trench isolation structure 23 and the back active structure 222 by CMP treatment, stopping the CMP at the SiGe1 layer closest to the bottom substrate 211 (see...). Figure 4H (c) in the middle.

[0123] Step 25: Continue thinning the shallow trench isolation structure 23 and the back active structure 222 by CMP treatment, stopping the CMP at the Si layer closest to the SiGe1 layer in step 24 above (see...). Figure 4I (a) in the middle.

[0124] Step 26: Etch the shallow trench isolation structure 23 to a predetermined height, stopping the etching until the back-side active structure 222 is exposed. The shallow trench isolation structure 23 surrounding the intermediate isolation dielectric layer 27 is not etched; the retained shallow trench isolation structure 23 forms the shallow trench isolation layer 231 (see...). Figure 4I (b) in the middle.

[0125] Step 27: Following the method for preparing the front semiconductor structure 11 described above, prepare the back semiconductor structure 12. Perform gate cutting on the first front gate structure 1114, the second front gate structure 1124, the first back gate structure 1214, and the second back gate structure 1224 in the semiconductor structure 10 to form a front gate cut-off structure 381 and a back gate cut-off structure 382; and remove the first front gate structure 1114, the second front gate structure 1124, the first back gate structure 1214, and the second back gate structure 1224 located on both sides of the source / drain structure to form a first groove. Fill the first groove with insulating material to form a front isolation band (singlediffusion break, SDB) 391 and a back isolation band 392 (see...). Figure 4I (c) in the middle.

[0126] The back semiconductor structure 12 includes: a first back transistor 121, a second back transistor 122, a back back channel transistor 123, a back spacer 282, a back source / drain sidewall 292, a first back source / drain structure 1211, a first back source / drain metal 1212, a first back interlayer dielectric layer 1213, a first back insulating isolation layer 322, a second back source / drain structure 1221, a second back source / drain metal 1222, a second back interlayer dielectric layer 1223, a back gate dielectric layer 332, a first back gate structure 1214, a second back gate structure 1224, a second back insulating isolation layer 342, a back channel dielectric layer 352, a third back source / drain structure 1231, a third back source / drain metal 1232, a third back gate structure 1234, a back gate lead-out structure 362, and a back metal interconnect layer 372. The first back-side source / drain structure 1211 is a P-type source / drain structure; the second back-side source / drain structure 1221 is an N-type source / drain structure; the first back-side source / drain metal 1212 is connected to the first signal line 241 through the fourth source / drain via; the second back-side source / drain metal 1222 is connected to the first back-side source / drain metal 1212 through the fifth source / drain via; the third back-side source / drain metal 1232 is connected to the second back-side source / drain metal 1222 through the sixth source / drain via; the metal lines in the back-side metal interconnect layer 372 are respectively connected to the first back-side source / drain metal 1212, the second back-side source / drain metal 1222, the third back-side source / drain metal 1232 and the back-side gate lead-out structure 362; the first back-side gate structure 1214 is connected to the second signal line 242 through the second gate via.

[0127] At this point, the semiconductor structure 10 has been successfully fabricated.

[0128] In this embodiment, the semiconductor structure includes six transistors stacked in a first direction, namely a back-side transistor, a second back-side transistor, a first back-side transistor, a first front-side transistor, a second front-side transistor, and a front-side back-side transistor. Inside the semiconductor structure, by introducing buried metal wiring technology, namely a first signal line and a second signal line, and by connecting the first signal line to the first front-side gate structure and the first back-side source / drain metal, and the second signal line to the first back-side gate structure and the first front-side source / drain metal, the semiconductor structure achieves internal interconnection while its vertical projected area is only the size of one transistor, which greatly reduces the layout area.

[0129] Furthermore, the reduction in layout area allows for better integration of the semiconductor structure and saves on manufacturing costs; it can also be used in the manufacturing process of next-generation integrated circuits, representing a novel SRAM design solution with great application potential.

[0130] Furthermore, the semiconductor structure provided in this application embodiment can be detected using analytical instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, the semiconductor structure provided in this application embodiment can be detected by TEM slicing. For example, it can be observed that the semiconductor structure has a first signal line and a second signal line, with the first signal line connected to the first front gate structure and the first back source / drain metal, and the second signal line connected to the first back gate structure and the first front source / drain metal; it can also be observed that an intermediate isolation dielectric layer is provided in the middle of the semiconductor structure to achieve isolation between the front semiconductor structure and the back semiconductor structure.

[0131] This application provides a semiconductor device, including the semiconductor structure as described in the above embodiments. Specific limitations of the semiconductor structure can be found above. Figure 3 The semiconductor structure shown will not be described in detail here.

[0132] This application provides an electronic device, including a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board. The semiconductor device includes the semiconductor structure described above. Specific limitations of the semiconductor structure can be found above. Figure 3 This will not be elaborated upon here.

[0133] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0134] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The semiconductor structure is a static random access memory (SRAM) cell, and the method includes: An active structure is formed on a substrate; the active structure includes a front active structure, a sacrificial structure, and a back active structure stacked sequentially in a first direction; Based on the aforementioned front active structure, a first front transistor, a second front transistor, and a front back transistor are sequentially stacked along the first direction; the first front source / drain metal in the first front transistor, the second front source / drain metal in the second front transistor, and the third front source / drain metal in the front back transistor are connected. Back-end processes are performed on the front-side back-end transistor to form a front-side metal interconnect layer; The substrate is flipped and thinned until the back-side active structure is exposed; Based on the back active structure, a first back transistor, a second back transistor, and a back back channel transistor are sequentially stacked along the first direction; the first back source / drain metal in the first back transistor, the second back source / drain metal in the second back transistor, and the third back source / drain metal in the back back channel transistor are connected. Back-end processes are performed on the back-end back-end transistor to form a back-end metal interconnect layer; The method further includes: removing the sacrificial structure to form a first gap, and filling the first gap with insulating material to form an intermediate isolation dielectric layer; the intermediate isolation dielectric layer is used to isolate the front active structure and the back active structure; embedding symmetrically distributed first signal lines and second signal lines on both sides of the intermediate isolation dielectric layer; the extending directions of the first signal lines and the second signal lines are consistent with the extending direction of the intermediate isolation dielectric layer; The first signal line is connected to the first front gate structure and the first back source / drain metal in the first front transistor, and the second signal line is connected to the first back gate structure and the first front source / drain metal in the first back transistor.

2. The method according to claim 1, characterized in that, The first front-side transistor, the second front-side transistor, and the front-side back-end transistor constitute a front-side semiconductor structure; The first front-side transistor, the second front-side transistor, and the front-side back-end transistor, which are sequentially stacked along the first direction based on the front-side active structure, include: Source-drain epitaxial growth is performed in the source-drain region of the front semiconductor structure to form the first front source-drain structure of the first front transistor. A first front-side source / drain metal and a first front-side insulating isolation layer are formed on the first front-side source / drain structure; the first front-side insulating isolation layer is used to isolate the first front-side transistor and the second front-side transistor in the front-side source / drain region; Source-drain epitaxial growth is performed on the first front insulating isolation layer in the front source-drain region to form the second front source-drain structure of the second front transistor; Metal material is deposited in the front gate region of the front semiconductor structure to form the first front gate structure; Metal material is deposited on the first front gate structure in the front gate region to form the second front gate structure of the second front transistor; A second front-side source / drain metal and a second front-side insulating isolation layer are formed on the second front-side source / drain structure; the second front-side insulating isolation layer is used to isolate the second front-side transistor and the front-side back-end transistor. A front-side back-end transistor is formed on the second front-side insulating isolation layer; Back-end processes are performed on the front-side back-end transistors to form the front-side metal interconnect layer.

3. The method according to claim 2, characterized in that, The formation of a front-side back-end transistor on the second front-side insulating layer includes: An insulating material is deposited on the second front insulating isolation layer to form a front channel dielectric layer; A third front-side source / drain structure and a third front-side gate structure are formed on the front-side channel dielectric layer; A third source / drain metal and a front gate lead-out structure are formed on the third front source / drain structure and the third front gate structure, respectively; the front gate lead-out structure is used to connect the third front gate structure and the front metal interconnect layer.

4. The method according to claim 1, characterized in that, The first back-side transistor, the second back-side transistor, and the back-side back-end transistor constitute a back-side semiconductor structure; The method, based on the back-side active structure, sequentially forming a first back-side transistor, a second back-side transistor, and a back-side back-channel transistor along the first direction, includes: Source-drain epitaxial growth is performed in the back-side source-drain region of the back-side semiconductor structure to form the first back-side source-drain structure of the first back-side transistor; A first back-side source / drain metal and a first back-side insulating isolation layer are formed on the first back-side source / drain structure; the first back-side insulating isolation layer is used to isolate the first back-side transistor and the second back-side transistor in the back-side source / drain region; Source-drain epitaxial growth is performed on the first back insulating layer in the back source-drain region to form the second back source-drain structure of the second back transistor; Metal material is deposited in the back gate region of the back semiconductor structure to form the first back gate structure; Metal material is deposited on the first back gate structure in the back gate region to form the second back gate structure of the second back transistor; A second back-side source / drain metal and a second back-side insulating layer are formed on the second back-side source / drain structure; the second back-side insulating layer is used to isolate the second back-side transistor and the back-side back-channel transistor. A back-end transistor is formed on the second back-end insulating layer; Back-end processes are performed on the back-end transistor to form a back-end metal interconnect layer.

5. The method according to claim 4, characterized in that, The formation of the back-side back-end transistor on the second back-side insulating layer includes: An insulating material is deposited on the second back insulating isolation layer to form a back channel dielectric layer; A third back-side source / drain structure and a third back-side gate structure are formed on the back-side channel dielectric layer; A third source / drain metal and a back gate lead-out structure are formed on the third back source / drain structure and the third back gate structure, respectively; the back gate lead-out structure is used to connect the third back gate structure and the back metal interconnect layer.

6. The method according to claim 1, characterized in that, The first front-facing transistor is a first-type transistor; the second front-facing transistor is a second-type transistor; the first back-facing transistor is a first-type transistor; the second back-facing transistor is a second-type transistor. The first type of transistor and the second type of transistor are complementary transistors.

7. The method according to claim 1, characterized in that, The first front transistor, the second front transistor, the first back transistor, and the second back transistor are any one of the following: fin field-effect transistors and gate-all-around field-effect transistors.

8. The method according to claim 1, characterized in that, The front-side back-end transistor and the back-side back-end transistor are any of the following: oxide thin-film transistor, planar field-effect transistor, fin field-effect transistor, and gate-all-around field-effect transistor.

9. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method according to any one of claims 1 to 8, and the semiconductor structure is a static random access memory (SRAM) cell, the semiconductor structure comprising: A front-side semiconductor structure; the front-side semiconductor structure includes a first front-side transistor, a second front-side transistor, and a front-side back-end transistor stacked in a first direction; the first front-side source / drain metal in the first front-side transistor, the second front-side source / drain metal in the second front-side transistor, and the third front-side source / drain metal in the front-side back-end transistor are connected; A back semiconductor structure; the front semiconductor structure and the back semiconductor structure are stacked in the first direction; the back semiconductor structure includes a first back transistor, a second back transistor, and a back back-end transistor stacked in the first direction; a first back source / drain metal in the first back transistor, a second back source / drain metal in the second back transistor, and a third back source / drain metal in the back back-end transistor are connected; In this configuration, an intermediate isolation dielectric layer is disposed between the front active structure of the front semiconductor structure and the back active structure of the back semiconductor structure; the intermediate isolation dielectric layer is used to isolate the front active structure and the back active structure; a first signal line and a second signal line are symmetrically distributed on both sides of the intermediate isolation dielectric layer; the extension directions of the first signal line and the second signal line are consistent with the extension direction of the intermediate isolation dielectric layer; the first signal line is respectively connected to the first front gate structure and the first back source / drain metal in the first front transistor, and the second signal line is respectively connected to the first back gate structure and the first front source / drain metal in the first back transistor.

10. A semiconductor device, characterized in that, include: The semiconductor structure as described in claim 9.

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